mirror of https://github.com/efabless/caravel.git
Update housekeeping views and openlane configuration
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336902
def/housekeeping.def
336902
def/housekeeping.def
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@ -2887,9 +2887,9 @@ MACRO housekeeping
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@ -3017,9 +3017,9 @@ MACRO housekeeping
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END
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END housekeeping
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||||
END LIBRARY
|
||||
|
|
1051900
mag/housekeeping.mag
1051900
mag/housekeeping.mag
File diff suppressed because it is too large
Load Diff
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@ -1,11 +1,11 @@
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|||
magic
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tech sky130A
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||||
magscale 1 2
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timestamp 1665915522
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||||
timestamp 1666031400
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
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|
||||
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|
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|
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|
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|
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|
||||
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|
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||||
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|
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|
||||
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|
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|
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|
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|
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|
||||
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rect 565 38016 73246 38552
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|
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|
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|
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|
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rect 565 36920 73166 37200
|
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rect 565 36384 73246 36920
|
||||
rect 880 36104 73246 36384
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|
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rect 565 35568 73246 36104
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rect 565 35288 73166 35568
|
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rect 565 34752 73246 35288
|
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rect 880 34472 73246 34752
|
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rect 800 33936 73246 34472
|
||||
rect 800 33656 73166 33936
|
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rect 800 33120 73246 33656
|
||||
rect 565 33936 73246 34472
|
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rect 565 33656 73166 33936
|
||||
rect 565 33120 73246 33656
|
||||
rect 880 32840 73246 33120
|
||||
rect 800 32304 73246 32840
|
||||
rect 800 32024 73166 32304
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rect 800 31488 73246 32024
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rect 565 32304 73246 32840
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rect 565 32024 73166 32304
|
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rect 565 31488 73246 32024
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rect 880 31208 73246 31488
|
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rect 800 30672 73246 31208
|
||||
rect 800 30392 73166 30672
|
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rect 800 29856 73246 30392
|
||||
rect 565 30672 73246 31208
|
||||
rect 565 30392 73166 30672
|
||||
rect 565 29856 73246 30392
|
||||
rect 880 29576 73246 29856
|
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rect 800 29040 73246 29576
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rect 800 28760 73166 29040
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||||
rect 800 28224 73246 28760
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rect 565 29040 73246 29576
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rect 565 28760 73166 29040
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rect 565 28224 73246 28760
|
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rect 880 27944 73246 28224
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rect 800 27408 73246 27944
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rect 800 27128 73166 27408
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rect 800 26592 73246 27128
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rect 565 27408 73246 27944
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rect 565 27128 73166 27408
|
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rect 565 26592 73246 27128
|
||||
rect 880 26312 73246 26592
|
||||
rect 800 25776 73246 26312
|
||||
rect 800 25496 73166 25776
|
||||
rect 800 24960 73246 25496
|
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rect 565 25776 73246 26312
|
||||
rect 565 25496 73166 25776
|
||||
rect 565 24960 73246 25496
|
||||
rect 880 24680 73246 24960
|
||||
rect 800 24144 73246 24680
|
||||
rect 800 23864 73166 24144
|
||||
rect 800 23328 73246 23864
|
||||
rect 565 24144 73246 24680
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rect 565 23864 73166 24144
|
||||
rect 565 23328 73246 23864
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rect 880 23048 73246 23328
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||||
rect 800 22512 73246 23048
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||||
rect 800 22232 73166 22512
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||||
rect 800 21696 73246 22232
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||||
rect 565 22512 73246 23048
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||||
rect 565 22232 73166 22512
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||||
rect 565 21696 73246 22232
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||||
rect 880 21416 73246 21696
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||||
rect 800 20880 73246 21416
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rect 800 20600 73166 20880
|
||||
rect 800 20064 73246 20600
|
||||
rect 565 20880 73246 21416
|
||||
rect 565 20600 73166 20880
|
||||
rect 565 20064 73246 20600
|
||||
rect 880 19784 73246 20064
|
||||
rect 800 19248 73246 19784
|
||||
rect 800 18968 73166 19248
|
||||
rect 800 18432 73246 18968
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||||
rect 565 19248 73246 19784
|
||||
rect 565 18968 73166 19248
|
||||
rect 565 18432 73246 18968
|
||||
rect 880 18152 73246 18432
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||||
rect 800 17616 73246 18152
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||||
rect 800 17336 73166 17616
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||||
rect 800 16800 73246 17336
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||||
rect 565 17616 73246 18152
|
||||
rect 565 17336 73166 17616
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||||
rect 565 16800 73246 17336
|
||||
rect 880 16520 73246 16800
|
||||
rect 800 15984 73246 16520
|
||||
rect 800 15704 73166 15984
|
||||
rect 800 15168 73246 15704
|
||||
rect 565 15984 73246 16520
|
||||
rect 565 15704 73166 15984
|
||||
rect 565 15168 73246 15704
|
||||
rect 880 14888 73246 15168
|
||||
rect 800 14352 73246 14888
|
||||
rect 800 14072 73166 14352
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||||
rect 800 13536 73246 14072
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||||
rect 565 14352 73246 14888
|
||||
rect 565 14072 73166 14352
|
||||
rect 565 13536 73246 14072
|
||||
rect 880 13256 73246 13536
|
||||
rect 800 12720 73246 13256
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||||
rect 800 12440 73166 12720
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||||
rect 800 11904 73246 12440
|
||||
rect 565 12720 73246 13256
|
||||
rect 565 12440 73166 12720
|
||||
rect 565 11904 73246 12440
|
||||
rect 880 11624 73246 11904
|
||||
rect 800 11088 73246 11624
|
||||
rect 800 10808 73166 11088
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||||
rect 800 10272 73246 10808
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||||
rect 565 11088 73246 11624
|
||||
rect 565 10808 73166 11088
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rect 565 10272 73246 10808
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||||
rect 880 9992 73246 10272
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||||
rect 800 9456 73246 9992
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||||
rect 800 9176 73166 9456
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||||
rect 800 8640 73246 9176
|
||||
rect 565 9456 73246 9992
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||||
rect 565 9176 73166 9456
|
||||
rect 565 8640 73246 9176
|
||||
rect 880 8360 73246 8640
|
||||
rect 800 7824 73246 8360
|
||||
rect 800 7544 73166 7824
|
||||
rect 800 7008 73246 7544
|
||||
rect 565 7824 73246 8360
|
||||
rect 565 7544 73166 7824
|
||||
rect 565 7008 73246 7544
|
||||
rect 880 6728 73246 7008
|
||||
rect 800 6192 73246 6728
|
||||
rect 800 5912 73166 6192
|
||||
rect 800 5376 73246 5912
|
||||
rect 565 6192 73246 6728
|
||||
rect 565 5912 73166 6192
|
||||
rect 565 5376 73246 5912
|
||||
rect 880 5096 73246 5376
|
||||
rect 800 4560 73246 5096
|
||||
rect 800 4280 73166 4560
|
||||
rect 800 3744 73246 4280
|
||||
rect 565 4560 73246 5096
|
||||
rect 565 4280 73166 4560
|
||||
rect 565 3744 73246 4280
|
||||
rect 880 3464 73246 3744
|
||||
rect 800 2928 73246 3464
|
||||
rect 800 2648 73166 2928
|
||||
rect 800 2112 73246 2648
|
||||
rect 565 2928 73246 3464
|
||||
rect 565 2648 73166 2928
|
||||
rect 565 2112 73246 2648
|
||||
rect 880 1939 73246 2112
|
||||
<< metal4 >>
|
||||
rect 4208 2128 4528 107760
|
||||
|
@ -855,13 +855,13 @@ rect 35588 2128 35908 107760
|
|||
rect 65648 2128 65968 107760
|
||||
rect 66308 2128 66628 107760
|
||||
<< obsm4 >>
|
||||
rect 1163 2347 4128 107269
|
||||
rect 4608 2347 4788 107269
|
||||
rect 5268 2347 34848 107269
|
||||
rect 35328 2347 35508 107269
|
||||
rect 35988 2347 65568 107269
|
||||
rect 66048 2347 66228 107269
|
||||
rect 66708 2347 71149 107269
|
||||
rect 1899 2483 4128 106317
|
||||
rect 4608 2483 4788 106317
|
||||
rect 5268 2483 34848 106317
|
||||
rect 35328 2483 35508 106317
|
||||
rect 35988 2483 65568 106317
|
||||
rect 66048 2483 66228 106317
|
||||
rect 66708 2483 71701 106317
|
||||
<< metal5 >>
|
||||
rect 1056 97206 72912 97526
|
||||
rect 1056 81888 72912 82208
|
||||
|
@ -870,8 +870,6 @@ rect 1056 51252 72912 51572
|
|||
rect 1056 35934 72912 36254
|
||||
rect 1056 20616 72912 20936
|
||||
rect 1056 5298 72912 5618
|
||||
<< obsm5 >>
|
||||
rect 10420 9020 18468 9340
|
||||
<< labels >>
|
||||
rlabel metal4 s 4868 2128 5188 107760 6 VGND
|
||||
port 1 nsew ground bidirectional
|
||||
|
@ -1607,8 +1605,8 @@ port 354 nsew signal input
|
|||
string FIXED_BBOX 0 0 74046 110190
|
||||
string LEFclass BLOCK
|
||||
string LEFview TRUE
|
||||
string GDS_END 24153662
|
||||
string GDS_FILE /home/hosni/caravel/openlane/housekeeping/runs/22_10_16_03_09/results/signoff/housekeeping.magic.gds
|
||||
string GDS_START 1166508
|
||||
string GDS_END 23070036
|
||||
string GDS_FILE /home/hosni/power/caravel/openlane/housekeeping/runs/22_10_17_11_22/results/signoff/housekeeping.magic.gds
|
||||
string GDS_START 1028052
|
||||
<< end >>
|
||||
|
||||
|
|
|
@ -40,6 +40,7 @@ set ::env(SYNTH_STRATEGY) "AREA 0"
|
|||
|
||||
set ::env(SYNTH_MAX_FANOUT) 20
|
||||
set ::env(SYNTH_BUFFERING) 0
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
|
||||
|
||||
## Floorplan
|
||||
set ::env(FP_SIZING) absolute
|
||||
|
@ -94,4 +95,5 @@ set ::env(GRT_MAX_DIODE_INS_ITERS) 10
|
|||
# set ::env(CTS_CLK_MAX_WIRE_LENGTH) 120
|
||||
set ::env(CTS_MAX_CAP) 0.25
|
||||
|
||||
set ::env(MAGIC_DEF_LABELS) 0
|
||||
set ::env(MAGIC_DEF_LABELS) 0
|
||||
set ::env(RSZ_DONT_TOUCH_RX) {mgmt_gpio_out_9_prebuff|mgmt_gpio_out\[9\]|mgmt_gpio_out_14_prebuff|mgmt_gpio_out\[14\]|mgmt_gpio_out_15_prebuff|mgmt_gpio_out\[15\]|pad_flash_clk\y|pad_flash_clk_prebuff}
|
|
@ -1,4 +1,5 @@
|
|||
sky130_fd_sc_hd__clkbuf_1
|
||||
sky130_fd_sc_hd__buf_1
|
||||
sky130_fd_sc_hd__clkdlybuf4s15_1
|
||||
sky130_fd_sc_hd__clkdlybuf4s15_2
|
||||
sky130_fd_sc_hd__clkdlybuf4s18_1
|
||||
|
@ -193,3 +194,12 @@ sky130_fd_sc_hd__or4bb_1
|
|||
sky130_fd_sc_hd__xnor2_1
|
||||
sky130_fd_sc_hd__xor2_1
|
||||
sky130_fd_sc_hd__ebufn_2
|
||||
sky130_fd_sc_hd__or4_1
|
||||
sky130_fd_sc_hd__or4_2
|
||||
sky130_fd_sc_hd__or4_4
|
||||
sky130_fd_sc_hd__or4_8
|
||||
sky130_fd_sc_hd__or4_12
|
||||
sky130_fd_sc_hd__or3_2
|
||||
sky130_fd_sc_hd__or3_4
|
||||
sky130_fd_sc_hd__or3_8
|
||||
sky130_fd_sc_hd__or3_12
|
||||
|
|
|
@ -1,2 +1,2 @@
|
|||
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
|
||||
/home/hosni/caravel/openlane/housekeeping,housekeeping,22_10_16_03_09,flow completed,0h10m59s0ms,0h7m14s0ms,-2.0,0.20397821850000003,-1,27.46,1741.04,-1,0,0,0,0,0,0,0,-1,0,-1,-1,557360,64424,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,340531607.0,0.0,58.02,76.87,26.49,60.61,2.55,8363,9422,189,1195,0,0,0,9086,156,1,144,323,4521,44,5,170,942,889,20,388,2646,0,3034,189331.584,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10.0,AREA 0,20,50,1,153.6,153.18,0.31,0.3,sky130_fd_sc_hd,3
|
||||
/home/hosni/power/caravel/openlane/housekeeping,housekeeping,22_10_17_11_22,flow completed,0h9m45s0ms,0h5m58s0ms,-2.0,0.20397821850000003,-1,27.72,1638.61,-1,0,0,0,0,0,0,0,-1,0,-1,-1,529052,61685,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,327868030.0,0.0,55.92,74.15,19.96,60.34,0.07,8367,9426,193,1199,0,0,0,9090,154,1,145,321,4522,44,5,170,942,889,21,388,2646,0,3034,189331.584,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10.0,AREA 0,20,50,1,153.6,153.18,0.31,0.3,sky130_fd_sc_hd,3
|
||||
|
|
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -254,6 +254,10 @@ module housekeeping #(
|
|||
wire cwstb; // Combination of SPI write strobe and back door write strobe
|
||||
wire csclk; // Combination of SPI SCK and back door access trigger
|
||||
|
||||
// Output clock signals buffer wires
|
||||
wire mgmt_gpio_out_9_prebuff, mgmt_gpio_out_14_prebuff, mgmt_gpio_out_15_prebuff, pad_flash_clk_prebuff;
|
||||
|
||||
|
||||
`ifdef USE_SRAM_RO_INTERFACE
|
||||
wire [31:0] sram_ro_data;
|
||||
`endif
|
||||
|
@ -275,7 +279,7 @@ module housekeeping #(
|
|||
|
||||
assign pad_flash_csb = (pass_thru_mgmt_delay) ? mgmt_gpio_in[3] : spimemio_flash_csb;
|
||||
assign pad_flash_csb_oeb = (pass_thru_mgmt_delay) ? 1'b0 : (~porb ? 1'b1 : 1'b0);
|
||||
assign pad_flash_clk = (pass_thru_mgmt) ? mgmt_gpio_in[4] : spimemio_flash_clk;
|
||||
assign pad_flash_clk_prebuff = (pass_thru_mgmt) ? mgmt_gpio_in[4] : spimemio_flash_clk;
|
||||
assign pad_flash_clk_oeb = (pass_thru_mgmt) ? 1'b0 : (~porb ? 1'b1 : 1'b0);
|
||||
assign pad_flash_io0_oeb = (pass_thru_mgmt_delay) ? 1'b0 : spimemio_flash_io0_oeb;
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||||
assign pad_flash_io1_oeb = (pass_thru_mgmt) ? 1'b1 : spimemio_flash_io1_oeb;
|
||||
|
@ -286,6 +290,15 @@ module housekeeping #(
|
|||
assign spimemio_flash_io0_di = (pass_thru_mgmt_delay) ? 1'b0 : pad_flash_io0_di;
|
||||
assign spimemio_flash_io1_di = (pass_thru_mgmt) ? 1'b0 : pad_flash_io1_di;
|
||||
|
||||
(* keep *) sky130_fd_sc_hd__clkbuf_8 pad_flashh_clk_buff_inst (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(VPWR),
|
||||
.VGND(VGND),
|
||||
.VPB(VPWR),
|
||||
.VNB(VGND),
|
||||
`endif
|
||||
.A(pad_flash_clk_prebuff),
|
||||
.X(pad_flash_clk));
|
||||
|
||||
wire [11:0] mfgr_id;
|
||||
wire [7:0] prod_id;
|
||||
|
@ -800,8 +813,19 @@ module housekeeping #(
|
|||
|
||||
assign mgmt_gpio_out[10] = (pass_thru_user_delay) ? mgmt_gpio_in[2]
|
||||
: mgmt_gpio_data[10];
|
||||
assign mgmt_gpio_out[9] = (pass_thru_user) ? mgmt_gpio_in[4]
|
||||
assign mgmt_gpio_out_9_prebuff = (pass_thru_user) ? mgmt_gpio_in[4]
|
||||
: mgmt_gpio_data[9];
|
||||
|
||||
(* keep *) sky130_fd_sc_hd__clkbuf_8 mgmt_gpio_9_buff_inst (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(VPWR),
|
||||
.VGND(VGND),
|
||||
.VPB(VPWR),
|
||||
.VNB(VGND),
|
||||
`endif
|
||||
.A(mgmt_gpio_out_9_prebuff),
|
||||
.X(mgmt_gpio_out[9]));
|
||||
|
||||
assign mgmt_gpio_out[8] = (pass_thru_user_delay) ? mgmt_gpio_in[3]
|
||||
: mgmt_gpio_data[8];
|
||||
|
||||
|
@ -840,10 +864,32 @@ module housekeeping #(
|
|||
// so the pad being under control of the user area takes precedence
|
||||
// over the system monitoring function.
|
||||
|
||||
assign mgmt_gpio_out[15] = (clk2_output_dest == 1'b1) ? user_clock
|
||||
assign mgmt_gpio_out_15_prebuff = (clk2_output_dest == 1'b1) ? user_clock
|
||||
: mgmt_gpio_data[15];
|
||||
assign mgmt_gpio_out[14] = (clk1_output_dest == 1'b1) ? wb_clk_i
|
||||
|
||||
(* keep *) sky130_fd_sc_hd__clkbuf_8 mgmt_gpio_15_buff_inst (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(VPWR),
|
||||
.VGND(VGND),
|
||||
.VPB(VPWR),
|
||||
.VNB(VGND),
|
||||
`endif
|
||||
.A(mgmt_gpio_out_15_prebuff),
|
||||
.X(mgmt_gpio_out[15]));
|
||||
|
||||
assign mgmt_gpio_out_14_prebuff = (clk1_output_dest == 1'b1) ? wb_clk_i
|
||||
: mgmt_gpio_data[14];
|
||||
|
||||
(* keep *) sky130_fd_sc_hd__clkbuf_8 mgmt_gpio_14_buff_inst (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(VPWR),
|
||||
.VGND(VGND),
|
||||
.VPB(VPWR),
|
||||
.VNB(VGND),
|
||||
`endif
|
||||
.A(mgmt_gpio_out_14_prebuff),
|
||||
.X(mgmt_gpio_out[14]));
|
||||
|
||||
assign mgmt_gpio_out[13] = (trap_output_dest == 1'b1) ? trap
|
||||
: mgmt_gpio_data[13];
|
||||
|
||||
|
|
Loading…
Reference in New Issue