[DATA] Update caravel_clocking module

lef/caravel_clocking.lef

@@ -213,35 +213,34 @@ MACRO caravel_clocking
         RECT 5.215 -0.050 5.375 0.060 ;
         RECT 6.585 -0.085 6.755 0.085 ;
         RECT 12.565 -0.085 12.735 0.085 ;
-        RECT 16.700 -0.085 16.870 0.085 ;
-        RECT 17.175 -0.050 17.335 0.060 ;
-        RECT 19.470 -0.085 19.640 0.085 ;
-        RECT 19.925 -0.085 20.095 0.085 ;
-        RECT 23.600 -0.055 23.720 0.055 ;
+        RECT 18.545 -0.085 18.715 0.085 ;
         RECT 24.525 -0.085 24.695 0.085 ;
-        RECT 26.365 -0.085 26.535 0.085 ;
-        RECT 29.580 -0.055 29.700 0.055 ;
-        RECT 30.780 -0.085 30.950 0.085 ;
-        RECT 34.645 -0.085 34.815 0.085 ;
+        RECT 26.360 -0.055 26.480 0.055 ;
+        RECT 29.585 -0.085 29.755 0.085 ;
+        RECT 30.500 -0.085 30.670 0.085 ;
+        RECT 31.885 -0.085 32.055 0.085 ;
+        RECT 35.560 -0.055 35.680 0.055 ;
         RECT 36.485 -0.085 36.655 0.085 ;
-        RECT 45.685 -0.085 45.855 0.085 ;
-        RECT 46.145 -0.085 46.315 0.085 ;
+        RECT 42.465 -0.085 42.635 0.085 ;
+        RECT 45.220 -0.055 45.340 0.055 ;
+        RECT 47.060 -0.085 47.230 0.085 ;
+        RECT 47.520 -0.055 47.640 0.055 ;
         RECT 48.445 -0.085 48.615 0.085 ;
-        RECT 50.285 -0.085 50.455 0.085 ;
-        RECT 53.500 -0.055 53.620 0.055 ;
         RECT 54.425 -0.085 54.595 0.085 ;
-        RECT 60.400 -0.055 60.520 0.055 ;
-        RECT 60.865 -0.085 61.035 0.085 ;
-        RECT 64.545 -0.085 64.715 0.085 ;
-        RECT 66.385 -0.085 66.555 0.085 ;
-        RECT 72.375 -0.050 72.535 0.060 ;
-        RECT 75.585 -0.085 75.755 0.085 ;
-        RECT 76.045 -0.085 76.215 0.085 ;
-        RECT 78.345 -0.085 78.515 0.085 ;
+        RECT 61.780 -0.085 61.950 0.085 ;
+        RECT 62.245 -0.085 62.415 0.085 ;
+        RECT 67.300 -0.085 67.470 0.085 ;
+        RECT 67.770 -0.085 67.940 0.085 ;
+        RECT 69.145 -0.085 69.315 0.085 ;
+        RECT 72.365 -0.085 72.535 0.085 ;
+        RECT 78.805 -0.085 78.975 0.085 ;
+        RECT 79.260 -0.085 79.430 0.085 ;
+        RECT 82.485 -0.085 82.655 0.085 ;
+        RECT 82.955 -0.050 83.115 0.060 ;
         RECT 84.325 -0.085 84.495 0.085 ;
-        RECT 86.170 -0.085 86.340 0.085 ;
-        RECT 88.935 -0.050 89.095 0.060 ;
-        RECT 90.310 -0.085 90.480 0.085 ;
+        RECT 87.545 -0.085 87.715 0.085 ;
+        RECT 89.380 -0.055 89.500 0.055 ;
+        RECT 90.305 -0.085 90.475 0.085 ;
         RECT 93.985 -0.085 94.155 0.085 ;
       LAYER li1 ;
         RECT 0.000 0.085 94.300 54.485 ;
@@ -265,22 +264,22 @@ MACRO caravel_clocking
         RECT 69.800 -0.240 71.340 0.000 ;
         RECT 85.300 -0.240 86.840 0.000 ;
       LAYER met3 ;
-        RECT 12.025 55.400 95.600 56.265 ;
-        RECT 12.025 49.320 96.000 55.400 ;
-        RECT 12.025 47.920 95.600 49.320 ;
-        RECT 12.025 41.840 96.000 47.920 ;
-        RECT 12.025 40.440 95.600 41.840 ;
-        RECT 12.025 34.360 96.000 40.440 ;
-        RECT 12.025 32.960 95.600 34.360 ;
-        RECT 12.025 26.880 96.000 32.960 ;
-        RECT 12.025 25.480 95.600 26.880 ;
-        RECT 12.025 19.400 96.000 25.480 ;
-        RECT 12.025 18.000 95.600 19.400 ;
-        RECT 12.025 11.920 96.000 18.000 ;
-        RECT 12.025 10.520 95.600 11.920 ;
-        RECT 12.025 4.440 96.000 10.520 ;
-        RECT 12.025 3.040 95.600 4.440 ;
-        RECT 12.025 0.000 96.000 3.040 ;
+        RECT 12.485 55.400 95.600 56.265 ;
+        RECT 12.485 49.320 96.000 55.400 ;
+        RECT 12.485 47.920 95.600 49.320 ;
+        RECT 12.485 41.840 96.000 47.920 ;
+        RECT 12.485 40.440 95.600 41.840 ;
+        RECT 12.485 34.360 96.000 40.440 ;
+        RECT 12.485 32.960 95.600 34.360 ;
+        RECT 12.485 26.880 96.000 32.960 ;
+        RECT 12.485 25.480 95.600 26.880 ;
+        RECT 12.485 19.400 96.000 25.480 ;
+        RECT 12.485 18.000 95.600 19.400 ;
+        RECT 12.485 11.920 96.000 18.000 ;
+        RECT 12.485 10.520 95.600 11.920 ;
+        RECT 12.485 4.440 96.000 10.520 ;
+        RECT 12.485 3.040 95.600 4.440 ;
+        RECT 12.485 0.000 96.000 3.040 ;
         RECT 23.270 -0.165 24.870 0.000 ;
         RECT 38.770 -0.165 40.370 0.000 ;
         RECT 54.270 -0.165 55.870 0.000 ;

maglef/caravel_clocking.mag

@@ -1,7 +1,7 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1638477074
+timestamp 1638662846
 << nwell >>
 rect -38 10053 18898 10619
 rect -38 8965 18898 9531
@@ -19,35 +19,34 @@ rect 305 -17 339 17
 rect 1043 -10 1075 12
 rect 1317 -17 1351 17
 rect 2513 -17 2547 17
-rect 3340 -17 3374 17
-rect 3435 -10 3467 12
-rect 3894 -17 3928 17
-rect 3985 -17 4019 17
-rect 4720 -11 4744 11
+rect 3709 -17 3743 17
 rect 4905 -17 4939 17
-rect 5273 -17 5307 17
-rect 5916 -11 5940 11
-rect 6156 -17 6190 17
-rect 6929 -17 6963 17
+rect 5272 -11 5296 11
+rect 5917 -17 5951 17
+rect 6100 -17 6134 17
+rect 6377 -17 6411 17
+rect 7112 -11 7136 11
 rect 7297 -17 7331 17
-rect 9137 -17 9171 17
-rect 9229 -17 9263 17
+rect 8493 -17 8527 17
+rect 9044 -11 9068 11
+rect 9412 -17 9446 17
+rect 9504 -11 9528 11
 rect 9689 -17 9723 17
-rect 10057 -17 10091 17
-rect 10700 -11 10724 11
 rect 10885 -17 10919 17
-rect 12080 -11 12104 11
-rect 12173 -17 12207 17
-rect 12909 -17 12943 17
-rect 13277 -17 13311 17
-rect 14475 -10 14507 12
-rect 15117 -17 15151 17
-rect 15209 -17 15243 17
-rect 15669 -17 15703 17
+rect 12356 -17 12390 17
+rect 12449 -17 12483 17
+rect 13460 -17 13494 17
+rect 13554 -17 13588 17
+rect 13829 -17 13863 17
+rect 14473 -17 14507 17
+rect 15761 -17 15795 17
+rect 15852 -17 15886 17
+rect 16497 -17 16531 17
+rect 16591 -10 16623 12
 rect 16865 -17 16899 17
-rect 17234 -17 17268 17
-rect 17787 -10 17819 12
-rect 18062 -17 18096 17
+rect 17509 -17 17543 17
+rect 17876 -11 17900 11
+rect 18061 -17 18095 17
 rect 18797 -17 18831 17
 << obsli1 >>
 rect 0 -17 18860 10897
@@ -86,22 +85,22 @@ rect 19200 3680 20000 3800
 rect 19200 2184 20000 2304
 rect 19200 688 20000 808
 << obsm3 >>
-rect 2405 11080 19120 11253
-rect 2405 9864 19200 11080
-rect 2405 9584 19120 9864
-rect 2405 8368 19200 9584
-rect 2405 8088 19120 8368
-rect 2405 6872 19200 8088
-rect 2405 6592 19120 6872
-rect 2405 5376 19200 6592
-rect 2405 5096 19120 5376
-rect 2405 3880 19200 5096
-rect 2405 3600 19120 3880
-rect 2405 2384 19200 3600
-rect 2405 2104 19120 2384
-rect 2405 888 19200 2104
-rect 2405 608 19120 888
-rect 2405 0 19200 608
+rect 2497 11080 19120 11253
+rect 2497 9864 19200 11080
+rect 2497 9584 19120 9864
+rect 2497 8368 19200 9584
+rect 2497 8088 19120 8368
+rect 2497 6872 19200 8088
+rect 2497 6592 19120 6872
+rect 2497 5376 19200 6592
+rect 2497 5096 19120 5376
+rect 2497 3880 19200 5096
+rect 2497 3600 19120 3880
+rect 2497 2384 19200 3600
+rect 2497 2104 19120 2384
+rect 2497 888 19200 2104
+rect 2497 608 19120 888
+rect 2497 0 19200 608
 rect 4654 -33 4974 0
 rect 7754 -33 8074 0
 rect 10854 -33 11174 0
@@ -190,7 +189,7 @@ string LEFclass BLOCK
 string FIXED_BBOX 0 0 20000 12000
 string LEFview TRUE
 string GDS_FILE ../gds/caravel_clocking.gds
-string GDS_END 1127518
-string GDS_START 370986
+string GDS_END 1197054
+string GDS_START 422960
 << end >>
 

openlane/caravel_clocking/base.sdc

@@ -5,20 +5,20 @@ create_clock [get_ports {"pll_clk90"} ] -name "pll_clk90"  -period 6.66666666666
 
 ## GENERATED CLOCKS
 # divided PLL clocks
-create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _357_/Y] 
-create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _360_/Y] 
+create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _351_/Y] 
+create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _354_/Y] 
 
 #  assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
-create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _418_/X] 
-create_generated_clock -name core_ext_clk_syncd -source [get_pins _432_/Q] -divide_by 1 [get_pins _418_/X] 
+create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _343_/X] 
+create_generated_clock -name core_ext_clk_syncd -source [get_pins _420_/Q] -divide_by 1 [get_pins _343_/X] 
 
 # assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
-create_generated_clock -name core_clk -source [get_pins _418_/X]  -divide_by 1 [get_pins _399_/X] 
-create_generated_clock -name core_clk_pll -source [get_pins _357_/Y]   -divide_by 1 [get_pins _399_/X] 
+create_generated_clock -name core_clk -source [get_pins _343_/X]  -divide_by 1 [get_ports core_clk] 
+create_generated_clock -name core_clk_pll -source [get_pins _351_/Y]   -divide_by 1 [get_ports core_clk] 
 
 # assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk;
-create_generated_clock -name user_clk -source [get_pins _418_/X]  -divide_by 1 [get_pins _400_/X] 
-create_generated_clock -name user_clk_pll -source [get_pins _360_/Y]   -divide_by 1 [get_pins _400_/X] 
+create_generated_clock -name user_clk -source [get_pins _343_/X]  -divide_by 1 [get_ports user_clk] 
+create_generated_clock -name user_clk_pll -source [get_pins _354_/Y]   -divide_by 1 [get_ports user_clk]  
 
 # logically exclusive clocks, the generated pll clocks and the ext core clk
 set_clock_groups -logically_exclusive -group core_ext_clk -group core_ext_clk_syncd

openlane/caravel_clocking/config.tcl

@@ -56,10 +56,11 @@ set ::env(FP_PDN_HPITCH) 16.9
 set ::env(FP_PDN_VPITCH) 15.5
 
 ## Placement
-set ::env(PL_TARGET_DENSITY) 0.70
+set ::env(PL_TARGET_DENSITY) 0.715
 
 set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
 set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
+set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.25
 
 ## Routing
 set ::env(GLB_RT_ADJUSTMENT) 0

openlane/caravel_clocking/no_synth.list

@@ -1,3 +1,4 @@
+sky130_fd_sc_hd__inv_2
 sky130_fd_sc_hd__clkbuf_1
 sky130_fd_sc_hd__clkbuf_16
 sky130_fd_sc_hd__clkbuf_2

sdc/caravel_clocking.sdc

@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Thu Dec  2 20:30:29 2021
+# Sun Dec  5 00:06:34 2021
 ###############################################################################
 current_design caravel_clocking
 ###############################################################################
@@ -18,15 +18,15 @@ create_clock -name pll_clk90 -period 6.6667 [get_ports {pll_clk90}]
 set_clock_transition 0.1500 [get_clocks {pll_clk90}]
 set_clock_uncertainty 0.2500 pll_clk90
 set_propagated_clock [get_clocks {pll_clk90}]
-create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_357_/Y}]
+create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_351_/Y}]
 set_propagated_clock [get_clocks {pll_clk_divided}]
-create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_360_/Y}]
+create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_354_/Y}]
 set_propagated_clock [get_clocks {pll_clk90_divided}]
-create_generated_clock -name core_ext_clk_syncd -source [get_pins {_432_/Q}] -divide_by 1 [get_pins {_418_/X}]
+create_generated_clock -name core_ext_clk_syncd -source [get_pins {_420_/Q}] -divide_by 1 [get_pins {_343_/X}]
 set_propagated_clock [get_clocks {core_ext_clk_syncd}]
-create_generated_clock -name core_clk_pll -source [get_pins {_357_/Y}] -divide_by 1 [get_pins {_399_/X}]
+create_generated_clock -name core_clk_pll -source [get_pins {_351_/Y}] -divide_by 1 [get_ports {core_clk}]
 set_propagated_clock [get_clocks {core_clk_pll}]
-create_generated_clock -name user_clk_pll -source [get_pins {_360_/Y}] -divide_by 1 [get_pins {_400_/X}]
+create_generated_clock -name user_clk_pll -source [get_pins {_354_/Y}] -divide_by 1 [get_ports {user_clk}]
 set_propagated_clock [get_clocks {user_clk_pll}]
 set_clock_groups -name group1 -logically_exclusive \
  -group [get_clocks {core_ext_clk_syncd}]

signoff/caravel_clocking/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 2021.11.23_01.42.34-9-gc3ec957
+openlane 2021.11.23_01.42.34-10-g445acc6

signoff/caravel_clocking/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow completed,0h1m51s0ms,0h1m36s0ms,90000.0,0.006,45000.0,68.96,668.83,270,0,0,0,0,0,0,0,0,0,0,-1,5326,1956,0.0,0.0,-1,-0.06,-1,0.0,0.0,-1,-0.15,-1,3312107.0,0.0,31.15,16.61,4.43,0.0,0.0,202,252,67,117,0,0,0,200,0,0,0,0,0,0,0,4,73,74,6,40,165,0,205,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.7,0,sky130_fd_sc_hd,0,4
+0,/home/ma/ef/caravel_openframe/openlane/caravel_clocking,caravel_clocking,caravel_clocking,flow completed,0h2m8s0ms,0h1m50s0ms,89000.0,0.006,44500.0,70.54,647.01,267,0,0,0,0,0,0,0,0,0,0,-1,5503,2015,0.0,0.0,-1,-0.11,-1,0.0,0.0,-1,-0.34,-1,3392030.0,0.0,32.92,17.74,4.07,0.0,0.0,202,252,67,117,0,0,0,200,0,3,4,15,20,14,10,35,73,74,5,40,165,0,205,90.9090909090909,11.0,10.0,DELAY 0,5,50,1,15.5,16.9,0.715,0,sky130_fd_sc_hd,0,4