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Merge pull request #214 from efabless/caravel_clocking-buffering 

Caravel clocking reharden
This commit is contained in:
Marwan Abbas 2022-10-13 20:13:45 +02:00 committed by GitHub
parent 3fa5ffb084 c7421fc1e0
commit 08ac55bed8
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GPG Key ID: 4AEE18F83AFDEB23
77 changed files with 204047 additions and 61508 deletions
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13896
def/caravel_clocking.def
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gds/caravel_clocking.gds.gz
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215
lef/caravel_clocking.lef
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@ -8,71 +8,75 @@ MACRO caravel_clocking
ORIGIN 0.000 0.000 ;
SIZE 100.000 BY 60.000 ;
PIN VGND
DIRECTION INPUT ;
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER met5 ;
RECT 0.000 24.060 94.300 25.660 ;
LAYER met4 ;
RECT 23.270 2.480 24.870 54.640 ;
END
PORT
LAYER met4 ;
RECT 38.770 2.480 40.370 54.640 ;
END
PORT
LAYER met4 ;
RECT 54.270 2.480 55.870 54.640 ;
END
PORT
LAYER met4 ;
RECT 69.770 2.480 71.370 54.640 ;
END
PORT
LAYER met4 ;
RECT 85.270 2.480 86.870 54.640 ;
END
PORT
LAYER met5 ;
RECT 0.000 40.960 94.300 42.560 ;
RECT 0.680 21.340 94.540 22.940 ;
END
PORT
LAYER met4 ;
RECT 23.270 -0.240 24.870 54.640 ;
END
PORT
LAYER met4 ;
RECT 38.770 -0.240 40.370 54.640 ;
END
PORT
LAYER met4 ;
RECT 54.270 -0.240 55.870 54.640 ;
END
PORT
LAYER met4 ;
RECT 69.770 -0.240 71.370 54.640 ;
END
PORT
LAYER met4 ;
RECT 85.270 -0.240 86.870 54.640 ;
LAYER met5 ;
RECT 0.680 38.240 94.540 39.840 ;
END
END VGND
PIN VPWR
DIRECTION INPUT ;
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER met5 ;
RECT 0.000 15.610 94.300 17.210 ;
LAYER met4 ;
RECT 15.520 2.480 17.120 54.640 ;
END
PORT
LAYER met4 ;
RECT 31.020 2.480 32.620 54.640 ;
END
PORT
LAYER met4 ;
RECT 46.520 2.480 48.120 54.640 ;
END
PORT
LAYER met4 ;
RECT 62.020 2.480 63.620 54.640 ;
END
PORT
LAYER met4 ;
RECT 77.520 2.480 79.120 54.640 ;
END
PORT
LAYER met4 ;
RECT 93.020 2.480 94.620 54.640 ;
END
PORT
LAYER met5 ;
RECT 0.000 32.510 94.300 34.110 ;
RECT 0.680 12.890 94.620 14.490 ;
END
PORT
LAYER met5 ;
RECT 0.000 49.410 94.300 51.010 ;
RECT 0.680 29.790 94.620 31.390 ;
END
PORT
LAYER met4 ;
RECT 15.520 -0.240 17.120 54.640 ;
END
PORT
LAYER met4 ;
RECT 31.020 -0.240 32.620 54.640 ;
END
PORT
LAYER met4 ;
RECT 46.520 -0.240 48.120 54.640 ;
END
PORT
LAYER met4 ;
RECT 62.020 -0.240 63.620 54.640 ;
END
PORT
LAYER met4 ;
RECT 77.520 -0.240 79.120 54.640 ;
LAYER met5 ;
RECT 0.680 46.690 94.620 48.290 ;
END
END VPWR
PIN core_clk
@ -196,100 +200,41 @@ MACRO caravel_clocking
END
END user_clk
OBS
LAYER nwell ;
RECT -0.190 50.265 94.490 53.095 ;
RECT -0.190 44.825 94.490 47.655 ;
RECT -0.190 39.385 94.490 42.215 ;
RECT -0.190 33.945 94.490 36.775 ;
RECT -0.190 28.505 94.490 31.335 ;
RECT -0.190 23.065 94.490 25.895 ;
RECT -0.190 17.625 94.490 20.455 ;
RECT -0.190 12.185 94.490 15.015 ;
RECT -0.190 6.745 94.490 9.575 ;
RECT -0.190 1.305 94.490 4.135 ;
LAYER pwell ;
RECT 0.145 -0.085 0.315 0.085 ;
RECT 1.525 -0.085 1.695 0.085 ;
RECT 5.215 -0.050 5.375 0.060 ;
RECT 6.585 -0.085 6.755 0.085 ;
RECT 7.965 -0.085 8.135 0.085 ;
RECT 11.640 -0.055 11.760 0.055 ;
RECT 13.025 -0.085 13.195 0.085 ;
RECT 13.485 -0.085 13.655 0.085 ;
RECT 14.865 -0.085 15.035 0.085 ;
RECT 18.545 -0.085 18.715 0.085 ;
RECT 27.745 -0.085 27.915 0.085 ;
RECT 28.205 -0.085 28.375 0.085 ;
RECT 30.505 -0.085 30.675 0.085 ;
RECT 32.160 -0.085 32.330 0.085 ;
RECT 36.485 -0.085 36.655 0.085 ;
RECT 37.865 -0.085 38.035 0.085 ;
RECT 38.325 -0.085 38.495 0.085 ;
RECT 42.740 -0.085 42.910 0.085 ;
RECT 46.605 -0.085 46.775 0.085 ;
RECT 48.445 -0.085 48.615 0.085 ;
RECT 52.120 -0.055 52.240 0.055 ;
RECT 53.510 -0.085 53.680 0.085 ;
RECT 55.800 -0.085 55.970 0.085 ;
RECT 56.265 -0.085 56.435 0.085 ;
RECT 60.400 -0.055 60.520 0.055 ;
RECT 60.865 -0.085 61.035 0.085 ;
RECT 65.000 -0.085 65.170 0.085 ;
RECT 65.460 -0.055 65.580 0.055 ;
RECT 66.385 -0.085 66.555 0.085 ;
RECT 72.360 -0.055 72.480 0.055 ;
RECT 72.825 -0.085 72.995 0.085 ;
RECT 76.045 -0.085 76.215 0.085 ;
RECT 78.345 -0.085 78.515 0.085 ;
RECT 85.250 -0.085 85.420 0.085 ;
RECT 86.625 -0.085 86.795 0.085 ;
RECT 87.085 -0.085 87.255 0.085 ;
RECT 90.305 -0.085 90.475 0.085 ;
RECT 92.605 -0.085 92.775 0.085 ;
RECT 93.985 -0.085 94.155 0.085 ;
LAYER li1 ;
RECT 0.000 0.085 94.300 54.485 ;
LAYER li1 ;
RECT 0.000 -0.085 94.300 0.085 ;
RECT 0.920 2.635 94.300 54.485 ;
LAYER met1 ;
RECT 0.000 -0.240 94.300 54.640 ;
RECT 0.920 0.380 96.070 57.080 ;
LAYER met2 ;
RECT 1.480 55.720 6.710 56.285 ;
RECT 7.550 55.720 20.970 56.285 ;
RECT 21.810 55.720 35.230 56.285 ;
RECT 36.070 55.720 49.490 56.285 ;
RECT 50.330 55.720 63.750 56.285 ;
RECT 64.590 55.720 78.010 56.285 ;
RECT 78.850 55.720 92.270 56.285 ;
RECT 93.110 55.720 94.210 56.285 ;
RECT 1.480 0.000 94.210 55.720 ;
RECT 23.300 -0.240 24.840 0.000 ;
RECT 38.800 -0.240 40.340 0.000 ;
RECT 54.300 -0.240 55.840 0.000 ;
RECT 69.800 -0.240 71.340 0.000 ;
RECT 85.300 -0.240 86.840 0.000 ;
RECT 2.400 55.720 6.710 57.110 ;
RECT 7.550 55.720 20.970 57.110 ;
RECT 21.810 55.720 35.230 57.110 ;
RECT 36.070 55.720 49.490 57.110 ;
RECT 50.330 55.720 63.750 57.110 ;
RECT 64.590 55.720 78.010 57.110 ;
RECT 78.850 55.720 92.270 57.110 ;
RECT 93.110 55.720 96.040 57.110 ;
RECT 2.400 0.350 96.040 55.720 ;
LAYER met3 ;
RECT 15.520 55.400 95.600 56.265 ;
RECT 15.520 49.320 96.000 55.400 ;
RECT 15.520 47.920 95.600 49.320 ;
RECT 15.520 41.840 96.000 47.920 ;
RECT 15.520 40.440 95.600 41.840 ;
RECT 15.520 34.360 96.000 40.440 ;
RECT 15.520 32.960 95.600 34.360 ;
RECT 15.520 26.880 96.000 32.960 ;
RECT 15.520 25.480 95.600 26.880 ;
RECT 15.520 19.400 96.000 25.480 ;
RECT 15.520 18.000 95.600 19.400 ;
RECT 15.520 11.920 96.000 18.000 ;
RECT 15.520 10.520 95.600 11.920 ;
RECT 15.520 4.440 96.000 10.520 ;
RECT 15.520 3.040 95.600 4.440 ;
RECT 15.520 0.000 96.000 3.040 ;
RECT 23.270 -0.165 24.870 0.000 ;
RECT 38.770 -0.165 40.370 0.000 ;
RECT 54.270 -0.165 55.870 0.000 ;
RECT 69.770 -0.165 71.370 0.000 ;
RECT 85.270 -0.165 86.870 0.000 ;
RECT 2.825 55.400 95.600 56.250 ;
RECT 2.825 49.320 96.000 55.400 ;
RECT 2.825 47.920 95.600 49.320 ;
RECT 2.825 41.840 96.000 47.920 ;
RECT 2.825 40.440 95.600 41.840 ;
RECT 2.825 34.360 96.000 40.440 ;
RECT 2.825 32.960 95.600 34.360 ;
RECT 2.825 26.880 96.000 32.960 ;
RECT 2.825 25.480 95.600 26.880 ;
RECT 2.825 19.400 96.000 25.480 ;
RECT 2.825 18.000 95.600 19.400 ;
RECT 2.825 11.920 96.000 18.000 ;
RECT 2.825 10.520 95.600 11.920 ;
RECT 2.825 4.440 96.000 10.520 ;
RECT 2.825 3.040 95.600 4.440 ;
RECT 2.825 2.555 96.000 3.040 ;
LAYER met4 ;
RECT 72.055 4.935 77.120 42.665 ;
RECT 79.520 4.935 84.870 42.665 ;
RECT 87.270 4.935 88.025 42.665 ;
END
END caravel_clocking
END LIBRARY

513
lib/caravel_clocking.lib Normal file
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@ -0,0 +1,513 @@
library (caravel_clocking) {
comment : "";
delay_model : table_lookup;
simulation : false;
capacitive_load_unit (1,pF);
leakage_power_unit : 1pW;
current_unit : "1A";
pulling_resistance_unit : "1kohm";
time_unit : "1ns";
voltage_unit : "1v";
library_features(report_delay_calculation);
input_threshold_pct_rise : 50;
input_threshold_pct_fall : 50;
output_threshold_pct_rise : 50;
output_threshold_pct_fall : 50;
slew_lower_threshold_pct_rise : 20;
slew_lower_threshold_pct_fall : 20;
slew_upper_threshold_pct_rise : 80;
slew_upper_threshold_pct_fall : 80;
slew_derate_from_library : 1.0;
nom_process : 1.0;
nom_temperature : 25.0;
nom_voltage : 1.80;
lu_table_template(template_1) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00232, 0.01077, 0.05000, 0.23208, 1.07722, 5.00000");
}
lu_table_template(template_10) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_11) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00232, 0.01077, 0.05000, 0.23208, 1.07722, 5.00000");
}
lu_table_template(template_12) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00232, 0.01077, 0.05000, 0.23208, 1.07722, 5.00000");
}
lu_table_template(template_13) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_14) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_15) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_16) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_17) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_18) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_19) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_2) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00232, 0.01077, 0.05000, 0.23208, 1.07722, 5.00000");
}
lu_table_template(template_20) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_21) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_22) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_3) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_4) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_5) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_6) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_7) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_8) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
lu_table_template(template_9) {
variable_1 : total_output_net_capacitance;
index_1 ("0.00050, 0.00191, 0.00726, 0.02767, 0.10546, 0.40192, 1.53169");
}
type ("sel") {
base_type : array;
data_type : bit;
bit_width : 3;
bit_from : 2;
bit_to : 0;
}
type ("sel2") {
base_type : array;
data_type : bit;
bit_width : 3;
bit_from : 2;
bit_to : 0;
}
cell ("caravel_clocking") {
pin("core_clk") {
direction : output;
capacitance : 0.2094;
timing() {
related_pin : "ext_clk";
timing_type : rising_edge;
cell_rise(template_3) {
values("1.77221,1.77409,1.78052,1.80015,1.85837,2.06019,2.82071");
}
rise_transition(template_3) {
values("0.02434,0.02582,0.03117,0.05049,0.12301,0.40937,1.50421");
}
cell_fall(template_4) {
values("0.85618,0.85790,0.86375,0.88030,0.92361,1.05078,1.51223");
}
fall_transition(template_4) {
values("0.02326,0.02436,0.02827,0.04095,0.08430,0.25146,0.91403");
}
}
timing() {
related_pin : "ext_clk";
timing_type : falling_edge;
cell_rise(template_5) {
values("-2.16414,-2.16227,-2.15583,-2.13620,-2.07798,-1.87616,-1.11564");
}
rise_transition(template_5) {
values("0.02434,0.02582,0.03117,0.05049,0.12301,0.40937,1.50421");
}
cell_fall(template_6) {
values("3.08430,3.08602,3.09188,3.10842,3.15174,3.27890,3.74035");
}
fall_transition(template_6) {
values("0.02326,0.02436,0.02827,0.04095,0.08430,0.25146,0.91403");
}
}
timing() {
related_pin : "core_clk";
timing_type : rising_edge;
cell_rise(template_7) {
values("1.77221,1.77409,1.78052,1.80015,1.85837,2.06019,2.82071");
}
rise_transition(template_7) {
values("0.02434,0.02582,0.03117,0.05049,0.12301,0.40937,1.50421");
}
cell_fall(template_8) {
values("-0.11202,-0.11030,-0.10445,-0.08790,-0.04459,0.08258,0.54403");
}
fall_transition(template_8) {
values("0.02326,0.02436,0.02827,0.04095,0.08430,0.25146,0.91403");
}
}
timing() {
related_pin : "core_clk";
timing_type : falling_edge;
cell_rise(template_9) {
values("-0.15692,-0.15505,-0.14862,-0.12898,-0.07076,0.13106,0.89158");
}
rise_transition(template_9) {
values("0.02434,0.02582,0.03117,0.05049,0.12301,0.40937,1.50421");
}
cell_fall(template_10) {
values("15.58430,15.58602,15.59188,15.60842,15.65173,15.77890,16.24035");
}
fall_transition(template_10) {
values("0.02326,0.02436,0.02827,0.04095,0.08430,0.25146,0.91403");
}
}
}
pin("ext_clk") {
direction : input;
capacitance : 0.0112;
}
pin("ext_clk_sel") {
direction : input;
capacitance : 0.0105;
timing() {
related_pin : "pll_clk";
timing_type : hold_rising;
rise_constraint(scalar) {
values("0.49684");
}
fall_constraint(scalar) {
values("-0.20537");
}
}
timing() {
related_pin : "pll_clk";
timing_type : setup_rising;
rise_constraint(scalar) {
values("-0.31427");
}
fall_constraint(scalar) {
values("0.41908");
}
}
}
pin("ext_reset") {
direction : input;
capacitance : 0.0201;
timing() {
related_pin : "ext_clk";
timing_type : hold_rising;
rise_constraint(scalar) {
values("-5.57870");
}
fall_constraint(scalar) {
values("-6.49938");
}
}
timing() {
related_pin : "ext_clk";
timing_type : setup_rising;
rise_constraint(scalar) {
values("5.64693");
}
fall_constraint(scalar) {
values("6.65725");
}
}
}
pin("pll_clk") {
direction : input;
capacitance : 0.0172;
}
pin("pll_clk90") {
direction : input;
capacitance : 0.0188;
}
pin("resetb") {
direction : input;
capacitance : 0.0094;
timing() {
related_pin : "ext_clk";
timing_sense : negative_unate;
timing_type : hold_falling;
rise_constraint(scalar) {
values("2.90140");
}
}
timing() {
related_pin : "ext_clk";
timing_sense : negative_unate;
timing_type : setup_falling;
rise_constraint(scalar) {
values("-2.00722");
}
}
timing() {
related_pin : "pll_clk";
timing_type : hold_rising;
rise_constraint(scalar) {
values("0.72445");
}
fall_constraint(scalar) {
values("-0.54299");
}
}
timing() {
related_pin : "pll_clk";
timing_type : setup_rising;
rise_constraint(scalar) {
values("0.25961");
}
fall_constraint(scalar) {
values("0.96820");
}
}
timing() {
related_pin : "pll_clk";
timing_sense : negative_unate;
timing_type : hold_falling;
rise_constraint(scalar) {
values("1.75066");
}
}
timing() {
related_pin : "pll_clk";
timing_sense : negative_unate;
timing_type : setup_falling;
rise_constraint(scalar) {
values("-0.99300");
}
}
timing() {
related_pin : "pll_clk90";
timing_sense : positive_unate;
timing_type : hold_rising;
rise_constraint(scalar) {
values("0.67864");
}
}
timing() {
related_pin : "pll_clk90";
timing_sense : positive_unate;
timing_type : setup_rising;
rise_constraint(scalar) {
values("0.04584");
}
}
timing() {
related_pin : "pll_clk90";
timing_sense : negative_unate;
timing_type : hold_falling;
rise_constraint(scalar) {
values("1.74186");
}
}
timing() {
related_pin : "pll_clk90";
timing_sense : negative_unate;
timing_type : setup_falling;
rise_constraint(scalar) {
values("-0.82009");
}
}
}
pin("resetb_sync") {
direction : output;
capacitance : 0.2000;
timing() {
related_pin : "ext_reset";
timing_sense : negative_unate;
timing_type : combinational;
cell_rise(template_1) {
values("1.49291,1.49553,1.50578,1.54124,1.68206,2.32279,5.28059");
}
rise_transition(template_1) {
values("0.02385,0.02585,0.03448,0.07350,0.26600,1.18188,5.39669");
}
cell_fall(template_2) {
values("0.55765,0.55968,0.56723,0.59033,0.65904,0.93079,2.17782");
}
fall_transition(template_2) {
values("0.01891,0.02021,0.02508,0.04333,0.11877,0.48588,2.21350");
}
}
timing() {
related_pin : "ext_clk";
timing_type : falling_edge;
cell_rise(template_11) {
values("16.39387,16.39649,16.40674,16.44221,16.58302,17.22375,20.18155");
}
rise_transition(template_11) {
values("0.02385,0.02585,0.03448,0.07350,0.26600,1.18188,5.39669");
}
cell_fall(template_12) {
values("16.37211,16.37413,16.38169,16.40478,16.47349,16.74524,17.99227");
}
fall_transition(template_12) {
values("0.01891,0.02021,0.02508,0.04333,0.11877,0.48588,2.21350");
}
}
}
pin("user_clk") {
direction : output;
capacitance : 0.2000;
timing() {
related_pin : "ext_clk";
timing_type : rising_edge;
cell_rise(template_13) {
values("1.64936,1.65123,1.65766,1.67713,1.73528,1.93733,2.70491");
}
rise_transition(template_13) {
values("0.02440,0.02589,0.03121,0.05053,0.12314,0.40881,1.50596");
}
cell_fall(template_14) {
values("-0.10797,-0.10629,-0.10034,-0.08375,-0.04057,0.08665,0.54822");
}
fall_transition(template_14) {
values("0.02337,0.02441,0.02829,0.04105,0.08438,0.25148,0.91299");
}
}
timing() {
related_pin : "ext_clk";
timing_type : falling_edge;
cell_rise(template_15) {
values("-0.15034,-0.14847,-0.14205,-0.12258,-0.06443,0.13762,0.90520");
}
rise_transition(template_15) {
values("0.02440,0.02589,0.03121,0.05053,0.12314,0.40881,1.50596");
}
cell_fall(template_16) {
values("15.44328,15.44496,15.45091,15.46750,15.51068,15.63790,16.09947");
}
fall_transition(template_16) {
values("0.02337,0.02441,0.02829,0.04105,0.08438,0.25148,0.91299");
}
}
timing() {
related_pin : "pll_clk";
timing_type : rising_edge;
cell_rise(template_17) {
values("2.24230,2.24417,2.25060,2.27007,2.32821,2.53027,3.29785");
}
rise_transition(template_17) {
values("0.02440,0.02589,0.03121,0.05053,0.12314,0.40881,1.50596");
}
cell_fall(template_18) {
values("2.55628,2.55796,2.56391,2.58051,2.62369,2.75090,3.21247");
}
fall_transition(template_18) {
values("0.02337,0.02441,0.02829,0.04105,0.08438,0.25148,0.91299");
}
}
timing() {
related_pin : "pll_clk90";
timing_type : rising_edge;
cell_rise(template_19) {
values("2.35748,2.35935,2.36578,2.38525,2.44339,2.64545,3.41303");
}
rise_transition(template_19) {
values("0.02440,0.02589,0.03121,0.05053,0.12314,0.40881,1.50596");
}
cell_fall(template_20) {
values("2.62006,2.62174,2.62769,2.64428,2.68746,2.81468,3.27625");
}
fall_transition(template_20) {
values("0.02337,0.02441,0.02829,0.04105,0.08438,0.25148,0.91299");
}
}
timing() {
related_pin : "pll_clk90";
timing_type : falling_edge;
cell_rise(template_21) {
values("6.65311,6.65498,6.66141,6.68088,6.73902,6.94108,7.70866");
}
rise_transition(template_21) {
values("0.02440,0.02589,0.03121,0.05053,0.12314,0.40881,1.50596");
}
cell_fall(template_22) {
values("6.91013,6.91180,6.91776,6.93435,6.97753,7.10474,7.56632");
}
fall_transition(template_22) {
values("0.02337,0.02441,0.02829,0.04105,0.08438,0.25148,0.91299");
}
}
}
pin("VPWR") {
direction : input;
capacitance : 0.0002;
}
pin("VGND") {
direction : input;
capacitance : 0.0002;
}
bus("sel") {
bus_type : sel;
direction : input;
capacitance : 0.0000;
pin("sel[2]") {
direction : input;
capacitance : 0.0148;
}
pin("sel[1]") {
direction : input;
capacitance : 0.0124;
}
pin("sel[0]") {
direction : input;
capacitance : 0.0091;
}
}
bus("sel2") {
bus_type : sel2;
direction : input;
capacitance : 0.0000;
pin("sel2[2]") {
direction : input;
capacitance : 0.0148;
}
pin("sel2[1]") {
direction : input;
capacitance : 0.0125;
}
pin("sel2[0]") {
direction : input;
capacitance : 0.0137;
}
}
}
}

56425
mag/caravel_clocking.mag
View File

File diff suppressed because it is too large Load Diff

222
maglef/caravel_clocking.mag
View File

@ -1,62 +1,11 @@
magic
tech sky130A
magscale 1 2
timestamp 1638876628
<< nwell >>
rect -38 10053 18898 10619
rect -38 8965 18898 9531
rect -38 7877 18898 8443
rect -38 6789 18898 7355
rect -38 5701 18898 6267
rect -38 4613 18898 5179
rect -38 3525 18898 4091
rect -38 2437 18898 3003
rect -38 1349 18898 1915
rect -38 261 18898 827
<< pwell >>
rect 29 -17 63 17
rect 305 -17 339 17
rect 1043 -10 1075 12
rect 1317 -17 1351 17
rect 1593 -17 1627 17
rect 2328 -11 2352 11
rect 2605 -17 2639 17
rect 2697 -17 2731 17
rect 2973 -17 3007 17
rect 3709 -17 3743 17
rect 5549 -17 5583 17
rect 5641 -17 5675 17
rect 6101 -17 6135 17
rect 6432 -17 6466 17
rect 7297 -17 7331 17
rect 7573 -17 7607 17
rect 7665 -17 7699 17
rect 8548 -17 8582 17
rect 9321 -17 9355 17
rect 9689 -17 9723 17
rect 10424 -11 10448 11
rect 10702 -17 10736 17
rect 11160 -17 11194 17
rect 11253 -17 11287 17
rect 12080 -11 12104 11
rect 12173 -17 12207 17
rect 13000 -17 13034 17
rect 13092 -11 13116 11
rect 13277 -17 13311 17
rect 14472 -11 14496 11
rect 14565 -17 14599 17
rect 15209 -17 15243 17
rect 15669 -17 15703 17
rect 17050 -17 17084 17
rect 17325 -17 17359 17
rect 17417 -17 17451 17
rect 18061 -17 18095 17
rect 18521 -17 18555 17
rect 18797 -17 18831 17
timestamp 1665683481
<< obsli1 >>
rect 0 -17 18860 10897
rect 184 527 18860 10897
<< obsm1 >>
rect 0 -48 18860 10928
rect 184 76 19214 11416
<< metal2 >>
rect 1398 11200 1454 12000
rect 4250 11200 4306 12000
@ -66,20 +15,15 @@ rect 12806 11200 12862 12000
rect 15658 11200 15714 12000
rect 18510 11200 18566 12000
<< obsm2 >>
rect 296 11144 1342 11257
rect 1510 11144 4194 11257
rect 4362 11144 7046 11257
rect 7214 11144 9898 11257
rect 10066 11144 12750 11257
rect 12918 11144 15602 11257
rect 15770 11144 18454 11257
rect 18622 11144 18842 11257
rect 296 0 18842 11144
rect 4660 -48 4968 0
rect 7760 -48 8068 0
rect 10860 -48 11168 0
rect 13960 -48 14268 0
rect 17060 -48 17368 0
rect 480 11144 1342 11422
rect 1510 11144 4194 11422
rect 4362 11144 7046 11422
rect 7214 11144 9898 11422
rect 10066 11144 12750 11422
rect 12918 11144 15602 11422
rect 15770 11144 18454 11422
rect 18622 11144 19208 11422
rect 480 70 19208 11144
<< metal3 >>
rect 19200 11160 20000 11280
rect 19200 9664 20000 9784
@ -90,75 +34,77 @@ rect 19200 3680 20000 3800
rect 19200 2184 20000 2304
rect 19200 688 20000 808
<< obsm3 >>
rect 3104 11080 19120 11253
rect 3104 9864 19200 11080
rect 3104 9584 19120 9864
rect 3104 8368 19200 9584
rect 3104 8088 19120 8368
rect 3104 6872 19200 8088
rect 3104 6592 19120 6872
rect 3104 5376 19200 6592
rect 3104 5096 19120 5376
rect 3104 3880 19200 5096
rect 3104 3600 19120 3880
rect 3104 2384 19200 3600
rect 3104 2104 19120 2384
rect 3104 888 19200 2104
rect 3104 608 19120 888
rect 3104 0 19200 608
rect 4654 -33 4974 0
rect 7754 -33 8074 0
rect 10854 -33 11174 0
rect 13954 -33 14274 0
rect 17054 -33 17374 0
rect 565 11080 19120 11250
rect 565 9864 19200 11080
rect 565 9584 19120 9864
rect 565 8368 19200 9584
rect 565 8088 19120 8368
rect 565 6872 19200 8088
rect 565 6592 19120 6872
rect 565 5376 19200 6592
rect 565 5096 19120 5376
rect 565 3880 19200 5096
rect 565 3600 19120 3880
rect 565 2384 19200 3600
rect 565 2104 19120 2384
rect 565 888 19200 2104
rect 565 608 19120 888
rect 565 511 19200 608
<< metal4 >>
rect 3104 -48 3424 10928
rect 4654 -48 4974 10928
rect 6204 -48 6524 10928
rect 7754 -48 8074 10928
rect 9304 -48 9624 10928
rect 10854 -48 11174 10928
rect 12404 -48 12724 10928
rect 13954 -48 14274 10928
rect 15504 -48 15824 10928
rect 17054 -48 17374 10928
rect 3104 496 3424 10928
rect 4654 496 4974 10928
rect 6204 496 6524 10928
rect 7754 496 8074 10928
rect 9304 496 9624 10928
rect 10854 496 11174 10928
rect 12404 496 12724 10928
rect 13954 496 14274 10928
rect 15504 496 15824 10928
rect 17054 496 17374 10928
rect 18604 496 18924 10928
<< obsm4 >>
rect 14411 987 15424 8533
rect 15904 987 16974 8533
rect 17454 987 17605 8533
<< metal5 >>
rect 0 9882 18860 10202
rect 0 8192 18860 8512
rect 0 6502 18860 6822
rect 0 4812 18860 5132
rect 0 3122 18860 3442
rect 136 9338 18924 9658
rect 136 7648 18908 7968
rect 136 5958 18924 6278
rect 136 4268 18908 4588
rect 136 2578 18924 2898
<< labels >>
rlabel metal5 s 0 4812 18860 5132 6 VGND
port 1 nsew ground input
rlabel metal5 s 0 8192 18860 8512 6 VGND
port 1 nsew ground input
rlabel metal4 s 4654 -48 4974 10928 6 VGND
port 1 nsew ground input
rlabel metal4 s 7754 -48 8074 10928 6 VGND
port 1 nsew ground input
rlabel metal4 s 10854 -48 11174 10928 6 VGND
port 1 nsew ground input
rlabel metal4 s 13954 -48 14274 10928 6 VGND
port 1 nsew ground input
rlabel metal4 s 17054 -48 17374 10928 6 VGND
port 1 nsew ground input
rlabel metal5 s 0 3122 18860 3442 6 VPWR
port 2 nsew power input
rlabel metal5 s 0 6502 18860 6822 6 VPWR
port 2 nsew power input
rlabel metal5 s 0 9882 18860 10202 6 VPWR
port 2 nsew power input
rlabel metal4 s 3104 -48 3424 10928 6 VPWR
port 2 nsew power input
rlabel metal4 s 6204 -48 6524 10928 6 VPWR
port 2 nsew power input
rlabel metal4 s 9304 -48 9624 10928 6 VPWR
port 2 nsew power input
rlabel metal4 s 12404 -48 12724 10928 6 VPWR
port 2 nsew power input
rlabel metal4 s 15504 -48 15824 10928 6 VPWR
port 2 nsew power input
rlabel metal4 s 4654 496 4974 10928 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 7754 496 8074 10928 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 10854 496 11174 10928 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 13954 496 14274 10928 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 17054 496 17374 10928 6 VGND
port 1 nsew ground bidirectional
rlabel metal5 s 136 4268 18908 4588 6 VGND
port 1 nsew ground bidirectional
rlabel metal5 s 136 7648 18908 7968 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 3104 496 3424 10928 6 VPWR
port 2 nsew power bidirectional
rlabel metal4 s 6204 496 6524 10928 6 VPWR
port 2 nsew power bidirectional
rlabel metal4 s 9304 496 9624 10928 6 VPWR
port 2 nsew power bidirectional
rlabel metal4 s 12404 496 12724 10928 6 VPWR
port 2 nsew power bidirectional
rlabel metal4 s 15504 496 15824 10928 6 VPWR
port 2 nsew power bidirectional
rlabel metal4 s 18604 496 18924 10928 6 VPWR
port 2 nsew power bidirectional
rlabel metal5 s 136 2578 18924 2898 6 VPWR
port 2 nsew power bidirectional
rlabel metal5 s 136 5958 18924 6278 6 VPWR
port 2 nsew power bidirectional
rlabel metal5 s 136 9338 18924 9658 6 VPWR
port 2 nsew power bidirectional
rlabel metal2 s 7102 11200 7158 12000 6 core_clk
port 3 nsew signal output
rlabel metal2 s 4250 11200 4306 12000 6 ext_clk
@ -190,11 +136,11 @@ port 16 nsew signal input
rlabel metal2 s 9954 11200 10010 12000 6 user_clk
port 17 nsew signal output
<< properties >>
string LEFclass BLOCK
string FIXED_BBOX 0 0 20000 12000
string LEFclass BLOCK
string LEFview TRUE
string GDS_FILE ../gds/caravel_clocking.gds
string GDS_END 1175822
string GDS_START 367538
string GDS_END 1397874
string GDS_FILE /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/caravel_clocking.magic.gds
string GDS_START 391844
<< end >>

76
openlane/caravel_clocking/base.sdc
View File

@ -3,37 +3,25 @@ create_clock [get_ports {"ext_clk"} ] -name "ext_clk" -period 25
create_clock [get_ports {"pll_clk"} ] -name "pll_clk" -period 6.6666666666667
create_clock [get_ports {"pll_clk90"} ] -name "pll_clk90" -period 6.6666666666667
set muxes_2 [list $::env(STD_CELL_LIBRARY)__mux2_1 $::env(STD_CELL_LIBRARY)__mux2_2 $::env(STD_CELL_LIBRARY)__mux2_4 $::env(STD_CELL_LIBRARY)__mux2_8]
foreach mux_2 $muxes_2 {
set mux2_instance [get_cells -of_objects core_clk -filter ref_name==$mux_2]
if { $mux2_instance ne "" } {
puts "\[caravel_clocking_sdc\] found mux2: $mux2_instance"
break
}
}
set core_clk_pin [get_pins -filter lib_pin_name==X -of_objects $mux2_instance]
## GENERATED CLOCKS
# divided PLL clocks
create_generated_clock -name pll_clk_divided -source [get_ports pll_clk] -divide_by 2 [get_pins _355_/Y]
create_generated_clock -name pll_clk90_divided -source [get_ports pll_clk90] -divide_by 2 [get_pins _357_/Y]
# assign core_ext_clk = (use_pll_first) ? ext_clk_syncd : ext_clk;
create_generated_clock -name core_ext_clk -source [get_ports ext_clk] -divide_by 1 [get_pins _347_/X]
create_generated_clock -name core_ext_clk_syncd -source [get_pins _444_/Q] -divide_by 1 [get_pins _347_/X]
# assign core_clk = (use_pll_second) ? pll_clk_divided : core_ext_clk;
create_generated_clock -name core_clk -source [get_pins _347_/X] -divide_by 1 [get_ports core_clk]
create_generated_clock -name core_clk_pll -source [get_pins _355_/Y] -divide_by 1 [get_ports core_clk]
# assign user_clk = (use_pll_second) ? pll_clk90_divided : core_ext_clk;
create_generated_clock -name user_clk -source [get_pins _347_/X] -divide_by 1 [get_ports user_clk]
create_generated_clock -name user_clk_pll -source [get_pins _357_/Y] -divide_by 1 [get_ports user_clk]
create_generated_clock -name core_clk -source $core_clk_pin -divide_by 1 [get_ports core_clk]
# logically exclusive clocks, the generated pll clocks and the ext core clk
set_clock_groups -logically_exclusive -group core_ext_clk -group core_ext_clk_syncd
set_clock_groups -logically_exclusive -group core_clk -group core_clk_pll
set_clock_groups -logically_exclusive -group user_clk -group user_clk_pll
set_clock_groups -logically_exclusive -group ext_clk -group {pll_clk pll_clk90 pll_clk_divided pll_clk90_divided}
set_clock_groups -logically_exclusive -group ext_clk -group {pll_clk90 pll_clk}
## INPUT/OUTPUT DELAYS
set ext_clk_input_delay_value 1
set ext_clk_output_delay_value [expr 25 * $::env(IO_PCT)]
set pll_clk_input_delay_value [expr 6.6666666666667 * $::env(IO_PCT)]
set pll_clk_output_delay_value [expr 6.6666666666667 * $::env(IO_PCT)]
puts "\[INFO\]: Setting output delay to: $ext_clk_output_delay_value"
puts "\[INFO\]: Setting input delay to: $ext_clk_input_delay_value"
set ext_clk_input_delay_value 5
set ext_clk_output_delay_value 5
set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {ext_clk_sel}]
@ -46,27 +34,31 @@ set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_d
set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[2]}]
set_output_delay $ext_clk_output_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb_sync}]
#set_output_delay $output_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {core_clk}]
#set_output_delay $output_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {user_clk}]
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
# TODO set this as parameter
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
puts "\[INFO\]: Setting load to: $cap_load"
set cap_load 0.2
set_load $cap_load [all_outputs]
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {ext_clk}]
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {pll_clk}]
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {pll_clk90}]
set_clock_uncertainty 0.2 [get_clocks {ext_clk}]
set_clock_uncertainty 0.2 [get_clocks {pll_clk}]
set_clock_uncertainty 0.2 [get_clocks {pll_clk90}]
set_clock_uncertainty 0.2 [get_clocks {core_clk}]
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {ext_clk}]
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_clk}]
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_clk90}]
set_clock_transition 0.15 [get_clocks {ext_clk}]
set_clock_transition 0.1 [get_clocks {pll_clk}]
set_clock_transition 0.1 [get_clocks {pll_clk90}]
set_clock_transition 0.1 [get_clocks {core_clk}]
set_max_transition 0.5 [all_clocks] -clock_path
#set clk_input [get_port serial_clock)]
#set clk_indx [lsearch [all_inputs] $clk_input]
#set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx ""]
set_input_transition 5.0 [all_inputs]
set_max_transition 0.75 [current_design]

64
openlane/caravel_clocking/base2.sdc Normal file
View File

@ -0,0 +1,64 @@
## MASTER CLOCKS
create_clock [get_ports {"ext_clk"} ] -name "ext_clk" -period 25
create_clock [get_ports {"pll_clk"} ] -name "pll_clk" -period 6.6666666666667
create_clock [get_ports {"pll_clk90"} ] -name "pll_clk90" -period 6.6666666666667
set muxes_2 [list $::env(STD_CELL_LIBRARY)__mux2_1 $::env(STD_CELL_LIBRARY)__mux2_2 $::env(STD_CELL_LIBRARY)__mux2_4 $::env(STD_CELL_LIBRARY)__mux2_8]
foreach mux_2 $muxes_2 {
set mux2_instance [get_cells -of_objects core_clk -filter ref_name==$mux_2]
if { $mux2_instance ne "" } {
puts "\[caravel_clocking_sdc\] found mux2: $mux2_instance"
break
}
}
set core_clk_pin [get_pins -filter lib_pin_name==X -of_objects $mux2_instance]
## GENERATED CLOCKS
create_generated_clock -name core_clk -source $core_clk_pin -divide_by 1 [get_ports core_clk]
# logically exclusive clocks, the generated pll clocks and the ext core clk
set_clock_groups -logically_exclusive -group ext_clk -group {pll_clk90 pll_clk}
## INPUT/OUTPUT DELAYS
set ext_clk_input_delay_value 5
set ext_clk_output_delay_value 5
set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {ext_clk_sel}]
#set_input_delay $input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb}]
set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[0]}]
set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[1]}]
set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[2]}]
set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[0]}]
set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[1]}]
set_input_delay $ext_clk_input_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[2]}]
set_output_delay $ext_clk_output_delay_value -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb_sync}]
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
# TODO set this as parameter
set cap_load 0.2
set_load $cap_load [all_outputs]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
set_clock_uncertainty 0.2 [get_clocks {ext_clk}]
set_clock_uncertainty 0.2 [get_clocks {pll_clk}]
set_clock_uncertainty 0.2 [get_clocks {pll_clk90}]
set_clock_uncertainty 0.2 [get_clocks {core_clk}]
set_clock_transition 0.15 [get_clocks {ext_clk}]
set_clock_transition 0.1 [get_clocks {pll_clk}]
set_clock_transition 0.1 [get_clocks {pll_clk90}]
set_clock_transition 0.1 [get_clocks {core_clk}]
set_max_transition 0.5 [all_clocks] -clock_path
#set clk_input [get_port serial_clock)]
#set clk_indx [lsearch [all_inputs] $clk_input]
#set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx ""]
set_input_transition 5.0 [all_inputs]
set_max_transition 0.75 [current_design]

22
openlane/caravel_clocking/buffer.tcl Normal file
View File

@ -0,0 +1,22 @@
# Copyright 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
source $::env(SCRIPTS_DIR)/openroad/common/io.tcl
read
source $::env(SCRIPTS_DIR)/openroad/insert_buffer.tcl
puts "inserting buffer on user_clk"
set user_clk_instance [get_property [get_cells -of_objects user_clk] name]
puts "insert_buffer ${user_clk_instance}/X ITerm sky130_fd_sc_hd__clkbuf_16 user_clk_buffered user_clk_out_buffer"
insert_buffer ${user_clk_instance}/X ITerm sky130_fd_sc_hd__clkbuf_16 user_clk_buffered user_clk_out_buffer
write

54
openlane/caravel_clocking/config.tcl
View File

@ -13,15 +13,14 @@
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) caravel_clocking
set ::env(DESIGN_IS_CORE) 1
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v\
$script_dir/../../verilog/rtl/clock_div.v\
$script_dir/../../verilog/rtl/caravel_clocking.v"
$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
$::env(DESIGN_DIR)/../../verilog/rtl/clock_div.v\
$::env(DESIGN_DIR)/../../verilog/rtl/caravel_clocking.v"
set ::env(CLOCK_PORT) "ext_clk"
set ::env(CLOCK_NET) "ext_clk core_clk pll_clk pll_clk90"
@ -32,48 +31,59 @@ set ::env(RUN_KLAYOUT) 0
## Synthesis
set ::env(SYNTH_STRATEGY) "DELAY 0"
set ::env(CLOCK_TREE_SYNTH) 1
set ::env(SYNTH_SIZING) 0
set ::env(SYNTH_BUFFERING) 0
set ::env(BASE_SDC_FILE) $script_dir/base.sdc
set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
set ::env(NO_SYNTH_CELL_LIST) $script_dir/no_synth.list
set ::env(NO_SYNTH_CELL_LIST) $::env(DESIGN_DIR)/no_synth.list
## Floorplan
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 100 60"
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/template/caravel_clocking.def
set ::env(FP_TAPCELL_DIST) 6
set ::env(LEFT_MARGIN_MULT) 0
set ::env(BOTTOM_MARGIN_MULT) 0
set ::env(LEFT_MARGIN_MULT) 2
set ::env(BOTTOM_MARGIN_MULT) 2
set ::env(TOP_MARGIN_MULT) "2"
set ::env(BOTTOM_MARGIN_MULT) "1"
set ::env(CELL_PAD) 0
set ::env(DPL_CELL_PADDING) 0
set ::env(GPL_CELL_PADDING) 0
set ::env(DIODE_PADDING) 0
## PDN
set ::env(FP_PDN_HPITCH) 16.9
set ::env(FP_PDN_VPITCH) 15.5
set ::env(FP_PDN_HSPACING) 6.85
set ::env(FP_PDN_VSPACING) 6.15
set ::env(FP_PDN_HOFFSET) 10.97
set ::env(FP_PDN_VOFFSET) 15.4
# vertical 21.29 15.61
## Placement
set ::env(PL_TARGET_DENSITY) 0.74
set ::env(PL_TARGET_DENSITY) 0.9
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.25
set ::env(GRT_RESIZER_HOLD_SLACK_MARGIN) 0.25
## Routing
set ::env(GLB_RT_ADJUSTMENT) 0
set ::env(GRT_ADJUSTMENT) 0
set ::env(GLB_RT_MINLAYER) 2
set ::env(GLB_RT_MAXLAYER) 6
# prevent signal routing on li1
set ::env(GLB_RT_OBS) "\
li1 0 54.64000 100.0 60,\
li1 94.29500 0 100 60"
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(GRT_RESIZER_TIMING_OPTIMIZATIONS) 1
## Diode Insertion
set ::env(DIODE_INSERTION_STRATEGY) 4
set ::env(SYNTH_EXTRA_MAPPING_FILE) $::env(SYNTH_MUX_MAP)
set ::env(RSZ_DONT_TOUCH_RX) "core_clk|user_clk"
set ::env(RSZ_USE_OLD_REMOVER) 1
set ::env(FP_PDN_SKIP_TRIM) 1
set ::env(CTS_MAX_CAP) 0.25
#set ::env(DRC_EXCLUDE_CELL_LIST) $::env(DESIGN_DIR)/drc_exclude.list
set ::env(SYNTH_MAX_FANOUT) 12

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sky130_fd_sc_hd__a2111oi_0
sky130_fd_sc_hd__a21boi_0
sky130_fd_sc_hd__and2_0
sky130_fd_sc_hd__buf_16
sky130_fd_sc_hd__clkdlybuf4s15_1
sky130_fd_sc_hd__clkdlybuf4s18_1
sky130_fd_sc_hd__fa_4
sky130_fd_sc_hd__lpflow_bleeder_1
sky130_fd_sc_hd__lpflow_clkbufkapwr_1
sky130_fd_sc_hd__lpflow_clkbufkapwr_16
sky130_fd_sc_hd__lpflow_clkbufkapwr_2
sky130_fd_sc_hd__lpflow_clkbufkapwr_4
sky130_fd_sc_hd__lpflow_clkbufkapwr_8
sky130_fd_sc_hd__lpflow_clkinvkapwr_1
sky130_fd_sc_hd__lpflow_clkinvkapwr_16
sky130_fd_sc_hd__lpflow_clkinvkapwr_2
sky130_fd_sc_hd__lpflow_clkinvkapwr_4
sky130_fd_sc_hd__lpflow_clkinvkapwr_8
sky130_fd_sc_hd__lpflow_decapkapwr_12
sky130_fd_sc_hd__lpflow_decapkapwr_3
sky130_fd_sc_hd__lpflow_decapkapwr_4
sky130_fd_sc_hd__lpflow_decapkapwr_6
sky130_fd_sc_hd__lpflow_decapkapwr_8
sky130_fd_sc_hd__lpflow_inputiso0n_1
sky130_fd_sc_hd__lpflow_inputiso0p_1
sky130_fd_sc_hd__lpflow_inputiso1n_1
sky130_fd_sc_hd__lpflow_inputiso1p_1
sky130_fd_sc_hd__lpflow_inputisolatch_1
sky130_fd_sc_hd__lpflow_isobufsrc_1
sky130_fd_sc_hd__lpflow_isobufsrc_16
sky130_fd_sc_hd__lpflow_isobufsrc_2
sky130_fd_sc_hd__lpflow_isobufsrc_4
sky130_fd_sc_hd__lpflow_isobufsrc_8
sky130_fd_sc_hd__lpflow_isobufsrckapwr_16
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4
sky130_fd_sc_hd__mux4_4
sky130_fd_sc_hd__o21ai_0
sky130_fd_sc_hd__o311ai_0
sky130_fd_sc_hd__or2_0
sky130_fd_sc_hd__probe_p_8
sky130_fd_sc_hd__probec_p_8
sky130_fd_sc_hd__xor3_1
sky130_fd_sc_hd__xor3_2
sky130_fd_sc_hd__xor3_4
sky130_fd_sc_hd__xnor3_1
sky130_fd_sc_hd__xnor3_2
sky130_fd_sc_hd__xnor3_4
sky130_fd_sc_hd__buf_1
sky130_fd_sc_hd__bufbuf_1
sky130_fd_sc_hd__bufinv_1
sky130_fd_sc_hd__clkbuf_1
sky130_fd_sc_hd__clkdlybuf4s15_1
sky130_fd_sc_hd__clkdlybuf4s18_1
sky130_fd_sc_hd__clkdlybuf4s25_1
sky130_fd_sc_hd__clkdlybuf4s50_1
sky130_fd_sc_hd__clkinv_1
sky130_fd_sc_hd__dlygate4sd1_1
sky130_fd_sc_hd__dlygate4sd2_1
sky130_fd_sc_hd__dlygate4sd3_1
sky130_fd_sc_hd__dlymetal6s2s_1
sky130_fd_sc_hd__dlymetal6s4s_1
sky130_fd_sc_hd__dlymetal6s6s_1

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# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
package require openlane
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
prep -ignore_mismatches -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 0
exec rm -rf $SCRIPT_DIR/runs/caravel_clocking_interactive
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/caravel_clocking_interactive
run_synthesis
init_floorplan
place_io
apply_def_template
tap_decap_or
run_power_grid_generation
global_placement_or
run_resizer_design
detailed_placement_or
run_cts
run_resizer_timing
remove_buffers_from_nets
puts_info "Running custom buffer script"
run_openroad_script $::env(DESIGN_DIR)/buffer.tcl\
-indexed_log [index_file $::env(cts_logs)/custom-buffer.log]\
-save "to=$::env(cts_tmpfiles),name=$::env(DESIGN_NAME).custom-buffered,def,sdc,odb,netlist,powered_netlist"
run_resizer_timing_routing
ins_diode_cells_4
ins_fill_cells
global_routing
detailed_routing
run_parasitics_sta
run_irdrop_report
run_magic
run_magic_spice_export;
run_lvs;
run_magic_drc
run_antenna_check
run_lef_cvc
calc_total_runtime
save_final_views
save_final_views -save_path .. -tag $::env(OPENLANE_RUN_TAG)
save_state
generate_final_summary_report
check_timing_violations

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signoff/caravel_clocking/OPENLANE_VERSION
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@ -1 +1 @@
openlane 2021.11.23_01.42.34-11-g0c24fcf
OpenLane e3a5189a1b0fc4290686fcf2ae46cd6d7947cf9f

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signoff/caravel_clocking/PDK_SOURCES
View File

@ -1,3 +1 @@
openlane cbb562bd43c5c410b1b498604803c3dd88a44856
skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
open_pdks c5730b574461889c82858b08d12ba42423d9c2cb
open_pdks de752ec0ba4da0ecb1fbcd309eeec4993d88f5bc

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design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
/home/kareem_farid/caravel/openlane/caravel_clocking,caravel_clocking,22_10_13_10_49,flow completed,0h2m11s0ms,-1,-2.0,0.006,-1,77.61,672.82,-1,0,0,0,0,0,0,0,-1,-1,-1,-1,9779,2723,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,3180689.0,0.0,40.08,35.75,0.45,0.0,0.0,215,265,67,117,0,0,0,213,0,3,4,15,18,14,14,41,79,86,4,38,157,0,195,4825.8784,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10.0,DELAY 0,12,50,1,15.5,16.9,0.9,0,sky130_fd_sc_hd,4
1 design design_name config flow_status total_runtime routed_runtime (Cell/mm^2)/Core_Util DIEAREA_mm^2 CellPer_mm^2 OpenDP_Util Peak_Memory_Usage_MB cell_count tritonRoute_violations Short_violations MetSpc_violations OffGrid_violations MinHole_violations Other_violations Magic_violations antenna_violations lvs_total_errors cvc_total_errors klayout_violations wire_length vias wns pl_wns optimized_wns fastroute_wns spef_wns tns pl_tns optimized_tns fastroute_tns spef_tns HPWL routing_layer1_pct routing_layer2_pct routing_layer3_pct routing_layer4_pct routing_layer5_pct routing_layer6_pct wires_count wire_bits public_wires_count public_wire_bits memories_count memory_bits processes_count cells_pre_abc AND DFF NAND NOR OR XOR XNOR MUX inputs outputs level EndCaps TapCells Diodes Total_Physical_Cells CoreArea_um^2 power_slowest_internal_uW power_slowest_switching_uW power_slowest_leakage_uW power_typical_internal_uW power_typical_switching_uW power_typical_leakage_uW power_fastest_internal_uW power_fastest_switching_uW power_fastest_leakage_uW critical_path_ns suggested_clock_period suggested_clock_frequency CLOCK_PERIOD SYNTH_STRATEGY SYNTH_MAX_FANOUT FP_CORE_UTIL FP_ASPECT_RATIO FP_PDN_VPITCH FP_PDN_HPITCH PL_TARGET_DENSITY GRT_ADJUSTMENT STD_CELL_LIBRARY DIODE_INSERTION_STRATEGY
2 /home/kareem_farid/caravel/openlane/caravel_clocking caravel_clocking 22_10_13_10_49 flow completed 0h2m11s0ms -1 -2.0 0.006 -1 77.61 672.82 -1 0 0 0 0 0 0 0 -1 -1 -1 -1 9779 2723 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.0 3180689.0 0.0 40.08 35.75 0.45 0.0 0.0 215 265 67 117 0 0 0 213 0 3 4 15 18 14 14 41 79 86 4 38 157 0 195 4825.8784 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10.0 100.0 10.0 DELAY 0 12 50 1 15.5 16.9 0.9 0 sky130_fd_sc_hd 4

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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.min.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.min.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.min.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
[INFO ODB-0128] Design: caravel_clocking
[INFO ODB-0130] Created 17 pins.
[INFO ODB-0131] Created 734 components and 3799 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2622 connections.
[INFO ODB-0133] Created 330 nets and 1176 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
Using RCX ruleset '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
[INFO RCX-0008] extracting parasitics of caravel_clocking ...
[INFO RCX-0435] Reading extraction model file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre ...
[INFO RCX-0436] RC segment generation caravel_clocking (max_merge_res 50.0) ...
[INFO RCX-0040] Final 1388 rc segments
[INFO RCX-0439] Coupling Cap extraction caravel_clocking ...
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
[INFO RCX-0043] 3159 wires to be extracted
[INFO RCX-0442] 54% completion -- 1727 wires have been extracted
[INFO RCX-0442] 100% completion -- 3159 wires have been extracted
[INFO RCX-0045] Extract 330 nets, 1718 rsegs, 1718 caps, 3478 ccs
[INFO RCX-0015] Finished extracting caravel_clocking.
Writing result to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/mca/process_corner_min/caravel_clocking.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing extracted parasitics to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/mca/process_corner_min/caravel_clocking.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 330 nets finished
[INFO RCX-0017] Finished writing SPEF ...

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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.max.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.max.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.max.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
[INFO ODB-0128] Design: caravel_clocking
[INFO ODB-0130] Created 17 pins.
[INFO ODB-0131] Created 734 components and 3799 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2622 connections.
[INFO ODB-0133] Created 330 nets and 1176 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
Using RCX ruleset '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
[INFO RCX-0008] extracting parasitics of caravel_clocking ...
[INFO RCX-0435] Reading extraction model file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre ...
[INFO RCX-0436] RC segment generation caravel_clocking (max_merge_res 50.0) ...
[INFO RCX-0040] Final 1908 rc segments
[INFO RCX-0439] Coupling Cap extraction caravel_clocking ...
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
[INFO RCX-0043] 3159 wires to be extracted
[INFO RCX-0442] 54% completion -- 1727 wires have been extracted
[INFO RCX-0442] 100% completion -- 3159 wires have been extracted
[INFO RCX-0045] Extract 330 nets, 2238 rsegs, 2238 caps, 3586 ccs
[INFO RCX-0015] Finished extracting caravel_clocking.
Writing result to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/mca/process_corner_max/caravel_clocking.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing extracted parasitics to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/mca/process_corner_max/caravel_clocking.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 330 nets finished
[INFO RCX-0017] Finished writing SPEF ...

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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.nom.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
[INFO ODB-0128] Design: caravel_clocking
[INFO ODB-0130] Created 17 pins.
[INFO ODB-0131] Created 734 components and 3799 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2622 connections.
[INFO ODB-0133] Created 330 nets and 1176 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
Using RCX ruleset '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
[INFO RCX-0008] extracting parasitics of caravel_clocking ...
[INFO RCX-0435] Reading extraction model file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre ...
[INFO RCX-0436] RC segment generation caravel_clocking (max_merge_res 50.0) ...
[INFO RCX-0040] Final 1429 rc segments
[INFO RCX-0439] Coupling Cap extraction caravel_clocking ...
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
[INFO RCX-0043] 3159 wires to be extracted
[INFO RCX-0442] 54% completion -- 1727 wires have been extracted
[INFO RCX-0442] 100% completion -- 3159 wires have been extracted
[INFO RCX-0045] Extract 330 nets, 1759 rsegs, 1759 caps, 3493 ccs
[INFO RCX-0015] Finished extracting caravel_clocking.
Writing result to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/mca/process_corner_nom/caravel_clocking.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing extracted parasitics to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/mca/process_corner_nom/caravel_clocking.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 330 nets finished
[INFO RCX-0017] Finished writing SPEF ...

13941
signoff/caravel_clocking/openlane-signoff/25-rcx_mcsta.nom.log Normal file
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File diff suppressed because it is too large Load Diff

5
signoff/caravel_clocking/openlane-signoff/26-rcx_sta.area.rpt Normal file
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===========================================================================
report_design_area
============================================================================
Design area 4243 u^2 88% utilization.

28
signoff/caravel_clocking/openlane-signoff/26-rcx_sta.clock_skew.rpt Normal file
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===========================================================================
report_clock_skew
============================================================================
Clock core_clk
No launch/capture paths found.
Clock ext_clk
Latency CRPR Skew
_419_/CLK ^
3.26
_418_/CLK ^
2.83 -0.28 0.15
Clock pll_clk
Latency CRPR Skew
_445_/CLK ^
3.06
_441_/CLK ^
0.78 -0.06 2.22
Clock pll_clk90
Latency CRPR Skew
_473_/CLK ^
3.01
_462_/CLK ^
0.77 -0.06 2.17

1906
signoff/caravel_clocking/openlane-signoff/26-rcx_sta.log Normal file
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File diff suppressed because it is too large Load Diff

844
signoff/caravel_clocking/openlane-signoff/26-rcx_sta.max.rpt Normal file
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===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: _417_ (rising edge-triggered flip-flop clocked by ext_clk')
Endpoint: resetb_sync (output port clocked by ext_clk)
Path Group: ext_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
12.50 12.50 clock ext_clk' (rise edge)
0.00 12.50 clock source latency
5.00 0.00 12.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 12.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 14.04 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 14.04 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.20 14.24 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 14.24 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.37 14.61 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 14.61 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.19 14.81 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 14.81 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.14 14.95 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 14.95 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.33 15.27 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 15.27 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.17 15.44 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 15.44 v clkbuf_1_1__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.15 15.60 v clkbuf_1_1__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_1_1__leaf_net10 (net)
0.04 0.00 15.60 v _266__7/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 15.64 ^ _266__7/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net37 (net)
0.02 0.00 15.64 ^ _417_/CLK (sky130_fd_sc_hd__dfstp_1)
0.03 0.35 15.99 v _417_/Q (sky130_fd_sc_hd__dfstp_1)
1 0.00 reset_delay[0] (net)
0.03 0.00 15.99 v _349_/B (sky130_fd_sc_hd__nor2_1)
0.29 0.25 16.24 ^ _349_/Y (sky130_fd_sc_hd__nor2_1)
1 0.02 net11 (net)
0.29 0.00 16.24 ^ output11/A (sky130_fd_sc_hd__buf_12)
0.24 0.31 16.54 ^ output11/X (sky130_fd_sc_hd__buf_12)
1 0.20 resetb_sync (net)
0.24 0.01 16.56 ^ resetb_sync (out)
16.56 data arrival time
25.00 25.00 clock ext_clk (rise edge)
0.00 25.00 clock network delay (propagated)
-0.20 24.80 clock uncertainty
0.00 24.80 clock reconvergence pessimism
-5.00 19.80 output external delay
19.80 data required time
-----------------------------------------------------------------------------
19.80 data required time
-16.56 data arrival time
-----------------------------------------------------------------------------
3.24 slack (MET)
Startpoint: _419_ (rising edge-triggered flip-flop clocked by ext_clk')
Endpoint: _418_ (rising edge-triggered flip-flop clocked by ext_clk')
Path Group: ext_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
12.50 12.50 clock ext_clk' (rise edge)
0.00 12.50 clock source latency
5.00 0.00 12.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 12.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 14.04 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 14.04 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.20 14.24 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 14.24 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.37 14.61 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 14.61 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.19 14.81 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 14.81 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.14 14.95 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 14.95 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.33 15.27 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 15.27 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.17 15.44 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 15.44 v clkbuf_1_0__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.14 0.24 15.69 v clkbuf_1_0__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.21 core_clk (net)
0.14 0.01 15.69 v _412__9/A (sky130_fd_sc_hd__inv_4)
0.04 0.07 15.76 ^ _412__9/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net39 (net)
0.04 0.00 15.76 ^ _419_/CLK (sky130_fd_sc_hd__dfstp_1)
0.05 0.52 16.28 ^ _419_/Q (sky130_fd_sc_hd__dfstp_1)
1 0.00 reset_delay[2] (net)
0.05 0.00 16.28 ^ _418_/D (sky130_fd_sc_hd__dfstp_1)
16.28 data arrival time
37.50 37.50 clock ext_clk' (rise edge)
0.00 37.50 clock source latency
5.00 0.00 37.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 37.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 38.89 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 38.89 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.18 39.07 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 39.07 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.34 39.41 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 39.41 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.17 39.59 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 39.59 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.12 39.71 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 39.71 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.30 40.01 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 40.01 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.15 40.16 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 40.16 v clkbuf_1_1__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.14 40.30 v clkbuf_1_1__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_1_1__leaf_net10 (net)
0.04 0.00 40.30 v _411__8/A (sky130_fd_sc_hd__inv_4)
0.02 0.03 40.33 ^ _411__8/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net38 (net)
0.02 0.00 40.33 ^ _418_/CLK (sky130_fd_sc_hd__dfstp_1)
-0.20 40.13 clock uncertainty
0.28 40.41 clock reconvergence pessimism
-0.06 40.36 library setup time
40.36 data required time
-----------------------------------------------------------------------------
40.36 data required time
-16.28 data arrival time
-----------------------------------------------------------------------------
24.07 slack (MET)
Startpoint: _418_ (rising edge-triggered flip-flop clocked by ext_clk')
Endpoint: _417_ (rising edge-triggered flip-flop clocked by ext_clk')
Path Group: ext_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
12.50 12.50 clock ext_clk' (rise edge)
0.00 12.50 clock source latency
5.00 0.00 12.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 12.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 14.04 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 14.04 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.20 14.24 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 14.24 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.37 14.61 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 14.61 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.19 14.81 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 14.81 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.14 14.95 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 14.95 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.33 15.27 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 15.27 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.17 15.44 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 15.44 v clkbuf_1_1__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.15 15.60 v clkbuf_1_1__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_1_1__leaf_net10 (net)
0.04 0.00 15.60 v _411__8/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 15.63 ^ _411__8/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net38 (net)
0.02 0.00 15.63 ^ _418_/CLK (sky130_fd_sc_hd__dfstp_1)
0.05 0.51 16.15 ^ _418_/Q (sky130_fd_sc_hd__dfstp_1)
1 0.00 reset_delay[1] (net)
0.05 0.00 16.15 ^ _417_/D (sky130_fd_sc_hd__dfstp_1)
16.15 data arrival time
37.50 37.50 clock ext_clk' (rise edge)
0.00 37.50 clock source latency
5.00 0.00 37.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 37.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 38.89 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 38.89 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.18 39.07 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 39.07 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.34 39.41 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 39.41 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.17 39.59 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 39.59 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.12 39.71 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 39.71 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.30 40.01 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 40.01 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.15 40.16 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 40.16 v clkbuf_1_1__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.14 40.30 v clkbuf_1_1__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_1_1__leaf_net10 (net)
0.04 0.00 40.30 v _266__7/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 40.34 ^ _266__7/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net37 (net)
0.02 0.00 40.34 ^ _417_/CLK (sky130_fd_sc_hd__dfstp_1)
-0.20 40.14 clock uncertainty
0.30 40.43 clock reconvergence pessimism
-0.06 40.37 library setup time
40.37 data required time
-----------------------------------------------------------------------------
40.37 data required time
-16.15 data arrival time
-----------------------------------------------------------------------------
24.23 slack (MET)
Startpoint: _428_ (rising edge-triggered flip-flop clocked by pll_clk)
Endpoint: _435_ (falling edge-triggered flip-flop clocked by pll_clk)
Path Group: pll_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.05 clknet_1_1__leaf_pll_clk (net)
0.07 0.00 0.85 ^ _428_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.06 0.41 1.26 v _428_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider.odd_0.rst_pulse (net)
0.06 0.00 1.26 v fanout24/A (sky130_fd_sc_hd__clkbuf_4)
0.11 0.22 1.48 v fanout24/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net24 (net)
0.11 0.00 1.48 v fanout23/A (sky130_fd_sc_hd__clkbuf_4)
0.10 0.23 1.72 v fanout23/X (sky130_fd_sc_hd__clkbuf_4)
12 0.04 net23 (net)
0.10 0.00 1.72 v _301_/A (sky130_fd_sc_hd__or2_1)
0.05 0.26 1.98 v _301_/X (sky130_fd_sc_hd__or2_1)
1 0.00 _001_ (net)
0.05 0.00 1.98 v _206_/A0 (sky130_fd_sc_hd__mux2_1)
0.11 0.37 2.35 v _206_/X (sky130_fd_sc_hd__mux2_1)
3 0.02 _003_ (net)
0.11 0.00 2.35 v _368_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.34 2.69 v _368_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _097_ (net)
0.06 0.00 2.69 v _435_/D (sky130_fd_sc_hd__dfrtn_1)
2.69 data arrival time
3.33 3.33 clock pll_clk (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.21 4.94 v clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.05 clknet_1_0__leaf_pll_clk (net)
0.05 0.00 4.94 v _435_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.74 clock uncertainty
0.06 4.80 clock reconvergence pessimism
-0.15 4.65 library setup time
4.65 data required time
-----------------------------------------------------------------------------
4.65 data required time
-2.69 data arrival time
-----------------------------------------------------------------------------
1.96 slack (MET)
Startpoint: _428_ (rising edge-triggered flip-flop clocked by pll_clk)
Endpoint: _433_ (falling edge-triggered flip-flop clocked by pll_clk)
Path Group: pll_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.05 clknet_1_1__leaf_pll_clk (net)
0.07 0.00 0.85 ^ _428_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.06 0.41 1.26 v _428_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider.odd_0.rst_pulse (net)
0.06 0.00 1.26 v fanout24/A (sky130_fd_sc_hd__clkbuf_4)
0.11 0.22 1.48 v fanout24/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net24 (net)
0.11 0.00 1.48 v fanout23/A (sky130_fd_sc_hd__clkbuf_4)
0.10 0.23 1.72 v fanout23/X (sky130_fd_sc_hd__clkbuf_4)
12 0.04 net23 (net)
0.10 0.00 1.72 v _301_/A (sky130_fd_sc_hd__or2_1)
0.05 0.26 1.98 v _301_/X (sky130_fd_sc_hd__or2_1)
1 0.00 _001_ (net)
0.05 0.00 1.98 v _206_/A0 (sky130_fd_sc_hd__mux2_1)
0.11 0.37 2.35 v _206_/X (sky130_fd_sc_hd__mux2_1)
3 0.02 _003_ (net)
0.11 0.00 2.35 v _367_/S (sky130_fd_sc_hd__mux2_1)
0.05 0.34 2.69 v _367_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _095_ (net)
0.05 0.00 2.69 v _433_/D (sky130_fd_sc_hd__dfrtn_1)
2.69 data arrival time
3.33 3.33 clock pll_clk (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.21 4.94 v clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.05 clknet_1_0__leaf_pll_clk (net)
0.05 0.00 4.94 v _433_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.74 clock uncertainty
0.06 4.80 clock reconvergence pessimism
-0.15 4.65 library setup time
4.65 data required time
-----------------------------------------------------------------------------
4.65 data required time
-2.69 data arrival time
-----------------------------------------------------------------------------
1.96 slack (MET)
Startpoint: _428_ (rising edge-triggered flip-flop clocked by pll_clk)
Endpoint: _434_ (rising edge-triggered flip-flop clocked by pll_clk')
Path Group: pll_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.05 clknet_1_1__leaf_pll_clk (net)
0.07 0.00 0.85 ^ _428_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.06 0.41 1.26 v _428_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider.odd_0.rst_pulse (net)
0.06 0.00 1.26 v fanout24/A (sky130_fd_sc_hd__clkbuf_4)
0.11 0.22 1.48 v fanout24/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net24 (net)
0.11 0.00 1.48 v fanout23/A (sky130_fd_sc_hd__clkbuf_4)
0.10 0.23 1.72 v fanout23/X (sky130_fd_sc_hd__clkbuf_4)
12 0.04 net23 (net)
0.10 0.00 1.72 v _301_/A (sky130_fd_sc_hd__or2_1)
0.05 0.26 1.98 v _301_/X (sky130_fd_sc_hd__or2_1)
1 0.00 _001_ (net)
0.05 0.00 1.98 v _206_/A0 (sky130_fd_sc_hd__mux2_1)
0.11 0.37 2.35 v _206_/X (sky130_fd_sc_hd__mux2_1)
3 0.02 _003_ (net)
0.11 0.00 2.35 v _286_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.35 2.69 v _286_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _096_ (net)
0.06 0.00 2.69 v _434_/D (sky130_fd_sc_hd__dfstp_2)
2.69 data arrival time
3.33 3.33 clock pll_clk' (rise edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.21 4.94 v clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.05 clknet_1_0__leaf_pll_clk (net)
0.05 0.00 4.94 v _414__6/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 4.98 ^ _414__6/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net36 (net)
0.02 0.00 4.98 ^ _434_/CLK (sky130_fd_sc_hd__dfstp_2)
-0.20 4.78 clock uncertainty
0.06 4.84 clock reconvergence pessimism
-0.08 4.76 library setup time
4.76 data required time
-----------------------------------------------------------------------------
4.76 data required time
-2.69 data arrival time
-----------------------------------------------------------------------------
2.07 slack (MET)
Startpoint: _428_ (rising edge-triggered flip-flop clocked by pll_clk)
Endpoint: _429_ (falling edge-triggered flip-flop clocked by pll_clk)
Path Group: pll_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.05 clknet_1_1__leaf_pll_clk (net)
0.07 0.00 0.85 ^ _428_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.08 0.38 1.23 ^ _428_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider.odd_0.rst_pulse (net)
0.08 0.00 1.23 ^ fanout24/A (sky130_fd_sc_hd__clkbuf_4)
0.16 0.25 1.47 ^ fanout24/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net24 (net)
0.16 0.00 1.48 ^ fanout23/A (sky130_fd_sc_hd__clkbuf_4)
0.14 0.26 1.74 ^ fanout23/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net23 (net)
0.15 0.00 1.74 ^ _217_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.36 2.11 v _217_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _006_ (net)
0.06 0.00 2.11 v _267_/A (sky130_fd_sc_hd__inv_2)
0.03 0.05 2.16 ^ _267_/Y (sky130_fd_sc_hd__inv_2)
1 0.00 _131_ (net)
0.03 0.00 2.16 ^ _364_/A1 (sky130_fd_sc_hd__o21ai_1)
0.05 0.06 2.22 v _364_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.00 _091_ (net)
0.05 0.00 2.22 v _429_/D (sky130_fd_sc_hd__dfrtn_1)
2.22 data arrival time
3.33 3.33 clock pll_clk (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.21 4.94 v clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.05 clknet_1_0__leaf_pll_clk (net)
0.05 0.00 4.94 v _429_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.74 clock uncertainty
0.06 4.80 clock reconvergence pessimism
-0.15 4.65 library setup time
4.65 data required time
-----------------------------------------------------------------------------
4.65 data required time
-2.22 data arrival time
-----------------------------------------------------------------------------
2.43 slack (MET)
Startpoint: _428_ (rising edge-triggered flip-flop clocked by pll_clk)
Endpoint: _431_ (falling edge-triggered flip-flop clocked by pll_clk)
Path Group: pll_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.05 clknet_1_1__leaf_pll_clk (net)
0.07 0.00 0.85 ^ _428_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.08 0.38 1.23 ^ _428_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider.odd_0.rst_pulse (net)
0.08 0.00 1.23 ^ fanout24/A (sky130_fd_sc_hd__clkbuf_4)
0.16 0.25 1.47 ^ fanout24/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net24 (net)
0.16 0.00 1.48 ^ fanout23/A (sky130_fd_sc_hd__clkbuf_4)
0.14 0.26 1.74 ^ fanout23/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net23 (net)
0.14 0.00 1.74 ^ _221_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.36 2.10 v _221_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _008_ (net)
0.06 0.00 2.10 v _269_/A (sky130_fd_sc_hd__inv_2)
0.03 0.05 2.16 ^ _269_/Y (sky130_fd_sc_hd__inv_2)
1 0.00 _132_ (net)
0.03 0.00 2.16 ^ _366_/A1 (sky130_fd_sc_hd__o21ai_1)
0.06 0.06 2.22 v _366_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.00 _093_ (net)
0.06 0.00 2.22 v _431_/D (sky130_fd_sc_hd__dfrtn_1)
2.22 data arrival time
3.33 3.33 clock pll_clk (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.73 v clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.21 4.93 v clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.04 clknet_1_1__leaf_pll_clk (net)
0.05 0.00 4.93 v _431_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.73 clock uncertainty
0.08 4.82 clock reconvergence pessimism
-0.16 4.66 library setup time
4.66 data required time
-----------------------------------------------------------------------------
4.66 data required time
-2.22 data arrival time
-----------------------------------------------------------------------------
2.44 slack (MET)
Startpoint: _453_ (rising edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _458_ (falling edge-triggered flip-flop clocked by pll_clk90)
Path Group: pll_clk90
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.86 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.08 0.43 1.29 v _453_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider2.odd_0.rst_pulse (net)
0.08 0.00 1.29 v fanout22/A (sky130_fd_sc_hd__clkbuf_4)
0.17 0.28 1.56 v fanout22/X (sky130_fd_sc_hd__clkbuf_4)
24 0.08 net22 (net)
0.17 0.01 1.57 v fanout21/A (sky130_fd_sc_hd__clkbuf_4)
0.11 0.28 1.85 v fanout21/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net21 (net)
0.11 0.00 1.86 v _306_/A (sky130_fd_sc_hd__or2_1)
0.05 0.26 2.11 v _306_/X (sky130_fd_sc_hd__or2_1)
1 0.00 _000_ (net)
0.05 0.00 2.11 v _207_/A0 (sky130_fd_sc_hd__mux2_1)
0.10 0.36 2.47 v _207_/X (sky130_fd_sc_hd__mux2_1)
3 0.01 _002_ (net)
0.10 0.00 2.47 v _395_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.35 2.81 v _395_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _111_ (net)
0.06 0.00 2.81 v _458_/D (sky130_fd_sc_hd__dfrtn_1)
2.81 data arrival time
3.33 3.33 clock pll_clk90 (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.20 4.93 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 4.94 v _458_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.74 clock uncertainty
0.06 4.80 clock reconvergence pessimism
-0.16 4.64 library setup time
4.64 data required time
-----------------------------------------------------------------------------
4.64 data required time
-2.81 data arrival time
-----------------------------------------------------------------------------
1.83 slack (MET)
Startpoint: _453_ (rising edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _460_ (falling edge-triggered flip-flop clocked by pll_clk90)
Path Group: pll_clk90
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.86 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.08 0.43 1.29 v _453_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider2.odd_0.rst_pulse (net)
0.08 0.00 1.29 v fanout22/A (sky130_fd_sc_hd__clkbuf_4)
0.17 0.28 1.56 v fanout22/X (sky130_fd_sc_hd__clkbuf_4)
24 0.08 net22 (net)
0.17 0.01 1.57 v fanout21/A (sky130_fd_sc_hd__clkbuf_4)
0.11 0.28 1.85 v fanout21/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net21 (net)
0.11 0.00 1.86 v _306_/A (sky130_fd_sc_hd__or2_1)
0.05 0.26 2.11 v _306_/X (sky130_fd_sc_hd__or2_1)
1 0.00 _000_ (net)
0.05 0.00 2.11 v _207_/A0 (sky130_fd_sc_hd__mux2_1)
0.10 0.36 2.47 v _207_/X (sky130_fd_sc_hd__mux2_1)
3 0.01 _002_ (net)
0.10 0.00 2.47 v _396_/S (sky130_fd_sc_hd__mux2_1)
0.05 0.34 2.80 v _396_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _113_ (net)
0.05 0.00 2.80 v _460_/D (sky130_fd_sc_hd__dfrtn_1)
2.80 data arrival time
3.33 3.33 clock pll_clk90 (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.20 4.93 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 4.94 v _460_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.74 clock uncertainty
0.06 4.80 clock reconvergence pessimism
-0.15 4.64 library setup time
4.64 data required time
-----------------------------------------------------------------------------
4.64 data required time
-2.80 data arrival time
-----------------------------------------------------------------------------
1.84 slack (MET)
Startpoint: _453_ (rising edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _459_ (rising edge-triggered flip-flop clocked by pll_clk90')
Path Group: pll_clk90
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.86 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.08 0.43 1.29 v _453_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider2.odd_0.rst_pulse (net)
0.08 0.00 1.29 v fanout22/A (sky130_fd_sc_hd__clkbuf_4)
0.17 0.28 1.56 v fanout22/X (sky130_fd_sc_hd__clkbuf_4)
24 0.08 net22 (net)
0.17 0.01 1.57 v fanout21/A (sky130_fd_sc_hd__clkbuf_4)
0.11 0.28 1.85 v fanout21/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net21 (net)
0.11 0.00 1.86 v _306_/A (sky130_fd_sc_hd__or2_1)
0.05 0.26 2.11 v _306_/X (sky130_fd_sc_hd__or2_1)
1 0.00 _000_ (net)
0.05 0.00 2.11 v _207_/A0 (sky130_fd_sc_hd__mux2_1)
0.10 0.36 2.47 v _207_/X (sky130_fd_sc_hd__mux2_1)
3 0.01 _002_ (net)
0.10 0.00 2.47 v _273_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.34 2.81 v _273_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _112_ (net)
0.06 0.00 2.81 v _459_/D (sky130_fd_sc_hd__dfstp_2)
2.81 data arrival time
3.33 3.33 clock pll_clk90' (rise edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.20 4.93 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 4.94 v _416__3/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 4.97 ^ _416__3/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net33 (net)
0.02 0.00 4.97 ^ _459_/CLK (sky130_fd_sc_hd__dfstp_2)
-0.20 4.77 clock uncertainty
0.06 4.84 clock reconvergence pessimism
-0.08 4.75 library setup time
4.75 data required time
-----------------------------------------------------------------------------
4.75 data required time
-2.81 data arrival time
-----------------------------------------------------------------------------
1.94 slack (MET)
Startpoint: _453_ (rising edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _456_ (falling edge-triggered flip-flop clocked by pll_clk90)
Path Group: pll_clk90
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.86 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.12 0.41 1.26 ^ _453_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider2.odd_0.rst_pulse (net)
0.12 0.00 1.27 ^ fanout22/A (sky130_fd_sc_hd__clkbuf_4)
0.26 0.33 1.60 ^ fanout22/X (sky130_fd_sc_hd__clkbuf_4)
24 0.09 net22 (net)
0.26 0.01 1.61 ^ fanout21/A (sky130_fd_sc_hd__clkbuf_4)
0.17 0.32 1.93 ^ fanout21/X (sky130_fd_sc_hd__clkbuf_4)
12 0.06 net21 (net)
0.17 0.00 1.93 ^ _238_/S (sky130_fd_sc_hd__mux2_1)
0.07 0.37 2.30 v _238_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 _019_ (net)
0.07 0.00 2.30 v _272_/A (sky130_fd_sc_hd__inv_2)
0.03 0.06 2.36 ^ _272_/Y (sky130_fd_sc_hd__inv_2)
1 0.00 _134_ (net)
0.03 0.00 2.36 ^ _394_/A1 (sky130_fd_sc_hd__o21ai_1)
0.06 0.06 2.42 v _394_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.00 _109_ (net)
0.06 0.00 2.42 v _456_/D (sky130_fd_sc_hd__dfrtn_1)
2.42 data arrival time
3.33 3.33 clock pll_clk90 (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.20 4.93 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 4.94 v _456_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.74 clock uncertainty
0.06 4.80 clock reconvergence pessimism
-0.16 4.64 library setup time
4.64 data required time
-----------------------------------------------------------------------------
4.64 data required time
-2.42 data arrival time
-----------------------------------------------------------------------------
2.22 slack (MET)
Startpoint: _453_ (rising edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _454_ (falling edge-triggered flip-flop clocked by pll_clk90)
Path Group: pll_clk90
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.86 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.08 0.43 1.29 v _453_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider2.odd_0.rst_pulse (net)
0.08 0.00 1.29 v fanout22/A (sky130_fd_sc_hd__clkbuf_4)
0.17 0.28 1.56 v fanout22/X (sky130_fd_sc_hd__clkbuf_4)
24 0.08 net22 (net)
0.17 0.01 1.57 v fanout21/A (sky130_fd_sc_hd__clkbuf_4)
0.11 0.28 1.85 v fanout21/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net21 (net)
0.11 0.00 1.86 v _283_/B1 (sky130_fd_sc_hd__a31oi_2)
0.26 0.28 2.14 ^ _283_/Y (sky130_fd_sc_hd__a31oi_2)
3 0.02 _140_ (net)
0.26 0.00 2.14 ^ _392_/A2 (sky130_fd_sc_hd__o21ai_1)
0.06 0.10 2.24 v _392_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.00 _107_ (net)
0.06 0.00 2.24 v _454_/D (sky130_fd_sc_hd__dfrtn_1)
2.24 data arrival time
3.33 3.33 clock pll_clk90 (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.20 4.93 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 4.94 v _454_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.74 clock uncertainty
0.06 4.80 clock reconvergence pessimism
-0.16 4.64 library setup time
4.64 data required time
-----------------------------------------------------------------------------
4.64 data required time
-2.24 data arrival time
-----------------------------------------------------------------------------
2.40 slack (MET)

711
signoff/caravel_clocking/openlane-signoff/26-rcx_sta.min.rpt Normal file
View File

@ -0,0 +1,711 @@
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _418_ (rising edge-triggered flip-flop clocked by ext_clk')
Endpoint: _417_ (rising edge-triggered flip-flop clocked by ext_clk')
Path Group: ext_clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
12.50 12.50 clock ext_clk' (rise edge)
0.00 12.50 clock source latency
5.00 0.00 12.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 12.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 13.89 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 13.89 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.18 14.07 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 14.07 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.34 14.41 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 14.41 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.17 14.59 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 14.59 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.12 14.71 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 14.71 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.30 15.01 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 15.01 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.15 15.16 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 15.16 v clkbuf_1_1__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.14 15.30 v clkbuf_1_1__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_1_1__leaf_net10 (net)
0.04 0.00 15.30 v _411__8/A (sky130_fd_sc_hd__inv_4)
0.02 0.03 15.33 ^ _411__8/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net38 (net)
0.02 0.00 15.33 ^ _418_/CLK (sky130_fd_sc_hd__dfstp_1)
0.03 0.32 15.66 v _418_/Q (sky130_fd_sc_hd__dfstp_1)
1 0.00 reset_delay[1] (net)
0.03 0.00 15.66 v _417_/D (sky130_fd_sc_hd__dfstp_1)
15.66 data arrival time
12.50 12.50 clock ext_clk' (rise edge)
0.00 12.50 clock source latency
5.00 0.00 12.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 12.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 14.04 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 14.04 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.20 14.24 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 14.24 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.37 14.61 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 14.61 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.19 14.81 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 14.81 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.14 14.95 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 14.95 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.33 15.27 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 15.27 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.17 15.44 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 15.44 v clkbuf_1_1__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.15 15.60 v clkbuf_1_1__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_1_1__leaf_net10 (net)
0.04 0.00 15.60 v _266__7/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 15.64 ^ _266__7/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net37 (net)
0.02 0.00 15.64 ^ _417_/CLK (sky130_fd_sc_hd__dfstp_1)
0.20 15.84 clock uncertainty
-0.30 15.54 clock reconvergence pessimism
-0.01 15.53 library hold time
15.53 data required time
-----------------------------------------------------------------------------
15.53 data required time
-15.66 data arrival time
-----------------------------------------------------------------------------
0.13 slack (MET)
Startpoint: _419_ (rising edge-triggered flip-flop clocked by ext_clk')
Endpoint: _418_ (rising edge-triggered flip-flop clocked by ext_clk')
Path Group: ext_clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
12.50 12.50 clock ext_clk' (rise edge)
0.00 12.50 clock source latency
5.00 0.00 12.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 12.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 13.89 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 13.89 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.18 14.07 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 14.07 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.34 14.41 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 14.41 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.17 14.59 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 14.59 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.12 14.71 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 14.71 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.30 15.01 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 15.01 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.15 15.16 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 15.16 v clkbuf_1_0__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.14 0.22 15.38 v clkbuf_1_0__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.21 core_clk (net)
0.14 0.01 15.39 v _412__9/A (sky130_fd_sc_hd__inv_4)
0.04 0.06 15.45 ^ _412__9/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net39 (net)
0.04 0.00 15.45 ^ _419_/CLK (sky130_fd_sc_hd__dfstp_1)
0.03 0.33 15.78 v _419_/Q (sky130_fd_sc_hd__dfstp_1)
1 0.00 reset_delay[2] (net)
0.03 0.00 15.78 v _418_/D (sky130_fd_sc_hd__dfstp_1)
15.78 data arrival time
12.50 12.50 clock ext_clk' (rise edge)
0.00 12.50 clock source latency
5.00 0.00 12.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 12.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 14.04 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 14.04 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.20 14.24 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 14.24 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.37 14.61 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 14.61 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.19 14.81 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 14.81 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.14 14.95 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 14.95 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.33 15.27 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 15.27 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.17 15.44 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 15.44 v clkbuf_1_1__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.15 15.60 v clkbuf_1_1__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_1_1__leaf_net10 (net)
0.04 0.00 15.60 v _411__8/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 15.63 ^ _411__8/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net38 (net)
0.02 0.00 15.63 ^ _418_/CLK (sky130_fd_sc_hd__dfstp_1)
0.20 15.83 clock uncertainty
-0.28 15.55 clock reconvergence pessimism
-0.01 15.54 library hold time
15.54 data required time
-----------------------------------------------------------------------------
15.54 data required time
-15.78 data arrival time
-----------------------------------------------------------------------------
0.24 slack (MET)
Startpoint: ext_reset (input port)
Endpoint: resetb_sync (output port clocked by ext_clk)
Path Group: ext_clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 ^ input external delay
5.00 0.00 0.00 ^ ext_reset (in)
2 0.02 ext_reset (net)
5.00 0.00 0.00 ^ input2/A (sky130_fd_sc_hd__clkbuf_1)
0.15 0.26 0.26 ^ input2/X (sky130_fd_sc_hd__clkbuf_1)
1 0.01 net2 (net)
0.15 0.00 0.26 ^ _349_/A (sky130_fd_sc_hd__nor2_1)
0.07 0.11 0.37 v _349_/Y (sky130_fd_sc_hd__nor2_1)
1 0.01 net11 (net)
0.07 0.00 0.37 v output11/A (sky130_fd_sc_hd__buf_12)
0.11 0.19 0.57 v output11/X (sky130_fd_sc_hd__buf_12)
1 0.20 resetb_sync (net)
0.12 0.01 0.58 v resetb_sync (out)
0.58 data arrival time
0.00 0.00 clock ext_clk (rise edge)
0.00 0.00 clock network delay (propagated)
0.20 0.20 clock uncertainty
0.00 0.20 clock reconvergence pessimism
-5.00 -4.80 output external delay
-4.80 data required time
-----------------------------------------------------------------------------
-4.80 data required time
-0.58 data arrival time
-----------------------------------------------------------------------------
5.38 slack (MET)
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_clk)
Endpoint: _423_ (rising edge-triggered flip-flop clocked by pll_clk)
Path Group: pll_clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.59 0.59 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.59 ^ clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.08 0.19 0.78 ^ clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.06 clknet_1_0__leaf_pll_clk (net)
0.08 0.00 0.78 ^ _448_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.05 0.31 1.09 v _448_/Q (sky130_fd_sc_hd__dfxtp_1)
2 0.01 ext_clk_syncd_pre (net)
0.05 0.00 1.09 v _423_/D (sky130_fd_sc_hd__dfrtp_1)
1.09 data arrival time
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.65 ^ clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.08 0.20 0.86 ^ clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.06 clknet_1_0__leaf_pll_clk (net)
0.08 0.00 0.86 ^ _423_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.20 1.06 clock uncertainty
-0.08 0.98 clock reconvergence pessimism
-0.04 0.94 library hold time
0.94 data required time
-----------------------------------------------------------------------------
0.94 data required time
-1.09 data arrival time
-----------------------------------------------------------------------------
0.15 slack (MET)
Startpoint: _420_ (rising edge-triggered flip-flop clocked by pll_clk)
Endpoint: _421_ (rising edge-triggered flip-flop clocked by pll_clk)
Path Group: pll_clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.59 0.59 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.59 ^ clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.18 0.77 ^ clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.05 clknet_1_1__leaf_pll_clk (net)
0.07 0.00 0.77 ^ _420_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.16 0.39 1.16 ^ _420_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.02 use_pll_first (net)
0.16 0.00 1.16 ^ _421_/D (sky130_fd_sc_hd__dfrtp_1)
1.16 data arrival time
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.65 ^ clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.08 0.20 0.86 ^ clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.06 clknet_1_0__leaf_pll_clk (net)
0.08 0.00 0.86 ^ _421_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.20 1.06 clock uncertainty
-0.06 1.00 clock reconvergence pessimism
-0.05 0.94 library hold time
0.94 data required time
-----------------------------------------------------------------------------
0.94 data required time
-1.16 data arrival time
-----------------------------------------------------------------------------
0.22 slack (MET)
Startpoint: _448_ (rising edge-triggered flip-flop clocked by pll_clk)
Endpoint: _448_ (rising edge-triggered flip-flop clocked by pll_clk)
Path Group: pll_clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.59 0.59 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.59 ^ clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.08 0.19 0.78 ^ clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.06 clknet_1_0__leaf_pll_clk (net)
0.08 0.00 0.78 ^ _448_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.09 0.33 1.11 ^ _448_/Q (sky130_fd_sc_hd__dfxtp_1)
2 0.01 ext_clk_syncd_pre (net)
0.09 0.00 1.11 ^ _380_/A0 (sky130_fd_sc_hd__mux2_1)
0.06 0.14 1.25 ^ _380_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _104_ (net)
0.06 0.00 1.25 ^ _448_/D (sky130_fd_sc_hd__dfxtp_1)
1.25 data arrival time
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.65 ^ clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.08 0.20 0.86 ^ clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.06 clknet_1_0__leaf_pll_clk (net)
0.08 0.00 0.86 ^ _448_/CLK (sky130_fd_sc_hd__dfxtp_1)
0.20 1.06 clock uncertainty
-0.08 0.98 clock reconvergence pessimism
-0.03 0.95 library hold time
0.95 data required time
-----------------------------------------------------------------------------
0.95 data required time
-1.25 data arrival time
-----------------------------------------------------------------------------
0.30 slack (MET)
Startpoint: _432_ (rising edge-triggered flip-flop clocked by pll_clk')
Endpoint: _432_ (rising edge-triggered flip-flop clocked by pll_clk')
Path Group: pll_clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
3.33 3.33 clock pll_clk' (rise edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.73 v clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.21 4.93 v clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.04 clknet_1_1__leaf_pll_clk (net)
0.05 0.00 4.93 v _413__5/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 4.97 ^ _413__5/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net35 (net)
0.02 0.00 4.97 ^ _432_/CLK (sky130_fd_sc_hd__dfstp_1)
0.09 0.37 5.35 v _432_/Q (sky130_fd_sc_hd__dfstp_1)
3 0.02 divider.odd_0.out_counter2 (net)
0.09 0.00 5.35 v _251_/A (sky130_fd_sc_hd__clkinv_4)
0.03 0.05 5.40 ^ _251_/Y (sky130_fd_sc_hd__clkinv_4)
2 0.01 _125_ (net)
0.03 0.00 5.40 ^ _295_/A1 (sky130_fd_sc_hd__o21ai_1)
0.04 0.06 5.46 v _295_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.00 _094_ (net)
0.04 0.00 5.46 v _432_/D (sky130_fd_sc_hd__dfstp_1)
5.46 data arrival time
3.33 3.33 clock pll_clk' (rise edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 4.87 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.87 v clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.23 5.10 v clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.04 clknet_1_1__leaf_pll_clk (net)
0.05 0.00 5.10 v _413__5/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 5.15 ^ _413__5/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net35 (net)
0.02 0.00 5.15 ^ _432_/CLK (sky130_fd_sc_hd__dfstp_1)
0.20 5.35 clock uncertainty
-0.17 5.17 clock reconvergence pessimism
-0.02 5.16 library hold time
5.16 data required time
-----------------------------------------------------------------------------
5.16 data required time
-5.46 data arrival time
-----------------------------------------------------------------------------
0.31 slack (MET)
Startpoint: _431_ (falling edge-triggered flip-flop clocked by pll_clk)
Endpoint: _431_ (falling edge-triggered flip-flop clocked by pll_clk)
Path Group: pll_clk
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
3.33 3.33 clock pll_clk (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.73 v clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.21 4.93 v clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.04 clknet_1_1__leaf_pll_clk (net)
0.05 0.00 4.93 v _431_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
0.13 0.43 5.36 ^ _431_/Q (sky130_fd_sc_hd__dfrtn_1)
4 0.01 divider.odd_0.counter2[2] (net)
0.13 0.00 5.36 ^ _365_/C (sky130_fd_sc_hd__nand3b_1)
0.05 0.08 5.44 v _365_/Y (sky130_fd_sc_hd__nand3b_1)
1 0.00 _182_ (net)
0.05 0.00 5.44 v _366_/B1 (sky130_fd_sc_hd__o21ai_1)
0.08 0.07 5.52 ^ _366_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.00 _093_ (net)
0.08 0.00 5.52 ^ _431_/D (sky130_fd_sc_hd__dfrtn_1)
5.52 data arrival time
3.33 3.33 clock pll_clk (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 4.87 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.87 v clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.23 5.10 v clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.04 clknet_1_1__leaf_pll_clk (net)
0.05 0.00 5.10 v _431_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
0.20 5.30 clock uncertainty
-0.17 5.13 clock reconvergence pessimism
0.08 5.21 library hold time
5.21 data required time
-----------------------------------------------------------------------------
5.21 data required time
-5.52 data arrival time
-----------------------------------------------------------------------------
0.31 slack (MET)
Startpoint: _457_ (rising edge-triggered flip-flop clocked by pll_clk90')
Endpoint: _457_ (rising edge-triggered flip-flop clocked by pll_clk90')
Path Group: pll_clk90
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
3.33 3.33 clock pll_clk90' (rise edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.73 v clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.21 4.94 v clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.05 0.00 4.94 v _415__2/A (sky130_fd_sc_hd__inv_4)
0.03 0.04 4.98 ^ _415__2/Y (sky130_fd_sc_hd__inv_4)
1 0.01 net32 (net)
0.03 0.00 4.98 ^ _457_/CLK (sky130_fd_sc_hd__dfstp_1)
0.07 0.36 5.35 v _457_/Q (sky130_fd_sc_hd__dfstp_1)
3 0.01 divider2.odd_0.out_counter2 (net)
0.07 0.00 5.35 v _248_/A (sky130_fd_sc_hd__inv_2)
0.05 0.07 5.42 ^ _248_/Y (sky130_fd_sc_hd__inv_2)
2 0.01 _122_ (net)
0.05 0.00 5.42 ^ _282_/A1 (sky130_fd_sc_hd__o21ai_1)
0.03 0.06 5.48 v _282_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.00 _110_ (net)
0.03 0.00 5.48 v _457_/D (sky130_fd_sc_hd__dfstp_1)
5.48 data arrival time
3.33 3.33 clock pll_clk90' (rise edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 4.88 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.88 v clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.23 5.11 v clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.05 0.00 5.11 v _415__2/A (sky130_fd_sc_hd__inv_4)
0.03 0.05 5.16 ^ _415__2/Y (sky130_fd_sc_hd__inv_4)
1 0.01 net32 (net)
0.03 0.00 5.16 ^ _457_/CLK (sky130_fd_sc_hd__dfstp_1)
0.20 5.36 clock uncertainty
-0.17 5.18 clock reconvergence pessimism
-0.01 5.17 library hold time
5.17 data required time
-----------------------------------------------------------------------------
5.17 data required time
-5.48 data arrival time
-----------------------------------------------------------------------------
0.31 slack (MET)
Startpoint: _452_ (rising edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _452_ (rising edge-triggered flip-flop clocked by pll_clk90)
Path Group: pll_clk90
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.59 0.59 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.59 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.18 0.77 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.77 ^ _452_/CLK (sky130_fd_sc_hd__dfstp_1)
0.07 0.38 1.15 v _452_/Q (sky130_fd_sc_hd__dfstp_1)
3 0.01 divider2.even_0.out_counter (net)
0.07 0.00 1.15 v _381_/B1 (sky130_fd_sc_hd__o21ai_1)
0.09 0.09 1.24 ^ _381_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.00 _188_ (net)
0.09 0.00 1.24 ^ _383_/A (sky130_fd_sc_hd__nand2_1)
0.03 0.05 1.29 v _383_/Y (sky130_fd_sc_hd__nand2_1)
1 0.00 _105_ (net)
0.03 0.00 1.29 v _452_/D (sky130_fd_sc_hd__dfstp_1)
1.29 data arrival time
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.86 ^ _452_/CLK (sky130_fd_sc_hd__dfstp_1)
0.20 1.06 clock uncertainty
-0.08 0.97 clock reconvergence pessimism
0.00 0.97 library hold time
0.97 data required time
-----------------------------------------------------------------------------
0.97 data required time
-1.29 data arrival time
-----------------------------------------------------------------------------
0.32 slack (MET)
Startpoint: _458_ (falling edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _458_ (falling edge-triggered flip-flop clocked by pll_clk90)
Path Group: pll_clk90
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
3.33 3.33 clock pll_clk90 (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.20 4.93 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 4.94 v _458_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
0.18 0.47 5.40 ^ _458_/Q (sky130_fd_sc_hd__dfrtn_1)
4 0.02 divider2.odd_0.initial_begin[0] (net)
0.18 0.00 5.40 ^ _395_/A0 (sky130_fd_sc_hd__mux2_1)
0.05 0.15 5.56 ^ _395_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _111_ (net)
0.05 0.00 5.56 ^ _458_/D (sky130_fd_sc_hd__dfrtn_1)
5.56 data arrival time
3.33 3.33 clock pll_clk90 (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 4.88 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.88 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.23 5.10 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 5.10 v _458_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
0.20 5.30 clock uncertainty
-0.17 5.14 clock reconvergence pessimism
0.08 5.22 library hold time
5.22 data required time
-----------------------------------------------------------------------------
5.22 data required time
-5.56 data arrival time
-----------------------------------------------------------------------------
0.34 slack (MET)
Startpoint: _460_ (falling edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _460_ (falling edge-triggered flip-flop clocked by pll_clk90)
Path Group: pll_clk90
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
3.33 3.33 clock pll_clk90 (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.20 4.93 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 4.94 v _460_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
0.20 0.48 5.42 ^ _460_/Q (sky130_fd_sc_hd__dfrtn_1)
4 0.02 divider2.odd_0.initial_begin[2] (net)
0.20 0.00 5.42 ^ _396_/A0 (sky130_fd_sc_hd__mux2_1)
0.04 0.15 5.57 ^ _396_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _113_ (net)
0.04 0.00 5.57 ^ _460_/D (sky130_fd_sc_hd__dfrtn_1)
5.57 data arrival time
3.33 3.33 clock pll_clk90 (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 4.88 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.88 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.23 5.10 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 5.10 v _460_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
0.20 5.30 clock uncertainty
-0.17 5.14 clock reconvergence pessimism
0.08 5.22 library hold time
5.22 data required time
-----------------------------------------------------------------------------
5.22 data required time
-5.57 data arrival time
-----------------------------------------------------------------------------
0.35 slack (MET)
Startpoint: _422_ (rising edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _422_ (rising edge-triggered flip-flop clocked by pll_clk90)
Path Group: pll_clk90
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.59 0.59 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.59 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.18 0.77 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.77 ^ _422_/CLK (sky130_fd_sc_hd__dfstp_1)
0.07 0.38 1.15 v _422_/Q (sky130_fd_sc_hd__dfstp_1)
4 0.01 divider2.odd_0.out_counter (net)
0.07 0.00 1.15 v _352_/A1 (sky130_fd_sc_hd__o21ai_1)
0.08 0.14 1.29 ^ _352_/Y (sky130_fd_sc_hd__o21ai_1)
1 0.00 _088_ (net)
0.08 0.00 1.29 ^ _422_/D (sky130_fd_sc_hd__dfstp_1)
1.29 data arrival time
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.85 ^ _422_/CLK (sky130_fd_sc_hd__dfstp_1)
0.20 1.05 clock uncertainty
-0.08 0.97 clock reconvergence pessimism
-0.04 0.93 library hold time
0.93 data required time
-----------------------------------------------------------------------------
0.93 data required time
-1.29 data arrival time
-----------------------------------------------------------------------------
0.35 slack (MET)

14
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===========================================================================
report_power
============================================================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 3.74e-04 4.56e-05 4.70e-10 4.20e-04 26.8%
Combinational 6.35e-04 5.15e-04 1.17e-09 1.15e-03 73.2%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 1.01e-03 5.61e-04 1.64e-09 1.57e-03 100.0%
64.3% 35.7% 0.0%

192
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===========================================================================
report_checks -unconstrained
============================================================================
Startpoint: _417_ (rising edge-triggered flip-flop clocked by ext_clk')
Endpoint: resetb_sync (output port clocked by ext_clk)
Path Group: ext_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
12.50 12.50 clock ext_clk' (rise edge)
0.00 12.50 clock source latency
5.00 0.00 12.50 v ext_clk (in)
2 0.01 ext_clk (net)
5.00 0.00 12.50 v clkbuf_0_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.54 14.04 v clkbuf_0_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_ext_clk (net)
0.16 0.00 14.04 v clkbuf_1_1__f_ext_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.20 14.24 v clkbuf_1_1__f_ext_clk/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_1__leaf_ext_clk (net)
0.03 0.00 14.24 v _209_/A0 (sky130_fd_sc_hd__mux2_1)
0.12 0.37 14.61 v _209_/X (sky130_fd_sc_hd__mux2_1)
1 0.02 _037_ (net)
0.12 0.00 14.61 v clkbuf_0__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.19 14.81 v clkbuf_0__037_/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0__037_ (net)
0.04 0.00 14.81 v clkbuf_1_0__f__037_/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.14 14.95 v clkbuf_1_0__f__037_/X (sky130_fd_sc_hd__clkbuf_16)
1 0.01 clknet_1_0__leaf__037_ (net)
0.03 0.00 14.95 v _210_/A0 (sky130_fd_sc_hd__mux2_1)
0.08 0.33 15.27 v _210_/X (sky130_fd_sc_hd__mux2_1)
1 0.01 net10 (net)
0.08 0.00 15.27 v clkbuf_0_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.03 0.17 15.44 v clkbuf_0_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_net10 (net)
0.03 0.00 15.44 v clkbuf_1_1__f_net10/A (sky130_fd_sc_hd__clkbuf_16)
0.04 0.15 15.60 v clkbuf_1_1__f_net10/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_1_1__leaf_net10 (net)
0.04 0.00 15.60 v _266__7/A (sky130_fd_sc_hd__inv_4)
0.02 0.04 15.64 ^ _266__7/Y (sky130_fd_sc_hd__inv_4)
1 0.00 net37 (net)
0.02 0.00 15.64 ^ _417_/CLK (sky130_fd_sc_hd__dfstp_1)
0.03 0.35 15.99 v _417_/Q (sky130_fd_sc_hd__dfstp_1)
1 0.00 reset_delay[0] (net)
0.03 0.00 15.99 v _349_/B (sky130_fd_sc_hd__nor2_1)
0.29 0.25 16.24 ^ _349_/Y (sky130_fd_sc_hd__nor2_1)
1 0.02 net11 (net)
0.29 0.00 16.24 ^ output11/A (sky130_fd_sc_hd__buf_12)
0.24 0.31 16.54 ^ output11/X (sky130_fd_sc_hd__buf_12)
1 0.20 resetb_sync (net)
0.24 0.01 16.56 ^ resetb_sync (out)
16.56 data arrival time
25.00 25.00 clock ext_clk (rise edge)
0.00 25.00 clock network delay (propagated)
-0.20 24.80 clock uncertainty
0.00 24.80 clock reconvergence pessimism
-5.00 19.80 output external delay
19.80 data required time
-----------------------------------------------------------------------------
19.80 data required time
-16.56 data arrival time
-----------------------------------------------------------------------------
3.24 slack (MET)
Startpoint: _428_ (rising edge-triggered flip-flop clocked by pll_clk)
Endpoint: _435_ (falling edge-triggered flip-flop clocked by pll_clk)
Path Group: pll_clk
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
13 0.05 clknet_1_1__leaf_pll_clk (net)
0.07 0.00 0.85 ^ _428_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.06 0.41 1.26 v _428_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider.odd_0.rst_pulse (net)
0.06 0.00 1.26 v fanout24/A (sky130_fd_sc_hd__clkbuf_4)
0.11 0.22 1.48 v fanout24/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net24 (net)
0.11 0.00 1.48 v fanout23/A (sky130_fd_sc_hd__clkbuf_4)
0.10 0.23 1.72 v fanout23/X (sky130_fd_sc_hd__clkbuf_4)
12 0.04 net23 (net)
0.10 0.00 1.72 v _301_/A (sky130_fd_sc_hd__or2_1)
0.05 0.26 1.98 v _301_/X (sky130_fd_sc_hd__or2_1)
1 0.00 _001_ (net)
0.05 0.00 1.98 v _206_/A0 (sky130_fd_sc_hd__mux2_1)
0.11 0.37 2.35 v _206_/X (sky130_fd_sc_hd__mux2_1)
3 0.02 _003_ (net)
0.11 0.00 2.35 v _368_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.34 2.69 v _368_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _097_ (net)
0.06 0.00 2.69 v _435_/D (sky130_fd_sc_hd__dfrtn_1)
2.69 data arrival time
3.33 3.33 clock pll_clk (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk (in)
2 0.02 pll_clk (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.21 4.94 v clkbuf_1_0__f_pll_clk/X (sky130_fd_sc_hd__clkbuf_16)
11 0.05 clknet_1_0__leaf_pll_clk (net)
0.05 0.00 4.94 v _435_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.74 clock uncertainty
0.06 4.80 clock reconvergence pessimism
-0.15 4.65 library setup time
4.65 data required time
-----------------------------------------------------------------------------
4.65 data required time
-2.69 data arrival time
-----------------------------------------------------------------------------
1.96 slack (MET)
Startpoint: _453_ (rising edge-triggered flip-flop clocked by pll_clk90)
Endpoint: _458_ (falling edge-triggered flip-flop clocked by pll_clk90)
Path Group: pll_clk90
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_clk90 (rise edge)
0.00 0.00 clock source latency
5.00 0.00 0.00 ^ pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 0.00 ^ clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.17 0.65 0.65 ^ clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.17 0.00 0.65 ^ clkbuf_1_1__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.07 0.20 0.85 ^ clkbuf_1_1__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
12 0.05 clknet_1_1__leaf_pll_clk90 (net)
0.07 0.00 0.86 ^ _453_/CLK (sky130_fd_sc_hd__dfrtp_1)
0.08 0.43 1.29 v _453_/Q (sky130_fd_sc_hd__dfrtp_1)
2 0.01 divider2.odd_0.rst_pulse (net)
0.08 0.00 1.29 v fanout22/A (sky130_fd_sc_hd__clkbuf_4)
0.17 0.28 1.56 v fanout22/X (sky130_fd_sc_hd__clkbuf_4)
24 0.08 net22 (net)
0.17 0.01 1.57 v fanout21/A (sky130_fd_sc_hd__clkbuf_4)
0.11 0.28 1.85 v fanout21/X (sky130_fd_sc_hd__clkbuf_4)
12 0.05 net21 (net)
0.11 0.00 1.86 v _306_/A (sky130_fd_sc_hd__or2_1)
0.05 0.26 2.11 v _306_/X (sky130_fd_sc_hd__or2_1)
1 0.00 _000_ (net)
0.05 0.00 2.11 v _207_/A0 (sky130_fd_sc_hd__mux2_1)
0.10 0.36 2.47 v _207_/X (sky130_fd_sc_hd__mux2_1)
3 0.01 _002_ (net)
0.10 0.00 2.47 v _395_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.35 2.81 v _395_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _111_ (net)
0.06 0.00 2.81 v _458_/D (sky130_fd_sc_hd__dfrtn_1)
2.81 data arrival time
3.33 3.33 clock pll_clk90 (fall edge)
0.00 3.33 clock source latency
5.00 0.00 3.33 v pll_clk90 (in)
2 0.02 pll_clk90 (net)
5.00 0.00 3.33 v clkbuf_0_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.16 1.39 4.73 v clkbuf_0_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
2 0.02 clknet_0_pll_clk90 (net)
0.16 0.00 4.73 v clkbuf_1_0__f_pll_clk90/A (sky130_fd_sc_hd__clkbuf_16)
0.05 0.20 4.93 v clkbuf_1_0__f_pll_clk90/X (sky130_fd_sc_hd__clkbuf_16)
8 0.04 clknet_1_0__leaf_pll_clk90 (net)
0.05 0.00 4.94 v _458_/CLK_N (sky130_fd_sc_hd__dfrtn_1)
-0.20 4.74 clock uncertainty
0.06 4.80 clock reconvergence pessimism
-0.16 4.64 library setup time
4.64 data required time
-----------------------------------------------------------------------------
4.64 data required time
-2.81 data arrival time
-----------------------------------------------------------------------------
1.83 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
No paths found.

64
signoff/caravel_clocking/openlane-signoff/26-rcx_sta.slew.rpt Normal file
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===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------
clkbuf_0_pll_clk90/A 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_input2_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_clkbuf_0_pll_clk90_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
clkbuf_0_pll_clk/A 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_clkbuf_0_pll_clk_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_input5_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_input9_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_input8_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_input4_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_input6_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_input1_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_input7_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_input3_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
clkbuf_0_ext_clk/A 0.75 5.00 -4.25 (VIOLATED)
input5/A 0.75 5.00 -4.25 (VIOLATED)
input8/A 0.75 5.00 -4.25 (VIOLATED)
input9/A 0.75 5.00 -4.25 (VIOLATED)
input7/A 0.75 5.00 -4.25 (VIOLATED)
input2/A 0.75 5.00 -4.25 (VIOLATED)
input6/A 0.75 5.00 -4.25 (VIOLATED)
ANTENNA_clkbuf_0_ext_clk_A/DIODE 0.75 5.00 -4.25 (VIOLATED)
input3/A 0.75 5.00 -4.25 (VIOLATED)
input1/A 0.75 5.00 -4.25 (VIOLATED)
input4/A 0.75 5.00 -4.25 (VIOLATED)
ext_clk 0.75 5.00 -4.25 (VIOLATED)
ext_clk_sel 0.75 5.00 -4.25 (VIOLATED)
ext_reset 0.75 5.00 -4.25 (VIOLATED)
pll_clk 0.75 5.00 -4.25 (VIOLATED)
pll_clk90 0.75 5.00 -4.25 (VIOLATED)
resetb 0.75 5.00 -4.25 (VIOLATED)
sel2[0] 0.75 5.00 -4.25 (VIOLATED)
sel2[1] 0.75 5.00 -4.25 (VIOLATED)
sel2[2] 0.75 5.00 -4.25 (VIOLATED)
sel[0] 0.75 5.00 -4.25 (VIOLATED)
sel[1] 0.75 5.00 -4.25 (VIOLATED)
sel[2] 0.75 5.00 -4.25 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
_276_/X 12 24 -12 (VIOLATED)
fanout13/X 12 24 -12 (VIOLATED)
fanout14/X 12 24 -12 (VIOLATED)
fanout15/X 12 24 -12 (VIOLATED)
fanout22/X 12 24 -12 (VIOLATED)
fanout28/X 12 24 -12 (VIOLATED)
fanout29/X 12 18 -6 (VIOLATED)
clkbuf_1_1__f_pll_clk/X 12 13 (VIOLATED)
===========================================================================
max slew violation count 36
max fanout violation count 8
max cap violation count 0
============================================================================

5
signoff/caravel_clocking/openlane-signoff/26-rcx_sta.tns.rpt Normal file
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===========================================================================
report_tns
============================================================================
tns 0.00

5
signoff/caravel_clocking/openlane-signoff/26-rcx_sta.wns.rpt Normal file
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===========================================================================
report_wns
============================================================================
wns 0.00

10
signoff/caravel_clocking/openlane-signoff/26-rcx_sta.worst_slack.rpt Normal file
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===========================================================================
report_worst_slack -max (Setup)
============================================================================
worst slack 1.83
===========================================================================
report_worst_slack -min (Hold)
============================================================================
worst slack 0.13

37
signoff/caravel_clocking/openlane-signoff/27-irdrop.log Normal file
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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.nom.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
[INFO ODB-0128] Design: caravel_clocking
[INFO ODB-0130] Created 17 pins.
[INFO ODB-0131] Created 734 components and 3799 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2622 connections.
[INFO ODB-0133] Created 330 nets and 1176 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
[INFO]: Setting RC values...
[INFO PSM-0002] Output voltage file is specified as: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/27-irdrop.rpt.
[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net VPWR is not explicitly set.
[WARNING PSM-0022] Using voltage 1.800V for VDD network.
[WARNING PSM-0063] Specified bump pitches of 140.000 and 140.000 are less than core width of 93.380 or core height of 51.680. Changing bump location to the center of the die at (47.610, 28.560).
[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
[INFO PSM-0031] Number of PDN nodes on net VPWR = 614.
[INFO PSM-0064] Number of voltage sources = 1.
[INFO PSM-0040] All PDN stripes on net VPWR are connected.
########## IR report #################
Worstcase voltage: 1.80e+00 V
Average IR drop : 3.56e-10 V
Worstcase IR drop: 5.93e-10 V
######################################

476
signoff/caravel_clocking/openlane-signoff/27-irdrop.rpt Normal file
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Instance name, X location, Y location, Voltage
PHY_37, 93.82, 54.4, 1.8
input2, 93.82, 54.4, 1.8
PHY_33, 93.82, 48.96, 1.8
PHY_35, 93.82, 48.96, 1.8
_381_, 93.82, 48.96, 1.8
PHY_29, 93.82, 43.52, 1.8
PHY_31, 93.82, 43.52, 1.8
fanout16, 93.82, 43.52, 1.8
PHY_25, 93.82, 38.08, 1.8
PHY_27, 93.82, 38.08, 1.8
_304_, 93.82, 38.08, 1.8
input4, 93.82, 38.08, 1.8
PHY_21, 93.82, 32.64, 1.8
PHY_23, 93.82, 32.64, 1.8
input5, 93.82, 32.64, 1.8
PHY_17, 93.82, 27.2, 1.8
PHY_19, 93.82, 27.2, 1.8
_358_, 93.82, 27.2, 1.8
PHY_13, 93.82, 21.76, 1.8
PHY_15, 93.82, 21.76, 1.8
_263_, 93.82, 21.76, 1.8
_361_, 93.82, 21.76, 1.8
PHY_11, 93.82, 16.32, 1.8
PHY_9, 93.82, 16.32, 1.8
input8, 93.82, 16.32, 1.8
input9, 93.82, 16.32, 1.8
PHY_5, 93.82, 10.88, 1.8
PHY_7, 93.82, 10.88, 1.8
_359_, 93.82, 10.88, 1.8
ANTENNA__276__A1, 93.82, 5.44, 1.8
PHY_1, 93.82, 5.44, 1.8
PHY_3, 93.82, 5.44, 1.8
input7, 93.82, 5.44, 1.8
ANTENNA__471__RESET_B, 78.32, 48.96, 1.8
_316_, 78.32, 48.96, 1.8
input6, 78.32, 48.96, 1.8
ANTENNA__275__A, 78.32, 43.52, 1.8
_258_, 78.32, 43.52, 1.8
_314_, 78.32, 43.52, 1.8
_452_, 78.32, 43.52, 1.8
_385_, 78.32, 38.08, 1.8
_468_, 78.32, 38.08, 1.8
clkbuf_1_1__f_divider2.out, 78.32, 38.08, 1.8
_386_, 78.32, 32.64, 1.8
_467_, 78.32, 32.64, 1.8
_471_, 78.32, 32.64, 1.8
_388_, 78.32, 27.2, 1.8
_466_, 78.32, 27.2, 1.8
ANTENNA__470__RESET_B, 78.32, 21.76, 1.8
_407_, 78.32, 21.76, 1.8
fanout20, 78.32, 21.76, 1.8
fanout22, 78.32, 21.76, 1.8
_428_, 78.32, 16.32, 1.8
fanout13, 78.32, 16.32, 1.8
_424_, 78.32, 10.88, 1.8
_438_, 78.32, 10.88, 1.8
fanout14, 78.32, 10.88, 1.8
ANTENNA_input5_A, 78.32, 5.44, 1.8
ANTENNA_input6_A, 78.32, 5.44, 1.8
_224_, 78.32, 5.44, 1.8
_225_, 78.32, 5.44, 1.8
_425_, 78.32, 5.44, 1.8
fanout17, 78.32, 5.44, 1.8
_281_, 62.82, 54.4, 1.8
_349_, 62.82, 54.4, 1.8
ANTENNA__351__B1, 62.82, 48.96, 1.8
ANTENNA__422__SET_B, 62.82, 48.96, 1.8
_266__7, 62.82, 48.96, 1.8
_472_, 62.82, 48.96, 1.8
clkbuf_0__037_, 62.82, 43.52, 1.8
_307_, 62.82, 38.08, 1.8
clkbuf_1_1__f_pll_clk90, 62.82, 38.08, 1.8
ANTENNA__240__S, 62.82, 32.64, 1.8
_389_, 62.82, 32.64, 1.8
_453_, 62.82, 32.64, 1.8
ANTENNA__461__RESET_B, 62.82, 27.2, 1.8
ANTENNA_clkbuf_0_pll_clk90_A, 62.82, 27.2, 1.8
_442_, 62.82, 27.2, 1.8
ANTENNA__453__RESET_B, 62.82, 21.76, 1.8
_288_, 62.82, 21.76, 1.8
_311_, 62.82, 21.76, 1.8
_447_, 62.82, 21.76, 1.8
_289_, 62.82, 16.32, 1.8
ANTENNA__408__A, 62.82, 10.88, 1.8
ANTENNA_input4_A, 62.82, 10.88, 1.8
_370_, 62.82, 10.88, 1.8
_436_, 62.82, 10.88, 1.8
ANTENNA__313__A_N, 62.82, 5.44, 1.8
ANTENNA__381__A1, 62.82, 5.44, 1.8
ANTENNA_input1_A, 62.82, 5.44, 1.8
ANTENNA_input7_A, 62.82, 5.44, 1.8
ANTENNA_input8_A, 62.82, 5.44, 1.8
ANTENNA_input9_A, 62.82, 5.44, 1.8
_257_, 62.82, 5.44, 1.8
_329_, 62.82, 5.44, 1.8
_369_, 62.82, 5.44, 1.8
_371_, 62.82, 5.44, 1.8
_280_, 47.32, 54.4, 1.8
ANTENNA__280__A2, 47.32, 48.96, 1.8
ANTENNA__280__B1, 47.32, 48.96, 1.8
ANTENNA__417__SET_B, 47.32, 48.96, 1.8
ANTENNA__457__SET_B, 47.32, 48.96, 1.8
_210_, 47.32, 48.96, 1.8
_282_, 47.32, 48.96, 1.8
_417_, 47.32, 48.96, 1.8
_421_, 47.32, 48.96, 1.8
_457_, 47.32, 43.52, 1.8
_239_, 47.32, 38.08, 1.8
_463_, 47.32, 38.08, 1.8
_240_, 47.32, 32.64, 1.8
_308_, 47.32, 32.64, 1.8
clkbuf_0_pll_clk, 47.32, 32.64, 1.8
clkbuf_0_pll_clk90, 47.32, 32.64, 1.8
_344_, 47.32, 27.2, 1.8
_420_, 47.32, 27.2, 1.8
_427_, 47.32, 27.2, 1.8
_208_, 47.32, 21.76, 1.8
_377_, 47.32, 21.76, 1.8
_291_, 47.32, 16.32, 1.8
_294_, 47.32, 16.32, 1.8
_413__5, 47.32, 16.32, 1.8
fanout27, 47.32, 16.32, 1.8
_251_, 47.32, 10.88, 1.8
_295_, 47.32, 10.88, 1.8
_365_, 47.32, 10.88, 1.8
_366_, 47.32, 10.88, 1.8
_431_, 47.32, 10.88, 1.8
ANTENNA__399__A1, 47.32, 5.44, 1.8
ANTENNA_fanout27_A, 47.32, 5.44, 1.8
FILLER_0_96, 47.32, 5.44, 1.8
FILLER_1_95, 47.32, 5.44, 1.8
_221_, 47.32, 5.44, 1.8
_292_, 47.32, 5.44, 1.8
_325_, 47.32, 5.44, 1.8
_326_, 47.32, 5.44, 1.8
_419__30, 31.82, 54.4, 1.8
ANTENNA__277__B1, 31.82, 48.96, 1.8
_233_, 31.82, 48.96, 1.8
ANTENNA__277__A2, 31.82, 43.52, 1.8
_412__9, 31.82, 43.52, 1.8
_419_, 31.82, 43.52, 1.8
_261_, 31.82, 38.08, 1.8
_462_, 31.82, 38.08, 1.8
clkbuf_1_1__f_net10, 31.82, 38.08, 1.8
_335_, 31.82, 32.64, 1.8
ANTENNA__335__A, 31.82, 27.2, 1.8
_299_, 31.82, 27.2, 1.8
_337_, 31.82, 27.2, 1.8
_441_, 31.82, 27.2, 1.8
ANTENNA__398__A1, 31.82, 21.76, 1.8
_228_, 31.82, 21.76, 1.8
_242_, 31.82, 21.76, 1.8
_333_, 31.82, 21.76, 1.8
_375_, 31.82, 21.76, 1.8
ANTENNA__398__A3, 31.82, 16.32, 1.8
_206_, 31.82, 16.32, 1.8
_317_, 31.82, 16.32, 1.8
_320_, 31.82, 16.32, 1.8
_363_, 31.82, 16.32, 1.8
_296_, 31.82, 10.88, 1.8
_298_, 31.82, 10.88, 1.8
_319_, 31.82, 10.88, 1.8
FILLER_0_66, 31.82, 5.44, 1.8
FILLER_1_69, 31.82, 5.44, 1.8
_219_, 31.82, 5.44, 1.8
_324_, 31.82, 5.44, 1.8
_236_, 16.32, 54.4, 1.8
input3, 16.32, 54.4, 1.8
ANTENNA__234__A1, 16.32, 48.96, 1.8
_455_, 16.32, 48.96, 1.8
_271__1, 16.32, 43.52, 1.8
_285_, 16.32, 43.52, 1.8
clkbuf_1_0__f_ext_clk, 16.32, 43.52, 1.8
_237_, 16.32, 38.08, 1.8
_249_, 16.32, 38.08, 1.8
_341_, 16.32, 38.08, 1.8
_448_, 16.32, 38.08, 1.8
ANTENNA__236__A1, 16.32, 32.64, 1.8
ANTENNA__237__A1, 16.32, 32.64, 1.8
ANTENNA__238__A1, 16.32, 32.64, 1.8
ANTENNA_fanout21_A, 16.32, 32.64, 1.8
_232_, 16.32, 32.64, 1.8
_274_, 16.32, 32.64, 1.8
_395_, 16.32, 32.64, 1.8
ANTENNA_input3_A, 16.32, 27.2, 1.8
_230_, 16.32, 27.2, 1.8
_259_, 16.32, 27.2, 1.8
_260_, 16.32, 27.2, 1.8
fanout21, 16.32, 27.2, 1.8
ANTENNA__400__A1, 16.32, 21.76, 1.8
ANTENNA__400__A3, 16.32, 21.76, 1.8
FILLER_7_27, 16.32, 21.76, 1.8
FILLER_8_34, 16.32, 21.76, 1.8
_439_, 16.32, 21.76, 1.8
_440_, 16.32, 21.76, 1.8
ANTENNA__333__B, 16.32, 16.32, 1.8
_435_, 16.32, 16.32, 1.8
FILLER_2_26, 16.32, 10.88, 1.8
_268__4, 16.32, 10.88, 1.8
_286_, 16.32, 10.88, 1.8
_318_, 16.32, 10.88, 1.8
_368_, 16.32, 10.88, 1.8
FILLER_2_35, 16.32, 5.44, 1.8
_430_, 16.32, 5.44, 1.8
PHY_36, 0.92, 54.4, 1.8
_272_, 8.62, 54.4, 1.8
_235_, 24.07, 54.4, 1.8
_244_, 39.57, 54.4, 1.8
ANTENNA__469__SET_B, 70.57, 54.4, 1.8
_211_, 70.57, 54.4, 1.8
ANTENNA__467__RESET_B, 86.07, 54.4, 1.8
_265_, 86.07, 54.4, 1.8
_313_, 86.07, 54.4, 1.8
ANTENNA__236__S, 0.92, 48.96, 1.8
PHY_32, 0.92, 48.96, 1.8
PHY_34, 0.92, 48.96, 1.8
fanout25, 0.92, 48.96, 1.8
fanout26, 0.92, 48.96, 1.8
fanout28, 0.92, 48.96, 1.8
_209_, 8.62, 48.96, 1.8
_380_, 8.62, 48.96, 1.8
_456_, 8.62, 48.96, 1.8
fanout29, 8.62, 48.96, 1.8
ANTENNA__233__A1, 24.07, 48.96, 1.8
ANTENNA__234__S, 24.07, 48.96, 1.8
ANTENNA__244__A1, 24.07, 48.96, 1.8
_234_, 24.07, 48.96, 1.8
_342_, 24.07, 48.96, 1.8
_423_, 24.07, 48.96, 1.8
clkbuf_1_0__f__037_, 24.07, 48.96, 1.8
ANTENNA__280__A1, 39.57, 48.96, 1.8
_418_, 39.57, 48.96, 1.8
_212_, 55.07, 48.96, 1.8
_248_, 55.07, 48.96, 1.8
ANTENNA__472__SET_B, 70.57, 48.96, 1.8
_245_, 70.57, 48.96, 1.8
clkbuf_0_divider2.out, 70.57, 48.96, 1.8
user_clk_out_buffer, 70.57, 48.96, 1.8
ANTENNA__281__A2, 86.07, 48.96, 1.8
ANTENNA__468__RESET_B, 86.07, 48.96, 1.8
_305_, 86.07, 48.96, 1.8
_382_, 86.07, 48.96, 1.8
_383_, 86.07, 48.96, 1.8
_406_, 86.07, 48.96, 1.8
PHY_28, 0.92, 43.52, 1.8
PHY_30, 0.92, 43.52, 1.8
_284_, 0.92, 43.52, 1.8
_391_, 0.92, 43.52, 1.8
_394_, 0.92, 43.52, 1.8
_238_, 8.62, 43.52, 1.8
_247_, 8.62, 43.52, 1.8
_454_, 8.62, 43.52, 1.8
ANTENNA__235__A1, 24.07, 43.52, 1.8
ANTENNA__465__SET_B, 24.07, 43.52, 1.8
ANTENNA_clkbuf_0_ext_clk_A, 24.07, 43.52, 1.8
_343_, 24.07, 43.52, 1.8
clkbuf_0_ext_clk, 24.07, 43.52, 1.8
clkbuf_1_0__f_pll_clk90, 24.07, 43.52, 1.8
ANTENNA__277__A1, 39.57, 43.52, 1.8
ANTENNA__421__RESET_B, 39.57, 43.52, 1.8
_411__8, 39.57, 43.52, 1.8
clkbuf_0_net10, 39.57, 43.52, 1.8
ANTENNA__463__RESET_B, 55.07, 43.52, 1.8
_345_, 55.07, 43.52, 1.8
_352_, 55.07, 43.52, 1.8
_469_, 55.07, 43.52, 1.8
ANTENNA__275__B, 70.57, 43.52, 1.8
_415__2, 70.57, 43.52, 1.8
_465_, 70.57, 43.52, 1.8
clkbuf_1_1__f__037_, 70.57, 43.52, 1.8
ANTENNA__387__A_N, 86.07, 43.52, 1.8
output11, 86.07, 43.52, 1.8
PHY_24, 0.92, 38.08, 1.8
PHY_26, 0.92, 38.08, 1.8
_278_, 0.92, 38.08, 1.8
_306_, 0.92, 38.08, 1.8
_340_, 0.92, 38.08, 1.8
_396_, 0.92, 38.08, 1.8
_207_, 8.62, 38.08, 1.8
_460_, 8.62, 38.08, 1.8
_277_, 24.07, 38.08, 1.8
_283_, 24.07, 38.08, 1.8
_347_, 39.57, 38.08, 1.8
clkbuf_1_1__f_divider.out, 39.57, 38.08, 1.8
clkbuf_1_1__f_ext_clk, 39.57, 38.08, 1.8
_351_, 55.07, 38.08, 1.8
_422_, 55.07, 38.08, 1.8
_315_, 70.57, 38.08, 1.8
_384_, 70.57, 38.08, 1.8
clkbuf_0_divider.out, 70.57, 38.08, 1.8
_276_, 86.07, 38.08, 1.8
_408_, 86.07, 38.08, 1.8
PHY_20, 0.92, 32.64, 1.8
PHY_22, 0.92, 32.64, 1.8
_270_, 0.92, 32.64, 1.8
_336_, 0.92, 32.64, 1.8
_338_, 0.92, 32.64, 1.8
_392_, 0.92, 32.64, 1.8
ANTENNA__336__A1, 8.62, 32.64, 1.8
ANTENNA__336__B1, 8.62, 32.64, 1.8
_273_, 8.62, 32.64, 1.8
_459_, 8.62, 32.64, 1.8
ANTENNA__283__A1, 24.07, 32.64, 1.8
ANTENNA__402__A1, 24.07, 32.64, 1.8
ANTENNA__402__A3, 24.07, 32.64, 1.8
_231_, 24.07, 32.64, 1.8
_279_, 24.07, 32.64, 1.8
clkbuf_1_0__f_net10, 24.07, 32.64, 1.8
ANTENNA__241__A1, 39.57, 32.64, 1.8
_241_, 39.57, 32.64, 1.8
_262_, 39.57, 32.64, 1.8
_346_, 39.57, 32.64, 1.8
_402_, 39.57, 32.64, 1.8
ANTENNA_clkbuf_0_pll_clk_A, 55.07, 32.64, 1.8
_397_, 55.07, 32.64, 1.8
clkbuf_1_0__f_divider2.out, 55.07, 32.64, 1.8
ANTENNA__397__A1, 70.57, 32.64, 1.8
ANTENNA__397__A2, 70.57, 32.64, 1.8
_275_, 70.57, 32.64, 1.8
_387_, 70.57, 32.64, 1.8
_473_, 70.57, 32.64, 1.8
_450_, 86.07, 32.64, 1.8
ANTENNA__306__B, 0.92, 27.2, 1.8
ANTENNA__336__A2, 0.92, 27.2, 1.8
ANTENNA_fanout28_A, 0.92, 27.2, 1.8
FILLER_9_3, 0.92, 27.2, 1.8
PHY_16, 0.92, 27.2, 1.8
PHY_18, 0.92, 27.2, 1.8
_339_, 0.92, 27.2, 1.8
_416__3, 0.92, 27.2, 1.8
_334_, 8.62, 27.2, 1.8
_393_, 8.62, 27.2, 1.8
_458_, 8.62, 27.2, 1.8
ANTENNA__242__A1, 24.07, 27.2, 1.8
ANTENNA__242__S, 24.07, 27.2, 1.8
ANTENNA__335__C, 24.07, 27.2, 1.8
_376_, 24.07, 27.2, 1.8
clkbuf_1_0__f_pll_clk, 24.07, 27.2, 1.8
_229_, 39.57, 27.2, 1.8
_243_, 39.57, 27.2, 1.8
_355_, 39.57, 27.2, 1.8
_378_, 39.57, 27.2, 1.8
_379_, 55.07, 27.2, 1.8
_461_, 55.07, 27.2, 1.8
ANTENNA__473__RESET_B, 70.57, 27.2, 1.8
_445_, 70.57, 27.2, 1.8
_470_, 70.57, 27.2, 1.8
_246_, 86.07, 27.2, 1.8
_350_, 86.07, 27.2, 1.8
_357_, 86.07, 27.2, 1.8
_409_, 86.07, 27.2, 1.8
_410_, 86.07, 27.2, 1.8
FILLER_8_3, 0.92, 21.76, 1.8
PHY_12, 0.92, 21.76, 1.8
PHY_14, 0.92, 21.76, 1.8
FILLER_6_14, 8.62, 21.76, 1.8
FILLER_7_15, 8.62, 21.76, 1.8
FILLER_7_23, 8.62, 21.76, 1.8
ANTENNA__333__A, 24.07, 21.76, 1.8
_215_, 24.07, 21.76, 1.8
_400_, 24.07, 21.76, 1.8
ANTENNA__243__A1, 39.57, 21.76, 1.8
ANTENNA__335__B, 39.57, 21.76, 1.8
_253_, 39.57, 21.76, 1.8
_300_, 39.57, 21.76, 1.8
_309_, 39.57, 21.76, 1.8
_353_, 39.57, 21.76, 1.8
_354_, 39.57, 21.76, 1.8
_264_, 55.07, 21.76, 1.8
_444_, 55.07, 21.76, 1.8
clkbuf_1_0__f_divider.out, 55.07, 21.76, 1.8
_446_, 70.57, 21.76, 1.8
_449_, 70.57, 21.76, 1.8
ANTENNA__466__RESET_B, 86.07, 21.76, 1.8
_348_, 86.07, 21.76, 1.8
_374_, 86.07, 21.76, 1.8
fanout18, 86.07, 21.76, 1.8
FILLER_6_3, 0.92, 16.32, 1.8
PHY_10, 0.92, 16.32, 1.8
PHY_8, 0.92, 16.32, 1.8
FILLER_4_14, 8.62, 16.32, 1.8
_367_, 8.62, 16.32, 1.8
_433_, 8.62, 16.32, 1.8
_213_, 24.07, 16.32, 1.8
_214_, 24.07, 16.32, 1.8
_254_, 24.07, 16.32, 1.8
_301_, 24.07, 16.32, 1.8
_332_, 24.07, 16.32, 1.8
_293_, 39.57, 16.32, 1.8
_321_, 39.57, 16.32, 1.8
_398_, 39.57, 16.32, 1.8
_399_, 39.57, 16.32, 1.8
_401_, 39.57, 16.32, 1.8
_432_, 39.57, 16.32, 1.8
_310_, 55.07, 16.32, 1.8
_312_, 55.07, 16.32, 1.8
_443_, 55.07, 16.32, 1.8
clkbuf_1_1__f_pll_clk, 55.07, 16.32, 1.8
ANTENNA__388__A, 70.57, 16.32, 1.8
ANTENNA__437__SET_B, 70.57, 16.32, 1.8
_390_, 70.57, 16.32, 1.8
_404_, 70.57, 16.32, 1.8
_405_, 70.57, 16.32, 1.8
_437_, 70.57, 16.32, 1.8
_451_, 70.57, 16.32, 1.8
_356_, 86.07, 16.32, 1.8
_362_, 86.07, 16.32, 1.8
_403_, 86.07, 16.32, 1.8
FILLER_4_3, 0.92, 10.88, 1.8
PHY_4, 0.92, 10.88, 1.8
PHY_6, 0.92, 10.88, 1.8
FILLER_3_15, 8.62, 10.88, 1.8
_414__6, 8.62, 10.88, 1.8
_434_, 8.62, 10.88, 1.8
_255_, 24.07, 10.88, 1.8
_287_, 24.07, 10.88, 1.8
_290_, 24.07, 10.88, 1.8
_297_, 24.07, 10.88, 1.8
_322_, 24.07, 10.88, 1.8
_323_, 24.07, 10.88, 1.8
ANTENNA__399__A2, 39.57, 10.88, 1.8
_217_, 39.57, 10.88, 1.8
_429_, 39.57, 10.88, 1.8
fanout19, 39.57, 10.88, 1.8
ANTENNA__276__B1, 55.07, 10.88, 1.8
ANTENNA__401__A2, 55.07, 10.88, 1.8
_269_, 55.07, 10.88, 1.8
_464_, 55.07, 10.88, 1.8
ANTENNA__390__A2, 70.57, 10.88, 1.8
_223_, 70.57, 10.88, 1.8
_302_, 70.57, 10.88, 1.8
_226_, 86.07, 10.88, 1.8
_227_, 86.07, 10.88, 1.8
_328_, 86.07, 10.88, 1.8
_330_, 86.07, 10.88, 1.8
_360_, 86.07, 10.88, 1.8
FILLER_0_3, 0.92, 5.44, 1.8
FILLER_2_3, 0.92, 5.44, 1.8
PHY_0, 0.92, 5.44, 1.8
PHY_2, 0.92, 5.44, 1.8
FILLER_1_15, 8.62, 5.44, 1.8
FILLER_1_23, 8.62, 5.44, 1.8
FILLER_1_56, 24.07, 5.44, 1.8
_250_, 24.07, 5.44, 1.8
_252_, 24.07, 5.44, 1.8
FILLER_0_88, 39.57, 5.44, 1.8
_216_, 39.57, 5.44, 1.8
_218_, 39.57, 5.44, 1.8
_256_, 39.57, 5.44, 1.8
_267_, 39.57, 5.44, 1.8
_364_, 39.57, 5.44, 1.8
ANTENNA_input2_A, 55.07, 5.44, 1.8
FILLER_0_110, 55.07, 5.44, 1.8
FILLER_0_118, 55.07, 5.44, 1.8
_220_, 55.07, 5.44, 1.8
_327_, 55.07, 5.44, 1.8
fanout23, 55.07, 5.44, 1.8
ANTENNA__245__A0, 70.57, 5.44, 1.8
ANTENNA__316__A2, 70.57, 5.44, 1.8
ANTENNA__390__A1, 70.57, 5.44, 1.8
ANTENNA__438__RESET_B, 70.57, 5.44, 1.8
ANTENNA__452__SET_B, 70.57, 5.44, 1.8
_222_, 70.57, 5.44, 1.8
_303_, 70.57, 5.44, 1.8
_372_, 70.57, 5.44, 1.8
_426_, 70.57, 5.44, 1.8
ANTENNA__246__A0, 86.07, 5.44, 1.8
ANTENNA__409__A1, 86.07, 5.44, 1.8
ANTENNA__450__D, 86.07, 5.44, 1.8
_331_, 86.07, 5.44, 1.8
_373_, 86.07, 5.44, 1.8
fanout15, 86.07, 5.44, 1.8
fanout24, 86.07, 5.44, 1.8
input1, 86.07, 5.44, 1.8

78
signoff/caravel_clocking/openlane-signoff/28-gds_ptrs.log Normal file
View File

@ -0,0 +1,78 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 3.0
Library name: caravel_clocking
Reading "sky130_fd_sc_hd__fill_2".
Reading "sky130_ef_sc_hd__decap_12".
Reading "sky130_fd_sc_hd__decap_8".
Reading "sky130_fd_sc_hd__decap_3".
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
Reading "sky130_fd_sc_hd__dfstp_1".
Reading "sky130_fd_sc_hd__inv_2".
Reading "sky130_fd_sc_hd__decap_4".
Reading "sky130_fd_sc_hd__xnor2_1".
Reading "sky130_fd_sc_hd__mux2_1".
Reading "sky130_fd_sc_hd__fill_1".
Reading "sky130_fd_sc_hd__o21ai_1".
Reading "sky130_fd_sc_hd__clkinv_2".
Reading "sky130_fd_sc_hd__diode_2".
Reading "sky130_fd_sc_hd__or3_1".
Reading "sky130_fd_sc_hd__nor3b_2".
Reading "sky130_fd_sc_hd__clkbuf_4".
Reading "sky130_fd_sc_hd__decap_6".
Reading "sky130_fd_sc_hd__nand2_1".
Reading "sky130_fd_sc_hd__o21bai_1".
Reading "sky130_fd_sc_hd__o31a_1".
Reading "sky130_fd_sc_hd__nor3_2".
Reading "sky130_fd_sc_hd__dfxtp_1".
Reading "sky130_fd_sc_hd__clkbuf_1".
Reading "sky130_fd_sc_hd__inv_4".
Reading "sky130_fd_sc_hd__nand3b_1".
Reading "sky130_fd_sc_hd__clkinv_4".
Reading "sky130_fd_sc_hd__a31oi_2".
Reading "sky130_fd_sc_hd__a21o_1".
Reading "sky130_fd_sc_hd__o31ai_1".
Reading "sky130_fd_sc_hd__nor2_1".
Reading "sky130_fd_sc_hd__o21a_1".
Reading "sky130_fd_sc_hd__o2111ai_4".
Reading "sky130_fd_sc_hd__dfrtn_1".
Reading "sky130_fd_sc_hd__dfrtp_2".
Reading "sky130_fd_sc_hd__dfstp_2".
Reading "sky130_fd_sc_hd__a41oi_1".
Reading "sky130_fd_sc_hd__nor3_1".
Reading "sky130_fd_sc_hd__a31o_2".
Reading "sky130_fd_sc_hd__and2_1".
Reading "sky130_fd_sc_hd__dfrtp_1".
Reading "sky130_fd_sc_hd__or2_1".
Reading "sky130_fd_sc_hd__o2111a_1".
Reading "sky130_fd_sc_hd__clkbuf_16".
Reading "sky130_fd_sc_hd__buf_4".
Reading "sky130_fd_sc_hd__o21a_4".
Reading "sky130_fd_sc_hd__o22a_1".
Reading "sky130_fd_sc_hd__a21oi_1".
Reading "sky130_fd_sc_hd__o2111ai_1".
Reading "sky130_fd_sc_hd__nand4b_1".
Reading "sky130_fd_sc_hd__and2b_2".
Reading "sky130_fd_sc_hd__nor4_1".
Reading "sky130_fd_sc_hd__clkbuf_2".
Reading "sky130_fd_sc_hd__nand2b_1".
Reading "sky130_fd_sc_hd__nand3_1".
Reading "sky130_fd_sc_hd__dfrtp_4".
Reading "sky130_fd_sc_hd__buf_12".
Reading "sky130_fd_sc_hd__buf_2".
Reading "sky130_fd_sc_hd__conb_1".
Reading "caravel_clocking".
[INFO]: Wrote /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/gds_ptrs.mag including GDS pointers.

118
signoff/caravel_clocking/openlane-signoff/28-gdsii.log Normal file
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@ -0,0 +1,118 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef.
This action cannot be undone.
LEF read, Line 78 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 79 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 115 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 121 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 122 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 123 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 156 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 165 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 167 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 168 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 169 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 206 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 207 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 210 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 211 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 248 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 249 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 251 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 252 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 253 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 797 lines.
Reading DEF data from file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def.
This action cannot be undone.
Processed 4 vias total.
Processed 734 subcell instances total.
Processed 17 pins total.
Processed 2 special nets total.
Processed 330 nets total.
DEF read: Processed 7840 lines.
Root cell box:
width x height ( llx, lly ), ( urx, ury ) area (units^2)
microns: 100.000 x 60.000 ( 0.000, 0.000), ( 100.000, 60.000) 6000.000
lambda: 10000.00 x 6000.00 ( 0.00, 0.00 ), ( 10000.00, 6000.00) 60000000.00
internal: 20000 x 12000 ( 0, 0 ), ( 20000, 12000) 240000000
Generating output for cell sky130_fd_sc_hd__fill_2
Generating output for cell sky130_ef_sc_hd__decap_12
Generating output for cell sky130_fd_sc_hd__decap_8
Generating output for cell sky130_fd_sc_hd__decap_3
Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
Generating output for cell sky130_fd_sc_hd__dfstp_1
Generating output for cell sky130_fd_sc_hd__inv_2
Generating output for cell sky130_fd_sc_hd__decap_4
Generating output for cell sky130_fd_sc_hd__xnor2_1
Generating output for cell sky130_fd_sc_hd__mux2_1
Generating output for cell sky130_fd_sc_hd__fill_1
Generating output for cell sky130_fd_sc_hd__o21ai_1
Generating output for cell sky130_fd_sc_hd__clkinv_2
Generating output for cell sky130_fd_sc_hd__diode_2
Generating output for cell sky130_fd_sc_hd__or3_1
Generating output for cell sky130_fd_sc_hd__nor3b_2
Generating output for cell sky130_fd_sc_hd__clkbuf_4
Generating output for cell sky130_fd_sc_hd__decap_6
Generating output for cell sky130_fd_sc_hd__nand2_1
Generating output for cell sky130_fd_sc_hd__o21bai_1
Generating output for cell sky130_fd_sc_hd__o31a_1
Generating output for cell sky130_fd_sc_hd__nor3_2
Generating output for cell sky130_fd_sc_hd__dfxtp_1
Generating output for cell sky130_fd_sc_hd__clkbuf_1
Generating output for cell sky130_fd_sc_hd__inv_4
Generating output for cell sky130_fd_sc_hd__nand3b_1
Generating output for cell sky130_fd_sc_hd__clkinv_4
Generating output for cell sky130_fd_sc_hd__a31oi_2
Generating output for cell sky130_fd_sc_hd__a21o_1
Generating output for cell sky130_fd_sc_hd__o31ai_1
Generating output for cell sky130_fd_sc_hd__nor2_1
Generating output for cell sky130_fd_sc_hd__o21a_1
Generating output for cell sky130_fd_sc_hd__o2111ai_4
Generating output for cell sky130_fd_sc_hd__dfrtn_1
Generating output for cell sky130_fd_sc_hd__dfrtp_2
Generating output for cell sky130_fd_sc_hd__dfstp_2
Generating output for cell sky130_fd_sc_hd__a41oi_1
Generating output for cell sky130_fd_sc_hd__nor3_1
Generating output for cell sky130_fd_sc_hd__a31o_2
Generating output for cell sky130_fd_sc_hd__and2_1
Generating output for cell sky130_fd_sc_hd__dfrtp_1
Generating output for cell sky130_fd_sc_hd__or2_1
Generating output for cell sky130_fd_sc_hd__o2111a_1
Generating output for cell sky130_fd_sc_hd__clkbuf_16
Generating output for cell sky130_fd_sc_hd__buf_4
Generating output for cell sky130_fd_sc_hd__o21a_4
Generating output for cell sky130_fd_sc_hd__o22a_1
Generating output for cell sky130_fd_sc_hd__a21oi_1
Generating output for cell sky130_fd_sc_hd__o2111ai_1
Generating output for cell sky130_fd_sc_hd__nand4b_1
Generating output for cell sky130_fd_sc_hd__and2b_2
Generating output for cell sky130_fd_sc_hd__nor4_1
Generating output for cell sky130_fd_sc_hd__clkbuf_2
Generating output for cell sky130_fd_sc_hd__nand2b_1
Generating output for cell sky130_fd_sc_hd__nand3_1
Generating output for cell sky130_fd_sc_hd__dfrtp_4
Generating output for cell sky130_fd_sc_hd__buf_12
Generating output for cell sky130_fd_sc_hd__buf_2
Generating output for cell sky130_fd_sc_hd__conb_1
Generating output for cell caravel_clocking
[INFO]: GDS Write Complete

228
signoff/caravel_clocking/openlane-signoff/28-lef.log Normal file
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@ -0,0 +1,228 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef.
This action cannot be undone.
LEF read, Line 78 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 79 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 115 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 121 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 122 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 123 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 156 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 165 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 167 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 168 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 169 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 206 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 207 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 210 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 211 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 248 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 249 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 251 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 252 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 253 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 797 lines.
caravel_clocking: 10000 rects
caravel_clocking: 20000 rects
[INFO]: Writing abstract LEF
Generating LEF output /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/caravel_clocking.lef for cell caravel_clocking:
Diagnostic: Write LEF header for cell caravel_clocking
Diagnostic: Writing LEF output for cell caravel_clocking
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_16" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__clkbuf_16.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_16.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__buf_12" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__buf_12.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__buf_12.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__clkbuf_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_4" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__clkbuf_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__buf_4" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__buf_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__buf_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__buf_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__buf_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__buf_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__clkbuf_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__dfrtp_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__dfrtp_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfstp_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__dfstp_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__dfstp_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfstp_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__dfstp_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__dfstp_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_4" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__dfrtp_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__dfrtp_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfrtn_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__dfrtn_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__dfrtn_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfxtp_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__dfxtp_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__dfxtp_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__dfrtp_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__dfrtp_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__conb_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__conb_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__conb_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__inv_4" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__inv_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__inv_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__or2_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__or2_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__or2_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o31a_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o31a_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o31a_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor4_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nor4_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nor4_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__mux2_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__mux2_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__mux2_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21ai_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o21ai_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o21ai_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21oi_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__a21oi_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a21oi_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o2111ai_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o2111ai_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21bai_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o21bai_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o21bai_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o31ai_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o31ai_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o31ai_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand3b_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nand3b_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nand3b_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o22a_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o22a_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o22a_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand3_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nand3_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nand3_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2b_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nand2b_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nand2b_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nand2_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nand2_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand4b_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nand4b_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nand4b_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__and2_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__and2_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor2_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nor2_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nor2_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__xnor2_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__xnor2_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__xnor2_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__or3_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__or3_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__or3_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21o_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__a21o_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a21o_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21a_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o21a_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o21a_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor3_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nor3_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nor3_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a31o_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__a31o_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a31o_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2b_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__and2b_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__and2b_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor3_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nor3_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nor3_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a31oi_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__a31oi_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a31oi_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a41oi_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__a41oi_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a41oi_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2111a_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o2111a_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o2111a_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor3b_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__nor3b_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nor3b_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__inv_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__inv_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__inv_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2111ai_4" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o2111ai_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o2111ai_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21a_4" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__o21a_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o21a_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkinv_4" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__clkinv_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkinv_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkinv_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__clkinv_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkinv_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__tapvpwrvgnd_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__tapvpwrvgnd_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__tapvpwrvgnd_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_3" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__decap_3.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_3.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_1" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__fill_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__fill_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_8" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__decap_8.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_8.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_ef_sc_hd__decap_12" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_ef_sc_hd__decap_12.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_ef_sc_hd__decap_12.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_4" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__decap_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_6" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__decap_6.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_6.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__diode_2" at bad file path /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/sky130_fd_sc_hd__diode_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__diode_2.mag.
The discovered version will be used.
Diagnostic: Scale value is 0.005000
[INFO]: LEF Write Complete

18
signoff/caravel_clocking/openlane-signoff/28-maglef.log Normal file
View File

@ -0,0 +1,18 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/caravel_clocking.lef.
This action cannot be undone.
LEF read: Processed 240 lines.
[INFO]: DONE GENERATING MAGLEF VIEW

115
signoff/caravel_clocking/openlane-signoff/29-spice.log Normal file
View File

@ -0,0 +1,115 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef.
This action cannot be undone.
LEF read, Line 78 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 79 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 115 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 121 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 122 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 123 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 156 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 165 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 167 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 168 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 169 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 206 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 207 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 210 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 211 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 248 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 249 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 251 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 252 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 253 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 797 lines.
Reading DEF data from file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def.
This action cannot be undone.
Processed 4 vias total.
Processed 734 subcell instances total.
Processed 17 pins total.
Processed 2 special nets total.
Processed 330 nets total.
DEF read: Processed 7840 lines.
Processing caravel_clocking
Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
Extracting sky130_ef_sc_hd__decap_12 into sky130_ef_sc_hd__decap_12.ext:
Extracting sky130_fd_sc_hd__decap_8 into sky130_fd_sc_hd__decap_8.ext:
Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:
Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
Extracting sky130_fd_sc_hd__dfstp_1 into sky130_fd_sc_hd__dfstp_1.ext:
Extracting sky130_fd_sc_hd__inv_2 into sky130_fd_sc_hd__inv_2.ext:
Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
Extracting sky130_fd_sc_hd__xnor2_1 into sky130_fd_sc_hd__xnor2_1.ext:
Extracting sky130_fd_sc_hd__mux2_1 into sky130_fd_sc_hd__mux2_1.ext:
Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:
Extracting sky130_fd_sc_hd__o21ai_1 into sky130_fd_sc_hd__o21ai_1.ext:
Extracting sky130_fd_sc_hd__clkinv_2 into sky130_fd_sc_hd__clkinv_2.ext:
Extracting sky130_fd_sc_hd__diode_2 into sky130_fd_sc_hd__diode_2.ext:
Extracting sky130_fd_sc_hd__or3_1 into sky130_fd_sc_hd__or3_1.ext:
Extracting sky130_fd_sc_hd__nor3b_2 into sky130_fd_sc_hd__nor3b_2.ext:
Extracting sky130_fd_sc_hd__clkbuf_4 into sky130_fd_sc_hd__clkbuf_4.ext:
Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext:
Extracting sky130_fd_sc_hd__nand2_1 into sky130_fd_sc_hd__nand2_1.ext:
Extracting sky130_fd_sc_hd__o21bai_1 into sky130_fd_sc_hd__o21bai_1.ext:
Extracting sky130_fd_sc_hd__o31a_1 into sky130_fd_sc_hd__o31a_1.ext:
Extracting sky130_fd_sc_hd__nor3_2 into sky130_fd_sc_hd__nor3_2.ext:
Extracting sky130_fd_sc_hd__dfxtp_1 into sky130_fd_sc_hd__dfxtp_1.ext:
Extracting sky130_fd_sc_hd__clkbuf_1 into sky130_fd_sc_hd__clkbuf_1.ext:
Extracting sky130_fd_sc_hd__inv_4 into sky130_fd_sc_hd__inv_4.ext:
Extracting sky130_fd_sc_hd__nand3b_1 into sky130_fd_sc_hd__nand3b_1.ext:
Extracting sky130_fd_sc_hd__clkinv_4 into sky130_fd_sc_hd__clkinv_4.ext:
Extracting sky130_fd_sc_hd__a31oi_2 into sky130_fd_sc_hd__a31oi_2.ext:
Extracting sky130_fd_sc_hd__a21o_1 into sky130_fd_sc_hd__a21o_1.ext:
Extracting sky130_fd_sc_hd__o31ai_1 into sky130_fd_sc_hd__o31ai_1.ext:
Extracting sky130_fd_sc_hd__nor2_1 into sky130_fd_sc_hd__nor2_1.ext:
Extracting sky130_fd_sc_hd__o21a_1 into sky130_fd_sc_hd__o21a_1.ext:
Extracting sky130_fd_sc_hd__o2111ai_4 into sky130_fd_sc_hd__o2111ai_4.ext:
Extracting sky130_fd_sc_hd__dfrtn_1 into sky130_fd_sc_hd__dfrtn_1.ext:
Extracting sky130_fd_sc_hd__dfrtp_2 into sky130_fd_sc_hd__dfrtp_2.ext:
Extracting sky130_fd_sc_hd__dfstp_2 into sky130_fd_sc_hd__dfstp_2.ext:
Extracting sky130_fd_sc_hd__a41oi_1 into sky130_fd_sc_hd__a41oi_1.ext:
Extracting sky130_fd_sc_hd__nor3_1 into sky130_fd_sc_hd__nor3_1.ext:
Extracting sky130_fd_sc_hd__a31o_2 into sky130_fd_sc_hd__a31o_2.ext:
Extracting sky130_fd_sc_hd__and2_1 into sky130_fd_sc_hd__and2_1.ext:
Extracting sky130_fd_sc_hd__dfrtp_1 into sky130_fd_sc_hd__dfrtp_1.ext:
Extracting sky130_fd_sc_hd__or2_1 into sky130_fd_sc_hd__or2_1.ext:
Extracting sky130_fd_sc_hd__o2111a_1 into sky130_fd_sc_hd__o2111a_1.ext:
Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext:
Extracting sky130_fd_sc_hd__buf_4 into sky130_fd_sc_hd__buf_4.ext:
Extracting sky130_fd_sc_hd__o21a_4 into sky130_fd_sc_hd__o21a_4.ext:
Extracting sky130_fd_sc_hd__o22a_1 into sky130_fd_sc_hd__o22a_1.ext:
Extracting sky130_fd_sc_hd__a21oi_1 into sky130_fd_sc_hd__a21oi_1.ext:
Extracting sky130_fd_sc_hd__o2111ai_1 into sky130_fd_sc_hd__o2111ai_1.ext:
Extracting sky130_fd_sc_hd__nand4b_1 into sky130_fd_sc_hd__nand4b_1.ext:
Extracting sky130_fd_sc_hd__and2b_2 into sky130_fd_sc_hd__and2b_2.ext:
Extracting sky130_fd_sc_hd__nor4_1 into sky130_fd_sc_hd__nor4_1.ext:
Extracting sky130_fd_sc_hd__clkbuf_2 into sky130_fd_sc_hd__clkbuf_2.ext:
Extracting sky130_fd_sc_hd__nand2b_1 into sky130_fd_sc_hd__nand2b_1.ext:
Extracting sky130_fd_sc_hd__nand3_1 into sky130_fd_sc_hd__nand3_1.ext:
Extracting sky130_fd_sc_hd__dfrtp_4 into sky130_fd_sc_hd__dfrtp_4.ext:
Extracting sky130_fd_sc_hd__buf_12 into sky130_fd_sc_hd__buf_12.ext:
Extracting sky130_fd_sc_hd__buf_2 into sky130_fd_sc_hd__buf_2.ext:
Extracting sky130_fd_sc_hd__conb_1 into sky130_fd_sc_hd__conb_1.ext:
Extracting caravel_clocking into caravel_clocking.ext:
caravel_clocking: 130 errors
Total of 130 errors (check feedback entries).
exttospice finished.

25
signoff/caravel_clocking/openlane-signoff/30-write_powered_def.log Normal file
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@ -0,0 +1,25 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.nom.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
[INFO ODB-0128] Design: caravel_clocking
[INFO ODB-0130] Created 17 pins.
[INFO ODB-0131] Created 734 components and 3799 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2622 connections.
[INFO ODB-0133] Created 330 nets and 1176 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.def
Top-level design name: caravel_clocking
Found default power net 'VPWR'
Found default ground net 'VGND'
Found 1 power ports.
Found 1 ground ports.
Modified power connections of 734/734 cells.

8
signoff/caravel_clocking/openlane-signoff/30-write_powered_verilog.log Normal file
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@ -0,0 +1,8 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Reading /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.odb
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing netlist to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/29-caravel_clocking.nl.v...
Writing powered netlist to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/29-caravel_clocking.pnl.v...

3
signoff/caravel_clocking/openlane-signoff/32-caravel_clocking.lef-count.log Normal file
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LVS reports no net, device, pin, or property mismatches.
Total errors = 0

1425
signoff/caravel_clocking/openlane-signoff/32-caravel_clocking.lef.json Normal file
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File diff suppressed because it is too large Load Diff

1104
signoff/caravel_clocking/openlane-signoff/32-caravel_clocking.lef.log Normal file
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File diff suppressed because it is too large Load Diff

391
signoff/caravel_clocking/openlane-signoff/32-lvs.lef.log Normal file
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@ -0,0 +1,391 @@
Netgen 1.5.234 compiled on Sun Oct 9 10:24:01 UTC 2022
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Generating JSON file result
Reading netlist file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/caravel_clocking.spice
Reading netlist file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/29-caravel_clocking.pnl.v
Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module sky130_fd_sc_hd__mux2_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkinv_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__inv_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkinv_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__inv_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__nor2_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__o21a_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__o2111ai_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__nor3b_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__o2111a_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__a41oi_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__o21ai_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__a31oi_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__nand3b_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__nand2_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__or2_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__nor3_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__and2b_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__a31o_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__xnor2_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__nor3_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__o21a_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__a21o_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__or3_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__o2111ai_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__a21oi_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__nand4b_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__nand2b_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__nand3_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__and2_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__o22a_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__o31ai_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__o21bai_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__o31a_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__nor4_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_16.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfstp_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfrtp_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfxtp_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfrtn_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfstp_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfrtp_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfrtp_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_3.
Creating placeholder cell definition for module sky130_fd_sc_hd__tapvpwrvgnd_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__buf_12.
Creating placeholder cell definition for module sky130_fd_sc_hd__diode_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__buf_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__buf_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__conb_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_8.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_2.
Creating placeholder cell definition for module sky130_ef_sc_hd__decap_12.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_6.
Reading setup file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
Comparison output logged to file /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/logs/signoff/32-caravel_clocking.lef.log
Logging to file "/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/logs/signoff/32-caravel_clocking.lef.log" enabled
Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices.
Circuit sky130_fd_sc_hd__fill_1 contains no devices.
Circuit sky130_fd_sc_hd__a41oi_1 contains no devices.
Circuit sky130_fd_sc_hd__nand3b_1 contains no devices.
Circuit sky130_fd_sc_hd__dfstp_1 contains no devices.
Circuit sky130_fd_sc_hd__o21ai_1 contains no devices.
Circuit sky130_fd_sc_hd__o2111ai_4 contains no devices.
Circuit sky130_fd_sc_hd__or3_1 contains no devices.
Circuit sky130_fd_sc_hd__clkbuf_16 contains no devices.
Circuit sky130_fd_sc_hd__diode_2 contains no devices.
Circuit sky130_fd_sc_hd__fill_2 contains no devices.
Circuit sky130_fd_sc_hd__dfrtn_1 contains no devices.
Circuit sky130_fd_sc_hd__o2111a_1 contains no devices.
Circuit sky130_fd_sc_hd__o22a_1 contains no devices.
Circuit sky130_fd_sc_hd__o21a_4 contains no devices.
Circuit sky130_ef_sc_hd__decap_12 contains no devices.
Circuit sky130_fd_sc_hd__xnor2_1 contains no devices.
Circuit sky130_fd_sc_hd__clkinv_4 contains no devices.
Circuit sky130_fd_sc_hd__nor3b_2 contains no devices.
Circuit sky130_fd_sc_hd__nor2_1 contains no devices.
Circuit sky130_fd_sc_hd__clkinv_2 contains no devices.
Circuit sky130_fd_sc_hd__nand2_1 contains no devices.
Circuit sky130_fd_sc_hd__decap_4 contains no devices.
Circuit sky130_fd_sc_hd__buf_12 contains no devices.
Circuit sky130_fd_sc_hd__inv_2 contains no devices.
Circuit sky130_fd_sc_hd__and2_1 contains no devices.
Circuit sky130_fd_sc_hd__and2b_2 contains no devices.
Circuit sky130_fd_sc_hd__mux2_1 contains no devices.
Circuit sky130_fd_sc_hd__nor3_2 contains no devices.
Circuit sky130_fd_sc_hd__or2_1 contains no devices.
Circuit sky130_fd_sc_hd__inv_4 contains no devices.
Circuit sky130_fd_sc_hd__decap_3 contains no devices.
Circuit sky130_fd_sc_hd__a21o_1 contains no devices.
Circuit sky130_fd_sc_hd__dfrtp_1 contains no devices.
Circuit sky130_fd_sc_hd__o21bai_1 contains no devices.
Circuit sky130_fd_sc_hd__o21a_1 contains no devices.
Circuit sky130_fd_sc_hd__o31ai_1 contains no devices.
Circuit sky130_fd_sc_hd__dfxtp_1 contains no devices.
Circuit sky130_fd_sc_hd__dfstp_2 contains no devices.
Circuit sky130_fd_sc_hd__clkbuf_2 contains no devices.
Circuit sky130_fd_sc_hd__clkbuf_4 contains no devices.
Circuit sky130_fd_sc_hd__o31a_1 contains no devices.
Circuit sky130_fd_sc_hd__nor4_1 contains no devices.
Circuit sky130_fd_sc_hd__decap_8 contains no devices.
Circuit sky130_fd_sc_hd__clkbuf_1 contains no devices.
Circuit sky130_fd_sc_hd__dfrtp_4 contains no devices.
Circuit sky130_fd_sc_hd__nand3_1 contains no devices.
Circuit sky130_fd_sc_hd__buf_4 contains no devices.
Circuit sky130_fd_sc_hd__nand2b_1 contains no devices.
Circuit sky130_fd_sc_hd__buf_2 contains no devices.
Circuit sky130_fd_sc_hd__nand4b_1 contains no devices.
Circuit sky130_fd_sc_hd__nor3_1 contains no devices.
Circuit sky130_fd_sc_hd__a31oi_2 contains no devices.
Circuit sky130_fd_sc_hd__a21oi_1 contains no devices.
Circuit sky130_fd_sc_hd__o2111ai_1 contains no devices.
Circuit sky130_fd_sc_hd__decap_6 contains no devices.
Circuit sky130_fd_sc_hd__a31o_2 contains no devices.
Circuit sky130_fd_sc_hd__dfrtp_2 contains no devices.
Circuit sky130_fd_sc_hd__conb_1 contains no devices.
Contents of circuit 1: Circuit: 'caravel_clocking'
Circuit caravel_clocking contains 734 device instances.
Class: sky130_fd_sc_hd__o2111ai_1 instances: 2
Class: sky130_fd_sc_hd__o2111ai_4 instances: 2
Class: sky130_fd_sc_hd__a31o_2 instances: 2
Class: sky130_fd_sc_hd__a21o_1 instances: 2
Class: sky130_fd_sc_hd__clkbuf_16 instances: 22
Class: sky130_fd_sc_hd__dfxtp_1 instances: 7
Class: sky130_fd_sc_hd__o31ai_1 instances: 2
Class: sky130_fd_sc_hd__a31oi_2 instances: 2
Class: sky130_fd_sc_hd__buf_2 instances: 1
Class: sky130_fd_sc_hd__buf_4 instances: 3
Class: sky130_fd_sc_hd__dfstp_1 instances: 17
Class: sky130_fd_sc_hd__dfstp_2 instances: 4
Class: sky130_ef_sc_hd__decap_12 instances: 9
Class: sky130_fd_sc_hd__dfrtp_1 instances: 19
Class: sky130_fd_sc_hd__dfrtp_2 instances: 1
Class: sky130_fd_sc_hd__dfrtp_4 instances: 1
Class: sky130_fd_sc_hd__inv_2 instances: 14
Class: sky130_fd_sc_hd__inv_4 instances: 9
Class: sky130_fd_sc_hd__clkbuf_1 instances: 9
Class: sky130_fd_sc_hd__clkbuf_2 instances: 2
Class: sky130_fd_sc_hd__clkbuf_4 instances: 11
Class: sky130_fd_sc_hd__or3_1 instances: 4
Class: sky130_fd_sc_hd__nand3_1 instances: 3
Class: sky130_fd_sc_hd__conb_1 instances: 1
Class: sky130_fd_sc_hd__and2b_2 instances: 2
Class: sky130_fd_sc_hd__nand4b_1 instances: 2
Class: sky130_fd_sc_hd__buf_12 instances: 1
Class: sky130_fd_sc_hd__clkinv_2 instances: 4
Class: sky130_fd_sc_hd__clkinv_4 instances: 7
Class: sky130_fd_sc_hd__decap_3 instances: 44
Class: sky130_fd_sc_hd__decap_4 instances: 8
Class: sky130_fd_sc_hd__decap_6 instances: 1
Class: sky130_fd_sc_hd__decap_8 instances: 10
Class: sky130_fd_sc_hd__or2_1 instances: 6
Class: sky130_fd_sc_hd__nand2_1 instances: 10
Class: sky130_fd_sc_hd__nand3b_1 instances: 6
Class: sky130_fd_sc_hd__mux2_1 instances: 52
Class: sky130_fd_sc_hd__dfrtn_1 instances: 8
Class: sky130_fd_sc_hd__and2_1 instances: 1
Class: sky130_fd_sc_hd__nor4_1 instances: 2
Class: sky130_fd_sc_hd__o22a_1 instances: 2
Class: sky130_fd_sc_hd__xnor2_1 instances: 10
Class: sky130_fd_sc_hd__nor3b_2 instances: 2
Class: sky130_fd_sc_hd__o21bai_1 instances: 4
Class: sky130_fd_sc_hd__nand2b_1 instances: 6
Class: sky130_fd_sc_hd__diode_2 instances: 93
Class: sky130_fd_sc_hd__o2111a_1 instances: 2
Class: sky130_fd_sc_hd__nor3_1 instances: 2
Class: sky130_fd_sc_hd__nor3_2 instances: 2
Class: sky130_fd_sc_hd__o31a_1 instances: 6
Class: sky130_fd_sc_hd__o21a_1 instances: 4
Class: sky130_fd_sc_hd__o21a_4 instances: 2
Class: sky130_fd_sc_hd__a41oi_1 instances: 2
Class: sky130_fd_sc_hd__o21ai_1 instances: 19
Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 157
Class: sky130_fd_sc_hd__a21oi_1 instances: 2
Class: sky130_fd_sc_hd__fill_1 instances: 80
Class: sky130_fd_sc_hd__fill_2 instances: 14
Class: sky130_fd_sc_hd__nor2_1 instances: 12
Circuit contains 333 nets.
Contents of circuit 2: Circuit: 'caravel_clocking'
Circuit caravel_clocking contains 734 device instances.
Class: sky130_fd_sc_hd__o2111ai_1 instances: 2
Class: sky130_fd_sc_hd__o2111ai_4 instances: 2
Class: sky130_fd_sc_hd__a31o_2 instances: 2
Class: sky130_fd_sc_hd__a21o_1 instances: 2
Class: sky130_fd_sc_hd__clkbuf_16 instances: 22
Class: sky130_fd_sc_hd__dfxtp_1 instances: 7
Class: sky130_fd_sc_hd__o31ai_1 instances: 2
Class: sky130_fd_sc_hd__a31oi_2 instances: 2
Class: sky130_fd_sc_hd__buf_2 instances: 1
Class: sky130_fd_sc_hd__buf_4 instances: 3
Class: sky130_fd_sc_hd__dfstp_1 instances: 17
Class: sky130_fd_sc_hd__dfstp_2 instances: 4
Class: sky130_ef_sc_hd__decap_12 instances: 9
Class: sky130_fd_sc_hd__dfrtp_1 instances: 19
Class: sky130_fd_sc_hd__dfrtp_2 instances: 1
Class: sky130_fd_sc_hd__dfrtp_4 instances: 1
Class: sky130_fd_sc_hd__inv_2 instances: 14
Class: sky130_fd_sc_hd__inv_4 instances: 9
Class: sky130_fd_sc_hd__clkbuf_1 instances: 9
Class: sky130_fd_sc_hd__clkbuf_2 instances: 2
Class: sky130_fd_sc_hd__clkbuf_4 instances: 11
Class: sky130_fd_sc_hd__or3_1 instances: 4
Class: sky130_fd_sc_hd__nand3_1 instances: 3
Class: sky130_fd_sc_hd__conb_1 instances: 1
Class: sky130_fd_sc_hd__and2b_2 instances: 2
Class: sky130_fd_sc_hd__nand4b_1 instances: 2
Class: sky130_fd_sc_hd__buf_12 instances: 1
Class: sky130_fd_sc_hd__clkinv_2 instances: 4
Class: sky130_fd_sc_hd__clkinv_4 instances: 7
Class: sky130_fd_sc_hd__decap_3 instances: 44
Class: sky130_fd_sc_hd__decap_4 instances: 8
Class: sky130_fd_sc_hd__decap_6 instances: 1
Class: sky130_fd_sc_hd__decap_8 instances: 10
Class: sky130_fd_sc_hd__or2_1 instances: 6
Class: sky130_fd_sc_hd__nand2_1 instances: 10
Class: sky130_fd_sc_hd__nand3b_1 instances: 6
Class: sky130_fd_sc_hd__mux2_1 instances: 52
Class: sky130_fd_sc_hd__dfrtn_1 instances: 8
Class: sky130_fd_sc_hd__and2_1 instances: 1
Class: sky130_fd_sc_hd__nor4_1 instances: 2
Class: sky130_fd_sc_hd__o22a_1 instances: 2
Class: sky130_fd_sc_hd__xnor2_1 instances: 10
Class: sky130_fd_sc_hd__nor3b_2 instances: 2
Class: sky130_fd_sc_hd__o21bai_1 instances: 4
Class: sky130_fd_sc_hd__nand2b_1 instances: 6
Class: sky130_fd_sc_hd__diode_2 instances: 93
Class: sky130_fd_sc_hd__o2111a_1 instances: 2
Class: sky130_fd_sc_hd__nor3_1 instances: 2
Class: sky130_fd_sc_hd__nor3_2 instances: 2
Class: sky130_fd_sc_hd__o31a_1 instances: 6
Class: sky130_fd_sc_hd__o21a_1 instances: 4
Class: sky130_fd_sc_hd__o21a_4 instances: 2
Class: sky130_fd_sc_hd__a41oi_1 instances: 2
Class: sky130_fd_sc_hd__o21ai_1 instances: 19
Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 157
Class: sky130_fd_sc_hd__a21oi_1 instances: 2
Class: sky130_fd_sc_hd__fill_1 instances: 80
Class: sky130_fd_sc_hd__fill_2 instances: 14
Class: sky130_fd_sc_hd__nor2_1 instances: 12
Circuit contains 333 nets.
Circuit was modified by parallel/series device merging.
New circuit summary:
Contents of circuit 1: Circuit: 'caravel_clocking'
Circuit caravel_clocking contains 345 device instances.
Class: sky130_fd_sc_hd__o2111ai_1 instances: 2
Class: sky130_fd_sc_hd__o2111ai_4 instances: 2
Class: sky130_fd_sc_hd__a31o_2 instances: 2
Class: sky130_fd_sc_hd__a21o_1 instances: 2
Class: sky130_fd_sc_hd__clkbuf_16 instances: 22
Class: sky130_fd_sc_hd__dfxtp_1 instances: 7
Class: sky130_fd_sc_hd__o31ai_1 instances: 2
Class: sky130_fd_sc_hd__a31oi_2 instances: 2
Class: sky130_fd_sc_hd__buf_2 instances: 1
Class: sky130_fd_sc_hd__buf_4 instances: 3
Class: sky130_fd_sc_hd__dfstp_1 instances: 17
Class: sky130_fd_sc_hd__dfstp_2 instances: 4
Class: sky130_ef_sc_hd__decap_12 instances: 1
Class: sky130_fd_sc_hd__dfrtp_1 instances: 19
Class: sky130_fd_sc_hd__dfrtp_2 instances: 1
Class: sky130_fd_sc_hd__dfrtp_4 instances: 1
Class: sky130_fd_sc_hd__inv_2 instances: 14
Class: sky130_fd_sc_hd__inv_4 instances: 9
Class: sky130_fd_sc_hd__clkbuf_1 instances: 9
Class: sky130_fd_sc_hd__clkbuf_2 instances: 2
Class: sky130_fd_sc_hd__clkbuf_4 instances: 11
Class: sky130_fd_sc_hd__or3_1 instances: 4
Class: sky130_fd_sc_hd__nand3_1 instances: 3
Class: sky130_fd_sc_hd__conb_1 instances: 1
Class: sky130_fd_sc_hd__and2b_2 instances: 2
Class: sky130_fd_sc_hd__nand4b_1 instances: 2
Class: sky130_fd_sc_hd__buf_12 instances: 1
Class: sky130_fd_sc_hd__clkinv_2 instances: 4
Class: sky130_fd_sc_hd__clkinv_4 instances: 7
Class: sky130_fd_sc_hd__decap_3 instances: 1
Class: sky130_fd_sc_hd__decap_4 instances: 1
Class: sky130_fd_sc_hd__decap_6 instances: 1
Class: sky130_fd_sc_hd__decap_8 instances: 1
Class: sky130_fd_sc_hd__or2_1 instances: 6
Class: sky130_fd_sc_hd__nand2_1 instances: 10
Class: sky130_fd_sc_hd__nand3b_1 instances: 6
Class: sky130_fd_sc_hd__mux2_1 instances: 52
Class: sky130_fd_sc_hd__dfrtn_1 instances: 8
Class: sky130_fd_sc_hd__and2_1 instances: 1
Class: sky130_fd_sc_hd__nor4_1 instances: 2
Class: sky130_fd_sc_hd__o22a_1 instances: 2
Class: sky130_fd_sc_hd__xnor2_1 instances: 10
Class: sky130_fd_sc_hd__nor3b_2 instances: 2
Class: sky130_fd_sc_hd__o21bai_1 instances: 4
Class: sky130_fd_sc_hd__nand2b_1 instances: 6
Class: sky130_fd_sc_hd__diode_2 instances: 19
Class: sky130_fd_sc_hd__o2111a_1 instances: 2
Class: sky130_fd_sc_hd__nor3_1 instances: 2
Class: sky130_fd_sc_hd__nor3_2 instances: 2
Class: sky130_fd_sc_hd__o31a_1 instances: 6
Class: sky130_fd_sc_hd__o21a_1 instances: 4
Class: sky130_fd_sc_hd__o21a_4 instances: 2
Class: sky130_fd_sc_hd__a41oi_1 instances: 2
Class: sky130_fd_sc_hd__o21ai_1 instances: 19
Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1
Class: sky130_fd_sc_hd__a21oi_1 instances: 2
Class: sky130_fd_sc_hd__fill_1 instances: 1
Class: sky130_fd_sc_hd__fill_2 instances: 1
Class: sky130_fd_sc_hd__nor2_1 instances: 12
Circuit contains 333 nets.
Contents of circuit 2: Circuit: 'caravel_clocking'
Circuit caravel_clocking contains 345 device instances.
Class: sky130_fd_sc_hd__o2111ai_1 instances: 2
Class: sky130_fd_sc_hd__o2111ai_4 instances: 2
Class: sky130_fd_sc_hd__a31o_2 instances: 2
Class: sky130_fd_sc_hd__a21o_1 instances: 2
Class: sky130_fd_sc_hd__clkbuf_16 instances: 22
Class: sky130_fd_sc_hd__dfxtp_1 instances: 7
Class: sky130_fd_sc_hd__o31ai_1 instances: 2
Class: sky130_fd_sc_hd__a31oi_2 instances: 2
Class: sky130_fd_sc_hd__buf_2 instances: 1
Class: sky130_fd_sc_hd__buf_4 instances: 3
Class: sky130_fd_sc_hd__dfstp_1 instances: 17
Class: sky130_fd_sc_hd__dfstp_2 instances: 4
Class: sky130_ef_sc_hd__decap_12 instances: 1
Class: sky130_fd_sc_hd__dfrtp_1 instances: 19
Class: sky130_fd_sc_hd__dfrtp_2 instances: 1
Class: sky130_fd_sc_hd__dfrtp_4 instances: 1
Class: sky130_fd_sc_hd__inv_2 instances: 14
Class: sky130_fd_sc_hd__inv_4 instances: 9
Class: sky130_fd_sc_hd__clkbuf_1 instances: 9
Class: sky130_fd_sc_hd__clkbuf_2 instances: 2
Class: sky130_fd_sc_hd__clkbuf_4 instances: 11
Class: sky130_fd_sc_hd__or3_1 instances: 4
Class: sky130_fd_sc_hd__nand3_1 instances: 3
Class: sky130_fd_sc_hd__conb_1 instances: 1
Class: sky130_fd_sc_hd__and2b_2 instances: 2
Class: sky130_fd_sc_hd__nand4b_1 instances: 2
Class: sky130_fd_sc_hd__buf_12 instances: 1
Class: sky130_fd_sc_hd__clkinv_2 instances: 4
Class: sky130_fd_sc_hd__clkinv_4 instances: 7
Class: sky130_fd_sc_hd__decap_3 instances: 1
Class: sky130_fd_sc_hd__decap_4 instances: 1
Class: sky130_fd_sc_hd__decap_6 instances: 1
Class: sky130_fd_sc_hd__decap_8 instances: 1
Class: sky130_fd_sc_hd__or2_1 instances: 6
Class: sky130_fd_sc_hd__nand2_1 instances: 10
Class: sky130_fd_sc_hd__nand3b_1 instances: 6
Class: sky130_fd_sc_hd__mux2_1 instances: 52
Class: sky130_fd_sc_hd__dfrtn_1 instances: 8
Class: sky130_fd_sc_hd__and2_1 instances: 1
Class: sky130_fd_sc_hd__nor4_1 instances: 2
Class: sky130_fd_sc_hd__o22a_1 instances: 2
Class: sky130_fd_sc_hd__xnor2_1 instances: 10
Class: sky130_fd_sc_hd__nor3b_2 instances: 2
Class: sky130_fd_sc_hd__o21bai_1 instances: 4
Class: sky130_fd_sc_hd__nand2b_1 instances: 6
Class: sky130_fd_sc_hd__diode_2 instances: 19
Class: sky130_fd_sc_hd__o2111a_1 instances: 2
Class: sky130_fd_sc_hd__nor3_1 instances: 2
Class: sky130_fd_sc_hd__nor3_2 instances: 2
Class: sky130_fd_sc_hd__o31a_1 instances: 6
Class: sky130_fd_sc_hd__o21a_1 instances: 4
Class: sky130_fd_sc_hd__o21a_4 instances: 2
Class: sky130_fd_sc_hd__a41oi_1 instances: 2
Class: sky130_fd_sc_hd__o21ai_1 instances: 19
Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1
Class: sky130_fd_sc_hd__a21oi_1 instances: 2
Class: sky130_fd_sc_hd__fill_1 instances: 1
Class: sky130_fd_sc_hd__fill_2 instances: 1
Class: sky130_fd_sc_hd__nor2_1 instances: 12
Circuit contains 333 nets.
Circuit 1 contains 345 devices, Circuit 2 contains 345 devices.
Circuit 1 contains 333 nets, Circuit 2 contains 333 nets.
Final result:
Circuits match uniquely.
.
Logging to file "/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/logs/signoff/32-caravel_clocking.lef.log" disabled
LVS Done.

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signoff/caravel_clocking/openlane-signoff/33-drc.log Normal file
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Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 3.0
Library name: caravel_clocking
Reading "sky130_fd_sc_hd__fill_2".
Reading "sky130_ef_sc_hd__decap_12".
Reading "sky130_fd_sc_hd__decap_8".
Reading "sky130_fd_sc_hd__decap_3".
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
Reading "sky130_fd_sc_hd__dfstp_1".
Reading "sky130_fd_sc_hd__inv_2".
Reading "sky130_fd_sc_hd__decap_4".
Reading "sky130_fd_sc_hd__xnor2_1".
Reading "sky130_fd_sc_hd__mux2_1".
Reading "sky130_fd_sc_hd__fill_1".
Reading "sky130_fd_sc_hd__o21ai_1".
Reading "sky130_fd_sc_hd__clkinv_2".
Reading "sky130_fd_sc_hd__diode_2".
Reading "sky130_fd_sc_hd__or3_1".
Reading "sky130_fd_sc_hd__nor3b_2".
Reading "sky130_fd_sc_hd__clkbuf_4".
Reading "sky130_fd_sc_hd__decap_6".
Reading "sky130_fd_sc_hd__nand2_1".
Reading "sky130_fd_sc_hd__o21bai_1".
Reading "sky130_fd_sc_hd__o31a_1".
Reading "sky130_fd_sc_hd__nor3_2".
Reading "sky130_fd_sc_hd__dfxtp_1".
Reading "sky130_fd_sc_hd__clkbuf_1".
Reading "sky130_fd_sc_hd__inv_4".
Reading "sky130_fd_sc_hd__nand3b_1".
Reading "sky130_fd_sc_hd__clkinv_4".
Reading "sky130_fd_sc_hd__a31oi_2".
Reading "sky130_fd_sc_hd__a21o_1".
Reading "sky130_fd_sc_hd__o31ai_1".
Reading "sky130_fd_sc_hd__nor2_1".
Reading "sky130_fd_sc_hd__o21a_1".
Reading "sky130_fd_sc_hd__o2111ai_4".
Reading "sky130_fd_sc_hd__dfrtn_1".
Reading "sky130_fd_sc_hd__dfrtp_2".
Reading "sky130_fd_sc_hd__dfstp_2".
Reading "sky130_fd_sc_hd__a41oi_1".
Reading "sky130_fd_sc_hd__nor3_1".
Reading "sky130_fd_sc_hd__a31o_2".
Reading "sky130_fd_sc_hd__and2_1".
Reading "sky130_fd_sc_hd__dfrtp_1".
Reading "sky130_fd_sc_hd__or2_1".
Reading "sky130_fd_sc_hd__o2111a_1".
Reading "sky130_fd_sc_hd__clkbuf_16".
Reading "sky130_fd_sc_hd__buf_4".
Reading "sky130_fd_sc_hd__o21a_4".
Reading "sky130_fd_sc_hd__o22a_1".
Reading "sky130_fd_sc_hd__a21oi_1".
Reading "sky130_fd_sc_hd__o2111ai_1".
Reading "sky130_fd_sc_hd__nand4b_1".
Reading "sky130_fd_sc_hd__and2b_2".
Reading "sky130_fd_sc_hd__nor4_1".
Reading "sky130_fd_sc_hd__clkbuf_2".
Reading "sky130_fd_sc_hd__nand2b_1".
Reading "sky130_fd_sc_hd__nand3_1".
Reading "sky130_fd_sc_hd__dfrtp_4".
Reading "sky130_fd_sc_hd__buf_12".
Reading "sky130_fd_sc_hd__buf_2".
Reading "sky130_fd_sc_hd__conb_1".
Reading "caravel_clocking".
[INFO]: Loading caravel_clocking
DRC style is now "drc(full)"
Loading DRC CIF style.
No errors found.
[INFO]: COUNT: 0
[INFO]: Should be divided by 3 or 4
[INFO]: DRC Checking DONE (/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/drc.rpt)
[INFO]: Saving mag view with DRC errors (/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/signoff/caravel_clocking.drc.mag)
[INFO]: Saved

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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Reading /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/results/routing/caravel_clocking.odb
[INFO ANT-0002] Found 0 net violations.
[INFO ANT-0001] Found 0 pin violations.

0
signoff/caravel_clocking/openlane-signoff/34-antenna_violators.rpt Normal file
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signoff/caravel_clocking/openlane-signoff/35-erc_screen.log Normal file
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CVC: Circuit Validation Check Version 1.1.0
CVC: Log output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt
CVC: Error output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt.error.gz
CVC: Debug output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt.debug.gz
CVC: Start: Thu Oct 13 17:51:27 2022
Using the following parameters for CVC (Circuit Validation Check) from /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/cvcrc
CVC_TOP = 'caravel_clocking'
CVC_NETLIST = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/caravel_clocking.cdl'
CVC_MODE = 'caravel_clocking'
CVC_MODEL_FILE = '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/models'
CVC_POWER_FILE = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/caravel_clocking.power'
CVC_FUSE_FILE = ''
CVC_REPORT_FILE = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt'
CVC_REPORT_TITLE = 'CVC $CVC_TOP'
CVC_CIRCUIT_ERROR_LIMIT = '100'
CVC_SEARCH_LIMIT = '100'
CVC_LEAK_LIMIT = '0.0002'
CVC_SOI = 'false'
CVC_SCRC = 'false'
CVC_VTH_GATES = 'false'
CVC_MIN_VTH_GATES = 'false'
CVC_IGNORE_VTH_FLOATING = 'false'
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
CVC_LEAK_OVERVOLTAGE = 'true'
CVC_LOGIC_DIODES = 'false'
CVC_ANALOG_GATES = 'true'
CVC_BACKUP_RESULTS = 'false'
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
CVC_SHORT_ERROR_THRESHOLD = '0'
CVC_BIAS_ERROR_THRESHOLD = '0'
CVC_FORWARD_ERROR_THRESHOLD = '0'
CVC_FLOATING_ERROR_THRESHOLD = '0'
CVC_GATE_ERROR_THRESHOLD = '0'
CVC_LEAK?_ERROR_THRESHOLD = '0'
CVC_EXPECTED_ERROR_THRESHOLD = '0'
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
CVC_CELL_ERROR_LIMIT_FILE = ''
CVC_CELL_CHECKSUM_FILE = ''
CVC_LARGE_CIRCUIT_SIZE = '10000000'
CVC_NET_CHECK_FILE = ''
CVC_MODEL_CHECK_FILE = ''
End of parameters
CVC: Reading device model settings...
CVC: Reading power settings...
CVC: Parsing netlist /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/caravel_clocking.cdl
Cdl fixed data size 26808
Usage CDL: Time: 0 Memory: 7052 I/O: 8 Swap: 0
CVC: Counting and linking...
Fatal error:could not find subcircuit: XFILLER_0_14(sky130_ef_sc_hd__decap_12) in caravel_clocking

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CVC: Log output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt
CVC: Error output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt.error.gz
CVC: Debug output to /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt.debug.gz
CVC: Circuit Validation Check Version 1.1.0
CVC: Start: Thu Oct 13 17:51:27 2022
Using the following parameters for CVC (Circuit Validation Check) from /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/cvcrc
CVC_TOP = 'caravel_clocking'
CVC_NETLIST = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/caravel_clocking.cdl'
CVC_MODE = 'caravel_clocking'
CVC_MODEL_FILE = '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/models'
CVC_POWER_FILE = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/caravel_clocking.power'
CVC_FUSE_FILE = ''
CVC_REPORT_FILE = '/home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/reports/signoff/caravel_clocking.rpt'
CVC_REPORT_TITLE = 'CVC $CVC_TOP'
CVC_CIRCUIT_ERROR_LIMIT = '100'
CVC_SEARCH_LIMIT = '100'
CVC_LEAK_LIMIT = '0.0002'
CVC_SOI = 'false'
CVC_SCRC = 'false'
CVC_VTH_GATES = 'false'
CVC_MIN_VTH_GATES = 'false'
CVC_IGNORE_VTH_FLOATING = 'false'
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
CVC_LEAK_OVERVOLTAGE = 'true'
CVC_LOGIC_DIODES = 'false'
CVC_ANALOG_GATES = 'true'
CVC_BACKUP_RESULTS = 'false'
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
CVC_SHORT_ERROR_THRESHOLD = '0'
CVC_BIAS_ERROR_THRESHOLD = '0'
CVC_FORWARD_ERROR_THRESHOLD = '0'
CVC_FLOATING_ERROR_THRESHOLD = '0'
CVC_GATE_ERROR_THRESHOLD = '0'
CVC_LEAK?_ERROR_THRESHOLD = '0'
CVC_EXPECTED_ERROR_THRESHOLD = '0'
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
CVC_CELL_ERROR_LIMIT_FILE = ''
CVC_CELL_CHECKSUM_FILE = ''
CVC_LARGE_CIRCUIT_SIZE = '10000000'
CVC_NET_CHECK_FILE = ''
CVC_MODEL_CHECK_FILE = ''
End of parameters
CVC: Reading device model settings...
CVC: Reading power settings...
CVC: Parsing netlist /home/kareem_farid/caravel/openlane/caravel_clocking/runs/22_10_13_10_49/tmp/signoff/caravel_clocking.cdl
Cdl fixed data size 26808
Usage CDL: Time: 0 Memory: 7052 I/O: 8 Swap: 0
CVC: Counting and linking...

BIN
signoff/caravel_clocking/openlane-signoff/caravel_clocking.rpt.debug.gz Normal file
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Binary file not shown.

BIN
signoff/caravel_clocking/openlane-signoff/caravel_clocking.rpt.error.gz Normal file
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###############################################################################
# Created by write_sdc
# Tue Dec 7 11:29:52 2021
# Thu Oct 13 17:49:58 2022
###############################################################################
current_design caravel_clocking
###############################################################################
@ -8,67 +8,58 @@ current_design caravel_clocking
###############################################################################
create_clock -name ext_clk -period 25.0000 [get_ports {ext_clk}]
set_clock_transition 0.1500 [get_clocks {ext_clk}]
set_clock_uncertainty 0.2500 ext_clk
set_clock_uncertainty 0.2000 ext_clk
set_propagated_clock [get_clocks {ext_clk}]
create_clock -name pll_clk -period 6.6667 [get_ports {pll_clk}]
set_clock_transition 0.1500 [get_clocks {pll_clk}]
set_clock_uncertainty 0.2500 pll_clk
set_clock_transition 0.1000 [get_clocks {pll_clk}]
set_clock_uncertainty 0.2000 pll_clk
set_propagated_clock [get_clocks {pll_clk}]
create_clock -name pll_clk90 -period 6.6667 [get_ports {pll_clk90}]
set_clock_transition 0.1500 [get_clocks {pll_clk90}]
set_clock_uncertainty 0.2500 pll_clk90
set_clock_transition 0.1000 [get_clocks {pll_clk90}]
set_clock_uncertainty 0.2000 pll_clk90
set_propagated_clock [get_clocks {pll_clk90}]
create_generated_clock -name pll_clk_divided -source [get_ports {pll_clk}] -divide_by 2 [get_pins {_355_/Y}]
set_propagated_clock [get_clocks {pll_clk_divided}]
create_generated_clock -name pll_clk90_divided -source [get_ports {pll_clk90}] -divide_by 2 [get_pins {_357_/Y}]
set_propagated_clock [get_clocks {pll_clk90_divided}]
create_generated_clock -name core_ext_clk_syncd -source [get_pins {_444_/Q}] -divide_by 1 [get_pins {_347_/X}]
set_propagated_clock [get_clocks {core_ext_clk_syncd}]
create_generated_clock -name core_clk_pll -source [get_pins {_355_/Y}] -divide_by 1 [get_ports {core_clk}]
set_propagated_clock [get_clocks {core_clk_pll}]
create_generated_clock -name user_clk_pll -source [get_pins {_357_/Y}] -divide_by 1 [get_ports {user_clk}]
set_propagated_clock [get_clocks {user_clk_pll}]
create_generated_clock -name core_clk -source [get_pins {_210_/X}] -divide_by 1 [get_ports {core_clk}]
set_clock_transition 0.1000 [get_clocks {core_clk}]
set_clock_uncertainty 0.2000 core_clk
set_propagated_clock [get_clocks {core_clk}]
set_clock_groups -name group1 -logically_exclusive \
-group [get_clocks {core_ext_clk_syncd}]
set_clock_groups -name group2 -logically_exclusive \
-group [get_clocks {core_clk_pll}]
set_clock_groups -name group3 -logically_exclusive \
-group [get_clocks {user_clk_pll}]
set_clock_groups -name group4 -logically_exclusive \
-group [get_clocks {ext_clk}]\
-group [list [get_clocks {pll_clk}]\
[get_clocks {pll_clk90}]\
[get_clocks {pll_clk90_divided}]\
[get_clocks {pll_clk_divided}]]
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {ext_clk_sel}]
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[0]}]
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[1]}]
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[2]}]
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[0]}]
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[1]}]
set_input_delay 1.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[2]}]
[get_clocks {pll_clk90}]]
set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {ext_clk_sel}]
set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[0]}]
set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[1]}]
set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel2[2]}]
set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[0]}]
set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[1]}]
set_input_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {sel[2]}]
set_output_delay 5.0000 -clock [get_clocks {ext_clk}] -add_delay [get_ports {resetb_sync}]
###############################################################################
# Environment
###############################################################################
set_load -pin_load 0.0334 [get_ports {core_clk}]
set_load -pin_load 0.0334 [get_ports {resetb_sync}]
set_load -pin_load 0.0334 [get_ports {user_clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_clk_sel}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_reset}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pll_clk}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pll_clk90}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel2[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel2[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {sel2[0]}]
set_load -pin_load 0.2000 [get_ports {core_clk}]
set_load -pin_load 0.2000 [get_ports {resetb_sync}]
set_load -pin_load 0.2000 [get_ports {user_clk}]
set_input_transition 5.0000 [get_ports {ext_clk}]
set_input_transition 5.0000 [get_ports {ext_clk_sel}]
set_input_transition 5.0000 [get_ports {ext_reset}]
set_input_transition 5.0000 [get_ports {pll_clk}]
set_input_transition 5.0000 [get_ports {pll_clk90}]
set_input_transition 5.0000 [get_ports {resetb}]
set_input_transition 5.0000 [get_ports {sel[2]}]
set_input_transition 5.0000 [get_ports {sel[1]}]
set_input_transition 5.0000 [get_ports {sel[0]}]
set_input_transition 5.0000 [get_ports {sel2[2]}]
set_input_transition 5.0000 [get_ports {sel2[1]}]
set_input_transition 5.0000 [get_ports {sel2[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################
# Design Rules
###############################################################################
set_max_fanout 5.0000 [current_design]
set_max_transition 0.7500 [current_design]
set_max_transition -clock_path 0.5000 [get_clocks {core_clk}]
set_max_transition -clock_path 0.5000 [get_clocks {ext_clk}]
set_max_transition -clock_path 0.5000 [get_clocks {pll_clk}]
set_max_transition -clock_path 0.5000 [get_clocks {pll_clk90}]
set_max_fanout 12.0000 [current_design]

10
signoff/caravel_clocking/openlane-signoff/drc.klayout.xml Normal file
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@ -0,0 +1,10 @@
<?xml version="1.0" ?>
<report-database>
<categories/>
<cells>
<cell>
<name>caravel_clocking</name>
</cell>
</cells>
<items/>
</report-database>

1
signoff/caravel_clocking/openlane-signoff/drc.rdb Normal file
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@ -0,0 +1 @@
$caravel_clocking 100

5
signoff/caravel_clocking/openlane-signoff/drc.rpt Normal file
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@ -0,0 +1,5 @@
caravel_clocking
----------------------------------------
[INFO]: COUNT: 0
[INFO]: Should be divided by 3 or 4

0
signoff/caravel_clocking/openlane-signoff/drc.tcl Normal file
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0
signoff/caravel_clocking/openlane-signoff/drc.tr Normal file
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260
signoff/caravel_clocking/openlane-signoff/spice.feedback.txt Normal file
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box 1380 1071 1409 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1443 1071 1472 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1564 1071 1593 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1627 1071 1685 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1719 1071 1777 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1811 1071 1869 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1903 1071 1961 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1995 1071 2053 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2087 1071 2145 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2179 1071 2237 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2271 1071 2300 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2300 1071 2329 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2363 1071 2421 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2455 1071 2513 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2547 1071 2576 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2668 1071 2697 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2697 1071 2731 1105
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
box 2731 1071 2789 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2823 1071 2852 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2852 1071 2881 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2915 1071 2937 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2935 1071 2973 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3007 1071 3065 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3099 1071 3157 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3191 1071 3249 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3283 1071 3341 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3375 1071 3433 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3467 1071 3525 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3559 1071 3617 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3651 1071 3709 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3743 1071 3772 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3864 1071 3893 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 3893 1071 3927 1105
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
box 3927 1071 3985 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4019 1071 4077 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4111 1071 4169 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4203 1071 4261 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4295 1071 4337 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4335 1071 4353 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4387 1071 4445 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4479 1071 4537 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4571 1071 4629 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4663 1071 4721 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4755 1071 4784 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4784 1071 4813 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4847 1071 4905 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 4939 1071 4968 1105
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1196 1615 1225 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1259 1615 1317 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1351 1615 1380 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 460 1615 489 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 489 1615 523 1649
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
box 523 1615 581 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 615 1615 673 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 707 1615 765 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 799 1615 857 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 891 1615 949 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 983 1615 1041 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1075 1615 1133 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1167 1615 1196 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1380 1615 1409 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1443 1615 1472 1649
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1196 2703 1225 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1259 2703 1317 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1351 2703 1380 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1472 2703 1501 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1535 2703 1537 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 460 2703 489 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 489 2703 523 2737
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
box 523 2703 581 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 615 2703 673 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 707 2703 765 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 799 2703 857 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 891 2703 949 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 983 2703 1041 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1075 2703 1133 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1167 2703 1196 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1380 2703 1409 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1443 2703 1472 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1564 2159 1593 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1627 2159 1685 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1719 2159 1777 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1811 2159 1869 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1903 2159 1932 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1932 2159 1961 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1995 2159 2053 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2087 2159 2145 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2179 2159 2237 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2271 2159 2329 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2363 2159 2392 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2392 2159 2421 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2455 2159 2513 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 2547 2159 2576 2193
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1535 2703 1564 2737
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 460 3791 489 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 489 3791 523 3825
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
box 523 3791 581 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 615 3791 673 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 707 3791 765 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 799 3791 857 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 891 3791 949 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 983 3791 1041 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1075 3791 1133 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1167 3791 1196 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1196 3791 1225 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1259 3791 1317 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1351 3791 1380 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1380 3791 1409 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1443 3791 1472 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1472 3791 1501 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1535 3791 1537 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1535 3791 1564 3825
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1196 4879 1225 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1259 4879 1317 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1351 4879 1380 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 460 4879 489 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 489 4879 523 4913
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
box 523 4879 581 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 615 4879 673 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 707 4879 765 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 799 4879 857 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 891 4879 949 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 983 4879 1041 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1075 4879 1133 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1167 4879 1196 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1380 4879 1409 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1443 4879 1472 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1472 4879 1501 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1535 4879 1537 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
box 1535 4879 1564 4913
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium

24456
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1841
verilog/gl/caravel_clocking.nl.v Normal file
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verilog/gl/caravel_clocking.v
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