Merge pull request #197 from efabless/digital_pll-buffers

Digital pll reimplmentation and rtl update
This commit is contained in:
Marwan Abbas 2022-10-13 20:07:49 +02:00 committed by GitHub
commit 3fa5ffb084
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GPG Key ID: 4AEE18F83AFDEB23
79 changed files with 260734 additions and 51681 deletions

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@ -8,28 +8,20 @@ MACRO digital_pll
ORIGIN 0.000 0.000 ;
SIZE 75.000 BY 75.000 ;
PIN VGND
DIRECTION INPUT ;
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER met5 ;
RECT 5.520 41.050 69.460 42.650 ;
END
PORT
LAYER met4 ;
RECT 41.040 5.200 42.640 68.240 ;
END
PORT
LAYER met5 ;
RECT 5.280 41.050 69.700 42.650 ;
END
END VGND
PIN VPWR
DIRECTION INPUT ;
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER met5 ;
RECT 5.520 21.050 69.460 22.650 ;
END
PORT
LAYER met5 ;
RECT 5.520 61.050 69.460 62.650 ;
END
PORT
LAYER met4 ;
RECT 21.040 5.200 22.640 68.240 ;
@ -38,6 +30,14 @@ MACRO digital_pll
LAYER met4 ;
RECT 61.040 5.200 62.640 68.240 ;
END
PORT
LAYER met5 ;
RECT 5.280 21.050 69.700 22.650 ;
END
PORT
LAYER met5 ;
RECT 5.280 61.050 69.700 62.650 ;
END
END VPWR
PIN clockp[0]
DIRECTION OUTPUT TRISTATE ;
@ -339,7 +339,7 @@ MACRO digital_pll
LAYER li1 ;
RECT 5.520 5.355 69.460 68.085 ;
LAYER met1 ;
RECT 2.830 5.200 72.150 68.980 ;
RECT 4.210 4.800 72.150 69.660 ;
LAYER met2 ;
RECT 3.410 70.720 8.090 72.605 ;
RECT 8.930 70.720 14.070 72.605 ;
@ -353,8 +353,8 @@ MACRO digital_pll
RECT 54.930 70.720 60.070 72.605 ;
RECT 60.910 70.720 65.590 72.605 ;
RECT 66.430 70.720 71.570 72.605 ;
RECT 2.860 4.280 72.120 70.720 ;
RECT 2.860 2.195 18.210 4.280 ;
RECT 3.130 4.280 72.120 70.720 ;
RECT 3.130 2.195 18.210 4.280 ;
RECT 19.050 2.195 55.470 4.280 ;
RECT 56.310 2.195 72.120 4.280 ;
LAYER met3 ;
@ -397,6 +397,8 @@ MACRO digital_pll
RECT 4.400 5.760 70.600 7.160 ;
RECT 4.000 3.080 71.000 5.760 ;
RECT 4.400 2.215 71.000 3.080 ;
LAYER met4 ;
RECT 43.535 47.095 43.865 50.145 ;
END
END digital_pll
END LIBRARY

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@ -1,11 +1,11 @@
magic
tech sky130A
magscale 1 2
timestamp 1638875309
timestamp 1665668948
<< obsli1 >>
rect 1104 1071 13892 13617
<< obsm1 >>
rect 566 1040 14430 13796
rect 842 960 14430 13932
<< metal2 >>
rect 570 14200 626 15000
rect 1674 14200 1730 15000
@ -35,8 +35,8 @@ rect 9882 14144 10818 14521
rect 10986 14144 12014 14521
rect 12182 14144 13118 14521
rect 13286 14144 14314 14521
rect 572 856 14424 14144
rect 572 439 3642 856
rect 626 856 14424 14144
rect 626 439 3642 856
rect 3810 439 11094 856
rect 11262 439 14424 856
<< metal3 >>
@ -106,23 +106,25 @@ rect 880 443 14200 616
rect 4208 1040 4528 13648
rect 8208 1040 8528 13648
rect 12208 1040 12528 13648
<< obsm4 >>
rect 8707 9419 8773 10029
<< metal5 >>
rect 1104 12210 13892 12530
rect 1104 8210 13892 8530
rect 1104 4210 13892 4530
rect 1056 12210 13940 12530
rect 1056 8210 13940 8530
rect 1056 4210 13940 4530
<< labels >>
rlabel metal5 s 1104 8210 13892 8530 6 VGND
port 1 nsew ground input
rlabel metal4 s 8208 1040 8528 13648 6 VGND
port 1 nsew ground input
rlabel metal5 s 1104 4210 13892 4530 6 VPWR
port 2 nsew power input
rlabel metal5 s 1104 12210 13892 12530 6 VPWR
port 2 nsew power input
port 1 nsew ground bidirectional
rlabel metal5 s 1056 8210 13940 8530 6 VGND
port 1 nsew ground bidirectional
rlabel metal4 s 4208 1040 4528 13648 6 VPWR
port 2 nsew power input
port 2 nsew power bidirectional
rlabel metal4 s 12208 1040 12528 13648 6 VPWR
port 2 nsew power input
port 2 nsew power bidirectional
rlabel metal5 s 1056 4210 13940 4530 6 VPWR
port 2 nsew power bidirectional
rlabel metal5 s 1056 12210 13940 12530 6 VPWR
port 2 nsew power bidirectional
rlabel metal3 s 0 416 800 536 6 clockp[0]
port 3 nsew signal output
rlabel metal3 s 0 1232 800 1352 6 clockp[1]
@ -198,11 +200,11 @@ port 38 nsew signal input
rlabel metal2 s 3698 0 3754 800 6 resetb
port 39 nsew signal input
<< properties >>
string LEFclass BLOCK
string FIXED_BBOX 0 0 15000 15000
string LEFclass BLOCK
string LEFview TRUE
string GDS_FILE ../gds/digital_pll.gds
string GDS_END 1091926
string GDS_START 342938
string GDS_END 1134054
string GDS_FILE /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.magic.gds
string GDS_START 324288
<< end >>

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@ -16,7 +16,7 @@ bc1e961e41d1d3a383a018279a08bf4108911f53 verilog/rtl/chip_io.v
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
653b230c7cbf092a6210ba7820bc942f312e53f3 verilog/rtl/debug_regs.v
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
3d64219536ccda4c35a787682f13f45bc0ee8e94 verilog/rtl/digital_pll.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
00d2c61e4f424dfce3635f96a1c1bfdeaf7d0cf8 verilog/rtl/gpio_control_block.v
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v

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@ -21,8 +21,8 @@ puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 1
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {pll_control_clock}]
puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {pll_control_clock}]
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_control_clock}]
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {pll_control_clock}]

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@ -12,13 +12,10 @@
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) digital_pll
set ::env(DESIGN_IS_CORE) 1
set ::env(VERILOG_FILES) $script_dir/../../verilog/rtl/digital_pll.v
set ::env(VERILOG_FILES) $::env(DESIGN_DIR)/../../verilog/rtl/digital_pll.v
set ::env(CLOCK_PORT) ""
set ::env(CLOCK_TREE_SYNTH) 0
@ -29,10 +26,10 @@ set ::env(SYNTH_MAX_FANOUT) 6
set ::env(SYNTH_BUFFERING) 0
set ::env(SYNTH_SIZING) 0
set ::env(BASE_SDC_FILE) $script_dir/base.sdc
set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
## Floorplan
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/template/digital_pll.def
set ::env(FP_SIZING) absolute
set ::env(DIE_AREA) "0 0 75 75"
@ -40,23 +37,29 @@ set ::env(DIE_AREA) "0 0 75 75"
set ::env(TOP_MARGIN_MULT) 2
set ::env(BOTTOM_MARGIN_MULT) 2
set ::env(CELL_PAD) 0
set ::env(DIODE_PADDING) 0
set ::env(DPL_CELL_PADDING) 0
set ::env(DRT_CELL_PADDING) 0
## PDN
set ::env(FP_PDN_VPITCH) 40
set ::env(FP_PDN_HPITCH) 40
set ::env(FP_PDN_HOFFSET) 16.41
set ::env(FP_PDN_HSPACING) 18.4
set ::env(FP_PDN_VSPACING) 18.4
## Placement
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_TARGET_DENSITY) 0.82
set ::env(PL_TARGET_DENSITY) 0.9
## Routing
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(GLB_RT_ADJUSTMENT) 0
set ::env(GLB_RT_MINLAYER) 2
set ::env(GLB_RT_MAXLAYER) 6
set ::env(GRT_ADJUSTMENT) 0
## Diode Insertion
set ::env(DIODE_INSERTION_STRATEGY) "4"
set ::env(STA_WRITE_LIB) 0
set ::env(FP_PDN_SKIPTRIM) 1

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@ -1 +1 @@
openlane 2021.11.23_01.42.34-11-g0c24fcf
OpenLane e3a5189a1b0fc4290686fcf2ae46cd6d7947cf9f

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@ -1,3 +1 @@
openlane cbb562bd43c5c410b1b498604803c3dd88a44856
skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
open_pdks c5730b574461889c82858b08d12ba42423d9c2cb
open_pdks de752ec0ba4da0ecb1fbcd309eeec4993d88f5bc

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@ -0,0 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
/home/kareem_farid/caravel/openlane/digital_pll,digital_pll,22_10_13_06_47,flow completed,0h1m38s0ms,0h1m17s0ms,-2.0,0.005625,-1,88.0,568.4,-1,0,0,0,0,0,0,0,-1,-1,-1,-1,6490,2398,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,4113715.0,0.0,27.14,26.98,0.0,0.0,0.0,580,776,121,305,0,0,0,614,5,3,17,11,297,19,12,27,56,70,11,46,50,0,96,4000.0864,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10.0,AREA 0,6,50,1,40,40,0.9,0,sky130_fd_sc_hd,4
1 design design_name config flow_status total_runtime routed_runtime (Cell/mm^2)/Core_Util DIEAREA_mm^2 CellPer_mm^2 OpenDP_Util Peak_Memory_Usage_MB cell_count tritonRoute_violations Short_violations MetSpc_violations OffGrid_violations MinHole_violations Other_violations Magic_violations antenna_violations lvs_total_errors cvc_total_errors klayout_violations wire_length vias wns pl_wns optimized_wns fastroute_wns spef_wns tns pl_tns optimized_tns fastroute_tns spef_tns HPWL routing_layer1_pct routing_layer2_pct routing_layer3_pct routing_layer4_pct routing_layer5_pct routing_layer6_pct wires_count wire_bits public_wires_count public_wire_bits memories_count memory_bits processes_count cells_pre_abc AND DFF NAND NOR OR XOR XNOR MUX inputs outputs level EndCaps TapCells Diodes Total_Physical_Cells CoreArea_um^2 power_slowest_internal_uW power_slowest_switching_uW power_slowest_leakage_uW power_typical_internal_uW power_typical_switching_uW power_typical_leakage_uW power_fastest_internal_uW power_fastest_switching_uW power_fastest_leakage_uW critical_path_ns suggested_clock_period suggested_clock_frequency CLOCK_PERIOD SYNTH_STRATEGY SYNTH_MAX_FANOUT FP_CORE_UTIL FP_ASPECT_RATIO FP_PDN_VPITCH FP_PDN_HPITCH PL_TARGET_DENSITY GRT_ADJUSTMENT STD_CELL_LIBRARY DIODE_INSERTION_STRATEGY
2 /home/kareem_farid/caravel/openlane/digital_pll digital_pll 22_10_13_06_47 flow completed 0h1m38s0ms 0h1m17s0ms -2.0 0.005625 -1 88.0 568.4 -1 0 0 0 0 0 0 0 -1 -1 -1 -1 6490 2398 0.0 0.0 -1 0.0 0.0 0.0 0.0 -1 0.0 0.0 4113715.0 0.0 27.14 26.98 0.0 0.0 0.0 580 776 121 305 0 0 0 614 5 3 17 11 297 19 12 27 56 70 11 46 50 0 96 4000.0864 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10.0 100.0 10.0 AREA 0 6 50 1 40 40 0.9 0 sky130_fd_sc_hd 4

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@ -0,0 +1,40 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.min.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.min.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.min.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
[INFO ODB-0128] Design: digital_pll
[INFO ODB-0130] Created 39 pins.
[INFO ODB-0131] Created 617 components and 3559 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2368 connections.
[INFO ODB-0133] Created 333 nets and 1190 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
Using RCX ruleset '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
[INFO RCX-0008] extracting parasitics of digital_pll ...
[INFO RCX-0435] Reading extraction model file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre ...
[INFO RCX-0436] RC segment generation digital_pll (max_merge_res 50.0) ...
[INFO RCX-0040] Final 1448 rc segments
[INFO RCX-0439] Coupling Cap extraction digital_pll ...
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
[INFO RCX-0043] 2492 wires to be extracted
[INFO RCX-0442] 52% completion -- 1308 wires have been extracted
[INFO RCX-0442] 100% completion -- 2492 wires have been extracted
[INFO RCX-0045] Extract 333 nets, 1781 rsegs, 1781 caps, 2746 ccs
[INFO RCX-0015] Finished extracting digital_pll.
Writing result to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/mca/process_corner_min/digital_pll.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing extracted parasitics to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/mca/process_corner_min/digital_pll.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 333 nets finished
[INFO RCX-0017] Finished writing SPEF ...

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@ -0,0 +1,40 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.max.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.max.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.max.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
[INFO ODB-0128] Design: digital_pll
[INFO ODB-0130] Created 39 pins.
[INFO ODB-0131] Created 617 components and 3559 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2368 connections.
[INFO ODB-0133] Created 333 nets and 1190 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
Using RCX ruleset '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
[INFO RCX-0008] extracting parasitics of digital_pll ...
[INFO RCX-0435] Reading extraction model file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre ...
[INFO RCX-0436] RC segment generation digital_pll (max_merge_res 50.0) ...
[INFO RCX-0040] Final 1752 rc segments
[INFO RCX-0439] Coupling Cap extraction digital_pll ...
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
[INFO RCX-0043] 2492 wires to be extracted
[INFO RCX-0442] 52% completion -- 1308 wires have been extracted
[INFO RCX-0442] 100% completion -- 2492 wires have been extracted
[INFO RCX-0045] Extract 333 nets, 2085 rsegs, 2085 caps, 2773 ccs
[INFO RCX-0015] Finished extracting digital_pll.
Writing result to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/mca/process_corner_max/digital_pll.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing extracted parasitics to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/mca/process_corner_max/digital_pll.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 333 nets finished
[INFO RCX-0017] Finished writing SPEF ...

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@ -0,0 +1,40 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
[INFO ODB-0128] Design: digital_pll
[INFO ODB-0130] Created 39 pins.
[INFO ODB-0131] Created 617 components and 3559 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2368 connections.
[INFO ODB-0133] Created 333 nets and 1190 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
Using RCX ruleset '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre'...
[INFO RCX-0431] Defined process_corner X with ext_model_index 0
[INFO RCX-0029] Defined extraction corner X
[INFO RCX-0008] extracting parasitics of digital_pll ...
[INFO RCX-0435] Reading extraction model file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre ...
[INFO RCX-0436] RC segment generation digital_pll (max_merge_res 50.0) ...
[INFO RCX-0040] Final 1456 rc segments
[INFO RCX-0439] Coupling Cap extraction digital_pll ...
[INFO RCX-0440] Coupling threshhold is 0.1000 fF, coupling capacitance less than 0.1000 fF will be grounded.
[INFO RCX-0043] 2492 wires to be extracted
[INFO RCX-0442] 52% completion -- 1308 wires have been extracted
[INFO RCX-0442] 100% completion -- 2492 wires have been extracted
[INFO RCX-0045] Extract 333 nets, 1789 rsegs, 1789 caps, 2747 ccs
[INFO RCX-0015] Finished extracting digital_pll.
Writing result to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/mca/process_corner_nom/digital_pll.spef...
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing extracted parasitics to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/mca/process_corner_nom/digital_pll.spef...
[INFO RCX-0016] Writing SPEF ...
[INFO RCX-0443] 333 nets finished
[INFO RCX-0017] Finished writing SPEF ...

File diff suppressed because it is too large Load Diff

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===========================================================================
report_design_area
============================================================================
Design area 3611 u^2 90% utilization.

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SKIPPED!

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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Reading /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.odb
min_report
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _394_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _395_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _394_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.33 0.33 ^ _394_/Q (sky130_fd_sc_hd__dfrtp_2)
1 0.00 pll_control.oscbuf[0] (net)
0.04 0.00 0.33 ^ _395_/D (sky130_fd_sc_hd__dfrtp_2)
0.33 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _395_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.03 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-0.33 data arrival time
-----------------------------------------------------------------------------
0.10 slack (MET)
Startpoint: _395_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _396_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _395_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.41 0.41 ^ _395_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.oscbuf[1] (net)
0.12 0.00 0.41 ^ _396_/D (sky130_fd_sc_hd__dfrtp_2)
0.41 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _396_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.04 0.21 library hold time
0.21 data required time
-----------------------------------------------------------------------------
0.21 data required time
-0.41 data arrival time
-----------------------------------------------------------------------------
0.20 slack (MET)
Startpoint: _379_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _379_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _379_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.36 0.36 ^ _379_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.06 0.00 0.36 ^ _287_/A (sky130_fd_sc_hd__or2_2)
0.03 0.09 0.45 ^ _287_/X (sky130_fd_sc_hd__or2_2)
1 0.00 _023_ (net)
0.03 0.00 0.45 ^ _379_/D (sky130_fd_sc_hd__dfrtp_2)
0.45 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _379_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-0.45 data arrival time
-----------------------------------------------------------------------------
0.22 slack (MET)
Startpoint: _381_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _381_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _381_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.34 0.35 ^ _381_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.prep[2] (net)
0.05 0.00 0.35 ^ _285_/A1 (sky130_fd_sc_hd__mux2_1)
0.04 0.11 0.46 ^ _285_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _025_ (net)
0.04 0.00 0.46 ^ _381_/D (sky130_fd_sc_hd__dfrtp_2)
0.46 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _381_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.03 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-0.46 data arrival time
-----------------------------------------------------------------------------
0.23 slack (MET)
Startpoint: _380_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _380_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _380_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.35 0.36 ^ _380_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[1] (net)
0.06 0.00 0.36 ^ _286_/A0 (sky130_fd_sc_hd__mux2_1)
0.04 0.11 0.47 ^ _286_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _024_ (net)
0.04 0.00 0.47 ^ _380_/D (sky130_fd_sc_hd__dfrtp_2)
0.47 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _380_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.03 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-0.47 data arrival time
-----------------------------------------------------------------------------
0.24 slack (MET)
min_report_end
max_report
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _388_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _270_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.35 3.96 v _270_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _032_ (net)
0.06 0.00 3.96 v _388_/D (sky130_fd_sc_hd__dfrtp_2)
3.96 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _388_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.96 data arrival time
-----------------------------------------------------------------------------
2.35 slack (MET)
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _392_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _260_/S (sky130_fd_sc_hd__mux2_1)
0.05 0.35 3.96 v _260_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _036_ (net)
0.05 0.00 3.96 v _392_/D (sky130_fd_sc_hd__dfrtp_2)
3.96 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _392_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.96 data arrival time
-----------------------------------------------------------------------------
2.35 slack (MET)
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _391_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _262_/S (sky130_fd_sc_hd__mux2_1)
0.05 0.34 3.96 v _262_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _035_ (net)
0.05 0.00 3.96 v _391_/D (sky130_fd_sc_hd__dfrtp_2)
3.96 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _391_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.96 data arrival time
-----------------------------------------------------------------------------
2.36 slack (MET)
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _390_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _264_/C1 (sky130_fd_sc_hd__o211a_2)
0.05 0.17 3.78 v _264_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _123_ (net)
0.05 0.00 3.78 v _265_/B (sky130_fd_sc_hd__xnor2_2)
0.05 0.14 3.92 v _265_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.00 _034_ (net)
0.05 0.00 3.92 v _390_/D (sky130_fd_sc_hd__dfrtp_2)
3.92 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _390_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.92 data arrival time
-----------------------------------------------------------------------------
2.39 slack (MET)
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _393_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _257_/A2 (sky130_fd_sc_hd__o22a_2)
0.04 0.26 3.87 v _257_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.04 0.00 3.87 v _393_/D (sky130_fd_sc_hd__dfrtp_2)
3.87 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _393_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.10 6.32 library setup time
6.32 data required time
-----------------------------------------------------------------------------
6.32 data required time
-3.87 data arrival time
-----------------------------------------------------------------------------
2.44 slack (MET)
max_report_end
check_report
===========================================================================
report_checks -unconstrained
============================================================================
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _388_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _270_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.35 3.96 v _270_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _032_ (net)
0.06 0.00 3.96 v _388_/D (sky130_fd_sc_hd__dfrtp_2)
3.96 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _388_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.96 data arrival time
-----------------------------------------------------------------------------
2.35 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
No paths found.
check_report_end
check_slew
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
dco 6 108 -102 (VIOLATED)
_355_/Y 6 25 -19 (VIOLATED)
ringosc.ibufp01/Y 6 24 -18 (VIOLATED)
_227_/X 6 13 -7 (VIOLATED)
_393_/Q 6 11 -5 (VIOLATED)
_292_/Y 6 10 -4 (VIOLATED)
_390_/Q 6 10 -4 (VIOLATED)
_181_/Y 6 9 -3 (VIOLATED)
_228_/X 6 9 -3 (VIOLATED)
_243_/X 6 8 -2 (VIOLATED)
_293_/X 6 8 -2 (VIOLATED)
_382_/Q 6 8 -2 (VIOLATED)
_391_/Q 6 8 -2 (VIOLATED)
_392_/Q 6 8 -2 (VIOLATED)
_241_/Y 6 7 (VIOLATED)
===========================================================================
max slew violation count 0
max fanout violation count 15
max cap violation count 0
============================================================================
check_slew_end
tns_report
===========================================================================
report_tns
============================================================================
tns 0.00
tns_report_end
wns_report
===========================================================================
report_wns
============================================================================
wns 0.00
wns_report_end
worst_slack
===========================================================================
report_worst_slack -max (Setup)
============================================================================
worst slack 2.35
===========================================================================
report_worst_slack -min (Hold)
============================================================================
worst slack 0.10
worst_slack_end
power_report
===========================================================================
report_power
============================================================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 1.48e-04 2.01e-05 1.84e-10 1.68e-04 33.2%
Combinational 1.48e-04 1.90e-04 1.25e-09 3.39e-04 66.8%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 2.96e-04 2.10e-04 1.43e-09 5.07e-04 100.0%
58.5% 41.5% 0.0%
power_report_end
area_report
===========================================================================
report_design_area
============================================================================
Design area 3611 u^2 90% utilization.
area_report_end
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing SDF to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/mca/process_corner_nom/digital_pll.sdf...

View File

@ -0,0 +1,322 @@
===========================================================================
report_checks -path_delay max (Setup)
============================================================================
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _388_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _270_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.35 3.96 v _270_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _032_ (net)
0.06 0.00 3.96 v _388_/D (sky130_fd_sc_hd__dfrtp_2)
3.96 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _388_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.96 data arrival time
-----------------------------------------------------------------------------
2.35 slack (MET)
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _392_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _260_/S (sky130_fd_sc_hd__mux2_1)
0.05 0.35 3.96 v _260_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _036_ (net)
0.05 0.00 3.96 v _392_/D (sky130_fd_sc_hd__dfrtp_2)
3.96 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _392_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.96 data arrival time
-----------------------------------------------------------------------------
2.35 slack (MET)
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _391_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _262_/S (sky130_fd_sc_hd__mux2_1)
0.05 0.34 3.96 v _262_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _035_ (net)
0.05 0.00 3.96 v _391_/D (sky130_fd_sc_hd__dfrtp_2)
3.96 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _391_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.96 data arrival time
-----------------------------------------------------------------------------
2.36 slack (MET)
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _390_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _264_/C1 (sky130_fd_sc_hd__o211a_2)
0.05 0.17 3.78 v _264_/X (sky130_fd_sc_hd__o211a_2)
1 0.01 _123_ (net)
0.05 0.00 3.78 v _265_/B (sky130_fd_sc_hd__xnor2_2)
0.05 0.14 3.92 v _265_/Y (sky130_fd_sc_hd__xnor2_2)
1 0.00 _034_ (net)
0.05 0.00 3.92 v _390_/D (sky130_fd_sc_hd__dfrtp_2)
3.92 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _390_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.92 data arrival time
-----------------------------------------------------------------------------
2.39 slack (MET)
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _393_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _257_/A2 (sky130_fd_sc_hd__o22a_2)
0.04 0.26 3.87 v _257_/X (sky130_fd_sc_hd__o22a_2)
1 0.00 _037_ (net)
0.04 0.00 3.87 v _393_/D (sky130_fd_sc_hd__dfrtp_2)
3.87 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _393_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.10 6.32 library setup time
6.32 data required time
-----------------------------------------------------------------------------
6.32 data required time
-3.87 data arrival time
-----------------------------------------------------------------------------
2.44 slack (MET)

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@ -0,0 +1,178 @@
===========================================================================
report_checks -path_delay min (Hold)
============================================================================
Startpoint: _394_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _395_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _394_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.04 0.33 0.33 ^ _394_/Q (sky130_fd_sc_hd__dfrtp_2)
1 0.00 pll_control.oscbuf[0] (net)
0.04 0.00 0.33 ^ _395_/D (sky130_fd_sc_hd__dfrtp_2)
0.33 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _395_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.03 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-0.33 data arrival time
-----------------------------------------------------------------------------
0.10 slack (MET)
Startpoint: _395_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _396_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _395_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.12 0.41 0.41 ^ _395_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.02 pll_control.oscbuf[1] (net)
0.12 0.00 0.41 ^ _396_/D (sky130_fd_sc_hd__dfrtp_2)
0.41 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _396_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.04 0.21 library hold time
0.21 data required time
-----------------------------------------------------------------------------
0.21 data required time
-0.41 data arrival time
-----------------------------------------------------------------------------
0.20 slack (MET)
Startpoint: _379_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _379_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _379_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.36 0.36 ^ _379_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[0] (net)
0.06 0.00 0.36 ^ _287_/A (sky130_fd_sc_hd__or2_2)
0.03 0.09 0.45 ^ _287_/X (sky130_fd_sc_hd__or2_2)
1 0.00 _023_ (net)
0.03 0.00 0.45 ^ _379_/D (sky130_fd_sc_hd__dfrtp_2)
0.45 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _379_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.02 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-0.45 data arrival time
-----------------------------------------------------------------------------
0.22 slack (MET)
Startpoint: _381_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _381_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _381_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.05 0.34 0.35 ^ _381_/Q (sky130_fd_sc_hd__dfrtp_2)
2 0.01 pll_control.prep[2] (net)
0.05 0.00 0.35 ^ _285_/A1 (sky130_fd_sc_hd__mux2_1)
0.04 0.11 0.46 ^ _285_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _025_ (net)
0.04 0.00 0.46 ^ _381_/D (sky130_fd_sc_hd__dfrtp_2)
0.46 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _381_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.03 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-0.46 data arrival time
-----------------------------------------------------------------------------
0.23 slack (MET)
Startpoint: _380_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _380_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: min
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _380_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.06 0.35 0.36 ^ _380_/Q (sky130_fd_sc_hd__dfrtp_2)
3 0.01 pll_control.prep[1] (net)
0.06 0.00 0.36 ^ _286_/A0 (sky130_fd_sc_hd__mux2_1)
0.04 0.11 0.47 ^ _286_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _024_ (net)
0.04 0.00 0.47 ^ _380_/D (sky130_fd_sc_hd__dfrtp_2)
0.47 data arrival time
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _380_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.25 0.25 clock uncertainty
0.00 0.25 clock reconvergence pessimism
-0.03 0.23 library hold time
0.23 data required time
-----------------------------------------------------------------------------
0.23 data required time
-0.47 data arrival time
-----------------------------------------------------------------------------
0.24 slack (MET)

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@ -0,0 +1,14 @@
===========================================================================
report_power
============================================================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
----------------------------------------------------------------
Sequential 1.48e-04 2.01e-05 1.84e-10 1.68e-04 33.2%
Combinational 1.48e-04 1.90e-04 1.25e-09 3.39e-04 66.8%
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
----------------------------------------------------------------
Total 2.96e-04 2.10e-04 1.43e-09 5.07e-04 100.0%
58.5% 41.5% 0.0%

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@ -0,0 +1,72 @@
===========================================================================
report_checks -unconstrained
============================================================================
Startpoint: _383_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Endpoint: _388_ (rising edge-triggered flip-flop clocked by pll_control_clock)
Path Group: pll_control_clock
Path Type: max
Fanout Cap Slew Delay Time Description
-----------------------------------------------------------------------------
0.00 0.00 clock pll_control_clock (rise edge)
0.00 0.00 clock source latency
0.09 0.00 0.00 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 0.00 ^ _383_/CLK (sky130_fd_sc_hd__dfrtp_2)
0.10 0.50 0.50 v _383_/Q (sky130_fd_sc_hd__dfrtp_2)
6 0.03 pll_control.count0[1] (net)
0.10 0.00 0.51 v _200_/A (sky130_fd_sc_hd__xor2_2)
0.09 0.23 0.73 v _200_/X (sky130_fd_sc_hd__xor2_2)
3 0.01 _062_ (net)
0.09 0.00 0.73 v _202_/A2 (sky130_fd_sc_hd__a211o_2)
0.07 0.39 1.12 v _202_/X (sky130_fd_sc_hd__a211o_2)
3 0.01 _064_ (net)
0.07 0.00 1.12 v _212_/A2 (sky130_fd_sc_hd__a21o_2)
0.05 0.25 1.38 v _212_/X (sky130_fd_sc_hd__a21o_2)
3 0.01 _074_ (net)
0.05 0.00 1.38 v _213_/A3 (sky130_fd_sc_hd__a32o_2)
0.05 0.29 1.67 v _213_/X (sky130_fd_sc_hd__a32o_2)
3 0.01 _075_ (net)
0.05 0.00 1.67 v _224_/B1 (sky130_fd_sc_hd__a2111oi_2)
0.26 0.34 2.01 ^ _224_/Y (sky130_fd_sc_hd__a2111oi_2)
1 0.00 _086_ (net)
0.26 0.00 2.01 ^ _227_/A1 (sky130_fd_sc_hd__o31a_2)
0.42 0.49 2.50 ^ _227_/X (sky130_fd_sc_hd__o31a_2)
13 0.08 _089_ (net)
0.42 0.00 2.50 ^ _233_/C_N (sky130_fd_sc_hd__or4bb_2)
0.09 0.67 3.17 v _233_/X (sky130_fd_sc_hd__or4bb_2)
1 0.00 _095_ (net)
0.09 0.00 3.17 v _238_/B (sky130_fd_sc_hd__and4_2)
0.06 0.25 3.42 v _238_/X (sky130_fd_sc_hd__and4_2)
3 0.01 _100_ (net)
0.06 0.00 3.42 v _243_/B1 (sky130_fd_sc_hd__o31a_2)
0.12 0.19 3.61 v _243_/X (sky130_fd_sc_hd__o31a_2)
8 0.03 _105_ (net)
0.12 0.00 3.61 v _270_/S (sky130_fd_sc_hd__mux2_1)
0.06 0.35 3.96 v _270_/X (sky130_fd_sc_hd__mux2_1)
1 0.00 _032_ (net)
0.06 0.00 3.96 v _388_/D (sky130_fd_sc_hd__dfrtp_2)
3.96 data arrival time
6.67 6.67 clock pll_control_clock (rise edge)
0.00 6.67 clock source latency
0.09 0.00 6.67 ^ ringosc.ibufp01/Y (sky130_fd_sc_hd__clkinv_8)
24 0.08 pll_control.clock (net)
0.09 0.00 6.67 ^ _388_/CLK (sky130_fd_sc_hd__dfrtp_2)
-0.25 6.42 clock uncertainty
0.00 6.42 clock reconvergence pessimism
-0.11 6.31 library setup time
6.31 data required time
-----------------------------------------------------------------------------
6.31 data required time
-3.96 data arrival time
-----------------------------------------------------------------------------
2.35 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
No paths found.

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@ -0,0 +1,30 @@
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
dco 6 108 -102 (VIOLATED)
_355_/Y 6 25 -19 (VIOLATED)
ringosc.ibufp01/Y 6 24 -18 (VIOLATED)
_227_/X 6 13 -7 (VIOLATED)
_393_/Q 6 11 -5 (VIOLATED)
_292_/Y 6 10 -4 (VIOLATED)
_390_/Q 6 10 -4 (VIOLATED)
_181_/Y 6 9 -3 (VIOLATED)
_228_/X 6 9 -3 (VIOLATED)
_243_/X 6 8 -2 (VIOLATED)
_293_/X 6 8 -2 (VIOLATED)
_382_/Q 6 8 -2 (VIOLATED)
_391_/Q 6 8 -2 (VIOLATED)
_392_/Q 6 8 -2 (VIOLATED)
_241_/Y 6 7 (VIOLATED)
===========================================================================
max slew violation count 0
max fanout violation count 15
max cap violation count 0
============================================================================

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@ -0,0 +1,5 @@
===========================================================================
report_tns
============================================================================
tns 0.00

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@ -0,0 +1,5 @@
===========================================================================
report_wns
============================================================================
wns 0.00

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@ -0,0 +1,10 @@
===========================================================================
report_worst_slack -max (Setup)
============================================================================
worst slack 2.35
===========================================================================
report_worst_slack -min (Hold)
============================================================================
worst slack 0.10

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@ -0,0 +1,38 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
[INFO ODB-0128] Design: digital_pll
[INFO ODB-0130] Created 39 pins.
[INFO ODB-0131] Created 617 components and 3559 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2368 connections.
[INFO ODB-0133] Created 333 nets and 1190 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
[INFO]: Setting RC values...
[INFO PSM-0002] Output voltage file is specified as: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/22-irdrop.rpt.
[WARNING PSM-0016] Voltage pad location (VSRC) file not specified, defaulting pad location to checkerboard pattern on core area.
[WARNING PSM-0017] X direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0018] Y direction bump pitch is not specified, defaulting to 140um.
[WARNING PSM-0019] Voltage on net VPWR is not explicitly set.
[WARNING PSM-0022] Using voltage 1.800V for VDD network.
[WARNING PSM-0063] Specified bump pitches of 140.000 and 140.000 are less than core width of 63.940 or core height of 62.560. Changing bump location to the center of the die at (37.490, 36.720).
[WARNING PSM-0065] VSRC location not specified, using default checkerboard pattern with one VDD every size bumps in x-direction and one in two bumps in the y-direction
[INFO PSM-0076] Setting metal node density to be standard cell height times 5.
[WARNING PSM-0030] VSRC location at (37.490um, 36.720um) and size 10.000um, is not located on an existing power stripe node. Moving to closest node at (21.840um, 21.850um).
[INFO PSM-0031] Number of PDN nodes on net VPWR = 268.
[INFO PSM-0064] Number of voltage sources = 1.
[INFO PSM-0040] All PDN stripes on net VPWR are connected.
########## IR report #################
Worstcase voltage: 1.80e+00 V
Average IR drop : 7.47e-10 V
Worstcase IR drop: 1.07e-09 V
######################################

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@ -0,0 +1,483 @@
Instance name, X location, Y location, Voltage
ringosc.dstage\[8\].id.delaybuf1, 61.84, 68, 1.8
ringosc.dstage\[8\].id.delayen0, 61.84, 68, 1.8
ringosc.dstage\[8\].id.delayen1, 61.84, 68, 1.8
ringosc.dstage\[8\].id.delayenb0, 61.84, 62.56, 1.8
ringosc.dstage\[9\].id.delaybuf1, 61.84, 62.56, 1.8
ringosc.dstage\[9\].id.delayenb0, 61.84, 62.56, 1.8
ANTENNA__342__A1, 61.84, 57.12, 1.8
ANTENNA__348__A1, 61.84, 57.12, 1.8
_349_, 61.84, 57.12, 1.8
_350_, 61.84, 57.12, 1.8
ringosc.dstage\[9\].id.delayen0, 61.84, 57.12, 1.8
ringosc.dstage\[9\].id.delayen1, 61.84, 57.12, 1.8
ringosc.dstage\[9\].id.delayenb1, 61.84, 57.12, 1.8
_176_, 61.84, 51.68, 1.8
_323_, 61.84, 51.68, 1.8
_342_, 61.84, 51.68, 1.8
ringosc.dstage\[10\].id.delaybuf0, 61.84, 51.68, 1.8
ringosc.dstage\[10\].id.delayen0, 61.84, 51.68, 1.8
ringosc.dstage\[10\].id.delayen1, 61.84, 51.68, 1.8
ringosc.dstage\[10\].id.delayenb0, 61.84, 51.68, 1.8
ringosc.dstage\[10\].id.delayint0, 61.84, 51.68, 1.8
ANTENNA__354__A1, 61.84, 46.24, 1.8
_344_, 61.84, 46.24, 1.8
_351_, 61.84, 46.24, 1.8
_354_, 61.84, 46.24, 1.8
ringosc.dstage\[10\].id.delayenb1, 61.84, 46.24, 1.8
ANTENNA__351__A1, 61.84, 40.8, 1.8
ANTENNA__354__A2, 61.84, 40.8, 1.8
_229_, 61.84, 40.8, 1.8
ringosc.dstage\[10\].id.delaybuf1, 61.84, 40.8, 1.8
ringosc.iss.ctrlen0, 61.84, 40.8, 1.8
ringosc.iss.delayen1, 61.84, 40.8, 1.8
ringosc.iss.delayenb0, 61.84, 40.8, 1.8
ringosc.iss.delayenb1, 61.84, 40.8, 1.8
FILLER_11_113, 61.84, 35.36, 1.8
ringosc.dstage\[11\].id.delayenb0, 61.84, 35.36, 1.8
ringosc.iss.const1, 61.84, 35.36, 1.8
ringosc.iss.delayen0, 61.84, 35.36, 1.8
ringosc.iss.reseten0, 61.84, 35.36, 1.8
ANTENNA__367__A, 61.84, 29.92, 1.8
_366_, 61.84, 29.92, 1.8
_367_, 61.84, 29.92, 1.8
_368_, 61.84, 29.92, 1.8
ringosc.dstage\[11\].id.delayen0, 61.84, 29.92, 1.8
ANTENNA__352__A_N, 61.84, 24.48, 1.8
ANTENNA__366__A, 61.84, 24.48, 1.8
FILLER_6_120, 61.84, 24.48, 1.8
FILLER_8_128, 61.84, 24.48, 1.8
_352_, 61.84, 24.48, 1.8
ringosc.dstage\[11\].id.delayenb1, 61.84, 24.48, 1.8
ANTENNA__353__A1, 61.84, 19.04, 1.8
ANTENNA__364__A, 61.84, 19.04, 1.8
ANTENNA__369__A, 61.84, 19.04, 1.8
_353_, 61.84, 19.04, 1.8
_358_, 61.84, 19.04, 1.8
_364_, 61.84, 19.04, 1.8
_369_, 61.84, 19.04, 1.8
ringosc.dstage\[11\].id.delayen1, 61.84, 19.04, 1.8
ANTENNA__358__A, 61.84, 13.6, 1.8
ANTENNA__372__A, 61.84, 13.6, 1.8
ANTENNA__373__A, 61.84, 13.6, 1.8
_181_, 61.84, 13.6, 1.8
_182_, 61.84, 13.6, 1.8
_372_, 61.84, 13.6, 1.8
_373_, 61.84, 13.6, 1.8
_395_, 61.84, 8.16, 1.8
_396_, 61.84, 8.16, 1.8
ringosc.dstage\[4\].id.delaybuf1, 21.84, 68, 1.8
ringosc.dstage\[4\].id.delayint0, 21.84, 68, 1.8
ANTENNA__309__A1, 21.84, 62.56, 1.8
ANTENNA__310__A2, 21.84, 62.56, 1.8
_306_, 21.84, 62.56, 1.8
_313_, 21.84, 62.56, 1.8
ringosc.dstage\[4\].id.delaybuf0, 21.84, 62.56, 1.8
ringosc.dstage\[6\].id.delayen1, 21.84, 62.56, 1.8
ringosc.dstage\[6\].id.delayenb0, 21.84, 62.56, 1.8
ringosc.dstage\[6\].id.delayint0, 21.84, 62.56, 1.8
ANTENNA__316__B2, 21.84, 57.12, 1.8
ANTENNA__317__A1, 21.84, 57.12, 1.8
_301_, 21.84, 57.12, 1.8
ringosc.dstage\[5\].id.delaybuf0, 21.84, 57.12, 1.8
ringosc.dstage\[5\].id.delayen1, 21.84, 57.12, 1.8
ringosc.dstage\[5\].id.delayenb0, 21.84, 57.12, 1.8
ringosc.dstage\[6\].id.delaybuf0, 21.84, 57.12, 1.8
ringosc.dstage\[6\].id.delayenb1, 21.84, 57.12, 1.8
ANTENNA__316__B1, 21.84, 51.68, 1.8
_316_, 21.84, 51.68, 1.8
ringosc.dstage\[1\].id.delayen0, 21.84, 51.68, 1.8
ringosc.dstage\[1\].id.delayint0, 21.84, 51.68, 1.8
ringosc.dstage\[2\].id.delayint0, 21.84, 51.68, 1.8
ringosc.dstage\[5\].id.delaybuf1, 21.84, 51.68, 1.8
ringosc.dstage\[5\].id.delayenb1, 21.84, 51.68, 1.8
ringosc.dstage\[5\].id.delayint0, 21.84, 51.68, 1.8
ANTENNA__317__A2, 21.84, 46.24, 1.8
_289_, 21.84, 46.24, 1.8
_297_, 21.84, 46.24, 1.8
ringosc.dstage\[1\].id.delaybuf0, 21.84, 46.24, 1.8
ringosc.dstage\[1\].id.delayen1, 21.84, 46.24, 1.8
ringosc.dstage\[1\].id.delayenb0, 21.84, 46.24, 1.8
ANTENNA__302__A1, 21.84, 40.8, 1.8
ANTENNA__378__A, 21.84, 40.8, 1.8
ringosc.dstage\[0\].id.delayen0, 21.84, 40.8, 1.8
ringosc.dstage\[0\].id.delayenb0, 21.84, 40.8, 1.8
ringosc.dstage\[0\].id.delayenb1, 21.84, 40.8, 1.8
ringosc.dstage\[0\].id.delayint0, 21.84, 40.8, 1.8
ringosc.dstage\[1\].id.delayenb1, 21.84, 40.8, 1.8
ANTENNA__377__A, 21.84, 35.36, 1.8
_188_, 21.84, 35.36, 1.8
_363_, 21.84, 35.36, 1.8
_377_, 21.84, 35.36, 1.8
ringosc.dstage\[0\].id.delaybuf1, 21.84, 35.36, 1.8
ringosc.dstage\[0\].id.delayen1, 21.84, 35.36, 1.8
ringosc.ibufp00, 21.84, 35.36, 1.8
_203_, 21.84, 29.92, 1.8
_386_, 21.84, 29.92, 1.8
_393_, 21.84, 29.92, 1.8
ringosc.ibufp01, 21.84, 29.92, 1.8
FILLER_8_42, 21.84, 24.48, 1.8
_193_, 21.84, 24.48, 1.8
_195_, 21.84, 24.48, 1.8
_210_, 21.84, 24.48, 1.8
_211_, 21.84, 24.48, 1.8
_275_, 21.84, 24.48, 1.8
_276_, 21.84, 24.48, 1.8
_399_, 21.84, 24.48, 1.8
ANTENNA__213__B1, 21.84, 19.04, 1.8
ANTENNA__362__A, 21.84, 19.04, 1.8
ANTENNA__376__A, 21.84, 19.04, 1.8
_185_, 21.84, 19.04, 1.8
_194_, 21.84, 19.04, 1.8
_202_, 21.84, 19.04, 1.8
_376_, 21.84, 19.04, 1.8
ANTENNA__213__A1, 21.84, 13.6, 1.8
ANTENNA__222__B2, 21.84, 13.6, 1.8
_196_, 21.84, 13.6, 1.8
_197_, 21.84, 13.6, 1.8
_198_, 21.84, 13.6, 1.8
_218_, 21.84, 13.6, 1.8
ANTENNA__375__A, 21.84, 8.16, 1.8
_186_, 21.84, 8.16, 1.8
_200_, 21.84, 8.16, 1.8
_284_, 21.84, 8.16, 1.8
_355_, 21.84, 8.16, 1.8
_375_, 21.84, 8.16, 1.8
_382_, 21.84, 8.16, 1.8
_398_, 21.84, 8.16, 1.8
PHY_44, 5.52, 68, 1.8
ANTENNA__337__A1, 69.46, 68, 1.8
PHY_45, 69.46, 68, 1.8
ringosc.dstage\[9\].id.delayint0, 69.46, 68, 1.8
ANTENNA__309__A2, 13.68, 68, 1.8
ringosc.dstage\[4\].id.delayen0, 13.68, 68, 1.8
ANTENNA__310__A1, 35.173, 68, 1.8
_309_, 35.173, 68, 1.8
ringosc.dstage\[6\].id.delaybuf1, 35.173, 68, 1.8
ringosc.dstage\[7\].id.delaybuf0, 35.173, 68, 1.8
_336_, 48.506, 68, 1.8
ringosc.dstage\[7\].id.delaybuf1, 48.506, 68, 1.8
ANTENNA__306__A1, 5.52, 62.56, 1.8
ANTENNA__306__A2, 5.52, 62.56, 1.8
PHY_40, 5.52, 62.56, 1.8
PHY_42, 5.52, 62.56, 1.8
_302_, 5.52, 62.56, 1.8
ringosc.dstage\[3\].id.delayen1, 5.52, 62.56, 1.8
PHY_41, 69.46, 62.56, 1.8
PHY_43, 69.46, 62.56, 1.8
ringosc.dstage\[9\].id.delaybuf0, 69.46, 62.56, 1.8
ringosc.dstage\[3\].id.delaybuf1, 13.68, 62.56, 1.8
ringosc.dstage\[4\].id.delayen1, 13.68, 62.56, 1.8
ringosc.dstage\[4\].id.delayenb0, 13.68, 62.56, 1.8
ringosc.dstage\[4\].id.delayenb1, 13.68, 62.56, 1.8
ANTENNA__312__A1, 35.173, 62.56, 1.8
ANTENNA__312__A2, 35.173, 62.56, 1.8
_308_, 35.173, 62.56, 1.8
_310_, 35.173, 62.56, 1.8
_312_, 35.173, 62.56, 1.8
_343_, 35.173, 62.56, 1.8
ringosc.dstage\[6\].id.delayen0, 35.173, 62.56, 1.8
ringosc.dstage\[7\].id.delayen1, 35.173, 62.56, 1.8
ringosc.dstage\[7\].id.delayenb1, 35.173, 62.56, 1.8
ANTENNA__343__A1, 48.506, 62.56, 1.8
ANTENNA__343__A2, 48.506, 62.56, 1.8
ANTENNA__346__B1, 48.506, 62.56, 1.8
_328_, 48.506, 62.56, 1.8
_337_, 48.506, 62.56, 1.8
ringosc.dstage\[7\].id.delayen0, 48.506, 62.56, 1.8
ringosc.dstage\[7\].id.delayenb0, 48.506, 62.56, 1.8
ringosc.dstage\[7\].id.delayint0, 48.506, 62.56, 1.8
ringosc.dstage\[8\].id.delaybuf0, 48.506, 62.56, 1.8
ringosc.dstage\[8\].id.delayint0, 48.506, 62.56, 1.8
ANTENNA__300__A1, 5.52, 57.12, 1.8
PHY_36, 5.52, 57.12, 1.8
PHY_38, 5.52, 57.12, 1.8
ringosc.dstage\[3\].id.delayen0, 5.52, 57.12, 1.8
ringosc.dstage\[3\].id.delayenb1, 5.52, 57.12, 1.8
ringosc.dstage\[3\].id.delayint0, 5.52, 57.12, 1.8
ANTENNA__342__A2, 69.46, 57.12, 1.8
ANTENNA__348__A2, 69.46, 57.12, 1.8
PHY_37, 69.46, 57.12, 1.8
PHY_39, 69.46, 57.12, 1.8
ANTENNA__305__A1, 13.68, 57.12, 1.8
ANTENNA__313__A_N, 13.68, 57.12, 1.8
ANTENNA__313__B, 13.68, 57.12, 1.8
_300_, 13.68, 57.12, 1.8
ANTENNA__293__A_N, 35.173, 57.12, 1.8
ANTENNA__314__A1, 35.173, 57.12, 1.8
_303_, 35.173, 57.12, 1.8
_304_, 35.173, 57.12, 1.8
_311_, 35.173, 57.12, 1.8
_329_, 35.173, 57.12, 1.8
_330_, 35.173, 57.12, 1.8
_332_, 35.173, 57.12, 1.8
_346_, 35.173, 57.12, 1.8
ANTENNA__341__B1, 48.506, 57.12, 1.8
ANTENNA__341__B2, 48.506, 57.12, 1.8
ANTENNA__350__B1, 48.506, 57.12, 1.8
ANTENNA__350__B2, 48.506, 57.12, 1.8
_325_, 48.506, 57.12, 1.8
_333_, 48.506, 57.12, 1.8
_335_, 48.506, 57.12, 1.8
_338_, 48.506, 57.12, 1.8
_340_, 48.506, 57.12, 1.8
_341_, 48.506, 57.12, 1.8
ringosc.dstage\[8\].id.delayenb1, 48.506, 57.12, 1.8
PHY_32, 5.52, 51.68, 1.8
PHY_34, 5.52, 51.68, 1.8
_299_, 5.52, 51.68, 1.8
ringosc.dstage\[3\].id.delayenb0, 5.52, 51.68, 1.8
PHY_33, 69.46, 51.68, 1.8
PHY_35, 69.46, 51.68, 1.8
ANTENNA__295__A1, 13.68, 51.68, 1.8
ANTENNA__295__A2, 13.68, 51.68, 1.8
_305_, 13.68, 51.68, 1.8
ringosc.dstage\[2\].id.delayen1, 13.68, 51.68, 1.8
ringosc.dstage\[3\].id.delaybuf0, 13.68, 51.68, 1.8
ringosc.dstage\[5\].id.delayen0, 13.68, 51.68, 1.8
ANTENNA__346__B2, 35.173, 51.68, 1.8
_293_, 35.173, 51.68, 1.8
_294_, 35.173, 51.68, 1.8
_298_, 35.173, 51.68, 1.8
_314_, 35.173, 51.68, 1.8
_315_, 35.173, 51.68, 1.8
_317_, 35.173, 51.68, 1.8
_326_, 35.173, 51.68, 1.8
_331_, 35.173, 51.68, 1.8
ANTENNA__326__A2, 48.506, 51.68, 1.8
ANTENNA__334__B1, 48.506, 51.68, 1.8
_177_, 48.506, 51.68, 1.8
_290_, 48.506, 51.68, 1.8
_291_, 48.506, 51.68, 1.8
_292_, 48.506, 51.68, 1.8
_324_, 48.506, 51.68, 1.8
_339_, 48.506, 51.68, 1.8
_347_, 48.506, 51.68, 1.8
_348_, 48.506, 51.68, 1.8
ANTENNA__299__A1, 5.52, 46.24, 1.8
ANTENNA__300__A2, 5.52, 46.24, 1.8
ANTENNA__305__A2, 5.52, 46.24, 1.8
PHY_28, 5.52, 46.24, 1.8
PHY_30, 5.52, 46.24, 1.8
ringosc.dstage\[2\].id.delayen0, 5.52, 46.24, 1.8
ringosc.dstage\[2\].id.delayenb0, 5.52, 46.24, 1.8
PHY_29, 69.46, 46.24, 1.8
PHY_31, 69.46, 46.24, 1.8
ringosc.dstage\[11\].id.delaybuf0, 69.46, 46.24, 1.8
ringosc.iss.delaybuf0, 69.46, 46.24, 1.8
ANTENNA__289__A1, 13.68, 46.24, 1.8
_295_, 13.68, 46.24, 1.8
ringosc.dstage\[2\].id.delaybuf0, 13.68, 46.24, 1.8
ringosc.dstage\[2\].id.delayenb1, 13.68, 46.24, 1.8
ANTENNA__319__A1, 35.173, 46.24, 1.8
ANTENNA__319__A2, 35.173, 46.24, 1.8
ANTENNA__326__A1, 35.173, 46.24, 1.8
_231_, 35.173, 46.24, 1.8
_248_, 35.173, 46.24, 1.8
_288_, 35.173, 46.24, 1.8
_319_, 35.173, 46.24, 1.8
_320_, 35.173, 46.24, 1.8
_321_, 35.173, 46.24, 1.8
_322_, 35.173, 46.24, 1.8
ringosc.dstage\[1\].id.delaybuf1, 35.173, 46.24, 1.8
ANTENNA__296__B, 48.506, 46.24, 1.8
ANTENNA__334__B2, 48.506, 46.24, 1.8
ANTENNA__337__A2, 48.506, 46.24, 1.8
FILLER_14_79, 48.506, 46.24, 1.8
_178_, 48.506, 46.24, 1.8
_240_, 48.506, 46.24, 1.8
_242_, 48.506, 46.24, 1.8
_296_, 48.506, 46.24, 1.8
_307_, 48.506, 46.24, 1.8
_327_, 48.506, 46.24, 1.8
_334_, 48.506, 46.24, 1.8
_345_, 48.506, 46.24, 1.8
ANTENNA__299__A2, 5.52, 40.8, 1.8
PHY_24, 5.52, 40.8, 1.8
PHY_26, 5.52, 40.8, 1.8
clockp_buffer_1, 5.52, 40.8, 1.8
ringosc.ibufp10, 5.52, 40.8, 1.8
ANTENNA__351__A2, 69.46, 40.8, 1.8
PHY_25, 69.46, 40.8, 1.8
PHY_27, 69.46, 40.8, 1.8
ringosc.iss.delayint0, 69.46, 40.8, 1.8
ANTENNA__289__A2, 13.68, 40.8, 1.8
_378_, 13.68, 40.8, 1.8
ringosc.dstage\[2\].id.delaybuf1, 13.68, 40.8, 1.8
ANTENNA__288__A, 35.173, 40.8, 1.8
FILLER_13_69, 35.173, 40.8, 1.8
_179_, 35.173, 40.8, 1.8
_230_, 35.173, 40.8, 1.8
_250_, 35.173, 40.8, 1.8
_254_, 35.173, 40.8, 1.8
_256_, 35.173, 40.8, 1.8
_318_, 35.173, 40.8, 1.8
ringosc.dstage\[0\].id.delaybuf0, 35.173, 40.8, 1.8
_180_, 48.506, 40.8, 1.8
_228_, 48.506, 40.8, 1.8
_241_, 48.506, 40.8, 1.8
_252_, 48.506, 40.8, 1.8
_265_, 48.506, 40.8, 1.8
_266_, 48.506, 40.8, 1.8
PHY_20, 5.52, 35.36, 1.8
PHY_22, 5.52, 35.36, 1.8
_190_, 5.52, 35.36, 1.8
ringosc.ibufp11, 5.52, 35.36, 1.8
FILLER_11_131, 69.46, 35.36, 1.8
PHY_21, 69.46, 35.36, 1.8
PHY_23, 69.46, 35.36, 1.8
_183_, 13.68, 35.36, 1.8
_189_, 13.68, 35.36, 1.8
_400_, 13.68, 35.36, 1.8
ANTENNA__363__A, 35.173, 35.36, 1.8
_251_, 35.173, 35.36, 1.8
_253_, 35.173, 35.36, 1.8
_255_, 35.173, 35.36, 1.8
_257_, 35.173, 35.36, 1.8
_261_, 35.173, 35.36, 1.8
FILLER_10_85, 48.506, 35.36, 1.8
FILLER_11_85, 48.506, 35.36, 1.8
FILLER_12_107, 48.506, 35.36, 1.8
_249_, 48.506, 35.36, 1.8
_262_, 48.506, 35.36, 1.8
_263_, 48.506, 35.36, 1.8
_264_, 48.506, 35.36, 1.8
ANTENNA__207__A1, 5.52, 29.92, 1.8
ANTENNA__225__B1, 5.52, 29.92, 1.8
PHY_16, 5.52, 29.92, 1.8
PHY_18, 5.52, 29.92, 1.8
_207_, 5.52, 29.92, 1.8
_401_, 5.52, 29.92, 1.8
ANTENNA__368__A, 69.46, 29.92, 1.8
PHY_17, 69.46, 29.92, 1.8
PHY_19, 69.46, 29.92, 1.8
ringosc.dstage\[11\].id.delayint0, 69.46, 29.92, 1.8
ANTENNA__215__B1, 13.68, 29.92, 1.8
ANTENNA__302__A2, 13.68, 29.92, 1.8
_184_, 13.68, 29.92, 1.8
_191_, 13.68, 29.92, 1.8
_205_, 13.68, 29.92, 1.8
_215_, 13.68, 29.92, 1.8
ANTENNA__370__A, 35.173, 29.92, 1.8
FILLER_9_78, 35.173, 29.92, 1.8
_244_, 35.173, 29.92, 1.8
_246_, 35.173, 29.92, 1.8
_258_, 35.173, 29.92, 1.8
_274_, 35.173, 29.92, 1.8
_370_, 35.173, 29.92, 1.8
_243_, 48.506, 29.92, 1.8
_245_, 48.506, 29.92, 1.8
_247_, 48.506, 29.92, 1.8
_259_, 48.506, 29.92, 1.8
_260_, 48.506, 29.92, 1.8
_267_, 48.506, 29.92, 1.8
_391_, 48.506, 29.92, 1.8
PHY_12, 5.52, 24.48, 1.8
PHY_14, 5.52, 24.48, 1.8
_204_, 5.52, 24.48, 1.8
_206_, 5.52, 24.48, 1.8
_217_, 5.52, 24.48, 1.8
_225_, 5.52, 24.48, 1.8
PHY_13, 69.46, 24.48, 1.8
PHY_15, 69.46, 24.48, 1.8
ringosc.dstage\[11\].id.delaybuf1, 69.46, 24.48, 1.8
_192_, 13.68, 24.48, 1.8
_212_, 13.68, 24.48, 1.8
_213_, 13.68, 24.48, 1.8
_214_, 13.68, 24.48, 1.8
FILLER_8_70, 35.173, 24.48, 1.8
_232_, 35.173, 24.48, 1.8
_269_, 35.173, 24.48, 1.8
_270_, 35.173, 24.48, 1.8
_277_, 35.173, 24.48, 1.8
_278_, 35.173, 24.48, 1.8
_365_, 35.173, 24.48, 1.8
_388_, 35.173, 24.48, 1.8
_233_, 48.506, 24.48, 1.8
_268_, 48.506, 24.48, 1.8
_390_, 48.506, 24.48, 1.8
_392_, 48.506, 24.48, 1.8
ANTENNA__214__B1, 5.52, 19.04, 1.8
PHY_10, 5.52, 19.04, 1.8
PHY_8, 5.52, 19.04, 1.8
_224_, 5.52, 19.04, 1.8
_237_, 5.52, 19.04, 1.8
ANTENNA__353__A2, 69.46, 19.04, 1.8
FILLER_4_132, 69.46, 19.04, 1.8
PHY_11, 69.46, 19.04, 1.8
PHY_9, 69.46, 19.04, 1.8
ANTENNA__216__A, 13.68, 19.04, 1.8
_209_, 13.68, 19.04, 1.8
_216_, 13.68, 19.04, 1.8
_226_, 13.68, 19.04, 1.8
_227_, 13.68, 19.04, 1.8
ANTENNA__219__A, 35.173, 19.04, 1.8
ANTENNA__222__A1, 35.173, 19.04, 1.8
ANTENNA__365__A, 35.173, 19.04, 1.8
_208_, 35.173, 19.04, 1.8
_362_, 35.173, 19.04, 1.8
_384_, 35.173, 19.04, 1.8
_385_, 35.173, 19.04, 1.8
ANTENNA__361__A, 48.506, 19.04, 1.8
FILLER_6_95, 48.506, 19.04, 1.8
_234_, 48.506, 19.04, 1.8
_238_, 48.506, 19.04, 1.8
_239_, 48.506, 19.04, 1.8
_271_, 48.506, 19.04, 1.8
_272_, 48.506, 19.04, 1.8
_361_, 48.506, 19.04, 1.8
_389_, 48.506, 19.04, 1.8
PHY_4, 5.52, 13.6, 1.8
PHY_6, 5.52, 13.6, 1.8
_222_, 5.52, 13.6, 1.8
_223_, 5.52, 13.6, 1.8
_236_, 5.52, 13.6, 1.8
FILLER_3_132, 69.46, 13.6, 1.8
PHY_5, 69.46, 13.6, 1.8
PHY_7, 69.46, 13.6, 1.8
_199_, 13.68, 13.6, 1.8
_201_, 13.68, 13.6, 1.8
_219_, 13.68, 13.6, 1.8
_221_, 13.68, 13.6, 1.8
_235_, 13.68, 13.6, 1.8
_273_, 35.173, 13.6, 1.8
_279_, 35.173, 13.6, 1.8
_280_, 35.173, 13.6, 1.8
_281_, 35.173, 13.6, 1.8
_380_, 35.173, 13.6, 1.8
ANTENNA__357__A, 48.506, 13.6, 1.8
FILLER_2_79, 48.506, 13.6, 1.8
_285_, 48.506, 13.6, 1.8
_286_, 48.506, 13.6, 1.8
_387_, 48.506, 13.6, 1.8
ANTENNA__235__A, 5.52, 8.16, 1.8
PHY_0, 5.52, 8.16, 1.8
PHY_2, 5.52, 8.16, 1.8
_374_, 5.52, 8.16, 1.8
_397_, 5.52, 8.16, 1.8
clockp_buffer_0, 5.52, 8.16, 1.8
ANTENNA__371__A, 69.46, 8.16, 1.8
ANTENNA__394__D, 69.46, 8.16, 1.8
PHY_1, 69.46, 8.16, 1.8
PHY_3, 69.46, 8.16, 1.8
_187_, 13.68, 8.16, 1.8
_220_, 13.68, 8.16, 1.8
ANTENNA__355__A, 35.173, 8.16, 1.8
ANTENNA__355__B, 35.173, 8.16, 1.8
ANTENNA__359__A, 35.173, 8.16, 1.8
ANTENNA__374__A, 35.173, 8.16, 1.8
_282_, 35.173, 8.16, 1.8
_283_, 35.173, 8.16, 1.8
_359_, 35.173, 8.16, 1.8
_360_, 35.173, 8.16, 1.8
_383_, 35.173, 8.16, 1.8
ANTENNA__356__A, 48.506, 8.16, 1.8
ANTENNA__360__A, 48.506, 8.16, 1.8
_287_, 48.506, 8.16, 1.8
_356_, 48.506, 8.16, 1.8
_357_, 48.506, 8.16, 1.8
_371_, 48.506, 8.16, 1.8
_379_, 48.506, 8.16, 1.8
_381_, 48.506, 8.16, 1.8
_394_, 48.506, 8.16, 1.8

View File

@ -0,0 +1,72 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 3.0
Library name: digital_pll
Reading "sky130_fd_sc_hd__diode_2".
Reading "sky130_fd_sc_hd__fill_1".
Reading "sky130_fd_sc_hd__decap_3".
Reading "sky130_fd_sc_hd__dfrtp_2".
Reading "sky130_fd_sc_hd__clkbuf_16".
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
Reading "sky130_fd_sc_hd__mux2_1".
Reading "sky130_fd_sc_hd__or2_2".
Reading "sky130_fd_sc_hd__nand2_2".
Reading "sky130_fd_sc_hd__nor2_2".
Reading "sky130_fd_sc_hd__nand3_2".
Reading "sky130_fd_sc_hd__xnor2_2".
Reading "sky130_fd_sc_hd__and2_2".
Reading "sky130_fd_sc_hd__xor2_2".
Reading "sky130_fd_sc_hd__a21oi_2".
Reading "sky130_fd_sc_hd__fill_2".
Reading "sky130_fd_sc_hd__o22a_2".
Reading "sky130_fd_sc_hd__a21o_2".
Reading "sky130_fd_sc_hd__and3_2".
Reading "sky130_fd_sc_hd__decap_4".
Reading "sky130_fd_sc_hd__or3b_2".
Reading "sky130_fd_sc_hd__a211o_2".
Reading "sky130_fd_sc_hd__o31a_2".
Reading "sky130_fd_sc_hd__or3_2".
Reading "sky130_fd_sc_hd__and4_2".
Reading "sky130_fd_sc_hd__o21a_2".
Reading "sky130_fd_sc_hd__a32o_2".
Reading "sky130_fd_sc_hd__a2111oi_2".
Reading "sky130_fd_sc_hd__nand2b_2".
Reading "sky130_fd_sc_hd__o211a_2".
Reading "sky130_fd_sc_hd__or4bb_2".
Reading "sky130_fd_sc_hd__decap_6".
Reading "sky130_fd_sc_hd__and3b_2".
Reading "sky130_fd_sc_hd__einvp_2".
Reading "sky130_fd_sc_hd__einvn_4".
Reading "sky130_fd_sc_hd__clkbuf_1".
Reading "sky130_fd_sc_hd__inv_2".
Reading "sky130_fd_sc_hd__a31o_2".
Reading "sky130_ef_sc_hd__decap_12".
Reading "sky130_fd_sc_hd__o2bb2a_2".
Reading "sky130_fd_sc_hd__clkinv_1".
Reading "sky130_fd_sc_hd__clkinv_8".
Reading "sky130_fd_sc_hd__einvn_8".
Reading "sky130_fd_sc_hd__clkinv_2".
Reading "sky130_fd_sc_hd__conb_1".
Reading "sky130_fd_sc_hd__einvp_1".
Reading "sky130_fd_sc_hd__clkbuf_2".
Reading "sky130_fd_sc_hd__a21bo_2".
Reading "sky130_fd_sc_hd__o21ai_2".
Reading "sky130_fd_sc_hd__or4_2".
Reading "sky130_fd_sc_hd__a22o_2".
Reading "sky130_fd_sc_hd__and2b_2".
Reading "sky130_fd_sc_hd__o221a_2".
Reading "digital_pll".
[INFO]: Wrote /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/gds_ptrs.mag including GDS pointers.

View File

@ -0,0 +1,112 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef.
This action cannot be undone.
LEF read, Line 78 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 79 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 115 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 121 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 122 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 123 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 156 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 165 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 167 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 168 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 169 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 206 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 207 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 210 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 211 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 248 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 249 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 251 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 252 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 253 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 797 lines.
Reading DEF data from file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def.
This action cannot be undone.
Processed 4 vias total.
Processed 617 subcell instances total.
Processed 39 pins total.
Processed 2 special nets total.
Processed 333 nets total.
DEF read: Processed 6580 lines.
Root cell box:
width x height ( llx, lly ), ( urx, ury ) area (units^2)
microns: 75.000 x 75.000 ( 0.000, 0.000), ( 75.000, 75.000) 5625.000
lambda: 7500.00 x 7500.00 ( 0.00, 0.00 ), ( 7500.00, 7500.00) 56250000.00
internal: 15000 x 15000 ( 0, 0 ), ( 15000, 15000) 225000000
Generating output for cell sky130_fd_sc_hd__diode_2
Generating output for cell sky130_fd_sc_hd__fill_1
Generating output for cell sky130_fd_sc_hd__decap_3
Generating output for cell sky130_fd_sc_hd__dfrtp_2
Generating output for cell sky130_fd_sc_hd__clkbuf_16
Generating output for cell sky130_fd_sc_hd__tapvpwrvgnd_1
Generating output for cell sky130_fd_sc_hd__mux2_1
Generating output for cell sky130_fd_sc_hd__or2_2
Generating output for cell sky130_fd_sc_hd__nand2_2
Generating output for cell sky130_fd_sc_hd__nor2_2
Generating output for cell sky130_fd_sc_hd__nand3_2
Generating output for cell sky130_fd_sc_hd__xnor2_2
Generating output for cell sky130_fd_sc_hd__and2_2
Generating output for cell sky130_fd_sc_hd__xor2_2
Generating output for cell sky130_fd_sc_hd__a21oi_2
Generating output for cell sky130_fd_sc_hd__fill_2
Generating output for cell sky130_fd_sc_hd__o22a_2
Generating output for cell sky130_fd_sc_hd__a21o_2
Generating output for cell sky130_fd_sc_hd__and3_2
Generating output for cell sky130_fd_sc_hd__decap_4
Generating output for cell sky130_fd_sc_hd__or3b_2
Generating output for cell sky130_fd_sc_hd__a211o_2
Generating output for cell sky130_fd_sc_hd__o31a_2
Generating output for cell sky130_fd_sc_hd__or3_2
Generating output for cell sky130_fd_sc_hd__and4_2
Generating output for cell sky130_fd_sc_hd__o21a_2
Generating output for cell sky130_fd_sc_hd__a32o_2
Generating output for cell sky130_fd_sc_hd__a2111oi_2
Generating output for cell sky130_fd_sc_hd__nand2b_2
Generating output for cell sky130_fd_sc_hd__o211a_2
Generating output for cell sky130_fd_sc_hd__or4bb_2
Generating output for cell sky130_fd_sc_hd__decap_6
Generating output for cell sky130_fd_sc_hd__and3b_2
Generating output for cell sky130_fd_sc_hd__einvp_2
Generating output for cell sky130_fd_sc_hd__einvn_4
Generating output for cell sky130_fd_sc_hd__clkbuf_1
Generating output for cell sky130_fd_sc_hd__inv_2
Generating output for cell sky130_fd_sc_hd__a31o_2
Generating output for cell sky130_ef_sc_hd__decap_12
Generating output for cell sky130_fd_sc_hd__o2bb2a_2
Generating output for cell sky130_fd_sc_hd__clkinv_1
Generating output for cell sky130_fd_sc_hd__clkinv_8
Generating output for cell sky130_fd_sc_hd__einvn_8
Generating output for cell sky130_fd_sc_hd__clkinv_2
Generating output for cell sky130_fd_sc_hd__conb_1
Generating output for cell sky130_fd_sc_hd__einvp_1
Generating output for cell sky130_fd_sc_hd__clkbuf_2
Generating output for cell sky130_fd_sc_hd__a21bo_2
Generating output for cell sky130_fd_sc_hd__o21ai_2
Generating output for cell sky130_fd_sc_hd__or4_2
Generating output for cell sky130_fd_sc_hd__a22o_2
Generating output for cell sky130_fd_sc_hd__and2b_2
Generating output for cell sky130_fd_sc_hd__o221a_2
Generating output for cell digital_pll
[INFO]: GDS Write Complete

View File

@ -0,0 +1,209 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef.
This action cannot be undone.
LEF read, Line 78 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 79 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 115 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 121 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 122 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 123 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 156 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 165 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 167 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 168 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 169 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 206 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 207 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 210 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 211 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 248 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 249 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 251 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 252 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 253 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 797 lines.
digital_pll: 10000 rects
[INFO]: Writing abstract LEF
Generating LEF output /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.lef for cell digital_pll:
Diagnostic: Write LEF header for cell digital_pll
Diagnostic: Writing LEF output for cell digital_pll
Warning: Parent cell lists instance of "sky130_fd_sc_hd__einvp_1" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__einvp_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__einvp_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkinv_1" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__clkinv_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkinv_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__einvn_4" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__einvn_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__einvn_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__einvn_8" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__einvn_8.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__einvn_8.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__einvp_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__einvp_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__einvp_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_1" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__clkbuf_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__or2_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__or2_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__or2_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__conb_1" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__conb_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__conb_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkinv_8" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__clkinv_8.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkinv_8.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkinv_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__clkinv_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkinv_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__clkbuf_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__clkbuf_16" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__clkbuf_16.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__clkbuf_16.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__dfrtp_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__dfrtp_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__dfrtp_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nor2_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__nor2_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nor2_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__nand2_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nand2_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a22o_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__a22o_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a22o_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21o_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__a21o_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a21o_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__and3b_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__and3b_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__and3b_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a32o_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__a32o_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a32o_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__or3_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__or3_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__or3_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21ai_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__o21ai_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o21ai_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__and3_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__and3_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__and3_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o221a_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__o221a_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o221a_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o22a_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__o22a_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o22a_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o211a_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__o211a_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o211a_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a211o_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__a211o_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a211o_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o31a_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__o31a_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o31a_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand2b_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__nand2b_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nand2b_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2b_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__and2b_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__and2b_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__mux2_1" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__mux2_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__mux2_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__nand3_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__nand3_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__nand3_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21oi_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__a21oi_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a21oi_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__xnor2_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__xnor2_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__xnor2_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o21a_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__o21a_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o21a_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__and2_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__and2_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__and2_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__o2bb2a_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__o2bb2a_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__o2bb2a_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__xor2_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__xor2_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__xor2_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a21bo_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__a21bo_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a21bo_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__or4_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__or4_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__or4_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__and4_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__and4_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__and4_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__or3b_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__or3b_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__or3b_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__or4bb_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__or4bb_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__or4bb_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a2111oi_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__a2111oi_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a2111oi_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__a31o_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__a31o_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__a31o_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__inv_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__inv_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__inv_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__tapvpwrvgnd_1" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__tapvpwrvgnd_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__tapvpwrvgnd_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_3" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__decap_3.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_3.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_1" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__fill_1.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_1.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_4" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__decap_4.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_4.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__fill_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__fill_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__fill_2.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_ef_sc_hd__decap_12" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_ef_sc_hd__decap_12.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_ef_sc_hd__decap_12.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__decap_6" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__decap_6.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__decap_6.mag.
The discovered version will be used.
Warning: Parent cell lists instance of "sky130_fd_sc_hd__diode_2" at bad file path /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/sky130_fd_sc_hd__diode_2.mag.
The cell exists in the search paths at /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/maglef/sky130_fd_sc_hd__diode_2.mag.
The discovered version will be used.
Diagnostic: Scale value is 0.005000
[INFO]: LEF Write Complete

View File

@ -0,0 +1,18 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.lef.
This action cannot be undone.
LEF read: Processed 404 lines.
[INFO]: DONE GENERATING MAGLEF VIEW

View File

@ -0,0 +1,17 @@
Input: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
Output: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.klayout.gds
Design: digital_pll
Technology File: /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/klayout/tech/sky130A.lyt
GDS File List: ['/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds']
LEF File: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef
[INFO] Clearing cells...
[INFO] Merging GDS files...
/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds
[INFO] Copying toplevel cell 'digital_pll'
WARNING: no fill config file specified
[INFO] Checking for missing GDS...
[INFO] All LEF cells have matching GDS cells
[INFO] Writing out GDS '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.klayout.gds'
[INFO] Done.

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@ -0,0 +1,820 @@
First Layout: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.gds
Second Layout: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.klayout.gds
Design Name: digital_pll
Output GDS will be: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.xor.xml
Reading /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.gds ..
Reading /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.klayout.gds ..
--- Running XOR for 10/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 146 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 146 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 146
"output" in: xor.drc:40
Polygons (raw): 146 (flat) 5 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
--- Running XOR for 11/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 47 (flat) 7 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 47 (flat) 7 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 47
"output" in: xor.drc:40
Polygons (raw): 47 (flat) 7 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 11/1 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 11/2 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 3
"output" in: xor.drc:40
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
--- Running XOR for 12/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 5 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 5 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 5
"output" in: xor.drc:40
Polygons (raw): 5 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 122/16 ---
"input" in: xor.drc:38
Polygons (raw): 569 (flat) 53 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 569 (flat) 53 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 13/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 8 (flat) 4 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 8 (flat) 4 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 8
"output" in: xor.drc:40
Polygons (raw): 8 (flat) 4 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 13/1 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
--- Running XOR for 13/2 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 3
"output" in: xor.drc:40
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 14/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
XOR differences: 1
"output" in: xor.drc:40
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 235/4 ---
"input" in: xor.drc:38
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 1
"output" in: xor.drc:40
Polygons (raw): 1 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 236/0 ---
"input" in: xor.drc:38
Polygons (raw): 483 (flat) 50 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 483 (flat) 50 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 3/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 1164 (flat) 1 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 1164 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 1164
"output" in: xor.drc:40
Polygons (raw): 1164 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 4/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 1164 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 1164 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 1164
"output" in: xor.drc:40
Polygons (raw): 1164 (flat) 1 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
--- Running XOR for 5/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 4168 (flat) 1835 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 4168 (flat) 1835 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 4168
"output" in: xor.drc:40
Polygons (raw): 4168 (flat) 1835 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 6/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 1317 (flat) 7 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 1317 (flat) 7 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 1317
"output" in: xor.drc:40
Polygons (raw): 1317 (flat) 7 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 64/16 ---
"input" in: xor.drc:38
Polygons (raw): 569 (flat) 53 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 569 (flat) 53 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 349.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
--- Running XOR for 64/20 ---
"input" in: xor.drc:38
Polygons (raw): 617 (flat) 53 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
"input" in: xor.drc:38
Polygons (raw): 617 (flat) 53 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 64/5 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 64/59 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 65/20 ---
"input" in: xor.drc:38
Polygons (raw): 1245 (flat) 138 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 1245 (flat) 138 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 65/44 ---
"input" in: xor.drc:38
Polygons (raw): 100 (flat) 2 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 100 (flat) 2 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 66/15 ---
"input" in: xor.drc:38
Polygons (raw): 2 (flat) 2 (hierarchical)
Elapsed: 0.010s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 2 (flat) 2 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
--- Running XOR for 66/20 ---
"input" in: xor.drc:38
Polygons (raw): 1620 (flat) 218 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"input" in: xor.drc:38
Polygons (raw): 1620 (flat) 218 (hierarchical)
Elapsed: 0.000s Memory: 348.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.030s Memory: 349.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
--- Running XOR for 66/44 ---
"input" in: xor.drc:38
Polygons (raw): 9720 (flat) 1249 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
"input" in: xor.drc:38
Polygons (raw): 9720 (flat) 1249 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.050s Memory: 349.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 349.00M
--- Running XOR for 67/16 ---
"input" in: xor.drc:38
Polygons (raw): 3438 (flat) 342 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
"input" in: xor.drc:38
Polygons (raw): 3438 (flat) 342 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.020s Memory: 349.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
--- Running XOR for 67/20 ---
"input" in: xor.drc:38
Polygons (raw): 4910 (flat) 1554 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
"input" in: xor.drc:38
Polygons (raw): 3746 (flat) 390 (hierarchical)
Elapsed: 0.000s Memory: 349.00M
"^" in: xor.drc:38
Polygons (raw): 86 (flat) 86 (hierarchical)
Elapsed: 0.060s Memory: 352.00M
XOR differences: 86
"output" in: xor.drc:40
Polygons (raw): 86 (flat) 86 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 67/44 ---
"input" in: xor.drc:38
Polygons (raw): 7822 (flat) 1976 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 6658 (flat) 812 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 1164 (flat) 1164 (hierarchical)
Elapsed: 0.030s Memory: 352.00M
XOR differences: 1164
"output" in: xor.drc:40
Polygons (raw): 1164 (flat) 1164 (hierarchical)
Elapsed: 0.010s Memory: 352.00M
--- Running XOR for 67/5 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 68/16 ---
"input" in: xor.drc:38
Polygons (raw): 1272 (flat) 110 (hierarchical)
Elapsed: 0.010s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 1272 (flat) 110 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 352.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 68/20 ---
"input" in: xor.drc:38
Polygons (raw): 6690 (flat) 5328 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 1481 (flat) 119 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 1017 (flat) 1017 (hierarchical)
Elapsed: 0.030s Memory: 352.00M
XOR differences: 1017
"output" in: xor.drc:40
Polygons (raw): 1017 (flat) 1017 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 68/44 ---
"input" in: xor.drc:38
Polygons (raw): 1317 (flat) 1317 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 1317 (flat) 1317 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
XOR differences: 1317
"output" in: xor.drc:40
Polygons (raw): 1317 (flat) 1317 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 68/5 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 352.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 69/16 ---
"input" in: xor.drc:38
Polygons (raw): 15 (flat) 15 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 15 (flat) 15 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
XOR differences: 15
"output" in: xor.drc:40
Polygons (raw): 15 (flat) 15 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 69/20 ---
"input" in: xor.drc:38
Polygons (raw): 2194 (flat) 2194 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 2194 (flat) 2194 (hierarchical)
Elapsed: 0.010s Memory: 352.00M
XOR differences: 2194
"output" in: xor.drc:40
Polygons (raw): 2194 (flat) 2194 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 69/44 ---
"input" in: xor.drc:38
Polygons (raw): 239 (flat) 239 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 239 (flat) 239 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
XOR differences: 239
"output" in: xor.drc:40
Polygons (raw): 239 (flat) 239 (hierarchical)
Elapsed: 0.010s Memory: 352.00M
--- Running XOR for 7/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 2232 (flat) 933 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 2232 (flat) 933 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
XOR differences: 2232
"output" in: xor.drc:40
Polygons (raw): 2232 (flat) 933 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 7/1 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 352.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 7/2 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 15 (flat) 15 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 15 (flat) 15 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
XOR differences: 15
"output" in: xor.drc:40
Polygons (raw): 15 (flat) 15 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 70/16 ---
"input" in: xor.drc:38
Polygons (raw): 22 (flat) 22 (hierarchical)
Elapsed: 0.010s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 22 (flat) 22 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
XOR differences: 22
"output" in: xor.drc:40
Polygons (raw): 22 (flat) 22 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 70/20 ---
"input" in: xor.drc:38
Polygons (raw): 335 (flat) 335 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 335 (flat) 335 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
XOR differences: 335
"output" in: xor.drc:40
Polygons (raw): 335 (flat) 335 (hierarchical)
Elapsed: 0.010s Memory: 352.00M
--- Running XOR for 70/44 ---
"input" in: xor.drc:38
Polygons (raw): 146 (flat) 146 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"^" in: xor.drc:38
Polygons (raw): 146 (flat) 146 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
XOR differences: 146
"output" in: xor.drc:40
Polygons (raw): 146 (flat) 146 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
--- Running XOR for 71/16 ---
"input" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 352.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
XOR differences: 3
"output" in: xor.drc:40
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 71/20 ---
"input" in: xor.drc:38
Polygons (raw): 6 (flat) 6 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 6 (flat) 6 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 6
"output" in: xor.drc:40
Polygons (raw): 6 (flat) 6 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 71/44 ---
"input" in: xor.drc:38
Polygons (raw): 5 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 5 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 5
"output" in: xor.drc:40
Polygons (raw): 5 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 72/16 ---
"input" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 3
"output" in: xor.drc:40
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 72/20 ---
"input" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 3
"output" in: xor.drc:40
Polygons (raw): 3 (flat) 3 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 78/44 ---
"input" in: xor.drc:38
Polygons (raw): 664 (flat) 56 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 664 (flat) 56 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 8/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 239 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 239 (flat) 5 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
XOR differences: 239
"output" in: xor.drc:40
Polygons (raw): 239 (flat) 5 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 81/23 ---
"input" in: xor.drc:38
Polygons (raw): 94 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 94 (flat) 1 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 81/4 ---
"input" in: xor.drc:38
Polygons (raw): 617 (flat) 53 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 617 (flat) 53 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
--- Running XOR for 83/44 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 9/0 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 271 (flat) 106 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 271 (flat) 106 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 271
"output" in: xor.drc:40
Polygons (raw): 271 (flat) 106 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 9/1 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
--- Running XOR for 9/2 ---
"input" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 22 (flat) 22 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 22 (flat) 22 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 22
"output" in: xor.drc:40
Polygons (raw): 22 (flat) 22 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 93/44 ---
"input" in: xor.drc:38
Polygons (raw): 667 (flat) 54 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 667 (flat) 54 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 94/20 ---
"input" in: xor.drc:38
Polygons (raw): 667 (flat) 54 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 667 (flat) 54 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
--- Running XOR for 95/20 ---
"input" in: xor.drc:38
Polygons (raw): 430 (flat) 57 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"input" in: xor.drc:38
Polygons (raw): 430 (flat) 57 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
"^" in: xor.drc:38
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.010s Memory: 353.00M
XOR differences: 0
"output" in: xor.drc:40
Polygons (raw): 0 (flat) 0 (hierarchical)
Elapsed: 0.000s Memory: 353.00M
Writing report database: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.xor.xml ..
Total elapsed: 0.770s Memory: 353.00M

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@ -0,0 +1 @@
Total XOR differences = 17361

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@ -0,0 +1,109 @@
Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Reading LEF data from file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef.
This action cannot be undone.
LEF read, Line 78 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 79 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 112 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 114 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 115 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 121 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 122 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 123 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 156 (Message): Unknown keyword "MINENCLOSEDAREA" in LEF file; ignoring.
LEF read, Line 164 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 165 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 167 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 168 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 169 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 206 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 207 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 209 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 210 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 211 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 248 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 249 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read, Line 251 (Message): Unknown keyword "MAXIMUMDENSITY" in LEF file; ignoring.
LEF read, Line 252 (Message): Unknown keyword "DENSITYCHECKWINDOW" in LEF file; ignoring.
LEF read, Line 253 (Message): Unknown keyword "DENSITYCHECKSTEP" in LEF file; ignoring.
LEF read, Line 290 (Message): Unknown keyword "ANTENNAMODEL" in LEF file; ignoring.
LEF read, Line 291 (Message): Unknown keyword "ANTENNADIFFSIDEAREARATIO" in LEF file; ignoring.
LEF read: Processed 797 lines.
Reading DEF data from file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def.
This action cannot be undone.
Processed 4 vias total.
Processed 617 subcell instances total.
Processed 39 pins total.
Processed 2 special nets total.
Processed 333 nets total.
DEF read: Processed 6580 lines.
Processing digital_pll
Extracting sky130_fd_sc_hd__diode_2 into sky130_fd_sc_hd__diode_2.ext:
Extracting sky130_fd_sc_hd__fill_1 into sky130_fd_sc_hd__fill_1.ext:
Extracting sky130_fd_sc_hd__decap_3 into sky130_fd_sc_hd__decap_3.ext:
Extracting sky130_fd_sc_hd__dfrtp_2 into sky130_fd_sc_hd__dfrtp_2.ext:
Extracting sky130_fd_sc_hd__clkbuf_16 into sky130_fd_sc_hd__clkbuf_16.ext:
Extracting sky130_fd_sc_hd__tapvpwrvgnd_1 into sky130_fd_sc_hd__tapvpwrvgnd_1.ext:
Extracting sky130_fd_sc_hd__mux2_1 into sky130_fd_sc_hd__mux2_1.ext:
Extracting sky130_fd_sc_hd__or2_2 into sky130_fd_sc_hd__or2_2.ext:
Extracting sky130_fd_sc_hd__nand2_2 into sky130_fd_sc_hd__nand2_2.ext:
Extracting sky130_fd_sc_hd__nor2_2 into sky130_fd_sc_hd__nor2_2.ext:
Extracting sky130_fd_sc_hd__nand3_2 into sky130_fd_sc_hd__nand3_2.ext:
Extracting sky130_fd_sc_hd__xnor2_2 into sky130_fd_sc_hd__xnor2_2.ext:
Extracting sky130_fd_sc_hd__and2_2 into sky130_fd_sc_hd__and2_2.ext:
Extracting sky130_fd_sc_hd__xor2_2 into sky130_fd_sc_hd__xor2_2.ext:
Extracting sky130_fd_sc_hd__a21oi_2 into sky130_fd_sc_hd__a21oi_2.ext:
Extracting sky130_fd_sc_hd__fill_2 into sky130_fd_sc_hd__fill_2.ext:
Extracting sky130_fd_sc_hd__o22a_2 into sky130_fd_sc_hd__o22a_2.ext:
Extracting sky130_fd_sc_hd__a21o_2 into sky130_fd_sc_hd__a21o_2.ext:
Extracting sky130_fd_sc_hd__and3_2 into sky130_fd_sc_hd__and3_2.ext:
Extracting sky130_fd_sc_hd__decap_4 into sky130_fd_sc_hd__decap_4.ext:
Extracting sky130_fd_sc_hd__or3b_2 into sky130_fd_sc_hd__or3b_2.ext:
Extracting sky130_fd_sc_hd__a211o_2 into sky130_fd_sc_hd__a211o_2.ext:
Extracting sky130_fd_sc_hd__o31a_2 into sky130_fd_sc_hd__o31a_2.ext:
Extracting sky130_fd_sc_hd__or3_2 into sky130_fd_sc_hd__or3_2.ext:
Extracting sky130_fd_sc_hd__and4_2 into sky130_fd_sc_hd__and4_2.ext:
Extracting sky130_fd_sc_hd__o21a_2 into sky130_fd_sc_hd__o21a_2.ext:
Extracting sky130_fd_sc_hd__a32o_2 into sky130_fd_sc_hd__a32o_2.ext:
Extracting sky130_fd_sc_hd__a2111oi_2 into sky130_fd_sc_hd__a2111oi_2.ext:
Extracting sky130_fd_sc_hd__nand2b_2 into sky130_fd_sc_hd__nand2b_2.ext:
Extracting sky130_fd_sc_hd__o211a_2 into sky130_fd_sc_hd__o211a_2.ext:
Extracting sky130_fd_sc_hd__or4bb_2 into sky130_fd_sc_hd__or4bb_2.ext:
Extracting sky130_fd_sc_hd__decap_6 into sky130_fd_sc_hd__decap_6.ext:
Extracting sky130_fd_sc_hd__and3b_2 into sky130_fd_sc_hd__and3b_2.ext:
Extracting sky130_fd_sc_hd__einvp_2 into sky130_fd_sc_hd__einvp_2.ext:
Extracting sky130_fd_sc_hd__einvn_4 into sky130_fd_sc_hd__einvn_4.ext:
Extracting sky130_fd_sc_hd__clkbuf_1 into sky130_fd_sc_hd__clkbuf_1.ext:
Extracting sky130_fd_sc_hd__inv_2 into sky130_fd_sc_hd__inv_2.ext:
Extracting sky130_fd_sc_hd__a31o_2 into sky130_fd_sc_hd__a31o_2.ext:
Extracting sky130_ef_sc_hd__decap_12 into sky130_ef_sc_hd__decap_12.ext:
Extracting sky130_fd_sc_hd__o2bb2a_2 into sky130_fd_sc_hd__o2bb2a_2.ext:
Extracting sky130_fd_sc_hd__clkinv_1 into sky130_fd_sc_hd__clkinv_1.ext:
Extracting sky130_fd_sc_hd__clkinv_8 into sky130_fd_sc_hd__clkinv_8.ext:
Extracting sky130_fd_sc_hd__einvn_8 into sky130_fd_sc_hd__einvn_8.ext:
Extracting sky130_fd_sc_hd__clkinv_2 into sky130_fd_sc_hd__clkinv_2.ext:
Extracting sky130_fd_sc_hd__conb_1 into sky130_fd_sc_hd__conb_1.ext:
Extracting sky130_fd_sc_hd__einvp_1 into sky130_fd_sc_hd__einvp_1.ext:
Extracting sky130_fd_sc_hd__clkbuf_2 into sky130_fd_sc_hd__clkbuf_2.ext:
Extracting sky130_fd_sc_hd__a21bo_2 into sky130_fd_sc_hd__a21bo_2.ext:
Extracting sky130_fd_sc_hd__o21ai_2 into sky130_fd_sc_hd__o21ai_2.ext:
Extracting sky130_fd_sc_hd__or4_2 into sky130_fd_sc_hd__or4_2.ext:
Extracting sky130_fd_sc_hd__a22o_2 into sky130_fd_sc_hd__a22o_2.ext:
Extracting sky130_fd_sc_hd__and2b_2 into sky130_fd_sc_hd__and2b_2.ext:
Extracting sky130_fd_sc_hd__o221a_2 into sky130_fd_sc_hd__o221a_2.ext:
Extracting digital_pll into digital_pll.ext:
digital_pll: 34 errors
Total of 34 errors (check feedback entries).
exttospice finished.

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@ -0,0 +1,25 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef
[WARNING ODB-0220] WARNING (LEFPARS-2036): SOURCE statement is obsolete in version 5.6 and later.
The LEF parser will ignore this statement.
To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef at line 930.
[INFO ODB-0223] Created 13 technology layers
[INFO ODB-0224] Created 25 technology vias
[INFO ODB-0225] Created 441 library cells
[INFO ODB-0226] Finished LEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/merged.nom.lef
[INFO ODB-0127] Reading DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
[INFO ODB-0128] Design: digital_pll
[INFO ODB-0130] Created 39 pins.
[INFO ODB-0131] Created 617 components and 3559 component-terminals.
[INFO ODB-0132] Created 2 special nets and 2368 connections.
[INFO ODB-0133] Created 333 nets and 1190 connections.
[INFO ODB-0134] Finished DEF file: /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.def
Top-level design name: digital_pll
Found default power net 'VPWR'
Found default ground net 'VGND'
Found 1 power ports.
Found 1 ground ports.
Modified power connections of 617/617 cells.

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@ -0,0 +1,8 @@
OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Reading /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.odb
Setting global connections for newly added cells...
[WARNING] Did not save OpenROAD database!
Writing netlist to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/26-digital_pll.nl.v...
Writing powered netlist to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/26-digital_pll.pnl.v...

File diff suppressed because it is too large Load Diff

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@ -0,0 +1,3 @@
LVS reports no net, device, pin, or property mismatches.
Total errors = 0

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@ -0,0 +1,355 @@
Netgen 1.5.234 compiled on Sun Oct 9 10:24:01 UTC 2022
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Generating JSON file result
Reading netlist file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.spice
Reading netlist file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/26-digital_pll.pnl.v
Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module sky130_fd_sc_hd__inv_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__xnor2_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__xor2_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__mux2_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__nand2_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__or2_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__and2_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__nor2_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__a21o_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__a211o_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__a31o_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__o211a_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__nand3_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__a32o_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__a21oi_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__or3_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__o22a_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__a2111oi_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__o21a_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__o31a_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__or4bb_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__and3_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__or3b_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__and4_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__or4_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__a21bo_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__o21ai_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__o2bb2a_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__nand2b_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__and2b_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__a22o_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__o221a_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__and3b_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__dfrtp_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_16.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkbuf_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__einvp_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__einvn_8.
Creating placeholder cell definition for module sky130_fd_sc_hd__einvn_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkinv_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkinv_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__clkinv_8.
Creating placeholder cell definition for module sky130_fd_sc_hd__conb_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__einvp_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_3.
Creating placeholder cell definition for module sky130_fd_sc_hd__tapvpwrvgnd_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__diode_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_1.
Creating placeholder cell definition for module sky130_fd_sc_hd__fill_2.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_4.
Creating placeholder cell definition for module sky130_fd_sc_hd__decap_6.
Creating placeholder cell definition for module sky130_ef_sc_hd__decap_12.
Reading setup file /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/netgen/sky130A_setup.tcl
Comparison output logged to file /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/logs/signoff/29-digital_pll.lef.log
Logging to file "/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/logs/signoff/29-digital_pll.lef.log" enabled
Circuit sky130_fd_sc_hd__and3_2 contains no devices.
Circuit sky130_fd_sc_hd__nor2_2 contains no devices.
Circuit sky130_fd_sc_hd__clkinv_1 contains no devices.
Circuit sky130_fd_sc_hd__a32o_2 contains no devices.
Circuit sky130_fd_sc_hd__o211a_2 contains no devices.
Circuit sky130_fd_sc_hd__xor2_2 contains no devices.
Circuit sky130_fd_sc_hd__a21o_2 contains no devices.
Circuit sky130_fd_sc_hd__einvp_2 contains no devices.
Circuit sky130_fd_sc_hd__fill_1 contains no devices.
Circuit sky130_fd_sc_hd__einvn_8 contains no devices.
Circuit sky130_fd_sc_hd__and2b_2 contains no devices.
Circuit sky130_fd_sc_hd__nand2_2 contains no devices.
Circuit sky130_fd_sc_hd__nand2b_2 contains no devices.
Circuit sky130_fd_sc_hd__or2_2 contains no devices.
Circuit sky130_fd_sc_hd__decap_3 contains no devices.
Circuit sky130_fd_sc_hd__xnor2_2 contains no devices.
Circuit sky130_fd_sc_hd__einvn_4 contains no devices.
Circuit sky130_fd_sc_hd__o21ai_2 contains no devices.
Circuit sky130_fd_sc_hd__o21a_2 contains no devices.
Circuit sky130_fd_sc_hd__fill_2 contains no devices.
Circuit sky130_fd_sc_hd__a21oi_2 contains no devices.
Circuit sky130_fd_sc_hd__diode_2 contains no devices.
Circuit sky130_fd_sc_hd__clkbuf_2 contains no devices.
Circuit sky130_fd_sc_hd__a22o_2 contains no devices.
Circuit sky130_fd_sc_hd__and2_2 contains no devices.
Circuit sky130_fd_sc_hd__o22a_2 contains no devices.
Circuit sky130_fd_sc_hd__clkbuf_1 contains no devices.
Circuit sky130_fd_sc_hd__or3_2 contains no devices.
Circuit sky130_fd_sc_hd__mux2_1 contains no devices.
Circuit sky130_fd_sc_hd__and4_2 contains no devices.
Circuit sky130_fd_sc_hd__dfrtp_2 contains no devices.
Circuit sky130_fd_sc_hd__or3b_2 contains no devices.
Circuit sky130_fd_sc_hd__a211o_2 contains no devices.
Circuit sky130_fd_sc_hd__a21bo_2 contains no devices.
Circuit sky130_fd_sc_hd__einvp_1 contains no devices.
Circuit sky130_fd_sc_hd__or4bb_2 contains no devices.
Circuit sky130_fd_sc_hd__inv_2 contains no devices.
Circuit sky130_fd_sc_hd__tapvpwrvgnd_1 contains no devices.
Circuit sky130_fd_sc_hd__decap_4 contains no devices.
Circuit sky130_fd_sc_hd__nand3_2 contains no devices.
Circuit sky130_fd_sc_hd__o221a_2 contains no devices.
Circuit sky130_fd_sc_hd__o2bb2a_2 contains no devices.
Circuit sky130_fd_sc_hd__and3b_2 contains no devices.
Circuit sky130_fd_sc_hd__clkbuf_16 contains no devices.
Circuit sky130_ef_sc_hd__decap_12 contains no devices.
Circuit sky130_fd_sc_hd__clkinv_2 contains no devices.
Circuit sky130_fd_sc_hd__o31a_2 contains no devices.
Circuit sky130_fd_sc_hd__clkinv_8 contains no devices.
Circuit sky130_fd_sc_hd__decap_6 contains no devices.
Circuit sky130_fd_sc_hd__or4_2 contains no devices.
Circuit sky130_fd_sc_hd__conb_1 contains no devices.
Circuit sky130_fd_sc_hd__a2111oi_2 contains no devices.
Circuit sky130_fd_sc_hd__a31o_2 contains no devices.
Contents of circuit 1: Circuit: 'digital_pll'
Circuit digital_pll contains 617 device instances.
Class: sky130_fd_sc_hd__a31o_2 instances: 1
Class: sky130_fd_sc_hd__a21o_2 instances: 12
Class: sky130_fd_sc_hd__clkbuf_16 instances: 2
Class: sky130_fd_sc_hd__or4_2 instances: 1
Class: sky130_fd_sc_hd__and3b_2 instances: 1
Class: sky130_fd_sc_hd__xor2_2 instances: 3
Class: sky130_ef_sc_hd__decap_12 instances: 2
Class: sky130_fd_sc_hd__dfrtp_2 instances: 23
Class: sky130_fd_sc_hd__and4_2 instances: 1
Class: sky130_fd_sc_hd__inv_2 instances: 6
Class: sky130_fd_sc_hd__clkbuf_1 instances: 13
Class: sky130_fd_sc_hd__clkbuf_2 instances: 12
Class: sky130_fd_sc_hd__or3_2 instances: 6
Class: sky130_fd_sc_hd__nand3_2 instances: 2
Class: sky130_fd_sc_hd__conb_1 instances: 1
Class: sky130_fd_sc_hd__and2b_2 instances: 1
Class: sky130_fd_sc_hd__a21bo_2 instances: 1
Class: sky130_fd_sc_hd__clkinv_1 instances: 13
Class: sky130_fd_sc_hd__clkinv_2 instances: 2
Class: sky130_fd_sc_hd__clkinv_8 instances: 2
Class: sky130_fd_sc_hd__and3_2 instances: 7
Class: sky130_fd_sc_hd__decap_3 instances: 54
Class: sky130_fd_sc_hd__decap_4 instances: 7
Class: sky130_fd_sc_hd__decap_6 instances: 1
Class: sky130_fd_sc_hd__or2_2 instances: 22
Class: sky130_fd_sc_hd__a2111oi_2 instances: 1
Class: sky130_fd_sc_hd__einvp_1 instances: 1
Class: sky130_fd_sc_hd__einvp_2 instances: 26
Class: sky130_fd_sc_hd__nand2_2 instances: 16
Class: sky130_fd_sc_hd__mux2_1 instances: 10
Class: sky130_fd_sc_hd__and2_2 instances: 11
Class: sky130_fd_sc_hd__o22a_2 instances: 5
Class: sky130_fd_sc_hd__xnor2_2 instances: 11
Class: sky130_fd_sc_hd__o221a_2 instances: 1
Class: sky130_fd_sc_hd__o211a_2 instances: 7
Class: sky130_fd_sc_hd__nand2b_2 instances: 2
Class: sky130_fd_sc_hd__diode_2 instances: 94
Class: sky130_fd_sc_hd__a211o_2 instances: 2
Class: sky130_fd_sc_hd__or3b_2 instances: 1
Class: sky130_fd_sc_hd__or4bb_2 instances: 1
Class: sky130_fd_sc_hd__a32o_2 instances: 8
Class: sky130_fd_sc_hd__a22o_2 instances: 12
Class: sky130_fd_sc_hd__o31a_2 instances: 3
Class: sky130_fd_sc_hd__o2bb2a_2 instances: 1
Class: sky130_fd_sc_hd__o21a_2 instances: 3
Class: sky130_fd_sc_hd__einvn_4 instances: 13
Class: sky130_fd_sc_hd__einvn_8 instances: 13
Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 50
Class: sky130_fd_sc_hd__o21ai_2 instances: 3
Class: sky130_fd_sc_hd__a21oi_2 instances: 6
Class: sky130_fd_sc_hd__fill_1 instances: 77
Class: sky130_fd_sc_hd__fill_2 instances: 7
Class: sky130_fd_sc_hd__nor2_2 instances: 36
Circuit contains 336 nets.
Contents of circuit 2: Circuit: 'digital_pll'
Circuit digital_pll contains 617 device instances.
Class: sky130_fd_sc_hd__a31o_2 instances: 1
Class: sky130_fd_sc_hd__a21o_2 instances: 12
Class: sky130_fd_sc_hd__clkbuf_16 instances: 2
Class: sky130_fd_sc_hd__or4_2 instances: 1
Class: sky130_fd_sc_hd__and3b_2 instances: 1
Class: sky130_fd_sc_hd__xor2_2 instances: 3
Class: sky130_ef_sc_hd__decap_12 instances: 2
Class: sky130_fd_sc_hd__dfrtp_2 instances: 23
Class: sky130_fd_sc_hd__and4_2 instances: 1
Class: sky130_fd_sc_hd__inv_2 instances: 6
Class: sky130_fd_sc_hd__clkbuf_1 instances: 13
Class: sky130_fd_sc_hd__clkbuf_2 instances: 12
Class: sky130_fd_sc_hd__or3_2 instances: 6
Class: sky130_fd_sc_hd__nand3_2 instances: 2
Class: sky130_fd_sc_hd__conb_1 instances: 1
Class: sky130_fd_sc_hd__and2b_2 instances: 1
Class: sky130_fd_sc_hd__a21bo_2 instances: 1
Class: sky130_fd_sc_hd__clkinv_1 instances: 13
Class: sky130_fd_sc_hd__clkinv_2 instances: 2
Class: sky130_fd_sc_hd__clkinv_8 instances: 2
Class: sky130_fd_sc_hd__and3_2 instances: 7
Class: sky130_fd_sc_hd__decap_3 instances: 54
Class: sky130_fd_sc_hd__decap_4 instances: 7
Class: sky130_fd_sc_hd__decap_6 instances: 1
Class: sky130_fd_sc_hd__or2_2 instances: 22
Class: sky130_fd_sc_hd__a2111oi_2 instances: 1
Class: sky130_fd_sc_hd__einvp_1 instances: 1
Class: sky130_fd_sc_hd__einvp_2 instances: 26
Class: sky130_fd_sc_hd__nand2_2 instances: 16
Class: sky130_fd_sc_hd__mux2_1 instances: 10
Class: sky130_fd_sc_hd__and2_2 instances: 11
Class: sky130_fd_sc_hd__o22a_2 instances: 5
Class: sky130_fd_sc_hd__xnor2_2 instances: 11
Class: sky130_fd_sc_hd__o221a_2 instances: 1
Class: sky130_fd_sc_hd__o211a_2 instances: 7
Class: sky130_fd_sc_hd__nand2b_2 instances: 2
Class: sky130_fd_sc_hd__diode_2 instances: 94
Class: sky130_fd_sc_hd__a211o_2 instances: 2
Class: sky130_fd_sc_hd__or3b_2 instances: 1
Class: sky130_fd_sc_hd__or4bb_2 instances: 1
Class: sky130_fd_sc_hd__a32o_2 instances: 8
Class: sky130_fd_sc_hd__a22o_2 instances: 12
Class: sky130_fd_sc_hd__o31a_2 instances: 3
Class: sky130_fd_sc_hd__o2bb2a_2 instances: 1
Class: sky130_fd_sc_hd__o21a_2 instances: 3
Class: sky130_fd_sc_hd__einvn_4 instances: 13
Class: sky130_fd_sc_hd__einvn_8 instances: 13
Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 50
Class: sky130_fd_sc_hd__o21ai_2 instances: 3
Class: sky130_fd_sc_hd__a21oi_2 instances: 6
Class: sky130_fd_sc_hd__fill_1 instances: 77
Class: sky130_fd_sc_hd__fill_2 instances: 7
Class: sky130_fd_sc_hd__nor2_2 instances: 36
Circuit contains 336 nets.
Circuit was modified by parallel/series device merging.
New circuit summary:
Contents of circuit 1: Circuit: 'digital_pll'
Circuit digital_pll contains 367 device instances.
Class: sky130_fd_sc_hd__a31o_2 instances: 1
Class: sky130_fd_sc_hd__a21o_2 instances: 12
Class: sky130_fd_sc_hd__clkbuf_16 instances: 2
Class: sky130_fd_sc_hd__or4_2 instances: 1
Class: sky130_fd_sc_hd__and3b_2 instances: 1
Class: sky130_fd_sc_hd__xor2_2 instances: 3
Class: sky130_ef_sc_hd__decap_12 instances: 1
Class: sky130_fd_sc_hd__dfrtp_2 instances: 23
Class: sky130_fd_sc_hd__and4_2 instances: 1
Class: sky130_fd_sc_hd__inv_2 instances: 6
Class: sky130_fd_sc_hd__clkbuf_1 instances: 13
Class: sky130_fd_sc_hd__clkbuf_2 instances: 12
Class: sky130_fd_sc_hd__or3_2 instances: 6
Class: sky130_fd_sc_hd__nand3_2 instances: 2
Class: sky130_fd_sc_hd__conb_1 instances: 1
Class: sky130_fd_sc_hd__and2b_2 instances: 1
Class: sky130_fd_sc_hd__a21bo_2 instances: 1
Class: sky130_fd_sc_hd__clkinv_1 instances: 13
Class: sky130_fd_sc_hd__clkinv_2 instances: 2
Class: sky130_fd_sc_hd__clkinv_8 instances: 2
Class: sky130_fd_sc_hd__and3_2 instances: 7
Class: sky130_fd_sc_hd__decap_3 instances: 1
Class: sky130_fd_sc_hd__decap_4 instances: 1
Class: sky130_fd_sc_hd__decap_6 instances: 1
Class: sky130_fd_sc_hd__or2_2 instances: 22
Class: sky130_fd_sc_hd__a2111oi_2 instances: 1
Class: sky130_fd_sc_hd__einvp_1 instances: 1
Class: sky130_fd_sc_hd__einvp_2 instances: 26
Class: sky130_fd_sc_hd__nand2_2 instances: 16
Class: sky130_fd_sc_hd__mux2_1 instances: 10
Class: sky130_fd_sc_hd__and2_2 instances: 11
Class: sky130_fd_sc_hd__o22a_2 instances: 5
Class: sky130_fd_sc_hd__xnor2_2 instances: 11
Class: sky130_fd_sc_hd__o221a_2 instances: 1
Class: sky130_fd_sc_hd__o211a_2 instances: 7
Class: sky130_fd_sc_hd__nand2b_2 instances: 2
Class: sky130_fd_sc_hd__diode_2 instances: 35
Class: sky130_fd_sc_hd__a211o_2 instances: 2
Class: sky130_fd_sc_hd__or3b_2 instances: 1
Class: sky130_fd_sc_hd__or4bb_2 instances: 1
Class: sky130_fd_sc_hd__a32o_2 instances: 8
Class: sky130_fd_sc_hd__a22o_2 instances: 12
Class: sky130_fd_sc_hd__o31a_2 instances: 3
Class: sky130_fd_sc_hd__o2bb2a_2 instances: 1
Class: sky130_fd_sc_hd__o21a_2 instances: 3
Class: sky130_fd_sc_hd__einvn_4 instances: 13
Class: sky130_fd_sc_hd__einvn_8 instances: 13
Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1
Class: sky130_fd_sc_hd__o21ai_2 instances: 3
Class: sky130_fd_sc_hd__a21oi_2 instances: 6
Class: sky130_fd_sc_hd__fill_1 instances: 1
Class: sky130_fd_sc_hd__fill_2 instances: 1
Class: sky130_fd_sc_hd__nor2_2 instances: 36
Circuit contains 336 nets.
Contents of circuit 2: Circuit: 'digital_pll'
Circuit digital_pll contains 367 device instances.
Class: sky130_fd_sc_hd__a31o_2 instances: 1
Class: sky130_fd_sc_hd__a21o_2 instances: 12
Class: sky130_fd_sc_hd__clkbuf_16 instances: 2
Class: sky130_fd_sc_hd__or4_2 instances: 1
Class: sky130_fd_sc_hd__and3b_2 instances: 1
Class: sky130_fd_sc_hd__xor2_2 instances: 3
Class: sky130_ef_sc_hd__decap_12 instances: 1
Class: sky130_fd_sc_hd__dfrtp_2 instances: 23
Class: sky130_fd_sc_hd__and4_2 instances: 1
Class: sky130_fd_sc_hd__inv_2 instances: 6
Class: sky130_fd_sc_hd__clkbuf_1 instances: 13
Class: sky130_fd_sc_hd__clkbuf_2 instances: 12
Class: sky130_fd_sc_hd__or3_2 instances: 6
Class: sky130_fd_sc_hd__nand3_2 instances: 2
Class: sky130_fd_sc_hd__conb_1 instances: 1
Class: sky130_fd_sc_hd__and2b_2 instances: 1
Class: sky130_fd_sc_hd__a21bo_2 instances: 1
Class: sky130_fd_sc_hd__clkinv_1 instances: 13
Class: sky130_fd_sc_hd__clkinv_2 instances: 2
Class: sky130_fd_sc_hd__clkinv_8 instances: 2
Class: sky130_fd_sc_hd__and3_2 instances: 7
Class: sky130_fd_sc_hd__decap_3 instances: 1
Class: sky130_fd_sc_hd__decap_4 instances: 1
Class: sky130_fd_sc_hd__decap_6 instances: 1
Class: sky130_fd_sc_hd__or2_2 instances: 22
Class: sky130_fd_sc_hd__a2111oi_2 instances: 1
Class: sky130_fd_sc_hd__einvp_1 instances: 1
Class: sky130_fd_sc_hd__einvp_2 instances: 26
Class: sky130_fd_sc_hd__nand2_2 instances: 16
Class: sky130_fd_sc_hd__mux2_1 instances: 10
Class: sky130_fd_sc_hd__and2_2 instances: 11
Class: sky130_fd_sc_hd__o22a_2 instances: 5
Class: sky130_fd_sc_hd__xnor2_2 instances: 11
Class: sky130_fd_sc_hd__o221a_2 instances: 1
Class: sky130_fd_sc_hd__o211a_2 instances: 7
Class: sky130_fd_sc_hd__nand2b_2 instances: 2
Class: sky130_fd_sc_hd__diode_2 instances: 35
Class: sky130_fd_sc_hd__a211o_2 instances: 2
Class: sky130_fd_sc_hd__or3b_2 instances: 1
Class: sky130_fd_sc_hd__or4bb_2 instances: 1
Class: sky130_fd_sc_hd__a32o_2 instances: 8
Class: sky130_fd_sc_hd__a22o_2 instances: 12
Class: sky130_fd_sc_hd__o31a_2 instances: 3
Class: sky130_fd_sc_hd__o2bb2a_2 instances: 1
Class: sky130_fd_sc_hd__o21a_2 instances: 3
Class: sky130_fd_sc_hd__einvn_4 instances: 13
Class: sky130_fd_sc_hd__einvn_8 instances: 13
Class: sky130_fd_sc_hd__tapvpwrvgnd_1 instances: 1
Class: sky130_fd_sc_hd__o21ai_2 instances: 3
Class: sky130_fd_sc_hd__a21oi_2 instances: 6
Class: sky130_fd_sc_hd__fill_1 instances: 1
Class: sky130_fd_sc_hd__fill_2 instances: 1
Class: sky130_fd_sc_hd__nor2_2 instances: 36
Circuit contains 336 nets.
Circuit 1 contains 367 devices, Circuit 2 contains 367 devices.
Circuit 1 contains 336 nets, Circuit 2 contains 336 nets.
Final result:
Circuits match uniquely.
.
Logging to file "/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/logs/signoff/29-digital_pll.lef.log" disabled
LVS Done.

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Magic 8.3 revision 324 - Compiled on Thu Sep 15 11:38:02 UTC 2022.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(vendor): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Using technology "sky130A", version 1.0.341-2-gde752ec
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 3.0
Library name: digital_pll
Reading "sky130_fd_sc_hd__diode_2".
Reading "sky130_fd_sc_hd__fill_1".
Reading "sky130_fd_sc_hd__decap_3".
Reading "sky130_fd_sc_hd__dfrtp_2".
Reading "sky130_fd_sc_hd__clkbuf_16".
Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
Reading "sky130_fd_sc_hd__mux2_1".
Reading "sky130_fd_sc_hd__or2_2".
Reading "sky130_fd_sc_hd__nand2_2".
Reading "sky130_fd_sc_hd__nor2_2".
Reading "sky130_fd_sc_hd__nand3_2".
Reading "sky130_fd_sc_hd__xnor2_2".
Reading "sky130_fd_sc_hd__and2_2".
Reading "sky130_fd_sc_hd__xor2_2".
Reading "sky130_fd_sc_hd__a21oi_2".
Reading "sky130_fd_sc_hd__fill_2".
Reading "sky130_fd_sc_hd__o22a_2".
Reading "sky130_fd_sc_hd__a21o_2".
Reading "sky130_fd_sc_hd__and3_2".
Reading "sky130_fd_sc_hd__decap_4".
Reading "sky130_fd_sc_hd__or3b_2".
Reading "sky130_fd_sc_hd__a211o_2".
Reading "sky130_fd_sc_hd__o31a_2".
Reading "sky130_fd_sc_hd__or3_2".
Reading "sky130_fd_sc_hd__and4_2".
Reading "sky130_fd_sc_hd__o21a_2".
Reading "sky130_fd_sc_hd__a32o_2".
Reading "sky130_fd_sc_hd__a2111oi_2".
Reading "sky130_fd_sc_hd__nand2b_2".
Reading "sky130_fd_sc_hd__o211a_2".
Reading "sky130_fd_sc_hd__or4bb_2".
Reading "sky130_fd_sc_hd__decap_6".
Reading "sky130_fd_sc_hd__and3b_2".
Reading "sky130_fd_sc_hd__einvp_2".
Reading "sky130_fd_sc_hd__einvn_4".
Reading "sky130_fd_sc_hd__clkbuf_1".
Reading "sky130_fd_sc_hd__inv_2".
Reading "sky130_fd_sc_hd__a31o_2".
Reading "sky130_ef_sc_hd__decap_12".
Reading "sky130_fd_sc_hd__o2bb2a_2".
Reading "sky130_fd_sc_hd__clkinv_1".
Reading "sky130_fd_sc_hd__clkinv_8".
Reading "sky130_fd_sc_hd__einvn_8".
Reading "sky130_fd_sc_hd__clkinv_2".
Reading "sky130_fd_sc_hd__conb_1".
Reading "sky130_fd_sc_hd__einvp_1".
Reading "sky130_fd_sc_hd__clkbuf_2".
Reading "sky130_fd_sc_hd__a21bo_2".
Reading "sky130_fd_sc_hd__o21ai_2".
Reading "sky130_fd_sc_hd__or4_2".
Reading "sky130_fd_sc_hd__a22o_2".
Reading "sky130_fd_sc_hd__and2b_2".
Reading "sky130_fd_sc_hd__o221a_2".
Reading "digital_pll".
[INFO]: Loading digital_pll
DRC style is now "drc(full)"
Loading DRC CIF style.
No errors found.
[INFO]: COUNT: 0
[INFO]: Should be divided by 3 or 4
[INFO]: DRC Checking DONE (/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/drc.rpt)
[INFO]: Saving mag view with DRC errors (/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/signoff/digital_pll.drc.mag)
[INFO]: Saved

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OpenROAD 4174c3ad802d2ac1d04d387d2c4b883903f6647e
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
Reading /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/results/routing/digital_pll.odb
[INFO ANT-0002] Found 0 net violations.
[INFO ANT-0001] Found 0 pin violations.

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CVC: Circuit Validation Check Version 1.1.0
CVC: Log output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.rpt
CVC: Error output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.rpt.error.gz
CVC: Debug output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.rpt.debug.gz
CVC: Start: Thu Oct 13 13:49:17 2022
Using the following parameters for CVC (Circuit Validation Check) from /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/cvcrc
CVC_TOP = 'digital_pll'
CVC_NETLIST = '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/digital_pll.cdl'
CVC_MODE = 'digital_pll'
CVC_MODEL_FILE = '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/models'
CVC_POWER_FILE = '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/digital_pll.power'
CVC_FUSE_FILE = ''
CVC_REPORT_FILE = '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.rpt'
CVC_REPORT_TITLE = 'CVC $CVC_TOP'
CVC_CIRCUIT_ERROR_LIMIT = '100'
CVC_SEARCH_LIMIT = '100'
CVC_LEAK_LIMIT = '0.0002'
CVC_SOI = 'false'
CVC_SCRC = 'false'
CVC_VTH_GATES = 'false'
CVC_MIN_VTH_GATES = 'false'
CVC_IGNORE_VTH_FLOATING = 'false'
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
CVC_LEAK_OVERVOLTAGE = 'true'
CVC_LOGIC_DIODES = 'false'
CVC_ANALOG_GATES = 'true'
CVC_BACKUP_RESULTS = 'false'
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
CVC_SHORT_ERROR_THRESHOLD = '0'
CVC_BIAS_ERROR_THRESHOLD = '0'
CVC_FORWARD_ERROR_THRESHOLD = '0'
CVC_FLOATING_ERROR_THRESHOLD = '0'
CVC_GATE_ERROR_THRESHOLD = '0'
CVC_LEAK?_ERROR_THRESHOLD = '0'
CVC_EXPECTED_ERROR_THRESHOLD = '0'
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
CVC_CELL_ERROR_LIMIT_FILE = ''
CVC_CELL_CHECKSUM_FILE = ''
CVC_LARGE_CIRCUIT_SIZE = '10000000'
CVC_NET_CHECK_FILE = ''
CVC_MODEL_CHECK_FILE = ''
End of parameters
CVC: Reading device model settings...
CVC: Reading power settings...
CVC: Parsing netlist /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/digital_pll.cdl
Cdl fixed data size 29223
Usage CDL: Time: 0 Memory: 6936 I/O: 3952 Swap: 0
CVC: Counting and linking...
Fatal error:could not find subcircuit: XFILLER_11_100(sky130_ef_sc_hd__decap_12) in digital_pll

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CVC: Log output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.rpt
CVC: Error output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.rpt.error.gz
CVC: Debug output to /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.rpt.debug.gz
CVC: Circuit Validation Check Version 1.1.0
CVC: Start: Thu Oct 13 13:49:17 2022
Using the following parameters for CVC (Circuit Validation Check) from /home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/cvcrc
CVC_TOP = 'digital_pll'
CVC_NETLIST = '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/digital_pll.cdl'
CVC_MODE = 'digital_pll'
CVC_MODEL_FILE = '/home/kareem_farid/caravel/deps/openlane-new/pdk/sky130A/libs.tech/openlane/cvc/models'
CVC_POWER_FILE = '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/digital_pll.power'
CVC_FUSE_FILE = ''
CVC_REPORT_FILE = '/home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/reports/signoff/digital_pll.rpt'
CVC_REPORT_TITLE = 'CVC $CVC_TOP'
CVC_CIRCUIT_ERROR_LIMIT = '100'
CVC_SEARCH_LIMIT = '100'
CVC_LEAK_LIMIT = '0.0002'
CVC_SOI = 'false'
CVC_SCRC = 'false'
CVC_VTH_GATES = 'false'
CVC_MIN_VTH_GATES = 'false'
CVC_IGNORE_VTH_FLOATING = 'false'
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
CVC_LEAK_OVERVOLTAGE = 'true'
CVC_LOGIC_DIODES = 'false'
CVC_ANALOG_GATES = 'true'
CVC_BACKUP_RESULTS = 'false'
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
CVC_SHORT_ERROR_THRESHOLD = '0'
CVC_BIAS_ERROR_THRESHOLD = '0'
CVC_FORWARD_ERROR_THRESHOLD = '0'
CVC_FLOATING_ERROR_THRESHOLD = '0'
CVC_GATE_ERROR_THRESHOLD = '0'
CVC_LEAK?_ERROR_THRESHOLD = '0'
CVC_EXPECTED_ERROR_THRESHOLD = '0'
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
CVC_CELL_ERROR_LIMIT_FILE = ''
CVC_CELL_CHECKSUM_FILE = ''
CVC_LARGE_CIRCUIT_SIZE = '10000000'
CVC_NET_CHECK_FILE = ''
CVC_MODEL_CHECK_FILE = ''
End of parameters
CVC: Reading device model settings...
CVC: Reading power settings...
CVC: Parsing netlist /home/kareem_farid/caravel/openlane/digital_pll/runs/22_10_13_06_47/tmp/signoff/digital_pll.cdl
Cdl fixed data size 29223
Usage CDL: Time: 0 Memory: 6936 I/O: 3952 Swap: 0
CVC: Counting and linking...

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@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
# Tue Dec 7 11:07:45 2021
# Thu Oct 13 13:47:47 2022
###############################################################################
current_design digital_pll
###############################################################################
@ -9,7 +9,6 @@ current_design digital_pll
create_clock -name pll_control_clock -period 6.6667 [get_pins {ringosc.ibufp01/Y}]
set_clock_transition 0.1500 [get_clocks {pll_control_clock}]
set_clock_uncertainty 0.2500 pll_control_clock
set_propagated_clock [get_clocks {pll_control_clock}]
set_input_delay 2.0000 -add_delay [get_ports {dco}]
set_input_delay 2.0000 -add_delay [get_ports {div[0]}]
set_input_delay 2.0000 -add_delay [get_ports {div[1]}]
@ -52,41 +51,41 @@ set_output_delay 2.0000 -add_delay [get_ports {clockp[1]}]
###############################################################################
set_load -pin_load 0.0334 [get_ports {clockp[1]}]
set_load -pin_load 0.0334 [get_ports {clockp[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dco}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {osc}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_1 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {dco}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {enable}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {osc}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetb}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {div[0]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[25]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[24]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[23]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[22]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[21]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[20]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[19]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[18]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[17]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[16]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[15]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[14]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[13]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[12]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[11]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[10]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[9]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[8]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[7]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[6]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[5]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[4]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[3]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[2]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[1]}]
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {ext_trim[0]}]
set_timing_derate -early 0.9500
set_timing_derate -late 1.0500
###############################################################################

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<?xml version="1.0" ?>
<report-database>
<categories/>
<cells>
<cell>
<name>digital_pll</name>
</cell>
</cells>
<items/>
</report-database>

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$digital_pll 100

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digital_pll
----------------------------------------
[INFO]: COUNT: 0
[INFO]: Should be divided by 3 or 4

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box 6900 5967 6929 6001
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium

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1703
verilog/gl/digital_pll.nl.v Normal file

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@ -43,6 +43,7 @@ module digital_pll(
output [1:0] clockp; // Two 90 degree clock phases
wire [1:0] clockp_buffer_in; // Input wires to clockp buffers
wire [25:0] itrim; // Internally generated trim bits
wire [25:0] otrim; // Trim bits applied to the ring oscillator
wire creset; // Controller reset
@ -58,16 +59,40 @@ module digital_pll(
ring_osc2x13 ringosc (
.reset(ireset),
.trim(itrim),
.clockp(clockp)
.clockp(clockp_buffer_in)
);
digital_pll_controller pll_control (
.reset(creset),
.clock(clockp[0]),
.clock(clockp_buffer_in[0]),
.osc(osc),
.div(div),
.trim(otrim)
);
(* keep *)
sky130_fd_sc_hd__clkbuf_16 clockp_buffer_0 (
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPWR),
.VNB(VGND),
`endif
.A(clockp_buffer_in[0]),
.X(clockp[0])
);
(* keep *)
sky130_fd_sc_hd__clkbuf_16 clockp_buffer_1 (
`ifdef USE_POWER_PINS
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPWR),
.VNB(VGND),
`endif
.A(clockp_buffer_in[1]),
.X(clockp[1])
);
endmodule
`default_nettype wire