mirror of https://github.com/efabless/caravel.git
Update gpio_control_block
This commit is contained in:
manarabdelaty
parent
53b09f43d1
commit
e68664101c
Binary file not shown.
Binary file not shown.
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@ -6,109 +6,109 @@ MACRO gpio_control_block
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CLASS BLOCK ;
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FOREIGN gpio_control_block ;
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ORIGIN 0.000 0.000 ;
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SIZE 170.000 BY 70.000 ;
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SIZE 170.000 BY 65.000 ;
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PIN gpio_defaults[0]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 0.720 170.000 1.320 ;
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LAYER met2 ;
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RECT 4.690 61.000 4.970 65.000 ;
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END
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END gpio_defaults[0]
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PIN gpio_defaults[10]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 16.360 170.000 16.960 ;
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LAYER met2 ;
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RECT 27.690 61.000 27.970 65.000 ;
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END
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END gpio_defaults[10]
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PIN gpio_defaults[11]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 18.400 170.000 19.000 ;
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LAYER met2 ;
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RECT 29.990 61.000 30.270 65.000 ;
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END
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END gpio_defaults[11]
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PIN gpio_defaults[12]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 19.760 170.000 20.360 ;
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LAYER met2 ;
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RECT 32.290 61.000 32.570 65.000 ;
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END
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END gpio_defaults[12]
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PIN gpio_defaults[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 2.080 170.000 2.680 ;
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LAYER met2 ;
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RECT 6.990 61.000 7.270 65.000 ;
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END
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END gpio_defaults[1]
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PIN gpio_defaults[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 3.440 170.000 4.040 ;
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LAYER met2 ;
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RECT 9.290 61.000 9.570 65.000 ;
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END
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END gpio_defaults[2]
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PIN gpio_defaults[3]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 5.480 170.000 6.080 ;
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LAYER met2 ;
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RECT 11.590 61.000 11.870 65.000 ;
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END
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END gpio_defaults[3]
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PIN gpio_defaults[4]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 6.840 170.000 7.440 ;
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LAYER met2 ;
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RECT 13.890 61.000 14.170 65.000 ;
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END
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END gpio_defaults[4]
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PIN gpio_defaults[5]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 8.200 170.000 8.800 ;
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LAYER met2 ;
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RECT 16.190 61.000 16.470 65.000 ;
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END
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END gpio_defaults[5]
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PIN gpio_defaults[6]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 10.240 170.000 10.840 ;
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LAYER met2 ;
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RECT 18.490 61.000 18.770 65.000 ;
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END
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END gpio_defaults[6]
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PIN gpio_defaults[7]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 11.600 170.000 12.200 ;
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LAYER met2 ;
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RECT 20.790 61.000 21.070 65.000 ;
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END
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END gpio_defaults[7]
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PIN gpio_defaults[8]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 13.640 170.000 14.240 ;
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LAYER met2 ;
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RECT 23.090 61.000 23.370 65.000 ;
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END
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END gpio_defaults[8]
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PIN gpio_defaults[9]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 15.000 170.000 15.600 ;
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LAYER met2 ;
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RECT 25.390 61.000 25.670 65.000 ;
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END
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END gpio_defaults[9]
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PIN mgmt_gpio_in
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@ -116,7 +116,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 24.520 170.000 25.120 ;
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RECT 70.000 6.160 170.000 6.760 ;
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END
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END mgmt_gpio_in
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PIN mgmt_gpio_oeb
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@ -124,7 +124,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 26.560 170.000 27.160 ;
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RECT 70.000 8.200 170.000 8.800 ;
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END
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END mgmt_gpio_oeb
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PIN mgmt_gpio_out
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@ -132,7 +132,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 27.920 170.000 28.520 ;
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RECT 70.000 10.240 170.000 10.840 ;
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END
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END mgmt_gpio_out
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PIN one
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@ -140,7 +140,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 23.160 170.000 23.760 ;
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RECT 70.000 4.120 170.000 4.720 ;
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END
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END one
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PIN pad_gpio_ana_en
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@ -148,7 +148,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 29.960 170.000 30.560 ;
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RECT 70.000 12.280 170.000 12.880 ;
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END
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END pad_gpio_ana_en
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PIN pad_gpio_ana_pol
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@ -156,7 +156,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 31.320 170.000 31.920 ;
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RECT 70.000 14.320 170.000 14.920 ;
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END
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END pad_gpio_ana_pol
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PIN pad_gpio_ana_sel
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@ -164,7 +164,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 32.680 170.000 33.280 ;
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RECT 70.000 16.360 170.000 16.960 ;
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END
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END pad_gpio_ana_sel
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PIN pad_gpio_dm[0]
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@ -172,7 +172,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 34.720 170.000 35.320 ;
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RECT 70.000 18.400 170.000 19.000 ;
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END
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END pad_gpio_dm[0]
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PIN pad_gpio_dm[1]
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@ -180,7 +180,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 36.080 170.000 36.680 ;
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RECT 70.000 20.440 170.000 21.040 ;
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END
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END pad_gpio_dm[1]
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PIN pad_gpio_dm[2]
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@ -188,7 +188,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 38.120 170.000 38.720 ;
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RECT 70.000 22.480 170.000 23.080 ;
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END
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END pad_gpio_dm[2]
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PIN pad_gpio_holdover
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@ -196,7 +196,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 39.480 170.000 40.080 ;
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RECT 70.000 24.520 170.000 25.120 ;
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END
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END pad_gpio_holdover
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PIN pad_gpio_ib_mode_sel
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@ -204,7 +204,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 40.840 170.000 41.440 ;
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RECT 70.000 26.560 170.000 27.160 ;
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END
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END pad_gpio_ib_mode_sel
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PIN pad_gpio_in
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@ -212,7 +212,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 42.880 170.000 43.480 ;
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RECT 70.000 28.600 170.000 29.200 ;
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END
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END pad_gpio_in
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PIN pad_gpio_inenb
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@ -220,7 +220,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 44.240 170.000 44.840 ;
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RECT 70.000 30.640 170.000 31.240 ;
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END
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END pad_gpio_inenb
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PIN pad_gpio_out
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@ -228,7 +228,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 46.280 170.000 46.880 ;
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RECT 70.000 32.680 170.000 33.280 ;
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END
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END pad_gpio_out
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PIN pad_gpio_outenb
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@ -236,7 +236,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 47.640 170.000 48.240 ;
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RECT 70.000 34.720 170.000 35.320 ;
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END
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END pad_gpio_outenb
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PIN pad_gpio_slow_sel
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@ -244,7 +244,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 49.000 170.000 49.600 ;
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RECT 70.000 36.760 170.000 37.360 ;
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END
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END pad_gpio_slow_sel
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PIN pad_gpio_vtrip_sel
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@ -252,7 +252,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 51.040 170.000 51.640 ;
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RECT 70.000 38.800 170.000 39.400 ;
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END
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END pad_gpio_vtrip_sel
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PIN resetn
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@ -260,7 +260,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 52.400 170.000 53.000 ;
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RECT 70.000 40.840 170.000 41.440 ;
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END
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END resetn
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PIN resetn_out
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@ -268,7 +268,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 54.440 170.000 55.040 ;
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RECT 70.000 42.880 170.000 43.480 ;
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END
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END resetn_out
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PIN serial_clock
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@ -276,7 +276,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 55.800 170.000 56.400 ;
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RECT 70.000 44.920 170.000 45.520 ;
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END
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END serial_clock
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PIN serial_clock_out
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@ -284,7 +284,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 57.160 170.000 57.760 ;
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RECT 70.000 46.960 170.000 47.560 ;
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END
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END serial_clock_out
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PIN serial_data_in
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@ -292,7 +292,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 59.200 170.000 59.800 ;
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RECT 70.000 49.000 170.000 49.600 ;
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END
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END serial_data_in
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PIN serial_data_out
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@ -300,7 +300,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 60.560 170.000 61.160 ;
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RECT 70.000 51.040 170.000 51.640 ;
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END
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END serial_data_out
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PIN serial_load
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@ -308,7 +308,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 62.600 170.000 63.200 ;
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RECT 70.000 53.080 170.000 53.680 ;
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END
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END serial_load
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PIN serial_load_out
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@ -316,7 +316,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 63.960 170.000 64.560 ;
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RECT 70.000 55.120 170.000 55.720 ;
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END
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END serial_load_out
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PIN user_gpio_in
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@ -324,7 +324,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 65.320 170.000 65.920 ;
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RECT 70.000 57.160 170.000 57.760 ;
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END
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END user_gpio_in
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PIN user_gpio_oeb
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@ -332,7 +332,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 67.360 170.000 67.960 ;
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RECT 70.000 59.200 170.000 59.800 ;
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END
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END user_gpio_oeb
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PIN user_gpio_out
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@ -340,7 +340,7 @@ MACRO gpio_control_block
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 68.720 170.000 69.320 ;
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RECT 70.000 61.240 170.000 61.840 ;
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END
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END user_gpio_out
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PIN vccd
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@ -348,43 +348,27 @@ MACRO gpio_control_block
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USE POWER ;
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PORT
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LAYER met5 ;
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RECT 1.800 8.080 52.020 9.680 ;
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RECT 4.600 5.900 49.220 7.500 ;
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END
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PORT
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LAYER met5 ;
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RECT -1.500 12.080 55.320 13.680 ;
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RECT 4.600 22.800 49.220 24.400 ;
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END
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PORT
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LAYER met5 ;
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RECT -1.500 27.580 55.320 29.180 ;
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END
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PORT
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LAYER met5 ;
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RECT -1.500 43.080 55.320 44.680 ;
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END
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PORT
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LAYER met5 ;
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RECT 1.800 58.320 52.020 59.920 ;
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RECT 4.600 39.700 49.220 41.300 ;
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END
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PORT
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LAYER met4 ;
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RECT 1.800 8.080 3.400 59.920 ;
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RECT 12.800 5.440 14.400 57.360 ;
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END
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PORT
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LAYER met4 ;
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RECT 50.420 8.080 52.020 59.920 ;
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RECT 28.300 5.200 29.900 57.360 ;
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END
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PORT
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LAYER met4 ;
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RECT 12.800 4.780 14.400 63.220 ;
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END
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PORT
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LAYER met4 ;
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RECT 28.300 4.780 29.900 63.220 ;
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END
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PORT
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LAYER met4 ;
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RECT 43.800 4.780 45.400 63.220 ;
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RECT 43.800 5.200 45.400 57.360 ;
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END
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END vccd
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PIN vccd1
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@ -392,31 +376,23 @@ MACRO gpio_control_block
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USE POWER ;
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PORT
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LAYER met5 ;
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RECT -4.800 1.480 58.620 3.080 ;
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RECT 4.600 11.140 49.220 12.740 ;
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END
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PORT
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LAYER met5 ;
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RECT -8.100 16.580 61.920 18.180 ;
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RECT 4.600 28.040 49.220 29.640 ;
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END
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PORT
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LAYER met5 ;
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RECT -8.100 32.080 61.920 33.680 ;
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END
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PORT
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LAYER met5 ;
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RECT -8.100 47.580 61.920 49.180 ;
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END
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PORT
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LAYER met5 ;
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RECT -4.800 64.920 58.620 66.520 ;
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RECT 4.600 44.940 49.220 46.540 ;
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END
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PORT
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LAYER met4 ;
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RECT -4.800 1.480 -3.200 66.520 ;
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RECT 17.800 5.440 19.400 57.120 ;
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END
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PORT
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LAYER met4 ;
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RECT 57.020 1.480 58.620 66.520 ;
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RECT 33.300 5.440 34.900 57.120 ;
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END
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END vccd1
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PIN vssd
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|
|
@ -424,39 +400,23 @@ MACRO gpio_control_block
|
|||
USE GROUND ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 4.780 55.320 6.380 ;
|
||||
RECT 4.600 14.350 49.220 15.950 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 19.830 55.320 21.430 ;
|
||||
RECT 4.600 31.250 49.220 32.850 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 35.330 55.320 36.930 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 50.830 55.320 52.430 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 61.620 55.320 63.220 ;
|
||||
RECT 4.600 48.150 49.220 49.750 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT -1.500 4.780 0.100 63.220 ;
|
||||
RECT 20.550 5.200 22.150 57.360 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 20.550 4.780 22.150 63.220 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 36.050 4.780 37.650 63.220 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 53.720 4.780 55.320 63.220 ;
|
||||
RECT 36.050 5.200 37.650 57.360 ;
|
||||
END
|
||||
END vssd
|
||||
PIN vssd1
|
||||
|
|
@ -464,27 +424,23 @@ MACRO gpio_control_block
|
|||
USE GROUND ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 -1.820 61.920 -0.220 ;
|
||||
RECT 4.600 19.590 49.220 21.190 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 24.330 61.920 25.930 ;
|
||||
RECT 4.600 36.490 49.220 38.090 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 39.830 61.920 41.430 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 68.220 61.920 69.820 ;
|
||||
RECT 4.600 53.390 49.220 54.990 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT -8.100 -1.820 -6.500 69.820 ;
|
||||
RECT 25.550 5.440 27.150 57.120 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 60.320 -1.820 61.920 69.820 ;
|
||||
RECT 41.050 5.440 42.650 57.120 ;
|
||||
END
|
||||
END vssd1
|
||||
PIN zero
|
||||
|
|
@ -492,52 +448,98 @@ MACRO gpio_control_block
|
|||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 70.000 21.800 170.000 22.400 ;
|
||||
RECT 70.000 2.080 170.000 2.680 ;
|
||||
END
|
||||
END zero
|
||||
OBS
|
||||
LAYER nwell ;
|
||||
RECT 4.410 55.705 49.410 57.310 ;
|
||||
RECT 4.410 50.265 49.410 53.095 ;
|
||||
RECT 4.410 44.825 49.410 47.655 ;
|
||||
RECT 4.410 39.385 49.410 42.215 ;
|
||||
RECT 4.410 33.945 49.410 36.775 ;
|
||||
RECT 4.410 28.505 49.410 31.335 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.600 10.795 52.755 57.205 ;
|
||||
RECT 4.600 5.355 49.220 61.455 ;
|
||||
LAYER met1 ;
|
||||
RECT 4.600 10.640 112.170 59.120 ;
|
||||
RECT 4.600 5.200 83.650 61.500 ;
|
||||
LAYER met2 ;
|
||||
RECT 5.160 0.835 112.150 69.205 ;
|
||||
RECT 5.250 60.720 6.710 61.610 ;
|
||||
RECT 7.550 60.720 9.010 61.610 ;
|
||||
RECT 9.850 60.720 11.310 61.610 ;
|
||||
RECT 12.150 60.720 13.610 61.610 ;
|
||||
RECT 14.450 60.720 15.910 61.610 ;
|
||||
RECT 16.750 60.720 18.210 61.610 ;
|
||||
RECT 19.050 60.720 20.510 61.610 ;
|
||||
RECT 21.350 60.720 22.810 61.610 ;
|
||||
RECT 23.650 60.720 25.110 61.610 ;
|
||||
RECT 25.950 60.720 27.410 61.610 ;
|
||||
RECT 28.250 60.720 29.710 61.610 ;
|
||||
RECT 30.550 60.720 32.010 61.610 ;
|
||||
RECT 32.850 60.720 83.630 61.610 ;
|
||||
RECT 4.700 2.195 83.630 60.720 ;
|
||||
LAYER met3 ;
|
||||
RECT 5.585 66.960 69.600 67.810 ;
|
||||
RECT 5.585 66.320 70.000 66.960 ;
|
||||
RECT 5.585 62.200 69.600 66.320 ;
|
||||
RECT 5.585 61.560 70.000 62.200 ;
|
||||
RECT 5.585 58.800 69.600 61.560 ;
|
||||
RECT 5.585 58.160 70.000 58.800 ;
|
||||
RECT 5.585 54.040 69.600 58.160 ;
|
||||
RECT 5.585 53.400 70.000 54.040 ;
|
||||
RECT 5.585 50.640 69.600 53.400 ;
|
||||
RECT 5.585 50.000 70.000 50.640 ;
|
||||
RECT 5.585 45.880 69.600 50.000 ;
|
||||
RECT 5.585 45.240 70.000 45.880 ;
|
||||
RECT 5.585 42.480 69.600 45.240 ;
|
||||
RECT 5.585 41.840 70.000 42.480 ;
|
||||
RECT 5.585 37.720 69.600 41.840 ;
|
||||
RECT 5.585 37.080 70.000 37.720 ;
|
||||
RECT 5.585 34.320 69.600 37.080 ;
|
||||
RECT 5.585 33.680 70.000 34.320 ;
|
||||
RECT 5.585 29.560 69.600 33.680 ;
|
||||
RECT 5.585 28.920 70.000 29.560 ;
|
||||
RECT 5.585 26.160 69.600 28.920 ;
|
||||
RECT 5.585 25.520 70.000 26.160 ;
|
||||
RECT 5.585 21.400 69.600 25.520 ;
|
||||
RECT 5.585 20.760 70.000 21.400 ;
|
||||
RECT 5.585 18.000 69.600 20.760 ;
|
||||
RECT 5.585 17.360 70.000 18.000 ;
|
||||
RECT 5.585 13.240 69.600 17.360 ;
|
||||
RECT 5.585 12.600 70.000 13.240 ;
|
||||
RECT 5.585 9.840 69.600 12.600 ;
|
||||
RECT 5.585 9.200 70.000 9.840 ;
|
||||
RECT 5.585 5.080 69.600 9.200 ;
|
||||
RECT 5.585 4.440 70.000 5.080 ;
|
||||
RECT 5.585 2.215 69.600 4.440 ;
|
||||
RECT 6.045 60.840 69.600 61.690 ;
|
||||
RECT 6.045 60.200 70.000 60.840 ;
|
||||
RECT 6.045 58.800 69.600 60.200 ;
|
||||
RECT 6.045 58.160 70.000 58.800 ;
|
||||
RECT 6.045 56.760 69.600 58.160 ;
|
||||
RECT 6.045 56.120 70.000 56.760 ;
|
||||
RECT 6.045 54.720 69.600 56.120 ;
|
||||
RECT 6.045 54.080 70.000 54.720 ;
|
||||
RECT 6.045 52.680 69.600 54.080 ;
|
||||
RECT 6.045 52.040 70.000 52.680 ;
|
||||
RECT 6.045 50.640 69.600 52.040 ;
|
||||
RECT 6.045 50.000 70.000 50.640 ;
|
||||
RECT 6.045 48.600 69.600 50.000 ;
|
||||
RECT 6.045 47.960 70.000 48.600 ;
|
||||
RECT 6.045 46.560 69.600 47.960 ;
|
||||
RECT 6.045 45.920 70.000 46.560 ;
|
||||
RECT 6.045 44.520 69.600 45.920 ;
|
||||
RECT 6.045 43.880 70.000 44.520 ;
|
||||
RECT 6.045 42.480 69.600 43.880 ;
|
||||
RECT 6.045 41.840 70.000 42.480 ;
|
||||
RECT 6.045 40.440 69.600 41.840 ;
|
||||
RECT 6.045 39.800 70.000 40.440 ;
|
||||
RECT 6.045 38.400 69.600 39.800 ;
|
||||
RECT 6.045 37.760 70.000 38.400 ;
|
||||
RECT 6.045 36.360 69.600 37.760 ;
|
||||
RECT 6.045 35.720 70.000 36.360 ;
|
||||
RECT 6.045 34.320 69.600 35.720 ;
|
||||
RECT 6.045 33.680 70.000 34.320 ;
|
||||
RECT 6.045 32.280 69.600 33.680 ;
|
||||
RECT 6.045 31.640 70.000 32.280 ;
|
||||
RECT 6.045 30.240 69.600 31.640 ;
|
||||
RECT 6.045 29.600 70.000 30.240 ;
|
||||
RECT 6.045 28.200 69.600 29.600 ;
|
||||
RECT 6.045 27.560 70.000 28.200 ;
|
||||
RECT 6.045 26.160 69.600 27.560 ;
|
||||
RECT 6.045 25.520 70.000 26.160 ;
|
||||
RECT 6.045 24.120 69.600 25.520 ;
|
||||
RECT 6.045 23.480 70.000 24.120 ;
|
||||
RECT 6.045 22.080 69.600 23.480 ;
|
||||
RECT 6.045 21.440 70.000 22.080 ;
|
||||
RECT 6.045 20.040 69.600 21.440 ;
|
||||
RECT 6.045 19.400 70.000 20.040 ;
|
||||
RECT 6.045 18.000 69.600 19.400 ;
|
||||
RECT 6.045 17.360 70.000 18.000 ;
|
||||
RECT 6.045 15.960 69.600 17.360 ;
|
||||
RECT 6.045 15.320 70.000 15.960 ;
|
||||
RECT 6.045 13.920 69.600 15.320 ;
|
||||
RECT 6.045 13.280 70.000 13.920 ;
|
||||
RECT 6.045 11.880 69.600 13.280 ;
|
||||
RECT 6.045 11.240 70.000 11.880 ;
|
||||
RECT 6.045 9.840 69.600 11.240 ;
|
||||
RECT 6.045 9.200 70.000 9.840 ;
|
||||
RECT 6.045 7.800 69.600 9.200 ;
|
||||
RECT 6.045 7.160 70.000 7.800 ;
|
||||
RECT 6.045 5.760 69.600 7.160 ;
|
||||
RECT 6.045 5.120 70.000 5.760 ;
|
||||
RECT 6.045 3.720 69.600 5.120 ;
|
||||
RECT 6.045 3.080 70.000 3.720 ;
|
||||
RECT 6.045 2.215 69.600 3.080 ;
|
||||
LAYER met4 ;
|
||||
RECT 6.280 13.160 11.380 27.240 ;
|
||||
RECT 6.280 8.160 11.380 22.240 ;
|
||||
END
|
||||
END gpio_control_block
|
||||
END LIBRARY
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1636033645
|
||||
timestamp 1636105901
|
||||
<< viali >>
|
||||
rect 1041 1853 1075 1887
|
||||
<< metal1 >>
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1636033646
|
||||
timestamp 1636105901
|
||||
<< nwell >>
|
||||
rect -38 2437 1418 2758
|
||||
rect -38 1349 1418 1915
|
||||
|
|
|
|||
|
|
@ -34,24 +34,23 @@ set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
|
|||
|
||||
## Floorplan
|
||||
set ::env(FP_SIZING) absolute
|
||||
set ::env(DIE_AREA) "0 0 170 70"
|
||||
set ::env(DIE_AREA) "0 0 170 65"
|
||||
|
||||
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
|
||||
|
||||
set ::env(FP_IO_VEXTEND) 20
|
||||
set ::env(FP_IO_VEXTEND) 0
|
||||
set ::env(FP_IO_HEXTEND) 0
|
||||
set ::env(FP_IO_HLENGTH) 100
|
||||
set ::env(FP_IO_VLENGTH) 4
|
||||
|
||||
set ::env(RIGHT_MARGIN_MULT) 262
|
||||
set ::env(LEFT_MARGIN_MULT) 10
|
||||
set ::env(TOP_MARGIN_MULT) 4
|
||||
set ::env(BOTTOM_MARGIN_MULT) 4
|
||||
set ::env(TOP_MARGIN_MULT) 2
|
||||
set ::env(BOTTOM_MARGIN_MULT) 2
|
||||
|
||||
set ::env(CELL_PAD) 0
|
||||
|
||||
## PDN
|
||||
set ::env(PDN_CFG) $script_dir/pdn.tcl
|
||||
set ::env(FP_PDN_AUTO_ADJUST) 0
|
||||
set ::env(FP_PDN_CORE_RING) 1
|
||||
|
||||
set ::env(FP_PDN_VWIDTH) 1.6
|
||||
set ::env(FP_PDN_HWIDTH) 1.6
|
||||
|
|
@ -60,17 +59,14 @@ set ::env(FP_HORIZONTAL_HALO) 2
|
|||
set ::env(FP_VERTICAL_HALO) 2
|
||||
|
||||
set ::env(FP_PDN_HOFFSET) 1.5
|
||||
set ::env(FP_PDN_VOFFSET) 8.5
|
||||
set ::env(FP_PDN_VOFFSET) 9.0
|
||||
|
||||
set ::env(FP_PDN_HPITCH) 15.5
|
||||
set ::env(FP_PDN_HPITCH) 16.9
|
||||
set ::env(FP_PDN_VPITCH) 15.5
|
||||
|
||||
set ::env(FP_PDN_VSPACING) 3.4
|
||||
set ::env(FP_PDN_HSPACING) 3.4
|
||||
|
||||
set ::env(FP_PDN_CORE_RING_VOFFSET) 2
|
||||
set ::env(FP_PDN_CORE_RING_HOFFSET) 2
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.91
|
||||
# for some reason resizer is leaving a floating net after running repair_tie_fanout command
|
||||
|
|
@ -86,10 +82,13 @@ set ::env(GLB_RT_ADJUSTMENT) 0.05
|
|||
|
||||
# Add obstructions on the areas that will lie underneath the padframe
|
||||
set ::env(GLB_RT_OBS) "\
|
||||
met5 67 0 170 70,
|
||||
met4 67 0 170 70,
|
||||
met2 120 0 170 70,
|
||||
met1 120 0 170 70"
|
||||
met5 67 0 170 65,
|
||||
met4 67 0 170 65,
|
||||
met2 120 0 170 65,
|
||||
met1 120 0 170 65"
|
||||
|
||||
## Diode Insertion
|
||||
set ::env(DIODE_INSERTION_STRATEGY) "4"
|
||||
|
||||
## Internal macros
|
||||
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
|
||||
|
|
|
|||
|
|
@ -0,0 +1,77 @@
|
|||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
package require openlane
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set save_path $script_dir/../..
|
||||
|
||||
prep -design $script_dir -tag gpio_control_block -overwrite
|
||||
|
||||
run_synthesis
|
||||
|
||||
init_floorplan
|
||||
|
||||
set ::env(SAVE_DEF) [index_file $::env(ioPlacer_tmp_file_tag).def]
|
||||
try_catch openroad -exit $script_dir/io_place.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(ioPlacer_log_file_tag).log 0]
|
||||
set_def $::env(SAVE_DEF)
|
||||
|
||||
file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/macro_placement.cfg
|
||||
manual_macro_placement f
|
||||
|
||||
tap_decap_or
|
||||
|
||||
run_power_grid_generation
|
||||
|
||||
run_placement
|
||||
|
||||
run_cts
|
||||
run_resizer_timing
|
||||
|
||||
run_routing
|
||||
|
||||
if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
|
||||
run_antenna_check
|
||||
heal_antenna_violators; # modifies the routed DEF
|
||||
}
|
||||
|
||||
run_magic
|
||||
|
||||
run_magic_spice_export
|
||||
|
||||
write_powered_verilog
|
||||
set_netlist $::env(lvs_result_file_tag).powered.v
|
||||
|
||||
run_magic_drc
|
||||
|
||||
run_lvs $::env(magic_result_file_tag).spice $::env(CURRENT_NETLIST)
|
||||
|
||||
run_antenna_check
|
||||
|
||||
run_lef_cvc
|
||||
|
||||
save_views -lef_path $::env(magic_result_file_tag).lef \
|
||||
-def_path $::env(tritonRoute_result_file_tag).def \
|
||||
-gds_path $::env(magic_result_file_tag).gds \
|
||||
-mag_path $::env(magic_result_file_tag).mag \
|
||||
-verilog_path $::env(CURRENT_NETLIST) \
|
||||
-spice_path $::env(magic_result_file_tag).spice \
|
||||
-save_path $save_path \
|
||||
-tag $::env(RUN_TAG)
|
||||
|
||||
calc_total_runtime
|
||||
save_state
|
||||
generate_final_summary_report
|
||||
|
||||
check_timing_violations
|
||||
|
|
@ -0,0 +1,88 @@
|
|||
# Copyright 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
## Needs OpenRoad Commit: 29db63fdda643f01d5a7705606a96681ab855a68
|
||||
|
||||
if {[catch {read_lef $::env(MERGED_LEF)} errmsg]} {
|
||||
puts stderr $errmsg
|
||||
exit 1
|
||||
}
|
||||
|
||||
if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
|
||||
puts stderr $errmsg
|
||||
exit 1
|
||||
}
|
||||
|
||||
ppl::set_hor_length $::env(FP_IO_HLENGTH)
|
||||
ppl::set_ver_length $::env(FP_IO_VLENGTH)
|
||||
ppl::set_hor_length_extend $::env(FP_IO_VEXTEND)
|
||||
ppl::set_ver_length_extend $::env(FP_IO_HEXTEND)
|
||||
ppl::set_ver_thick_multiplier $::env(FP_IO_VTHICKNESS_MULT)
|
||||
ppl::set_hor_thick_multiplier $::env(FP_IO_HTHICKNESS_MULT)
|
||||
|
||||
set tech [[ord::get_db] getTech]
|
||||
set HMETAL [[$tech findRoutingLayer $::env(FP_IO_HMETAL)] getName]
|
||||
set VMETAL [[$tech findRoutingLayer $::env(FP_IO_VMETAL)] getName]
|
||||
|
||||
# East pins
|
||||
set_io_pin_constraint -pin_names {user_gpio_out} -region right:60-62
|
||||
set_io_pin_constraint -pin_names {user_gpio_oeb} -region right:58-60
|
||||
set_io_pin_constraint -pin_names {user_gpio_in} -region right:56-58
|
||||
set_io_pin_constraint -pin_names {serial_load_out} -region right:54-56
|
||||
set_io_pin_constraint -pin_names {serial_load} -region right:52-54
|
||||
set_io_pin_constraint -pin_names {serial_data_out} -region right:50-52
|
||||
set_io_pin_constraint -pin_names {serial_data_in} -region right:48-50
|
||||
set_io_pin_constraint -pin_names {serial_clock_out} -region right:46-48
|
||||
set_io_pin_constraint -pin_names {serial_clock} -region right:44-46
|
||||
set_io_pin_constraint -pin_names {resetn_out} -region right:42-44
|
||||
set_io_pin_constraint -pin_names {resetn} -region right:40-42
|
||||
set_io_pin_constraint -pin_names {pad_gpio_vtrip_sel} -region right:38-40
|
||||
set_io_pin_constraint -pin_names {pad_gpio_slow_sel} -region right:36-38
|
||||
set_io_pin_constraint -pin_names {pad_gpio_outenb} -region right:34-36
|
||||
set_io_pin_constraint -pin_names {pad_gpio_out} -region right:32-34
|
||||
set_io_pin_constraint -pin_names {pad_gpio_inenb} -region right:30-32
|
||||
set_io_pin_constraint -pin_names {pad_gpio_in} -region right:28-30
|
||||
set_io_pin_constraint -pin_names {pad_gpio_ib_mode_sel} -region right:26-28
|
||||
set_io_pin_constraint -pin_names {pad_gpio_holdover} -region right:24-26
|
||||
set_io_pin_constraint -pin_names {pad_gpio_dm[2]} -region right:22-24
|
||||
set_io_pin_constraint -pin_names {pad_gpio_dm[1]} -region right:20-22
|
||||
set_io_pin_constraint -pin_names {pad_gpio_dm[0]} -region right:18-20
|
||||
set_io_pin_constraint -pin_names {pad_gpio_ana_sel} -region right:16-18
|
||||
set_io_pin_constraint -pin_names {pad_gpio_ana_pol} -region right:14-16
|
||||
set_io_pin_constraint -pin_names {pad_gpio_ana_en} -region right:12-14
|
||||
set_io_pin_constraint -pin_names {mgmt_gpio_out} -region right:10-12
|
||||
set_io_pin_constraint -pin_names {mgmt_gpio_oeb} -region right:8-10
|
||||
set_io_pin_constraint -pin_names {mgmt_gpio_in} -region right:6-8
|
||||
set_io_pin_constraint -pin_names {one} -region right:4-6
|
||||
set_io_pin_constraint -pin_names {zero} -region right:2-4
|
||||
|
||||
# North pins
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[0]} -region top:4-6
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[1]} -region top:6-8
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[2]} -region top:8-10
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[3]} -region top:10-12
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[4]} -region top:12-15
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[5]} -region top:15-17
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[6]} -region top:17-19
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[7]} -region top:19-21
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[8]} -region top:21-24
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[9]} -region top:24-26
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[10]} -region top:26-28
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[11]} -region top:28-31
|
||||
set_io_pin_constraint -pin_names {gpio_defaults[12]} -region top:31-33
|
||||
|
||||
place_pins -min_distance 2 -hor_layers $HMETAL -ver_layers $VMETAL -exclude left:* -exclude bottom:*
|
||||
|
||||
|
||||
write_def $::env(SAVE_DEF)
|
||||
|
|
@ -1 +1 @@
|
|||
gpio_logic_high 5.98 13.40 N
|
||||
gpio_logic_high 5.98 8.40 N
|
||||
|
|
|
|||
|
|
@ -29,6 +29,7 @@ set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
|
|||
if { $::env(VDD_NET) == "vccd1" } {
|
||||
# Used if the design is the core of the chip
|
||||
define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
|
||||
add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
} else {
|
||||
|
|
@ -59,13 +60,24 @@ if { $::env(VDD_NET) == "vccd1" } {
|
|||
orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
power_pins "vccd1"
|
||||
ground_pins "vssd1"
|
||||
blockages $::env(MACRO_BLOCKAGES_LAYER)
|
||||
blockages "met1 met2 met3 met4 met5"
|
||||
straps {
|
||||
}
|
||||
connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
|
||||
}
|
||||
set ::halo [list $::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)]
|
||||
pdngen::specify_grid macro [subst $macro]
|
||||
} else {
|
||||
set macro {
|
||||
orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
power_pins "vccd1"
|
||||
ground_pins "vssd1"
|
||||
blockages "met1 met2 met3 met4 met5"
|
||||
straps {
|
||||
}
|
||||
}
|
||||
set ::halo [list $::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)]
|
||||
pdngen::specify_grid macro [subst $macro]
|
||||
}
|
||||
|
||||
# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
|
||||
|
|
|
|||
|
|
@ -1,23 +0,0 @@
|
|||
#E
|
||||
gpio_defaults.*
|
||||
zero
|
||||
one
|
||||
mgmt_.*
|
||||
pad_gpio_ana_en.*
|
||||
pad_gpio_ana_pol.*
|
||||
pad_gpio_ana_sel.*
|
||||
pad_gpio_dm.*
|
||||
pad_gpio_holdover.*
|
||||
pad_gpio_ib_mode_sel.*
|
||||
pad_gpio_in.*
|
||||
pad_gpio_out.*
|
||||
pad_gpio_slow_sel.*
|
||||
pad_gpio_vtrip_sel.*
|
||||
resetn.*
|
||||
serial_clock.*
|
||||
serial_data_in.*
|
||||
serial_data_out.*
|
||||
serial_load.*
|
||||
user_gpio_in.*
|
||||
user_gpio_oeb.*
|
||||
user_gpio_out.*
|
||||
|
|
@ -1 +1 @@
|
|||
openlane 2021.09.09_03.00.48-52-gc99f895
|
||||
openlane 2021.09.09_03.00.48-53-g97579eb
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/project/openlane/gpio_control_block,gpio_control_block,gpio_control_block,flow_completed,0h2m34s,-1,21008.403361344535,0.0119,10504.201680672268,78.72,502.84,125,0,0,0,0,0,0,0,0,0,-1,-1,6391,1178,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,4686917.0,0.0,12.7,12.38,26.08,-1,16.48,81,109,48,76,0,0,0,66,0,0,0,0,0,0,0,4,24,44,4,34,25,0,59,38.46153846153846,26,25,AREA 0,5,50,1,15.5,15.5,0.91,0.05,sky130_fd_sc_hd,0,3
|
||||
0,/project/openlane/gpio_control_block,gpio_control_block,gpio_control_block,flow_completed,0h1m59s,-1,22624.434389140275,0.01105,11312.217194570138,70.3,485.43,125,0,0,0,0,0,0,0,0,0,-1,-1,4876,1068,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,3826992.0,0.0,12.67,12.17,18.08,-1,14.14,81,109,48,76,0,0,0,66,0,0,0,0,0,0,0,4,24,44,4,38,28,0,66,38.46153846153846,26,25,AREA 0,5,50,1,15.5,16.9,0.91,0.05,sky130_fd_sc_hd,0,4
|
||||
|
|
|
|||
|
|
|
@ -1 +1 @@
|
|||
openlane 2021.09.09_03.00.48-52-gc99f895
|
||||
openlane 2021.09.09_03.00.48-53-g97579eb
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/project/openlane/gpio_logic_high,gpio_logic_high,gpio_logic_high,flow_completed,0h0m51s,-1,17857.14285714286,0.00011200000000000001,8928.57142857143,7.14,441.08,1,0,-1,-1,-1,-1,0,0,-1,0,0,-1,4,3,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,421.0,0.0,0.0,0.0,0.0,0.0,0.0,3,3,3,3,0,0,0,1,0,0,0,0,0,0,0,4,-1,-1,-1,10,3,0,13,90.9090909090909,11.0,10.0,AREA 0,5,50,1,7.4,153.18,0.8,0.0,sky130_fd_sc_hd,0,3
|
||||
0,/project/openlane/gpio_logic_high,gpio_logic_high,gpio_logic_high,flow_completed,0h0m55s,-1,17857.14285714286,0.00011200000000000001,8928.57142857143,7.14,439.57,1,0,-1,-1,-1,-1,0,0,-1,0,0,-1,4,3,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,365.0,0.0,0.0,0.0,0.0,0.0,0.0,3,3,3,3,0,0,0,1,0,0,0,0,0,0,0,4,-1,-1,-1,10,3,0,13,90.9090909090909,11.0,10.0,AREA 0,5,50,1,7.4,153.18,0.8,0.0,sky130_fd_sc_hd,0,3
|
||||
|
|
|
|||
|
|
|
@ -1,5 +1,9 @@
|
|||
* NGSPICE file created from gpio_control_block.ext - technology: sky130A
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfbbn_1 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
|
||||
.ends
|
||||
|
|
@ -8,18 +12,10 @@
|
|||
.subckt sky130_fd_sc_hd__clkbuf_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2b_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2b_1 A B_N VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
|
@ -28,6 +24,26 @@
|
|||
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_12 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2_1 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
|
@ -36,10 +52,6 @@
|
|||
.subckt sky130_fd_sc_hd__and2_1 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
|
@ -64,10 +76,6 @@
|
|||
.subckt sky130_fd_sc_hd__clkbuf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_12 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dlymetal6s2s_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dlymetal6s2s_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
|
@ -76,6 +84,10 @@
|
|||
.subckt sky130_fd_sc_hd__ebufn_1 A TE_B VGND VNB VPB VPWR Z
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkdlybuf4s25_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkdlybuf4s25_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__mux2_1 A0 A1 S VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
|
@ -100,314 +112,327 @@
|
|||
+ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
|
||||
+ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
|
||||
+ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
|
||||
XFILLER_3_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_200_ _162_/X _220_/D _166_/X _164_/X vssd vssd vccd vccd _200_/Q _200_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_131_ _131_/A vssd vssd vccd vccd _131_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_13_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_5 gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_6_78 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XANTENNA_input18_A serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_114_ _190_/A _116_/B vssd vssd vccd vccd _115_/A sky130_fd_sc_hd__or2b_1
|
||||
Xoutput31 _202_/Q vssd vssd vccd vccd pad_gpio_inenb sky130_fd_sc_hd__buf_2
|
||||
X_130_ _130_/A vssd vssd vccd vccd _131_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_113_ _113_/A vssd vssd vccd vccd _113_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput32 _196_/X vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__buf_2
|
||||
XFILLER_6_46 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XANTENNA_6 gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_1_90 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_189_ _189_/A vssd vssd vccd vccd _189_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_0_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_9_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_9_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_0_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_6_36 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_112_ _130_/A vssd vssd vccd vccd _113_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XANTENNA_7 gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_1_80 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xoutput33 _193_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__buf_2
|
||||
XFILLER_3_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_3_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
X_188_ _188_/A vssd vssd vccd vccd _189_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_15_9 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_9_14 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_111_ _111_/A vssd vssd vccd vccd _111_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_0_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xoutput34 _200_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_2
|
||||
Xoutput23 _208_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_8 gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_6_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_input8_A gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_input16_A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_187_ _187_/A vssd vssd vccd vccd _187_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_18_79 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_18_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_110_ _190_/A _110_/B vssd vssd vccd vccd _111_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_1_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xoutput35 _201_/Q vssd vssd vccd vccd pad_gpio_vtrip_sel sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_9 gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput24 _210_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_2
|
||||
XFILLER_7_92 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_12_15 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xoutput24 _210_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_2
|
||||
X_186_ one _223_/Q vssd vssd vccd vccd _187_/A sky130_fd_sc_hd__and2_1
|
||||
XFILLER_4_60 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_4_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_169_ _190_/A _171_/B vssd vssd vccd vccd _170_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_1_50 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xoutput36 _190_/X vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_2
|
||||
Xoutput25 _209_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_input21_A user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_13_92 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xoutput25 _209_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_2
|
||||
X_185_ _197_/A vssd vssd vccd vccd _185_/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_4_61 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_168_ _168_/A vssd vssd vccd vccd _168_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_1_62 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_1_84 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xoutput37 _191_/X vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput26 _205_/Q vssd vssd vccd vccd pad_gpio_dm[0] sky130_fd_sc_hd__buf_2
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_input6_A gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_input14_A mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_4_40 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xconst_source vssd vssd vccd vccd one zero sky130_fd_sc_hd__conb_1
|
||||
X_184_ _184_/A vssd vssd vccd vccd _194_/S sky130_fd_sc_hd__clkbuf_1
|
||||
X_219_ _191_/A _219_/D _190_/A vssd vssd vccd vccd _220_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_167_ _188_/A vssd vssd vccd vccd _168_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_219_ _191_/A _219_/D _190_/A vssd vssd vccd vccd _220_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_1_74 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xoutput38 _187_/X vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_2
|
||||
XFILLER_15_39 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xoutput27 _206_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_2
|
||||
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_12_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_4_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
X_166_ _166_/A vssd vssd vccd vccd _166_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_183_ _207_/Q _206_/Q vssd vssd vccd vccd _184_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_1_86 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xoutput39 _192_/X vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__buf_2
|
||||
Xoutput28 _207_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_2
|
||||
X_218_ _222_/CLK _218_/D _190_/A vssd vssd vccd vccd _219_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_149_ _161_/A vssd vssd vccd vccd _150_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_218_ _223_/CLK _218_/D _190_/A vssd vssd vccd vccd _219_/D sky130_fd_sc_hd__dfrtp_1
|
||||
Xoutput28 _207_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_2
|
||||
XFILLER_7_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_182_ _182_/A vssd vssd vccd vccd _182_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_165_ _190_/A _165_/B vssd vssd vccd vccd _166_/A sky130_fd_sc_hd__or2_1
|
||||
X_217_ _223_/CLK _217_/D _190_/A vssd vssd vccd vccd _218_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_148_ _148_/A vssd vssd vccd vccd _148_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_217_ _222_/CLK _217_/D _190_/A vssd vssd vccd vccd _218_/D sky130_fd_sc_hd__dfrtp_1
|
||||
Xoutput29 _199_/Q vssd vssd vccd vccd pad_gpio_holdover sky130_fd_sc_hd__buf_2
|
||||
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_181_ _204_/Q _195_/S vssd vssd vccd vccd _182_/A sky130_fd_sc_hd__and2_1
|
||||
XANTENNA_input12_A gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_input4_A gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_164_ _164_/A vssd vssd vccd vccd _164_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_1_77 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_10_20 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_216_ _223_/CLK _216_/D _190_/A vssd vssd vccd vccd _217_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_181_ _204_/Q _195_/S vssd vssd vccd vccd _182_/A sky130_fd_sc_hd__and2_1
|
||||
X_216_ _222_/CLK _216_/D _190_/A vssd vssd vccd vccd _217_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_147_ _190_/A _147_/B vssd vssd vccd vccd _148_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_16_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_180_ _180_/A vssd vssd vccd vccd _180_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_163_ _190_/A _165_/B vssd vssd vccd vccd _164_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_1_67 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_1_78 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_129_ _129_/A vssd vssd vccd vccd _129_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_215_ _222_/CLK _215_/D _190_/A vssd vssd vccd vccd _216_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_146_ _146_/A vssd vssd vccd vccd _146_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_129_ _129_/A vssd vssd vccd vccd _129_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_215_ _223_/CLK _215_/D _190_/A vssd vssd vccd vccd _216_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_13_65 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_4_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_162_ _162_/A vssd vssd vccd vccd _162_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_13_10 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_8_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_8_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xinput1 gpio_defaults[0] vssd vssd vccd vccd _177_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_214_ _222_/CLK _214_/D _190_/A vssd vssd vccd vccd _215_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_145_ _190_/A _147_/B vssd vssd vccd vccd _146_/A sky130_fd_sc_hd__or2b_1
|
||||
X_214_ _191_/A _214_/D _190_/A vssd vssd vccd vccd _215_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_128_ _190_/A _128_/B vssd vssd vccd vccd _129_/A sky130_fd_sc_hd__or2_1
|
||||
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xgpio_in_buf _185_/Y gpio_in_buf/TE vssd vssd vccd vccd output40/A sky130_fd_sc_hd__einvp_2
|
||||
XANTENNA_input10_A gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_13_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_input2_A gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_161_ _161_/A vssd vssd vccd vccd _162_/A sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput2 gpio_defaults[10] vssd vssd vccd vccd _134_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_16_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_213_ _191_/A _213_/D _190_/A vssd vssd vccd vccd _214_/D sky130_fd_sc_hd__dfrtp_1
|
||||
Xgpio_in_buf _185_/Y gpio_in_buf/TE vssd vssd vccd vccd output40/A sky130_fd_sc_hd__einvp_2
|
||||
X_213_ _222_/CLK _213_/D _190_/A vssd vssd vccd vccd _214_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_127_ _127_/A vssd vssd vccd vccd _127_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_144_ _144_/A vssd vssd vccd vccd _144_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_144_ _144_/A vssd vssd vccd vccd _144_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_4_47 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
X_160_ _160_/A vssd vssd vccd vccd _160_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_212_ _191_/A _212_/D _190_/A vssd vssd vccd vccd _213_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_10_68 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_10_13 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_1_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_143_ _161_/A vssd vssd vccd vccd _144_/A sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput3 gpio_defaults[11] vssd vssd vccd vccd _128_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_212_ _222_/CLK hold1/X _190_/A vssd vssd vccd vccd _213_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_143_ _161_/A vssd vssd vccd vccd _144_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_1_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
X_126_ _190_/A _128_/B vssd vssd vccd vccd _127_/A sky130_fd_sc_hd__or2b_1
|
||||
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_13_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_4_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
X_109_ _109_/A vssd vssd vccd vccd _109_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_5_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XTAP_60 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput4 gpio_defaults[12] vssd vssd vccd vccd _122_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_211_ _191_/A _211_/D _190_/A vssd vssd vccd vccd _212_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_1_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
X_211_ _191_/A _211_/D _190_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_1
|
||||
X_142_ _142_/A vssd vssd vccd vccd _142_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XANTENNA_20 gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_125_ _125_/A vssd vssd vccd vccd _125_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_16_13 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_2_81 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_108_ _190_/A _110_/B vssd vssd vccd vccd _109_/A sky130_fd_sc_hd__or2b_1
|
||||
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_61 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_141_ _190_/A _141_/B vssd vssd vccd vccd _142_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_10_37 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_18_9 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xinput5 gpio_defaults[1] vssd vssd vccd vccd _141_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_210_ _189_/X _219_/D _105_/X _103_/X vssd vssd vccd vccd _210_/Q _210_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xclkbuf_1_1_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _191_/A sky130_fd_sc_hd__clkbuf_2
|
||||
XANTENNA_21 serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_124_ _130_/A vssd vssd vccd vccd _125_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XANTENNA_10 gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_2_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_14_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
X_107_ _188_/A vssd vssd vccd vccd _130_/A sky130_fd_sc_hd__dlymetal6s2s_1
|
||||
XANTENNA_input19_A serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_5_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_62 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_140_ _140_/A vssd vssd vccd vccd _140_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput6 gpio_defaults[2] vssd vssd vccd vccd _171_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XANTENNA_11 gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_40 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_106_ _192_/A vssd vssd vccd vccd _188_/A sky130_fd_sc_hd__inv_2
|
||||
Xinput20 user_gpio_oeb vssd vssd vccd vccd _193_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_16_7 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_11_92 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_123_ _123_/A vssd vssd vccd vccd _123_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_13_49 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_63 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput7 gpio_defaults[3] vssd vssd vccd vccd _153_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_41 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput21 user_gpio_out vssd vssd vccd vccd _196_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
X_199_ _168_/X _214_/D _172_/X _170_/X vssd vssd vccd vccd _199_/Q _199_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XANTENNA_12 mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_122_ _190_/A _122_/B vssd vssd vccd vccd _123_/A sky130_fd_sc_hd__or2_1
|
||||
Xinput10 gpio_defaults[6] vssd vssd vccd vccd _110_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_11_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_122_ _190_/A _122_/B vssd vssd vccd vccd _123_/A sky130_fd_sc_hd__or2_1
|
||||
Xinput21 user_gpio_out vssd vssd vccd vccd _196_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
X_105_ _105_/A vssd vssd vccd vccd _105_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_198_ _174_/X _212_/D _178_/X _176_/X vssd vssd vccd vccd _198_/Q _198_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_8_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_64 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_198_ _174_/X hold1/A _178_/X _176_/X vssd vssd vccd vccd _198_/Q _198_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput8 gpio_defaults[4] vssd vssd vccd vccd _147_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_2_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_10_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XANTENNA_13 mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xinput11 gpio_defaults[7] vssd vssd vccd vccd _104_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_104_ _190_/A _104_/B vssd vssd vccd vccd _105_/A sky130_fd_sc_hd__or2_1
|
||||
X_121_ _121_/A vssd vssd vccd vccd _121_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput11 gpio_defaults[7] vssd vssd vccd vccd _104_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_12_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_input17_A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_input9_A gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_65 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput9 gpio_defaults[5] vssd vssd vccd vccd _116_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_197_ _197_/A _180_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_1
|
||||
XANTENNA_14 one vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xinput12 gpio_defaults[8] vssd vssd vccd vccd _165_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_197_ _197_/A _180_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_1
|
||||
X_120_ _190_/A _122_/B vssd vssd vccd vccd _121_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_16_18 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_2_64 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_16_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_103_ _103_/A vssd vssd vccd vccd _103_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_5_53 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_196_ _196_/A0 _195_/X _198_/Q vssd vssd vccd vccd _196_/X sky130_fd_sc_hd__mux2_1
|
||||
Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_196_ _196_/A0 _195_/X _198_/Q vssd vssd vccd vccd _196_/X sky130_fd_sc_hd__mux2_1
|
||||
XFILLER_2_76 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_15 one vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_179_ _202_/Q _204_/Q vssd vssd vccd vccd _180_/A sky130_fd_sc_hd__or2b_1
|
||||
Xinput13 gpio_defaults[9] vssd vssd vccd vccd _159_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_102_ _190_/A _104_/B vssd vssd vccd vccd _103_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_8_20 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_179_ _202_/Q _204_/Q vssd vssd vccd vccd _180_/A sky130_fd_sc_hd__or2b_1
|
||||
XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xgpio_logic_high gpio_in_buf/TE vccd1 vssd1 gpio_logic_high
|
||||
XTAP_34 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_16 pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_195_ _195_/A0 _194_/X _195_/S vssd vssd vccd vccd _195_/X sky130_fd_sc_hd__mux2_1
|
||||
Xinput14 mgmt_gpio_oeb vssd vssd vccd vccd _195_/S sky130_fd_sc_hd__clkbuf_1
|
||||
X_178_ _178_/A vssd vssd vccd vccd _178_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_8_10 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_input15_A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_194_ _194_/A0 _195_/A0 _194_/S vssd vssd vccd vccd _194_/X sky130_fd_sc_hd__mux2_1
|
||||
XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_35 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_17 serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_input7_A gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_194_ _194_/A0 _195_/A0 _194_/S vssd vssd vccd vccd _194_/X sky130_fd_sc_hd__mux2_1
|
||||
X_177_ _177_/A _190_/A vssd vssd vccd vccd _178_/A sky130_fd_sc_hd__or2_1
|
||||
Xinput15 mgmt_gpio_out vssd vssd vccd vccd _195_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_8_33 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_14_43 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_36 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_18 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_193_ _193_/A0 _182_/X _198_/Q vssd vssd vccd vccd _193_/X sky130_fd_sc_hd__mux2_1
|
||||
XFILLER_11_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_11_44 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_159_ _190_/A _159_/B vssd vssd vccd vccd _160_/A sky130_fd_sc_hd__or2_1
|
||||
X_176_ _176_/A vssd vssd vccd vccd _176_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_159_ _190_/A _159_/B vssd vssd vccd vccd _160_/A sky130_fd_sc_hd__or2_1
|
||||
Xinput16 pad_gpio_in vssd vssd vccd vccd _197_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_8_45 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_192_ _192_/A vssd vssd vccd vccd _192_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_59 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_input20_A user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_48 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_37 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput17 resetn vssd vssd vccd vccd _190_/A sky130_fd_sc_hd__buf_12
|
||||
XANTENNA_19 user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_175_ _190_/A _177_/A vssd vssd vccd vccd _176_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_11_78 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_11_12 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xinput17 resetn vssd vssd vccd vccd _190_/A sky130_fd_sc_hd__buf_12
|
||||
X_158_ _158_/A vssd vssd vccd vccd _158_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_8_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_8_35 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_input13_A gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xclkbuf_1_0_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _222_/CLK sky130_fd_sc_hd__clkbuf_2
|
||||
XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_38 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xclkbuf_1_0_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _223_/CLK sky130_fd_sc_hd__clkbuf_2
|
||||
XFILLER_0_80 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_191_ _191_/A vssd vssd vccd vccd _191_/X sky130_fd_sc_hd__buf_2
|
||||
XFILLER_11_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_11_46 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_input5_A gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
|
||||
XFILLER_2_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_157_ _190_/A _159_/B vssd vssd vccd vccd _158_/A sky130_fd_sc_hd__or2b_1
|
||||
X_174_ _174_/A vssd vssd vccd vccd _174_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput18 serial_data_in vssd vssd vccd vccd _211_/D sky130_fd_sc_hd__clkbuf_1
|
||||
X_157_ _190_/A _159_/B vssd vssd vccd vccd _158_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_5_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_209_ _130_/A _218_/D _111_/X _109_/X vssd vssd vccd vccd _209_/Q _209_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_0_92 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XTAP_39 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_173_ _188_/A vssd vssd vccd vccd _174_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_190_ _190_/A vssd vssd vccd vccd _190_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xinput19 serial_load vssd vssd vccd vccd _192_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_190_ _190_/A vssd vssd vccd vccd _190_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_2_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
X_156_ _156_/A vssd vssd vccd vccd _156_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_3_92 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_3_70 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_8_15 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_139_ _190_/A _141_/B vssd vssd vccd vccd _140_/A sky130_fd_sc_hd__or2b_1
|
||||
X_208_ _113_/X _217_/D _117_/X _115_/X vssd vssd vccd vccd _208_/Q _208_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XPHY_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
X_155_ _161_/A vssd vssd vccd vccd _156_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_172_ _172_/A vssd vssd vccd vccd _172_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_138_ _138_/A vssd vssd vccd vccd _138_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_207_ _119_/X _223_/Q _123_/X _121_/X vssd vssd vccd vccd _207_/Q _207_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_14_15 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_0_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_6_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_6_60 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_input11_A gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_171_ _190_/A _171_/B vssd vssd vccd vccd _172_/A sky130_fd_sc_hd__or2_1
|
||||
XPHY_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_input3_A gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_154_ _154_/A vssd vssd vccd vccd _154_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_223_ _223_/CLK _223_/D _190_/A vssd vssd vccd vccd _223_/Q sky130_fd_sc_hd__dfrtp_1
|
||||
X_223_ _191_/A _223_/D _190_/A vssd vssd vccd vccd _223_/Q sky130_fd_sc_hd__dfrtp_1
|
||||
X_137_ _161_/A vssd vssd vccd vccd _138_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XANTENNA__186__A one vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_206_ _125_/X _223_/D _129_/X _127_/X vssd vssd vccd vccd _206_/Q _206_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_15_81 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_37 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_170_ _170_/A vssd vssd vccd vccd _170_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_205_ _131_/X _222_/D _135_/X _133_/X vssd vssd vccd vccd _205_/Q _194_/A0 sky130_fd_sc_hd__dfbbn_1
|
||||
X_136_ _188_/A vssd vssd vccd vccd _161_/A sky130_fd_sc_hd__dlymetal6s2s_1
|
||||
X_222_ _223_/CLK _222_/D _190_/A vssd vssd vccd vccd _223_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_3_62 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
X_153_ _190_/A _153_/B vssd vssd vccd vccd _154_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_0_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_136_ _188_/A vssd vssd vccd vccd _161_/A sky130_fd_sc_hd__dlymetal6s2s_1
|
||||
X_222_ _222_/CLK _222_/D _190_/A vssd vssd vccd vccd _223_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_0_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
X_205_ _131_/X _222_/D _135_/X _133_/X vssd vssd vccd vccd _205_/Q _194_/A0 sky130_fd_sc_hd__dfbbn_1
|
||||
X_119_ _119_/A vssd vssd vccd vccd _119_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_0 gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_221_ _191_/A _221_/D _190_/A vssd vssd vccd vccd _222_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_12_72 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_152_ _152_/A vssd vssd vccd vccd _152_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_221_ _191_/A _221_/D _190_/A vssd vssd vccd vccd _222_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_204_ _138_/X _213_/D _142_/X _140_/X vssd vssd vccd vccd _204_/Q _204_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_135_ _135_/A vssd vssd vccd vccd _135_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_0_75 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_118_ _130_/A vssd vssd vccd vccd _119_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_14_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_0_64 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
X_135_ _135_/A vssd vssd vccd vccd _135_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_1 gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_11_19 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_9_7 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_input1_A gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_220_ _191_/A _220_/D _190_/A vssd vssd vccd vccd _221_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_134_ _190_/A _134_/B vssd vssd vccd vccd _135_/A sky130_fd_sc_hd__or2_1
|
||||
X_203_ _144_/X _216_/D _148_/X _146_/X vssd vssd vccd vccd _203_/Q _203_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_151_ _190_/A _153_/B vssd vssd vccd vccd _152_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_15_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_63 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_203_ _144_/X _216_/D _148_/X _146_/X vssd vssd vccd vccd _203_/Q _203_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_0_76 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_134_ _190_/A _134_/B vssd vssd vccd vccd _135_/A sky130_fd_sc_hd__or2_1
|
||||
X_117_ _117_/A vssd vssd vccd vccd _117_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_8 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_2 gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_12_41 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_150_ _150_/A vssd vssd vccd vccd _150_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_202_ _150_/X _215_/D _154_/X _152_/X vssd vssd vccd vccd _202_/Q _202_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_133_ _133_/A vssd vssd vccd vccd _133_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_3 gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_116_ _190_/A _116_/B vssd vssd vccd vccd _117_/A sky130_fd_sc_hd__or2_1
|
||||
Xoutput40 output40/A vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_clkbuf_0_serial_clock_A serial_clock vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_15_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_201_ _156_/X _221_/D _160_/X _158_/X vssd vssd vccd vccd _201_/Q _201_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_132_ _190_/A _134_/B vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_18_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_9_10 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_115_ _115_/A vssd vssd vccd vccd _115_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput30 _203_/Q vssd vssd vccd vccd pad_gpio_ib_mode_sel sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_4 gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
.ends
|
||||
|
||||
|
|
|
|||
|
|
@ -208,6 +208,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
wire net39;
|
||||
wire net4;
|
||||
wire net40;
|
||||
wire net41;
|
||||
wire net5;
|
||||
wire net6;
|
||||
wire net7;
|
||||
|
|
@ -227,253 +228,182 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
wire \shift_register[8] ;
|
||||
wire \shift_register[9] ;
|
||||
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_0 (.DIODE(gpio_defaults[10]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__186__A (.DIODE(one),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_1 (.DIODE(gpio_defaults[11]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_serial_clock_A (.DIODE(serial_clock),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_10 (.DIODE(gpio_defaults[8]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input10_A (.DIODE(gpio_defaults[6]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_11 (.DIODE(gpio_defaults[9]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input11_A (.DIODE(gpio_defaults[7]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_12 (.DIODE(mgmt_gpio_oeb),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input12_A (.DIODE(gpio_defaults[8]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_13 (.DIODE(mgmt_gpio_out),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input13_A (.DIODE(gpio_defaults[9]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_14 (.DIODE(one),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input14_A (.DIODE(mgmt_gpio_oeb),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_15 (.DIODE(one),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input15_A (.DIODE(mgmt_gpio_out),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_16 (.DIODE(pad_gpio_in),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input16_A (.DIODE(pad_gpio_in),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_17 (.DIODE(serial_data_in),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input17_A (.DIODE(resetn),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_18 (.DIODE(user_gpio_oeb),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input18_A (.DIODE(serial_data_in),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_19 (.DIODE(user_gpio_out),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input19_A (.DIODE(serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_2 (.DIODE(gpio_defaults[12]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input1_A (.DIODE(gpio_defaults[0]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_20 (.DIODE(gpio_defaults[0]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input20_A (.DIODE(user_gpio_oeb),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_21 (.DIODE(serial_load),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input21_A (.DIODE(user_gpio_out),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_3 (.DIODE(gpio_defaults[1]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input2_A (.DIODE(gpio_defaults[10]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_4 (.DIODE(gpio_defaults[2]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input3_A (.DIODE(gpio_defaults[11]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_5 (.DIODE(gpio_defaults[3]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input4_A (.DIODE(gpio_defaults[12]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_6 (.DIODE(gpio_defaults[4]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input5_A (.DIODE(gpio_defaults[1]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_7 (.DIODE(gpio_defaults[5]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input6_A (.DIODE(gpio_defaults[2]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_8 (.DIODE(gpio_defaults[6]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input7_A (.DIODE(gpio_defaults[3]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_9 (.DIODE(gpio_defaults[7]),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input8_A (.DIODE(gpio_defaults[4]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_26 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_input9_A (.DIODE(gpio_defaults[5]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_75 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_0_26 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_85 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_0_38 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_10_13 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_50 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_10_20 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_0_52 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_10_29 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_0_64 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_10_37 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_3 FILLER_0_76 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_10_68 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_0_80 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_11_12 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_92 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_11_19 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_11_44 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_11_46 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_11_55 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_11_57 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_11_93 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_11_78 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_12_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_11_92 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_13_55 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_12_15 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_14_43 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_12_3 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_15_52 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_12_41 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_12_72 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_13_10 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_13_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_13_49 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_13_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_13_65 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_13_92 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_14_15 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_14_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_14_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_15_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_15_39 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_15_81 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_15_9 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_16_13 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_16_18 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_16_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_16_7 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_16_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
|
|
@ -481,51 +411,127 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_26 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_18_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_67 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_18_79 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_1_77 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_18_85 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_1_86 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_18_9 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_93 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_1_26 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_2_93 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_1_38 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_26 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_1_50 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_3_92 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_1_62 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_61 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_74 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_5_26 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_78 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_5_53 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_80 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_5_80 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_84 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_90 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_2_26 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_2_38 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_2_50 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_2_52 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_12 FILLER_2_64 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_2_76 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_2_81 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_3_26 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_3_34 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_3_62 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_3_70 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_4_26 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_4_34 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_40 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_47 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_4_52 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_60 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_93 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
|
|
@ -533,11 +539,23 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_6_46 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_6_26 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_6_78 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_6_36 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_6_60 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_6_93 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_7_52 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
|
|
@ -545,39 +563,43 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_8_10 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_2 FILLER_8_15 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_8_20 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_12 FILLER_8_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_8_3 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_8_35 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_8_33 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_8_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_8_45 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_8_83 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_9_14 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_9_10 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_9_3 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_3 FILLER_9_13 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_9_63 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__decap_4 FILLER_9_3 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_9_8 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_9_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_9_7 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
|
|
@ -693,6 +715,22 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_34 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_35 (.VGND(vssd),
|
||||
.VNB(vssd),
|
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.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_36 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_37 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
|
|
@ -717,14 +755,6 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_34 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_35 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_36 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_37 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_38 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_39 (.VGND(vssd),
|
||||
|
|
@ -767,6 +797,20 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_58 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_59 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_60 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_61 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_62 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_63 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_64 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_65 (.VGND(vssd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__or2b_1 _102_ (.A(net17),
|
||||
.B_N(net11),
|
||||
.X(_073_),
|
||||
|
|
@ -1520,10 +1564,10 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__dfrtp_1 _212_ (.D(\shift_register[0] ),
|
||||
sky130_fd_sc_hd__dfrtp_1 _212_ (.D(net41),
|
||||
.Q(\shift_register[1] ),
|
||||
.RESET_B(net17),
|
||||
.CLK(clknet_1_1_0_serial_clock),
|
||||
.CLK(clknet_1_0_0_serial_clock),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
|
|
@ -1531,7 +1575,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
sky130_fd_sc_hd__dfrtp_1 _213_ (.D(\shift_register[1] ),
|
||||
.Q(\shift_register[2] ),
|
||||
.RESET_B(net17),
|
||||
.CLK(clknet_1_1_0_serial_clock),
|
||||
.CLK(clknet_1_0_0_serial_clock),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
|
|
@ -1539,7 +1583,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
sky130_fd_sc_hd__dfrtp_1 _214_ (.D(\shift_register[2] ),
|
||||
.Q(\shift_register[3] ),
|
||||
.RESET_B(net17),
|
||||
.CLK(clknet_1_1_0_serial_clock),
|
||||
.CLK(clknet_1_0_0_serial_clock),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
|
|
@ -1611,7 +1655,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
sky130_fd_sc_hd__dfrtp_1 _223_ (.D(\shift_register[11] ),
|
||||
.Q(serial_data_pre),
|
||||
.RESET_B(net17),
|
||||
.CLK(clknet_1_0_0_serial_clock),
|
||||
.CLK(clknet_1_1_0_serial_clock),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
|
|
@ -1650,6 +1694,12 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
gpio_logic_high gpio_logic_high (.gpio_logic1(gpio_logic1),
|
||||
.vccd1(vccd1),
|
||||
.vssd1(vssd1));
|
||||
sky130_fd_sc_hd__clkdlybuf4s25_1 hold1 (.A(\shift_register[0] ),
|
||||
.X(net41),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__clkbuf_1 input1 (.A(gpio_defaults[0]),
|
||||
.X(net1),
|
||||
.VGND(vssd),
|
||||
|
|
|
|||
Loading…
Reference in New Issue