Mgmt protect update (#58)

* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect

* mgmt_protect updated

* mgmt_protect updated

* remove some via3 to fix power shorts

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>

lef/mgmt_protect.lef

@@ -9247,7 +9247,7 @@ MACRO mgmt_protect
       LAYER li1 ;
         RECT 5.520 5.355 1094.340 152.405 ;
       LAYER met1 ;
-        RECT 373.220 160.000 593.470 160.040 ;
+        RECT 275.700 160.000 484.680 160.040 ;
         RECT 0.070 0.040 1098.870 160.000 ;
       LAYER met2 ;
         RECT 0.100 155.720 0.730 159.790 ;
@@ -10363,7 +10363,7 @@ MACRO mgmt_protect
         RECT 1095.450 0.010 1096.450 4.280 ;
         RECT 1097.290 0.010 1098.290 4.280 ;
       LAYER met3 ;
-        RECT 4.000 152.000 1096.000 156.225 ;
+        RECT 4.000 152.000 1096.000 159.625 ;
         RECT 4.000 150.600 1095.600 152.000 ;
         RECT 4.000 136.360 1096.000 150.600 ;
         RECT 4.000 134.960 1095.600 136.360 ;
@@ -10391,48 +10391,58 @@ MACRO mgmt_protect
         RECT 4.000 7.120 1095.600 8.520 ;
         RECT 4.000 0.175 1096.000 7.120 ;
       LAYER met4 ;
-        RECT 341.615 4.800 395.920 150.105 ;
-        RECT 397.620 5.040 400.020 150.105 ;
-        RECT 401.720 5.040 404.120 150.105 ;
-        RECT 405.820 5.040 471.170 150.105 ;
+        RECT 341.615 152.960 1065.065 154.185 ;
+        RECT 341.615 4.800 395.920 152.960 ;
+        RECT 397.620 152.720 471.170 152.960 ;
+        RECT 397.620 5.040 400.020 152.720 ;
+        RECT 401.720 5.040 404.120 152.720 ;
+        RECT 405.820 5.040 471.170 152.720 ;
         RECT 397.620 4.800 471.170 5.040 ;
-        RECT 472.870 5.040 475.270 150.105 ;
-        RECT 476.970 5.040 479.370 150.105 ;
-        RECT 481.070 5.040 546.420 150.105 ;
+        RECT 472.870 152.720 546.420 152.960 ;
+        RECT 472.870 5.040 475.270 152.720 ;
+        RECT 476.970 5.040 479.370 152.720 ;
+        RECT 481.070 5.040 546.420 152.720 ;
         RECT 472.870 4.800 546.420 5.040 ;
-        RECT 548.120 5.040 550.520 150.105 ;
-        RECT 552.220 5.040 554.620 150.105 ;
-        RECT 556.320 5.040 621.670 150.105 ;
+        RECT 548.120 152.720 621.670 152.960 ;
+        RECT 548.120 5.040 550.520 152.720 ;
+        RECT 552.220 5.040 554.620 152.720 ;
+        RECT 556.320 5.040 621.670 152.720 ;
         RECT 548.120 4.800 621.670 5.040 ;
-        RECT 623.370 5.040 625.770 150.105 ;
-        RECT 627.470 5.040 629.870 150.105 ;
-        RECT 631.570 5.040 696.920 150.105 ;
+        RECT 623.370 152.720 696.920 152.960 ;
+        RECT 623.370 5.040 625.770 152.720 ;
+        RECT 627.470 5.040 629.870 152.720 ;
+        RECT 631.570 5.040 696.920 152.720 ;
         RECT 623.370 4.800 696.920 5.040 ;
-        RECT 698.620 5.040 701.020 150.105 ;
-        RECT 702.720 5.040 705.120 150.105 ;
-        RECT 706.820 5.040 772.170 150.105 ;
+        RECT 698.620 152.720 772.170 152.960 ;
+        RECT 698.620 5.040 701.020 152.720 ;
+        RECT 702.720 5.040 705.120 152.720 ;
+        RECT 706.820 5.040 772.170 152.720 ;
         RECT 698.620 4.800 772.170 5.040 ;
-        RECT 773.870 5.040 776.270 150.105 ;
-        RECT 777.970 5.040 780.370 150.105 ;
-        RECT 782.070 5.040 847.420 150.105 ;
+        RECT 773.870 152.720 847.420 152.960 ;
+        RECT 773.870 5.040 776.270 152.720 ;
+        RECT 777.970 5.040 780.370 152.720 ;
+        RECT 782.070 5.040 847.420 152.720 ;
         RECT 773.870 4.800 847.420 5.040 ;
-        RECT 849.120 5.040 851.520 150.105 ;
-        RECT 853.220 5.040 855.620 150.105 ;
-        RECT 857.320 5.040 922.670 150.105 ;
+        RECT 849.120 152.720 922.670 152.960 ;
+        RECT 849.120 5.040 851.520 152.720 ;
+        RECT 853.220 5.040 855.620 152.720 ;
+        RECT 857.320 5.040 922.670 152.720 ;
         RECT 849.120 4.800 922.670 5.040 ;
-        RECT 924.370 5.040 926.770 150.105 ;
-        RECT 928.470 5.040 930.870 150.105 ;
-        RECT 932.570 5.040 933.670 150.105 ;
-        RECT 935.370 5.040 936.670 150.105 ;
-        RECT 938.370 5.040 997.920 150.105 ;
+        RECT 924.370 152.720 997.920 152.960 ;
+        RECT 924.370 5.040 926.770 152.720 ;
+        RECT 928.470 5.040 930.870 152.720 ;
+        RECT 932.570 5.040 933.670 152.720 ;
+        RECT 935.370 5.040 936.670 152.720 ;
+        RECT 938.370 5.040 997.920 152.720 ;
         RECT 924.370 4.800 997.920 5.040 ;
-        RECT 999.620 5.040 1002.020 150.105 ;
-        RECT 1003.720 5.040 1006.120 150.105 ;
-        RECT 1007.820 5.040 1008.920 150.105 ;
-        RECT 1010.620 5.040 1011.920 150.105 ;
-        RECT 1013.620 5.040 1065.065 150.105 ;
+        RECT 999.620 152.720 1065.065 152.960 ;
+        RECT 999.620 5.040 1002.020 152.720 ;
+        RECT 1003.720 5.040 1006.120 152.720 ;
+        RECT 1007.820 5.040 1008.920 152.720 ;
+        RECT 1010.620 5.040 1011.920 152.720 ;
+        RECT 1013.620 5.040 1065.065 152.720 ;
         RECT 999.620 4.800 1065.065 5.040 ;
-        RECT 341.615 2.215 1065.065 4.800 ;
+        RECT 341.615 0.175 1065.065 4.800 ;
   END
 END mgmt_protect
 END LIBRARY

maglef/mgmt_protect.mag

@@ -1,11 +1,11 @@
 magic
 tech sky130A
 magscale 1 2
-timestamp 1640363172
+timestamp 1649102424
 << obsli1 >>
 rect 1104 1071 218868 30481
 << obsm1 >>
-rect 74644 32000 118694 32008
+rect 55140 32000 96936 32008
 rect 14 8 219774 32000
 << metal2 >>
 rect 202 31200 258 32400
@@ -2247,7 +2247,7 @@ rect -400 5312 800 5432
 rect 219200 4632 220400 4752
 rect 219200 1504 220400 1624
 << obsm3 >>
-rect 800 30400 219200 31245
+rect 800 30400 219200 31925
 rect 800 30120 219120 30400
 rect 800 27272 219200 30120
 rect 800 26992 219120 27272
@@ -2327,48 +2327,58 @@ rect 216354 1088 216534 30464
 rect 216914 1088 217094 30464
 rect 217514 1088 217694 30464
 << obsm4 >>
-rect 68323 960 79184 30021
-rect 79524 1008 80004 30021
-rect 80344 1008 80824 30021
-rect 81164 1008 94234 30021
+rect 68323 30592 213013 30837
+rect 68323 960 79184 30592
+rect 79524 30544 94234 30592
+rect 79524 1008 80004 30544
+rect 80344 1008 80824 30544
+rect 81164 1008 94234 30544
+rect 94574 30544 109284 30592
 rect 79524 960 94234 1008
-rect 94574 1008 95054 30021
-rect 95394 1008 95874 30021
-rect 96214 1008 109284 30021
+rect 94574 1008 95054 30544
+rect 95394 1008 95874 30544
+rect 96214 1008 109284 30544
+rect 109624 30544 124334 30592
 rect 94574 960 109284 1008
-rect 109624 1008 110104 30021
-rect 110444 1008 110924 30021
-rect 111264 1008 124334 30021
+rect 109624 1008 110104 30544
+rect 110444 1008 110924 30544
+rect 111264 1008 124334 30544
+rect 124674 30544 139384 30592
 rect 109624 960 124334 1008
-rect 124674 1008 125154 30021
-rect 125494 1008 125974 30021
-rect 126314 1008 139384 30021
+rect 124674 1008 125154 30544
+rect 125494 1008 125974 30544
+rect 126314 1008 139384 30544
+rect 139724 30544 154434 30592
 rect 124674 960 139384 1008
-rect 139724 1008 140204 30021
-rect 140544 1008 141024 30021
-rect 141364 1008 154434 30021
+rect 139724 1008 140204 30544
+rect 140544 1008 141024 30544
+rect 141364 1008 154434 30544
+rect 154774 30544 169484 30592
 rect 139724 960 154434 1008
-rect 154774 1008 155254 30021
-rect 155594 1008 156074 30021
-rect 156414 1008 169484 30021
+rect 154774 1008 155254 30544
+rect 155594 1008 156074 30544
+rect 156414 1008 169484 30544
+rect 169824 30544 184534 30592
 rect 154774 960 169484 1008
-rect 169824 1008 170304 30021
-rect 170644 1008 171124 30021
-rect 171464 1008 184534 30021
+rect 169824 1008 170304 30544
+rect 170644 1008 171124 30544
+rect 171464 1008 184534 30544
+rect 184874 30544 199584 30592
 rect 169824 960 184534 1008
-rect 184874 1008 185354 30021
-rect 185694 1008 186174 30021
-rect 186514 1008 186734 30021
-rect 187074 1008 187334 30021
-rect 187674 1008 199584 30021
+rect 184874 1008 185354 30544
+rect 185694 1008 186174 30544
+rect 186514 1008 186734 30544
+rect 187074 1008 187334 30544
+rect 187674 1008 199584 30544
+rect 199924 30544 213013 30592
 rect 184874 960 199584 1008
-rect 199924 1008 200404 30021
-rect 200744 1008 201224 30021
-rect 201564 1008 201784 30021
-rect 202124 1008 202384 30021
-rect 202724 1008 213013 30021
+rect 199924 1008 200404 30544
+rect 200744 1008 201224 30544
+rect 201564 1008 201784 30544
+rect 202124 1008 202384 30544
+rect 202724 1008 213013 30544
 rect 199924 960 213013 1008
-rect 68323 443 213013 960
+rect 68323 35 213013 960
 << labels >>
 rlabel metal3 s -400 5312 800 5432 6 caravel_clk
 port 1 nsew signal input
@@ -4724,8 +4734,8 @@ port 1134 nsew ground input
 string LEFclass BLOCK
 string FIXED_BBOX 0 0 220000 32000
 string LEFview TRUE
-string GDS_FILE ../gds/mgmt_protect.gds
-string GDS_END 9255108
-string GDS_START 792212
+string GDS_FILE /home/marwan/caravel/openlane/mgmt_protect/runs/mgmt_protect/results/finishing/mgmt_protect.gds
+string GDS_END 8059676
+string GDS_START 770596
 << end >>
 

openlane/mgmt_protect/config.tcl

@@ -106,7 +106,7 @@ set ::env(GLB_RT_OBS) "\
 	met4 990.00000 5.17000 1022.000 153.39500"
 	
 ## Diode Insertion 
-set ::env(DIODE_INSERTION_STRATEGY) 1
+set ::env(DIODE_INSERTION_STRATEGY) 4
 
 ## Internal Macros 
 set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
@@ -127,4 +127,9 @@ set ::env(EXTRA_GDS_FILES) "\
 	$script_dir/../../gds/mgmt_protect_hv.gds"
 
 ## LVS
-set ::env(QUIT_ON_LVS_ERROR) 0
+set ::env(QUIT_ON_LVS_ERROR) 0
+
+# mprj_dat_i_user
+# mprj_ack_i_user
+# user_irq_core
+set ::env(DONT_TOUCH_PORTS) "la_data_out_core\[*\] mprj_ack_i_user mprj_dat_i_user\[*\] user_irq_core\[*\]"

openlane/mgmt_protect/resizer.patch

@@ -0,0 +1,99 @@
+diff --git a/scripts/openroad/resizer.tcl b/scripts/openroad/resizer.tcl
+index ea74dde..843e195 100644
+--- a/scripts/openroad/resizer.tcl
++++ b/scripts/openroad/resizer.tcl
+@@ -11,6 +11,62 @@
+ # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ # See the License for the specific language governing permissions and
+ # limitations under the License.
++set ::env(OPENLANE_LOG_DEBUG) 1
++proc puts_debug {debug_message} {
++    if { $::env(OPENLANE_LOG_DEBUG) } {
++        puts "\[DEBUG\] $debug_message"
++    }
++}
++
++
++proc set_special {net_name} {
++    puts_debug "1"
++    set odb_net [odb::dbBlock_findNet $::odb_block $net_name]
++    puts_debug "2"
++    odb::dbNet_setSpecial $odb_net
++    puts "\[INFO\] special set on $net_name $odb_net"
++}
++
++proc set_special_multi {net_pattern} {
++    set odb_nets [odb::dbBlock_getNets $::odb_block]
++    set net_pattern_escaped [string map {"\[" "\\\["} $net_pattern]
++    set net_pattern_escaped [string map {"\]" "\\\]"} $net_pattern_escaped]
++    set net_matches {}
++    foreach net $odb_nets {
++        set net_name [odb::dbNet_getName $net]
++        if { [string match $net_pattern_escaped $net_name] } {
++            puts "\[INFO\] $net_name matches $net_pattern"
++            lappend net_matches $net_name
++        }
++    }
++    foreach net $net_matches {
++        puts_debug "setting special multi on $net"
++        set_special "$net"
++    }
++}
++
++proc clear_special_multi {net_pattern} {
++    set odb_nets [odb::dbBlock_getNets $::odb_block]
++    set net_pattern_escaped [string map {"\[" "\\\["} $net_pattern]
++    set net_pattern_escaped [string map {"\]" "\\\]"} $net_pattern_escaped]
++    set net_matches {}
++    foreach net $odb_nets {
++        set net_name [odb::dbNet_getName $net]
++        if { [string match $net_pattern_escaped $net_name] } {
++            lappend net_matches $net_name
++        }
++    }
++    foreach net $net_matches {
++        clear_special $net
++    }
++}
++
++proc clear_special {net_name} {
++    set block [[[::ord::get_db] getChip] getBlock]
++    set odb_net [odb::dbBlock_findNet $block $net_name]
++    odb::dbNet_clearSpecial $odb_net
++    puts "\[INFO\] clear special on $net_name"
++}
+ 
+ foreach lib $::env(LIB_RESIZER_OPT) {
+     read_liberty $lib
+@@ -44,6 +100,12 @@ if { [info exists ::env(DONT_USE_CELLS)] } {
+     set_dont_use $::env(DONT_USE_CELLS)
+ }
+ 
++variable odb_block [[[::ord::get_db] getChip] getBlock]
++#set_special la_data_out_core\[0\]
++foreach net_pattern $::env(DONT_TOUCH_PORTS) {
++    set_special_multi $net_pattern
++}
++
+ if { [info exists ::env(PL_RESIZER_BUFFER_INPUT_PORTS)] && $::env(PL_RESIZER_BUFFER_INPUT_PORTS) } {
+     buffer_ports -inputs
+ }
+@@ -51,6 +113,11 @@ if { [info exists ::env(PL_RESIZER_BUFFER_INPUT_PORTS)] && $::env(PL_RESIZER_BUF
+ if { [info exists ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS)] && $::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) } {
+     buffer_ports -outputs
+ }
++
++foreach net_pattern $::env(DONT_TOUCH_PORTS) {
++    clear_special_multi $net_pattern
++}
++
+ # Resize
+ if { [info exists ::env(PL_RESIZER_MAX_WIRE_LENGTH)] && $::env(PL_RESIZER_MAX_WIRE_LENGTH) } {
+     repair_design -max_wire_length $::env(PL_RESIZER_MAX_WIRE_LENGTH) \
+@@ -85,4 +152,4 @@ write_sdc $::env(SAVE_SDC)
+ # Run post design optimizations STA
+ estimate_parasitics -placement
+ set ::env(RUN_STANDALONE) 0
+-source $::env(SCRIPTS_DIR)/openroad/sta.tcl 
+\ No newline at end of file
++source $::env(SCRIPTS_DIR)/openroad/sta.tcl 

sdc/mgmt_protect.sdc

@@ -1,6 +1,6 @@
 ###############################################################################
 # Created by write_sdc
-# Fri Dec 24 16:20:39 2021
+# Mon Apr  4 19:54:47 2022
 ###############################################################################
 current_design mgmt_protect
 ###############################################################################

signoff/mgmt_protect/OPENLANE_VERSION

@@ -1 +1 @@
-openlane 2021.11.23_01.42.34-25-g8c734bc
+openlane 2021.12.29_01.44.14

signoff/mgmt_protect/PDK_SOURCES

@@ -1,3 +1,4 @@
-openlane 8c734bc051d0f302abd9a5437688f8dc75ffb32f
-skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
-open_pdks 476f7428f7f686de51a5164c702629a9b9f2da46
+-ne skywater-pdk 
+c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
+-ne open_pdks 
+27ecf1c16911f7dd4428ffab96f62c1fb876ea70

signoff/mgmt_protect/final_summary_report.csv

@@ -1,2 +1,2 @@
 ,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
-0,/home/ma/ef/caravel.latest/openlane/mgmt_protect,mgmt_protect,mgmt_protect,flow completed,0h7m3s0ms,0h5m41s0ms,14250.0,0.17600000000000002,7125.0,10.79,741.34,1254,0,0,0,0,0,0,9,70,53,-1,-1,400978,20544,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,386343993.0,0.0,59.95,26.3,46.54,16.17,-1,388,2353,59,2024,0,0,0,1254,0,0,0,0,0,0,0,0,329,329,1,140,2130,2799,5069,111.11111111111111,9,8,AREA 0,5,50,1,150.5,5.44,0.14,0.05,sky130_fd_sc_hd,0,1
+0,/home/marwan/caravel/openlane/mgmt_protect,mgmt_protect,mgmt_protect,flow completed,0h7m18s0ms,0h5m47s0ms,14250.0,0.17600000000000002,7125.0,10.79,1040.11,1254,0,0,0,0,0,0,9,64,50,-1,-1,396210,17435,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,386343993.0,0.0,59.64,25.12,45.15,16.44,-1,388,2353,59,2024,0,0,0,1254,0,0,0,0,0,0,0,0,329,329,1,140,2130,0,2270,125.0,8.0,8,AREA 0,5,50,1,150.5,5.44,0.14,0.05,sky130_fd_sc_hd,0,4