mirror of https://github.com/efabless/caravel.git
Merge branch 'caravel_redesign' into caravel_redesign-top-level
This commit is contained in:
marwaneltoukhy
commit
7ec1eeb010
|
|
@ -778,7 +778,7 @@ COMPONENTS 624 ;
|
|||
+ PLACED ( 204800 1744665 ) FE ;
|
||||
- sky130_fd_sc_hd__tapvpwrvgnd_1_165 sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
+ PLACED ( 202080 1744665 ) E ;
|
||||
- sky130_fd_sc_hd__buf_8_150 sky130_fd_sc_hd__buf_8
|
||||
- sky130_ef_sc_hd__decap_12_100 sky130_ef_sc_hd__decap_12
|
||||
+ PLACED ( 207520 1745125 ) E ;
|
||||
- sky130_fd_sc_hd__tapvpwrvgnd_1_162 sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
+ PLACED ( 207520 1744665 ) E ;
|
||||
|
|
@ -2122,7 +2122,7 @@ NONDEFAULTRULES 3 ;
|
|||
+ LAYER met3 WIDTH 1850 ;
|
||||
END NONDEFAULTRULES
|
||||
|
||||
NETS 265 ;
|
||||
NETS 263 ;
|
||||
- sky130_fd_sc_hd__buf_8_29/A ( sky130_fd_sc_hd__buf_8_29 A )
|
||||
( sky130_fd_sc_hd__buf_8_19 X )
|
||||
+ ROUTED met1 ( 3384835 3615175 ) mcon_170_1090
|
||||
|
|
@ -5897,8 +5897,6 @@ NETS 265 ;
|
|||
NEW met2 ( 205975 1740375 ) ( 206685 * )
|
||||
NEW met2 ( 205975 1740195 ) ( 206685 * )
|
||||
NEW met2 ( 741440 212790 ) ( 742390 * ) ;
|
||||
- sky130_fd_sc_hd__buf_8_150/X ( sky130_fd_sc_hd__buf_8_150 X ) ;
|
||||
- sky130_fd_sc_hd__buf_8_150/A ( sky130_fd_sc_hd__buf_8_150 A ) ;
|
||||
- mgmt_io_in_unbuf[19] ( sky130_fd_sc_hd__buf_8_172 A )
|
||||
+ ROUTED met1 ( 218665 3057740 ) ( * 3060710 )
|
||||
NEW met1 ( 218665 3057600 ) ( 218945 * )
|
||||
|
|
@ -6731,8 +6729,8 @@ NETS 265 ;
|
|||
( sky130_fd_sc_hd__buf_8_151 VNB )
|
||||
( sky130_fd_sc_hd__buf_8_0 VNB )
|
||||
( sky130_fd_sc_hd__tapvpwrvgnd_1_162 VGND )
|
||||
( sky130_fd_sc_hd__buf_8_150 VNB )
|
||||
( sky130_fd_sc_hd__buf_8_150 VGND )
|
||||
( sky130_ef_sc_hd__decap_12_100 VNB )
|
||||
( sky130_ef_sc_hd__decap_12_100 VGND )
|
||||
( sky130_fd_sc_hd__tapvpwrvgnd_1_165 VGND )
|
||||
( sky130_fd_sc_hd__buf_8_152 VGND )
|
||||
( sky130_fd_sc_hd__buf_8_153 VGND )
|
||||
|
|
@ -7927,8 +7925,8 @@ NETS 265 ;
|
|||
( sky130_fd_sc_hd__buf_8_151 VPB )
|
||||
( sky130_fd_sc_hd__buf_8_0 VPB )
|
||||
( sky130_fd_sc_hd__tapvpwrvgnd_1_162 VPWR )
|
||||
( sky130_fd_sc_hd__buf_8_150 VPWR )
|
||||
( sky130_fd_sc_hd__buf_8_150 VPB )
|
||||
( sky130_ef_sc_hd__decap_12_100 VPWR )
|
||||
( sky130_ef_sc_hd__decap_12_100 VPB )
|
||||
( sky130_fd_sc_hd__tapvpwrvgnd_1_165 VPWR )
|
||||
( sky130_fd_sc_hd__tapvpwrvgnd_1_164 VPWR )
|
||||
( sky130_fd_sc_hd__buf_8_153 VPWR )
|
||||
|
|
|
|||
|
|
@ -16,15 +16,21 @@ VIAS 18 ;
|
|||
+ RECT via ( -75 -75 ) ( 75 75 )
|
||||
+ RECT via ( 245 -75 ) ( 395 75 )
|
||||
+ RECT via ( 565 -75 ) ( 715 75 ) ;
|
||||
- via_260_260_hv
|
||||
+ RECT met1 ( -160 -130 ) ( 160 130 )
|
||||
+ RECT met2 ( -130 -160 ) ( 130 160 )
|
||||
+ RECT via ( -75 -75 ) ( 75 75 ) ;
|
||||
- via_260_660_vh
|
||||
+ RECT met1 ( -130 -360 ) ( 130 360 )
|
||||
+ RECT met2 ( -160 -330 ) ( 160 330 )
|
||||
+ RECT via ( -75 -235 ) ( 75 -85 )
|
||||
+ RECT via ( -75 85 ) ( 75 235 ) ;
|
||||
- via_260_260_hv
|
||||
+ RECT met1 ( -160 -130 ) ( 160 130 )
|
||||
+ RECT met2 ( -130 -160 ) ( 130 160 )
|
||||
+ RECT via ( -75 -75 ) ( 75 75 ) ;
|
||||
- via_1090_260_hv
|
||||
+ RECT met1 ( -575 -130 ) ( 575 130 )
|
||||
+ RECT met2 ( -545 -160 ) ( 545 160 )
|
||||
+ RECT via ( -395 -75 ) ( -245 75 )
|
||||
+ RECT via ( -75 -75 ) ( 75 75 )
|
||||
+ RECT via ( 245 -75 ) ( 395 75 ) ;
|
||||
- via_300_1785_hh
|
||||
+ RECT met1 ( -180 -892.5 ) ( 180 892.5 )
|
||||
+ RECT met2 ( -180 -892.5 ) ( 180 892.5 )
|
||||
|
|
@ -33,12 +39,6 @@ VIAS 18 ;
|
|||
+ RECT via ( -75 -75 ) ( 75 75 )
|
||||
+ RECT via ( -75 245 ) ( 75 395 )
|
||||
+ RECT via ( -75 565 ) ( 75 715 ) ;
|
||||
- via_1090_260_hv
|
||||
+ RECT met1 ( -575 -130 ) ( 575 130 )
|
||||
+ RECT met2 ( -545 -160 ) ( 545 160 )
|
||||
+ RECT via ( -395 -75 ) ( -245 75 )
|
||||
+ RECT via ( -75 -75 ) ( 75 75 )
|
||||
+ RECT via ( 245 -75 ) ( 395 75 ) ;
|
||||
- via_260_260_vh
|
||||
+ RECT met1 ( -130 -160 ) ( 130 160 )
|
||||
+ RECT met2 ( -160 -130 ) ( 160 130 )
|
||||
|
|
@ -60,12 +60,6 @@ VIAS 18 ;
|
|||
+ RECT mcon ( -85 -445 ) ( 85 -275 )
|
||||
+ RECT mcon ( -85 -85 ) ( 85 85 )
|
||||
+ RECT mcon ( -85 275 ) ( 85 445 ) ;
|
||||
- via_260_1090_vh
|
||||
+ RECT met1 ( -130 -575 ) ( 130 575 )
|
||||
+ RECT met2 ( -160 -545 ) ( 160 545 )
|
||||
+ RECT via ( -75 -395 ) ( 75 -245 )
|
||||
+ RECT via ( -75 -75 ) ( 75 75 )
|
||||
+ RECT via ( -75 245 ) ( 75 395 ) ;
|
||||
- via_1785_300_hh
|
||||
+ RECT met1 ( -922.5 -150 ) ( 922.5 150 )
|
||||
+ RECT met2 ( -922.5 -150 ) ( 922.5 150 )
|
||||
|
|
@ -74,6 +68,12 @@ VIAS 18 ;
|
|||
+ RECT via ( -75 -75 ) ( 75 75 )
|
||||
+ RECT via ( 245 -75 ) ( 395 75 )
|
||||
+ RECT via ( 565 -75 ) ( 715 75 ) ;
|
||||
- via_260_1090_vh
|
||||
+ RECT met1 ( -130 -575 ) ( 130 575 )
|
||||
+ RECT met2 ( -160 -545 ) ( 160 545 )
|
||||
+ RECT via ( -75 -395 ) ( 75 -245 )
|
||||
+ RECT via ( -75 -75 ) ( 75 75 )
|
||||
+ RECT via ( -75 245 ) ( 75 395 ) ;
|
||||
- mcon_1090_170
|
||||
+ RECT li1 ( -545 -85 ) ( 545 85 )
|
||||
+ RECT met1 ( -575 -115 ) ( 575 115 )
|
||||
|
|
@ -927,11 +927,6 @@ PINS 98 ;
|
|||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 665242.5 221390 ) N ;
|
||||
- mgmt_io_in_unbuf[9] + NET mgmt_io_in_unbuf[9]
|
||||
+ DIRECTION INPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 220065 3058127.5 ) N ;
|
||||
- vssd + NET vssd
|
||||
+ DIRECTION INPUT
|
||||
+ USE GROUND
|
||||
|
|
@ -952,16 +947,6 @@ PINS 98 ;
|
|||
+ USE POWER
|
||||
+ PORT
|
||||
+ LAYER met3 ( -225 -742.5 ) ( 225 742.5 ) + PLACED ( 200490 3017942.5 ) N ;
|
||||
- mgmt_io_in_unbuf[7] + NET mgmt_io_in_unbuf[7]
|
||||
+ DIRECTION INPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 217825 3062127.5 ) N ;
|
||||
- mgmt_io_in_unbuf[8] + NET mgmt_io_in_unbuf[8]
|
||||
+ DIRECTION INPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 218945 3060127.5 ) N ;
|
||||
- mgmt_io_in_unbuf[15] + NET mgmt_io_in_unbuf[15]
|
||||
+ DIRECTION INPUT
|
||||
+ USE SIGNAL
|
||||
|
|
@ -982,16 +967,6 @@ PINS 98 ;
|
|||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -735 ) ( 70 735 ) + PLACED ( 223285 1772915 ) N ;
|
||||
- mgmt_io_in_unbuf[11] + NET mgmt_io_in_unbuf[11]
|
||||
+ DIRECTION INPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 222305 3054127.5 ) N ;
|
||||
- mgmt_io_in_unbuf[10] + NET mgmt_io_in_unbuf[10]
|
||||
+ DIRECTION INPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 221185 3056127.5 ) N ;
|
||||
- mgmt_io_in_buf[4] + NET mgmt_io_in_buf[4]
|
||||
+ DIRECTION OUTPUT
|
||||
+ USE SIGNAL
|
||||
|
|
@ -1242,31 +1217,6 @@ PINS 98 ;
|
|||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -717.5 ) ( 70 717.5 ) + PLACED ( 3370290 3639887.5 ) N ;
|
||||
- mgmt_io_out_buf[7] + NET mgmt_io_out_buf[7]
|
||||
+ DIRECTION OUTPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 218385 3061127.5 ) N ;
|
||||
- mgmt_io_out_buf[8] + NET mgmt_io_out_buf[8]
|
||||
+ DIRECTION OUTPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 219505 3059127.5 ) N ;
|
||||
- mgmt_io_out_buf[9] + NET mgmt_io_out_buf[9]
|
||||
+ DIRECTION OUTPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 220625 3057127.5 ) N ;
|
||||
- mgmt_io_out_buf[10] + NET mgmt_io_out_buf[10]
|
||||
+ DIRECTION OUTPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 221745 3055127.5 ) N ;
|
||||
- mgmt_io_out_buf[11] + NET mgmt_io_out_buf[11]
|
||||
+ DIRECTION OUTPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 222865 3053127.5 ) N ;
|
||||
- mgmt_io_out_buf[12] + NET mgmt_io_out_buf[12]
|
||||
+ DIRECTION OUTPUT
|
||||
+ USE SIGNAL
|
||||
|
|
@ -1307,6 +1257,44 @@ PINS 98 ;
|
|||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -627.5 -70 ) ( 627.5 70 ) + PLACED ( 662382.5 222930 ) N ;
|
||||
- mgmt_io_out_buf[11] + NET mgmt_io_out_buf[11]
|
||||
+ DIRECTION OUTPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 222865 3053127.5 ) N ;
|
||||
- mgmt_io_out_buf[10] + NET mgmt_io_out_buf[10]
|
||||
+ DIRECTION OUTPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 221745 3055127.5 ) N ;
|
||||
- mgmt_io_in_unbuf[10] + NET mgmt_io_in_unbuf[10]
|
||||
+ DIRECTION INPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 221185 3056127.5 ) N ;
|
||||
- mgmt_io_in_unbuf[11] + NET mgmt_io_in_unbuf[11]
|
||||
+ DIRECTION INPUT
|
||||
+ USE SIGNAL
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 222305 3054127.5 ) N ;
|
||||
- mgmt_io_out_buf[9] + NET mgmt_io_out_buf[9]
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 220625 3057322.5 ) N ;
|
||||
- mgmt_io_in_unbuf[9] + NET mgmt_io_in_unbuf[9]
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 220065 3058322.5 ) N ;
|
||||
- mgmt_io_out_buf[8] + NET mgmt_io_out_buf[8]
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 219505 3059322.5 ) N ;
|
||||
- mgmt_io_in_unbuf[8] + NET mgmt_io_in_unbuf[8]
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 218945 3060322.5 ) N ;
|
||||
- mgmt_io_out_buf[7] + NET mgmt_io_out_buf[7]
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 218385 3061187.5 ) N ;
|
||||
- mgmt_io_in_unbuf[7] + NET mgmt_io_in_unbuf[7]
|
||||
+ PORT
|
||||
+ LAYER met1 ( -70 -652.5 ) ( 70 652.5 ) + PLACED ( 217825 3062187.5 ) N ;
|
||||
END PINS
|
||||
|
||||
NONDEFAULTRULES 4 ;
|
||||
|
|
@ -2787,7 +2775,7 @@ NETS 147 ;
|
|||
NEW met1 ( 203105 2997310 ) ( 203225 * )
|
||||
NEW met1 ( 203165 2997845 ) via_260_1090_vh ;
|
||||
- mgmt_io_in_unbuf[9] ( sky130_fd_sc_hd__buf_8_175 A )
|
||||
+ ROUTED met1 ( 220065 3002785 ) ( * 3058710 )
|
||||
+ ROUTED met1 ( 220065 3002785 ) ( * 3058905 )
|
||||
NEW met1 ( 219945 3002645 ) ( 220065 * )
|
||||
NEW met1 ( 220005 3002555 ) via_260_260_vh ( * 3002495 )
|
||||
( 221530 * )
|
||||
|
|
@ -2916,7 +2904,7 @@ NETS 147 ;
|
|||
NEW met2 ( 3366060 2219805 ) ( 3367490 * )
|
||||
NEW met1 ( 3367630 2219775 ) ( 3367750 * ) ;
|
||||
- mgmt_io_out_buf[9] ( sky130_fd_sc_hd__buf_8_174 X )
|
||||
+ ROUTED met1 ( 220625 3055225 ) ( * 3057710 )
|
||||
+ ROUTED met1 ( 220625 3055225 ) ( * 3057905 )
|
||||
NEW met1 ( 220345 3055085 ) ( 220625 * )
|
||||
NEW met1 ( 220345 3001815 ) ( * 3054945 )
|
||||
NEW met1 ( 220225 3001675 ) ( 220345 * )
|
||||
|
|
@ -3113,9 +3101,9 @@ NETS 147 ;
|
|||
NEW met1 ( 203105 3003290 ) ( 203225 * )
|
||||
NEW met1 ( 203165 3003825 ) via_260_1090_vh ;
|
||||
- mgmt_io_out_buf[8] ( sky130_fd_sc_hd__buf_8_173 X )
|
||||
+ ROUTED met1 ( 219505 3057280 ) ( * 3059710 )
|
||||
NEW met1 ( 219225 3057140 ) ( 219505 * )
|
||||
NEW met1 ( 219225 3007795 ) ( * 3057000 )
|
||||
+ ROUTED met1 ( 219505 3057440 ) ( * 3059905 )
|
||||
NEW met1 ( 219225 3057300 ) ( 219505 * )
|
||||
NEW met1 ( 219225 3007795 ) ( * 3057160 )
|
||||
NEW met1 ( 219105 3007655 ) ( 219225 * )
|
||||
NEW met1 ( 219165 3007565 ) via_260_260_vh ( * 3007505 )
|
||||
( 221530 * )
|
||||
|
|
@ -3237,7 +3225,7 @@ NETS 147 ;
|
|||
NEW met1 ( 2168770 212875 ) via_260_850_vh
|
||||
NEW met1 ( 2168775 212875 ) mcon_170_850 ;
|
||||
- mgmt_io_in_unbuf[8] ( sky130_fd_sc_hd__buf_8_172 A )
|
||||
+ ROUTED met1 ( 218945 3008765 ) ( * 3060710 )
|
||||
+ ROUTED met1 ( 218945 3008765 ) ( * 3060905 )
|
||||
NEW met1 ( 218825 3008625 ) ( 218945 * )
|
||||
NEW met1 ( 218885 3008535 ) via_260_260_vh ( * 3008475 )
|
||||
( 221530 * )
|
||||
|
|
@ -3356,7 +3344,7 @@ NETS 147 ;
|
|||
NEW li1 ( 2169725 215935 ) mcon_1090_170
|
||||
NEW met2 ( 2169250 215850 ) ( 2170200 * ) ;
|
||||
- mgmt_io_in_unbuf[7] ( sky130_fd_sc_hd__buf_8_171 A )
|
||||
+ ROUTED met1 ( 217825 3014745 ) ( * 3062710 )
|
||||
+ ROUTED met1 ( 217825 3014745 ) ( * 3062770 )
|
||||
NEW met1 ( 217705 3014605 ) ( 217825 * )
|
||||
NEW met1 ( 217765 3014515 ) via_260_260_vh ( * 3014455 )
|
||||
( 221530 * )
|
||||
|
|
@ -3429,7 +3417,7 @@ NETS 147 ;
|
|||
NEW li1 ( 2163745 215935 ) mcon_1090_170
|
||||
NEW met2 ( 2163270 215850 ) ( 2164220 * ) ;
|
||||
- mgmt_io_out_buf[7] ( sky130_fd_sc_hd__buf_8_170 X )
|
||||
+ ROUTED met1 ( 218385 3059305 ) ( * 3061710 )
|
||||
+ ROUTED met1 ( 218385 3059305 ) ( * 3061770 )
|
||||
NEW met1 ( 218105 3059165 ) ( 218385 * )
|
||||
NEW met1 ( 218105 3013775 ) ( * 3059025 )
|
||||
NEW met1 ( 217985 3013635 ) ( 218105 * )
|
||||
|
|
|
|||
Binary file not shown.
Binary file not shown.
|
|
@ -231,30 +231,6 @@ MACRO gpio_signal_buffering_alt
|
|||
RECT 3364.340 1184.250 3364.480 1185.685 ;
|
||||
END
|
||||
END mgmt_io_in_buf[0]
|
||||
PIN mgmt_io_out_buf[7]
|
||||
DIRECTION OUTPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 218.315 3060.475 218.455 3061.780 ;
|
||||
END
|
||||
END mgmt_io_out_buf[7]
|
||||
PIN mgmt_io_out_buf[8]
|
||||
DIRECTION OUTPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 219.435 3058.475 219.575 3059.780 ;
|
||||
END
|
||||
END mgmt_io_out_buf[8]
|
||||
PIN mgmt_io_out_buf[9]
|
||||
DIRECTION OUTPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 220.555 3056.475 220.695 3057.780 ;
|
||||
END
|
||||
END mgmt_io_out_buf[9]
|
||||
PIN mgmt_io_out_buf[10]
|
||||
DIRECTION OUTPUT ;
|
||||
USE SIGNAL ;
|
||||
|
|
@ -287,30 +263,6 @@ MACRO gpio_signal_buffering_alt
|
|||
RECT 221.115 3055.475 221.255 3056.780 ;
|
||||
END
|
||||
END mgmt_io_in_unbuf[10]
|
||||
PIN mgmt_io_in_unbuf[9]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 219.995 3057.475 220.135 3058.780 ;
|
||||
END
|
||||
END mgmt_io_in_unbuf[9]
|
||||
PIN mgmt_io_in_unbuf[8]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 218.875 3059.475 219.015 3060.780 ;
|
||||
END
|
||||
END mgmt_io_in_unbuf[8]
|
||||
PIN mgmt_io_in_unbuf[7]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 217.755 3061.475 217.895 3062.780 ;
|
||||
END
|
||||
END mgmt_io_in_unbuf[7]
|
||||
PIN mgmt_io_out_buf[12]
|
||||
DIRECTION OUTPUT ;
|
||||
USE SIGNAL ;
|
||||
|
|
@ -751,6 +703,42 @@ MACRO gpio_signal_buffering_alt
|
|||
RECT 200.265 3017.200 200.715 3018.685 ;
|
||||
END
|
||||
END vccd
|
||||
PIN mgmt_io_out_buf[9]
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 220.555 3056.670 220.695 3057.975 ;
|
||||
END
|
||||
END mgmt_io_out_buf[9]
|
||||
PIN mgmt_io_in_unbuf[9]
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 219.995 3057.670 220.135 3058.975 ;
|
||||
END
|
||||
END mgmt_io_in_unbuf[9]
|
||||
PIN mgmt_io_out_buf[8]
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 219.435 3058.670 219.575 3059.975 ;
|
||||
END
|
||||
END mgmt_io_out_buf[8]
|
||||
PIN mgmt_io_in_unbuf[8]
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 218.875 3059.670 219.015 3060.975 ;
|
||||
END
|
||||
END mgmt_io_in_unbuf[8]
|
||||
PIN mgmt_io_out_buf[7]
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 218.315 3060.535 218.455 3061.840 ;
|
||||
END
|
||||
END mgmt_io_out_buf[7]
|
||||
PIN mgmt_io_in_unbuf[7]
|
||||
PORT
|
||||
LAYER met1 ;
|
||||
RECT 217.755 3061.535 217.895 3062.840 ;
|
||||
END
|
||||
END mgmt_io_in_unbuf[7]
|
||||
OBS
|
||||
LAYER nwell ;
|
||||
RECT 3377.675 3601.870 3379.280 3608.690 ;
|
||||
|
|
@ -12146,8 +12134,8 @@ MACRO gpio_signal_buffering_alt
|
|||
RECT 205.735 2986.200 206.705 2986.460 ;
|
||||
RECT 207.170 2984.730 207.650 3024.940 ;
|
||||
RECT 209.890 2984.730 210.370 3019.030 ;
|
||||
RECT 217.755 3014.675 217.895 3061.475 ;
|
||||
RECT 218.315 3059.235 218.455 3060.475 ;
|
||||
RECT 217.755 3014.675 217.895 3061.535 ;
|
||||
RECT 218.315 3059.235 218.455 3060.535 ;
|
||||
RECT 217.635 3014.355 217.895 3014.675 ;
|
||||
RECT 218.035 3059.095 218.455 3059.235 ;
|
||||
RECT 218.035 3013.705 218.175 3059.095 ;
|
||||
|
|
@ -12197,11 +12185,11 @@ MACRO gpio_signal_buffering_alt
|
|||
RECT 217.495 1726.450 217.755 1726.770 ;
|
||||
RECT 217.895 3009.520 218.155 3009.840 ;
|
||||
RECT 217.895 1725.800 218.035 3009.520 ;
|
||||
RECT 218.875 3008.695 219.015 3059.475 ;
|
||||
RECT 219.435 3057.210 219.575 3058.475 ;
|
||||
RECT 218.875 3008.695 219.015 3059.670 ;
|
||||
RECT 219.435 3057.370 219.575 3058.670 ;
|
||||
RECT 218.755 3008.375 219.015 3008.695 ;
|
||||
RECT 219.155 3057.070 219.575 3057.210 ;
|
||||
RECT 219.155 3007.725 219.295 3057.070 ;
|
||||
RECT 219.155 3057.230 219.575 3057.370 ;
|
||||
RECT 219.155 3007.725 219.295 3057.230 ;
|
||||
RECT 219.035 3007.405 219.295 3007.725 ;
|
||||
RECT 217.775 1725.480 218.035 1725.800 ;
|
||||
RECT 218.735 3004.160 218.995 3004.480 ;
|
||||
|
|
@ -12213,8 +12201,8 @@ MACRO gpio_signal_buffering_alt
|
|||
RECT 218.615 1720.470 218.875 1720.790 ;
|
||||
RECT 219.015 3003.540 219.275 3003.860 ;
|
||||
RECT 219.015 1719.820 219.155 3003.540 ;
|
||||
RECT 219.995 3002.715 220.135 3057.475 ;
|
||||
RECT 220.555 3055.155 220.695 3056.475 ;
|
||||
RECT 219.995 3002.715 220.135 3057.670 ;
|
||||
RECT 220.555 3055.155 220.695 3056.670 ;
|
||||
RECT 219.875 3002.395 220.135 3002.715 ;
|
||||
RECT 220.275 3055.015 220.695 3055.155 ;
|
||||
RECT 220.275 3001.745 220.415 3055.015 ;
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1665943375
|
||||
timestamp 1665957051
|
||||
<< locali >>
|
||||
rect 416588 996667 416806 996673
|
||||
rect 661989 996585 662207 996591
|
||||
|
|
@ -7576,6 +7576,10 @@ use sky130_ef_sc_hd__decap_12 sky130_ef_sc_hd__decap_12_99
|
|||
timestamp 1663859327
|
||||
transform 0 -1 676117 -1 0 441604
|
||||
box -38 -48 1142 592
|
||||
use sky130_ef_sc_hd__decap_12 sky130_ef_sc_hd__decap_12_100
|
||||
timestamp 1663859327
|
||||
transform 0 1 41504 -1 0 350129
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__buf_8 sky130_fd_sc_hd__buf_8_0 $PDKPATH/libs.ref/sky130_fd_sc_hd/mag
|
||||
timestamp 1663859327
|
||||
transform 0 -1 41504 -1 0 351325
|
||||
|
|
@ -8172,10 +8176,6 @@ use sky130_fd_sc_hd__buf_8 sky130_fd_sc_hd__buf_8_149
|
|||
timestamp 1663859327
|
||||
transform 0 -1 41504 -1 0 345345
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__buf_8 sky130_fd_sc_hd__buf_8_150
|
||||
timestamp 1663859327
|
||||
transform 0 1 41504 -1 0 350129
|
||||
box -38 -48 1142 592
|
||||
use sky130_fd_sc_hd__buf_8 sky130_fd_sc_hd__buf_8_151
|
||||
timestamp 1663859327
|
||||
transform 0 1 40416 1 0 350221
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1665943807
|
||||
timestamp 1665967863
|
||||
<< locali >>
|
||||
rect 676332 721460 676338 721678
|
||||
rect 41261 602778 41267 602996
|
||||
|
|
@ -311,8 +311,8 @@ rect 41978 603414 42000 603771
|
|||
rect 42060 603414 42074 603771
|
||||
rect 41219 602996 41271 603008
|
||||
rect 41978 603006 42074 603414
|
||||
rect 43551 602935 43579 612556
|
||||
rect 43663 611847 43691 612356
|
||||
rect 43551 602935 43579 612568
|
||||
rect 43663 611847 43691 612368
|
||||
rect 43527 602929 43579 602935
|
||||
rect 43527 602871 43579 602877
|
||||
rect 43607 611819 43691 611847
|
||||
|
|
@ -384,12 +384,12 @@ rect 43579 601962 43631 601968
|
|||
rect 43579 601904 43631 601910
|
||||
rect 41241 345185 41293 345197
|
||||
rect 43579 345160 43607 601904
|
||||
rect 43775 601739 43803 612156
|
||||
rect 43887 611442 43915 611956
|
||||
rect 43775 601739 43803 612195
|
||||
rect 43887 611474 43915 611995
|
||||
rect 43751 601733 43803 601739
|
||||
rect 43751 601675 43803 601681
|
||||
rect 43831 611414 43915 611442
|
||||
rect 43831 601545 43859 611414
|
||||
rect 43831 611446 43915 611474
|
||||
rect 43831 601545 43859 611446
|
||||
rect 43807 601539 43859 601545
|
||||
rect 43807 601481 43859 601487
|
||||
rect 43555 345154 43607 345160
|
||||
|
|
@ -480,8 +480,8 @@ rect 43723 344094 43775 344100
|
|||
rect 43803 600766 43855 600772
|
||||
rect 43803 600708 43855 600714
|
||||
rect 43803 343964 43831 600708
|
||||
rect 43999 600543 44027 611756
|
||||
rect 44111 611031 44139 611556
|
||||
rect 43999 600543 44027 611795
|
||||
rect 44111 611031 44139 611595
|
||||
rect 43975 600537 44027 600543
|
||||
rect 43975 600479 44027 600485
|
||||
rect 44055 611003 44139 611031
|
||||
|
|
@ -5363,8 +5363,6 @@ flabel metal1 132723 44376 132974 44404 0 FreeSans 288 0 0 0 mgmt_io_oeb_buf[0]
|
|||
port 91 nsew signal output
|
||||
flabel metal1 132923 44264 133174 44292 0 FreeSans 288 0 0 0 mgmt_io_oeb_buf[1]
|
||||
port 92 nsew signal output
|
||||
flabel metal1 43999 611495 44027 611756 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[9]
|
||||
port 70 nsew signal input
|
||||
flabel metal3 40074 346985 40164 347282 0 FreeSans 400 90 0 0 vssd
|
||||
port 135 nsew ground input
|
||||
flabel metal3 40076 345792 40166 346089 0 FreeSans 400 90 0 0 vccd
|
||||
|
|
@ -5373,10 +5371,6 @@ flabel metal3 40053 604641 40143 604938 0 FreeSans 400 90 0 0 vssd
|
|||
port 135 nsew ground input
|
||||
flabel metal3 40053 603440 40143 603737 0 FreeSans 400 90 0 0 vccd
|
||||
port 136 nsew power input
|
||||
flabel metal1 43551 612295 43579 612556 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[7]
|
||||
port 72 nsew signal input
|
||||
flabel metal1 43775 611895 43803 612156 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[8]
|
||||
port 71 nsew signal input
|
||||
flabel metal1 45315 353236 45343 353530 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[15]
|
||||
port 78 nsew signal input
|
||||
flabel metal1 45091 353636 45119 353930 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[14]
|
||||
|
|
@ -5385,10 +5379,6 @@ flabel metal1 44867 354036 44895 354330 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[1
|
|||
port 80 nsew signal input
|
||||
flabel metal1 44643 354436 44671 354730 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[12]
|
||||
port 81 nsew signal input
|
||||
flabel metal1 44447 610695 44475 610956 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[11]
|
||||
port 68 nsew signal input
|
||||
flabel metal1 44223 611095 44251 611356 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[10]
|
||||
port 69 nsew signal input
|
||||
flabel metal1 673764 235250 673792 235537 0 FreeSans 288 90 0 0 mgmt_io_in_buf[4]
|
||||
port 44 nsew signal output
|
||||
flabel metal1 674212 234450 674240 234737 0 FreeSans 288 90 0 0 mgmt_io_in_buf[6]
|
||||
|
|
@ -5489,16 +5479,6 @@ flabel metal1 673848 455768 673876 456055 0 FreeSans 288 90 0 0 mgmt_io_out_buf[
|
|||
port 24 nsew signal output
|
||||
flabel metal1 674044 727834 674072 728121 0 FreeSans 288 90 0 0 mgmt_io_out_buf[6]
|
||||
port 12 nsew signal output
|
||||
flabel metal1 43663 612095 43691 612356 0 FreeSans 288 90 0 0 mgmt_io_out_buf[7]
|
||||
port 63 nsew signal output
|
||||
flabel metal1 43887 611695 43915 611956 0 FreeSans 288 90 0 0 mgmt_io_out_buf[8]
|
||||
port 64 nsew signal output
|
||||
flabel metal1 44111 611295 44139 611556 0 FreeSans 288 90 0 0 mgmt_io_out_buf[9]
|
||||
port 65 nsew signal output
|
||||
flabel metal1 44335 610895 44363 611156 0 FreeSans 288 90 0 0 mgmt_io_out_buf[10]
|
||||
port 66 nsew signal output
|
||||
flabel metal1 44559 610495 44587 610756 0 FreeSans 288 90 0 0 mgmt_io_out_buf[11]
|
||||
port 67 nsew signal output
|
||||
flabel metal1 44755 354236 44783 354530 0 FreeSans 288 90 0 0 mgmt_io_out_buf[12]
|
||||
port 74 nsew signal output
|
||||
flabel metal1 44979 353836 45007 354130 0 FreeSans 288 90 0 0 mgmt_io_out_buf[13]
|
||||
|
|
@ -5515,6 +5495,26 @@ flabel metal1 131951 44740 132202 44768 0 FreeSans 288 0 0 0 mgmt_io_out_buf[18]
|
|||
port 85 nsew signal output
|
||||
flabel metal1 132351 44572 132602 44600 0 FreeSans 288 0 0 0 mgmt_io_out_buf[19]
|
||||
port 86 nsew signal output
|
||||
flabel metal1 44559 610495 44587 610756 0 FreeSans 288 90 0 0 mgmt_io_out_buf[11]
|
||||
port 67 nsew signal output
|
||||
flabel metal1 44335 610895 44363 611156 0 FreeSans 288 90 0 0 mgmt_io_out_buf[10]
|
||||
port 66 nsew signal output
|
||||
flabel metal1 44223 611095 44251 611356 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[10]
|
||||
port 69 nsew signal input
|
||||
flabel metal1 44447 610695 44475 610956 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[11]
|
||||
port 68 nsew signal input
|
||||
flabel metal1 44111 611334 44139 611595 0 FreeSans 288 90 0 0 mgmt_io_out_buf[9]
|
||||
port 137 nsew
|
||||
flabel metal1 43999 611534 44027 611795 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[9]
|
||||
port 138 nsew
|
||||
flabel metal1 43887 611734 43915 611995 0 FreeSans 288 90 0 0 mgmt_io_out_buf[8]
|
||||
port 140 nsew
|
||||
flabel metal1 43775 611934 43803 612195 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[8]
|
||||
port 141 nsew
|
||||
flabel metal1 43663 612107 43691 612368 0 FreeSans 288 90 0 0 mgmt_io_out_buf[7]
|
||||
port 142 nsew
|
||||
flabel metal1 43551 612307 43579 612568 0 FreeSans 288 90 0 0 mgmt_io_in_unbuf[7]
|
||||
port 143 nsew
|
||||
<< properties >>
|
||||
string FIXED_BBOX 0 0 717600 1037600
|
||||
<< end >>
|
||||
|
|
|
|||
2
manifest
2
manifest
|
|
@ -26,7 +26,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
|||
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
|
||||
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
||||
095aba3128be2f6f776ddf66596249c85471cd75 verilog/rtl/gpio_signal_buffering.v
|
||||
c710b0f81476b05e26edbf7d62c1b4b30486d9ff verilog/rtl/gpio_signal_buffering_alt.v
|
||||
1a7e1e050b963054f5b62784249f713c90eaaaf0 verilog/rtl/gpio_signal_buffering_alt.v
|
||||
4290fcaf6bbcff701c2c47c7a23ce4fd4698e888 verilog/rtl/housekeeping.v
|
||||
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
|
||||
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
|
||||
|
|
|
|||
|
|
@ -230,6 +230,9 @@ if {\
|
|||
|
||||
}
|
||||
proc report_results {design rc_corner proc_corner} {
|
||||
report_global_timing -separate_all_groups -significant_digits 4 > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-global.rpt
|
||||
report_analysis_coverage -significant_digits 4 -nosplit -status_details {untested} > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-coverage.rpt
|
||||
|
||||
report_constraint -all_violators -significant_digits 4 -nosplit > $::env(OUT_DIR)/reports/${rc_corner}/${design}.${proc_corner}${proc_corner}-all_viol.rpt
|
||||
|
||||
report_timing -delay min -path_type full_clock_expanded -transition_time -capacitance -nets -nosplit \
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@ def run_sta(caravel_root, mcw_root, pt_lib_root, log_dir, signoff_dir, design):
|
|||
"-d",
|
||||
f"{design}",
|
||||
"-o",
|
||||
f"{signoff_dir}/{design}/standalone_pvr",
|
||||
f"{signoff_dir}/{design}",
|
||||
"-l",
|
||||
f"{log_dir}",
|
||||
]
|
||||
|
|
|
|||
|
|
@ -42,7 +42,7 @@ from tests.timer.timer import *
|
|||
from tests.uart.uart import *
|
||||
from tests.spi_master.spi_master import *
|
||||
from tests.logicAnalyzer.la import *
|
||||
|
||||
from tests.debug.debug import *
|
||||
|
||||
|
||||
# archive tests
|
||||
|
|
|
|||
|
|
@ -2,273 +2,12 @@
|
|||
"Tests": {
|
||||
"_comment0" :"level is priorty of the test low is better, SW spcify if the test uses SW, RTL regressions run this test in RTL ",
|
||||
"_comment1" :"GL regressions run this test in gatelevel, GL_SDF regression run this test with SDF included"
|
||||
|
||||
,"bitbang_no_cpu_all_o" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"test disable CPU and control the wishbone to configure gpio[4:37] as mgmt output using bitbang and check them"}
|
||||
,"bitbang_cpu_all_o" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt output using bitbang and check them"}
|
||||
,"gpio_all_o" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt output using automatic approach firmware and check them"}
|
||||
,"gpio_all_o_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user output using automatic approach firmware and check them"}
|
||||
,"gpio_all_i" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt input using automatic approach firmware and check them"}
|
||||
,"gpio_all_i_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user input using automatic approach firmware and check them"}
|
||||
,"gpio_all_i_pu" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them"}
|
||||
,"gpio_all_i_pu_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user input pull up using automatic approach firmware and check them"}
|
||||
,"gpio_all_i_pd" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them"}
|
||||
,"gpio_all_i_pd_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user input pull down using automatic approach firmware and check them"}
|
||||
,"gpio_all_bidir_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user bidir using automatic approach firmware and check them"}
|
||||
,"bitbang_cpu_all_10" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 10"}
|
||||
,"bitbang_cpu_all_01" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 01"}
|
||||
,"bitbang_cpu_all_1100" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 1100"}
|
||||
,"bitbang_cpu_all_0011" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 0011"}
|
||||
,"bitbang_no_cpu_all_i" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"test disable CPU and control the wishbone to configure gpio[0:31] as mgmt input using bitbang and check them"}
|
||||
,"bitbang_cpu_all_i" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":" configure gpio[0:37] as mgmt input using bitbang and check them"}
|
||||
|
||||
,"bitbang_spi_o" :{"level":0,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"SW":true,
|
||||
"description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"}
|
||||
|
||||
,"bitbang_spi_i" :{"level":0,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"SW":true,
|
||||
"description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"}
|
||||
,"hk_regs_wr_wb_cpu" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"bit bash test for housekeeping registers"}
|
||||
,"hk_regs_wr_wb" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"write then read (the written value) from random housekeeping registers through the firmware but without using CPU, the SPI and system regs can't be read using firmware so the test only GPIO regs inside housekeeping "}
|
||||
,"hk_regs_wr_spi" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"write then read(the written value) from random housekeeping registers through the SPI housekeeping"}
|
||||
,"hk_regs_rst_spi" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check reset value of house keeping registers by reading them trough the spi housekeeping"}
|
||||
,"helloWorld" :{"level":3,
|
||||
"SW":false,
|
||||
"RTL":[],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"hello world test"}
|
||||
|
||||
,"cpu_stress" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"stress the cpu with heavy processing"}
|
||||
,"mem_dff2" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"Memory stress for all space of dff2"}
|
||||
,"mem_dff" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"Memory stress for all space of dff"}
|
||||
,"IRQ_external" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test external interrupt by mprj 7"}
|
||||
,"IRQ_timer" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test timer0 interrupt"}
|
||||
,"IRQ_uart" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test timer0 interrupt"}
|
||||
,"mgmt_gpio_out" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"tests blinking of mgmt gpio bit as an output"}
|
||||
,"mgmt_gpio_in" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"tests blinking of mgmt gpio bit as an output"}
|
||||
,"mgmt_gpio_bidir" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"send random number of blinks through mgmt_gpio and expect to recieve the same number back "}
|
||||
,"timer0_oneshot" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check timer0 oneshot mode"}
|
||||
,"timer0_periodic" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check timer0 periodic mode"}
|
||||
,"uart_tx" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test uart transmit"}
|
||||
,"uart_rx" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test uart reception"}
|
||||
,"uart_loopback" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test uart in loopback mode input and output is shorted"}
|
||||
,"spi_master_rd" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"using SPI master for reading from external memory"}
|
||||
|
||||
,"spi_master_temp" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"To be deleted"}
|
||||
|
||||
,"user_pass_thru_rd" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"use the housekeeping spi in user pass thru mode to read from external mem"}
|
||||
|
||||
|
||||
,"pll" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"Check pll diffrent configuration"}
|
||||
|
||||
,"clock_redirect" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check clock redirect is working as expected"}
|
||||
|
||||
,"hk_disable" :{"level":0,
|
||||
"SW":true,
|
||||
|
|
@ -276,6 +15,197 @@
|
|||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check Housekeeping SPI disable register is working"}
|
||||
,"uart_rx" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test uart reception"}
|
||||
,"hk_regs_rst_spi" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check reset value of house keeping registers by reading them trough the spi housekeeping"}
|
||||
|
||||
,"gpio_all_i_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user input using automatic approach firmware and check them"}
|
||||
|
||||
,"gpio_all_i_pu" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them"}
|
||||
|
||||
,"gpio_all_i_pu_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user input pull up using automatic approach firmware and check them"}
|
||||
|
||||
,"gpio_all_i_pd" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them"}
|
||||
|
||||
,"gpio_all_i_pd_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user input pull down using automatic approach firmware and check them"}
|
||||
|
||||
,"gpio_all_bidir_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user bidir using automatic approach firmware and check them"}
|
||||
|
||||
,"gpio_all_o" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt output using automatic approach firmware and check them"}
|
||||
|
||||
,"gpio_all_o_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user output using automatic approach firmware and check them"}
|
||||
,"hk_regs_wr_wb_cpu" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"bit bash test for housekeeping registers"}
|
||||
,"IRQ_timer" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test timer0 interrupt"}
|
||||
|
||||
,"bitbang_cpu_all_i" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":" configure gpio[0:37] as mgmt input using bitbang and check them"}
|
||||
|
||||
,"bitbang_spi_o" :{"level":0,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"SW":true,
|
||||
"description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"}
|
||||
|
||||
,"mgmt_gpio_out" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"tests blinking of mgmt gpio bit as an output"}
|
||||
|
||||
,"bitbang_spi_i" :{"level":0,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"SW":true,
|
||||
"description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"}
|
||||
,"hk_regs_wr_spi" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"write then read(the written value) from random housekeeping registers through the SPI housekeeping"}
|
||||
|
||||
,"IRQ_external" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test external interrupt by mprj 7"}
|
||||
|
||||
,"IRQ_uart" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test timer0 interrupt"}
|
||||
|
||||
,"mgmt_gpio_in" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"tests blinking of mgmt gpio bit as an output"}
|
||||
|
||||
,"timer0_oneshot" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check timer0 oneshot mode"}
|
||||
|
||||
,"uart_loopback" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test uart in loopback mode input and output is shorted"}
|
||||
|
||||
,"timer0_periodic" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check timer0 periodic mode"}
|
||||
|
||||
,"uart_tx" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test uart transmit"}
|
||||
|
||||
,"spi_master_rd" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"using SPI master for reading from external memory"}
|
||||
|
||||
,"user_pass_thru_rd" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"use the housekeeping spi in user pass thru mode to read from external mem"}
|
||||
|
||||
,"clock_redirect" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check clock redirect is working as expected"}
|
||||
|
||||
,"mgmt_gpio_bidir" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"send random number of blinks through mgmt_gpio and expect to recieve the same number back "}
|
||||
|
||||
,"la" :{"level":0,
|
||||
"SW":true,
|
||||
|
|
@ -283,5 +213,104 @@
|
|||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check logic analyzer input and output enable"}
|
||||
|
||||
,"pll" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"Check pll diffrent configuration"}
|
||||
|
||||
,"spi_master_temp" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"To be deleted"}
|
||||
|
||||
,"bitbang_cpu_all_o" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","gpio_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt output using bitbang and check them"}
|
||||
|
||||
,"mem_dff" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"Memory stress for all space of dff"}
|
||||
|
||||
,"bitbang_cpu_all_01" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 01"}
|
||||
|
||||
,"mem_dff2" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"Memory stress for all space of dff2"}
|
||||
|
||||
,"bitbang_cpu_all_10" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 10"}
|
||||
|
||||
,"bitbang_cpu_all_1100" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 1100"}
|
||||
|
||||
,"bitbang_cpu_all_0011" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 0011"}
|
||||
,"cpu_stress" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"stress the cpu with heavy processing"}
|
||||
,"bitbang_no_cpu_all_o" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","gpio_rtl","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"test disable CPU and control the wishbone to configure gpio[4:37] as mgmt output using bitbang and check them"}
|
||||
,"bitbang_no_cpu_all_i" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"test disable CPU and control the wishbone to configure gpio[0:31] as mgmt input using bitbang and check them"}
|
||||
,"hk_regs_wr_wb" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"write then read (the written value) from random housekeeping registers through the firmware but without using CPU, the SPI and system regs can't be read using firmware so the test only GPIO regs inside housekeeping "}
|
||||
,"helloWorld" :{"level":3,
|
||||
"SW":false,
|
||||
"RTL":[],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"hello world test"}
|
||||
,"debug" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":[],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":""}
|
||||
}
|
||||
}
|
||||
|
|
@ -80,6 +80,7 @@ async def bitbang_no_cpu_all_o(dut):
|
|||
await clock_in_right_o_left_i_standard(cpu,0) # 1 and 36
|
||||
await clock_in_end_output(cpu) # 0 and 37 and load
|
||||
|
||||
await caravelEnv.release_csb()
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
|
||||
|
|
|
|||
|
|
@ -57,7 +57,7 @@ async def bitbang_cpu_all_o(dut):
|
|||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_10(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=2863378)
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=1581680)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
|
@ -68,11 +68,17 @@ async def bitbang_cpu_all_10(dut):
|
|||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = True # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift(uut._id(gpio,False),type)
|
||||
if not Macros['GL']:
|
||||
shift(uut._id(gpio,False),type)
|
||||
else:
|
||||
shift(uut._id(f'\\{gpio} ',False),type)
|
||||
type = not type
|
||||
type = True # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift(uut._id(gpio,False),type)
|
||||
if not Macros['GL']:
|
||||
shift(uut._id(gpio,False),type)
|
||||
else:
|
||||
shift(uut._id(f'\\{gpio} ',False),type)
|
||||
type = not type
|
||||
|
||||
|
||||
|
|
@ -82,9 +88,14 @@ def shift(gpio,shift_type):
|
|||
else:
|
||||
bits = "1010101010101"
|
||||
fail = False
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
|
||||
if not Macros['GL']:
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
|
||||
for i in range(13):
|
||||
if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
|
||||
if not Macros['GL']:
|
||||
shift_register = gpio._id(f"shift_register",False).value.binstr[i]
|
||||
else:
|
||||
shift_register = gpio._id(f"\\shift_register[{i}] ",False).value.binstr
|
||||
if shift_register != bits[i]:
|
||||
fail = True
|
||||
cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
|
||||
if not fail:
|
||||
|
|
@ -104,11 +115,17 @@ async def bitbang_cpu_all_01(dut):
|
|||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = False # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift(uut._id(gpio,False),type)
|
||||
if not Macros['GL']:
|
||||
shift(uut._id(gpio,False),type)
|
||||
else:
|
||||
shift(uut._id(f'\\{gpio} ',False),type)
|
||||
type = not type
|
||||
type = False # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift(uut._id(gpio,False),type)
|
||||
if not Macros['GL']:
|
||||
shift(uut._id(gpio,False),type)
|
||||
else:
|
||||
shift(uut._id(f'\\{gpio} ',False),type)
|
||||
type = not type
|
||||
|
||||
@cocotb.test()
|
||||
|
|
@ -123,13 +140,19 @@ async def bitbang_cpu_all_0011(dut):
|
|||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = 0 # type of shifting 01 or 10
|
||||
type = 2 # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
if not Macros['GL']:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
else:
|
||||
shift_2(uut._id(f'\\{gpio} ',False),type)
|
||||
type = (type + 1) %4
|
||||
type = 0 # type of shifting 01 or 10
|
||||
type = 2 # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
if not Macros['GL']:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
else:
|
||||
shift_2(uut._id(f'\\{gpio} ',False),type)
|
||||
type = (type + 1) %4
|
||||
|
||||
@cocotb.test()
|
||||
|
|
@ -144,28 +167,44 @@ async def bitbang_cpu_all_1100(dut):
|
|||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = 2 # type of shifting 01 or 10
|
||||
type = 0 # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
if not Macros['GL']:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
else:
|
||||
shift_2(uut._id(f'\\{gpio} ',False),type)
|
||||
type = (type + 1) %4
|
||||
type = 2 # type of shifting 01 or 10
|
||||
type = 0 # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
if not Macros['GL']:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
else:
|
||||
shift_2(uut._id(f'\\{gpio} ',False),type)
|
||||
type = (type + 1) %4
|
||||
|
||||
def shift_2(gpio,shift_type):
|
||||
if shift_type == 0:
|
||||
bits = "1001100110011"
|
||||
elif shift_type == 1:
|
||||
bits = "1100110011001"
|
||||
elif shift_type == 2:
|
||||
bits = "0110011001100"
|
||||
elif shift_type == 3:
|
||||
bits = "0011001100110"
|
||||
elif shift_type == 1:
|
||||
bits = "0110011001100"
|
||||
elif shift_type == 2:
|
||||
bits = "1100110011001"
|
||||
elif shift_type == 3:
|
||||
bits = "1001100110011"
|
||||
fail = False
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
|
||||
if not Macros['GL']:
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value.binstr[::-1]} expected {bits}")
|
||||
else :
|
||||
shift_reg =''
|
||||
for i in range(13):
|
||||
shift_reg += gpio._id(f"\\shift_register[{i}] ",False).value.binstr
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} shift {shift_reg} expected {bits}")
|
||||
for i in range(13):
|
||||
if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
|
||||
if not Macros['GL']:
|
||||
shift_register = gpio._id(f"shift_register",False).value.binstr[12-i]
|
||||
else:
|
||||
shift_register = gpio._id(f"\\shift_register[{i}] ",False).value.binstr
|
||||
if shift_register != bits[i]:
|
||||
fail = True
|
||||
cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
|
||||
if not fail:
|
||||
|
|
|
|||
|
|
@ -0,0 +1,72 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
void main()
|
||||
{
|
||||
int j;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
|
||||
// Set clock to 64 kbaud and enable the UART. It is important to do this
|
||||
// before applying the configuration, or else the Tx line initializes as
|
||||
// zero, which indicates the start of a byte to the receiver.
|
||||
|
||||
|
||||
// Now, apply the configuration
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
// reg_uart_enable = 1;
|
||||
// start of the test
|
||||
reg_debug_1 = 0xAA;
|
||||
// very long wait
|
||||
for (j = 0; j < 160; j++);
|
||||
for (j = 0; j < 160; j++);
|
||||
for (j = 0; j < 160; j++);
|
||||
|
||||
|
||||
// Set clock to 64 kbaud and enable the UART. It is important to do this
|
||||
// before applying the configuration, or else the Tx line initializes as
|
||||
// zero, which indicates the start of a byte to the receiver.
|
||||
|
||||
// // these instruction work without using interrupt, they seem to be timing dependent
|
||||
// reg_uart_enable = 1;
|
||||
// reg_debug_irq_en = 1;
|
||||
// reg_reset = 1;
|
||||
|
||||
|
||||
// irq_setmask(0);
|
||||
// irq_setie(1);
|
||||
// irq_setmask(irq_getmask() | (1 << USER_IRQ_3_INTERRUPT));
|
||||
|
||||
// for (j = 0; j < 500; j++);
|
||||
|
||||
// // reg_uart_data = 0xab;
|
||||
|
||||
// // Allow transmission to complete before signalling that the program
|
||||
// // has ended.
|
||||
// for (j = 0; j < 160; j++);
|
||||
}
|
||||
|
|
@ -0,0 +1,114 @@
|
|||
from curses import baudrate
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer,Edge
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from interfaces.caravel import GPIO_MODE
|
||||
from interfaces.common import Macros
|
||||
|
||||
|
||||
bit_time_ns = 0
|
||||
reg = Regs()
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def debug(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=375862)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
# calculate bit time
|
||||
clk = clock.period/1000
|
||||
global bit_time_ns
|
||||
bit_time_ns = round(10**5 * clk / (96))
|
||||
cocotb.log.info(f"[TEST] bit time in nano second = {bit_time_ns}")
|
||||
caravelEnv.drive_gpio_in((0,0),0) # IO[0] affects the uart selecting btw system and debug
|
||||
caravelEnv.drive_gpio_in((5,5),1)
|
||||
# wait for start of sending
|
||||
await wait_reg1(cpu,caravelEnv,0XAA)
|
||||
cocotb.log.info(f"[TEST] Start debug test")
|
||||
# send random data to address 30'h00400024 and expect to recieve the same data back it back
|
||||
address = 0x00000410
|
||||
data = random.getrandbits(32)
|
||||
data = 0xFFFFFFFF
|
||||
cocotb.log.info (f"[TEST] Executing DFF2 write address={hex(address)} data = {hex(data)}")
|
||||
await wb_write(caravelEnv,address,data)
|
||||
receieved_data = await wb_read(caravelEnv,address)
|
||||
if data != receieved_data:
|
||||
cocotb.log.error(f"[TEST] DFF2 write failed expected data = {hex(data)} recieved data = {hex(receieved_data)}")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] DFF2 write succeeded")
|
||||
|
||||
|
||||
async def start_of_tx(caravelEnv):
|
||||
while (True): # wait for the start of the transimission it 1 then 0
|
||||
if (caravelEnv.monitor_gpio((6,6)).integer == 0):
|
||||
break
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
|
||||
async def uart_send_char(caravelEnv,char):
|
||||
cocotb.log.info (f"[uart_send_char] start sending on uart {char}")
|
||||
#send start bit
|
||||
caravelEnv.drive_gpio_in((5,5),0)
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
#send bits
|
||||
for i in range(8):
|
||||
caravelEnv.drive_gpio_in((5,5),char[i])
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
|
||||
# stop of frame
|
||||
caravelEnv.drive_gpio_in((5,5),1)
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
# insert 4 bit delay just for debugging
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
|
||||
async def uart_get_char(caravelEnv):
|
||||
await start_of_tx(caravelEnv)
|
||||
char = ''
|
||||
for i in range (8):
|
||||
char = char + caravelEnv.monitor_gpio((6,6)).binstr
|
||||
await Timer(bit_time_ns, units='ns')
|
||||
cocotb.log.info (f"[uart_get_char] recieving {char} from uart")
|
||||
|
||||
return char
|
||||
|
||||
async def wb_write(caravelEnv,addr,data):
|
||||
addr_bits = bin(addr)[2:].zfill(32)[::-1]
|
||||
data_bits = bin(data)[2:].zfill(32)[::-1]
|
||||
cocotb.log.info(f"[TEST] address bits = {addr_bits} {type(addr_bits)}")
|
||||
await uart_send_char(caravelEnv, '10000000') # write cmd
|
||||
await uart_send_char(caravelEnv, '10000000') # size
|
||||
await uart_send_char(caravelEnv, addr_bits[24:32])
|
||||
await uart_send_char(caravelEnv, addr_bits[16:24])
|
||||
await uart_send_char(caravelEnv, addr_bits[8:16])
|
||||
await uart_send_char(caravelEnv, addr_bits[0:8])
|
||||
await uart_send_char(caravelEnv, data_bits[24:32])
|
||||
await uart_send_char(caravelEnv, data_bits[16:24])
|
||||
await uart_send_char(caravelEnv, data_bits[8:16])
|
||||
await uart_send_char(caravelEnv, data_bits[0:8])
|
||||
|
||||
|
||||
async def wb_read(caravelEnv,addr):
|
||||
addr_bits = bin(addr)[2:].zfill(32)[::-1]
|
||||
await uart_send_char(caravelEnv, '01000000') # read cmd
|
||||
await uart_send_char(caravelEnv, '10000000') # size
|
||||
await uart_send_char(caravelEnv, addr_bits[24:32])
|
||||
await uart_send_char(caravelEnv, addr_bits[16:24])
|
||||
await uart_send_char(caravelEnv, addr_bits[8:16])
|
||||
await uart_send_char(caravelEnv, addr_bits[0:8])
|
||||
data_bits = await uart_get_char(caravelEnv)
|
||||
data_bits += await uart_get_char(caravelEnv)
|
||||
data_bits += await uart_get_char(caravelEnv)
|
||||
data_bits += await uart_get_char(caravelEnv)
|
||||
return int(data_bits,2)
|
||||
|
|
@ -231,6 +231,7 @@ class RunRegression:
|
|||
self.test_arg = test
|
||||
self.testlist_arg = testlist
|
||||
self.corners = corner
|
||||
self.total_start_time = datetime.now()
|
||||
if type_arg is None:
|
||||
type_arg = "RTL"
|
||||
self.type_arg = type_arg
|
||||
|
|
@ -338,13 +339,13 @@ class RunRegression:
|
|||
def update_reg_log(self):
|
||||
file_name=f"sim/{os.getenv('RUNTAG')}/runs.log"
|
||||
f = open(file_name, "w")
|
||||
f.write(f"{'Test':<25} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
|
||||
f.write(f"{'Test':<33} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
|
||||
for test,sim_types in self.tests.items():
|
||||
for sim_type,corners in sim_types.items():
|
||||
for corner,status in corners.items():
|
||||
new_test_name= f"{sim_type}-{test}-{corner}"
|
||||
f.write(f"{new_test_name:<33} {status['status']:<10} {status['starttime']:<15} {status['endtime']:<15} {status['duration']:<13} {status['pass']:<5}\n")
|
||||
f.write(f"\n\nTotal: ({self.passed_tests})passed ({self.failed_tests})failed ({self.unknown_tests})unknown ")
|
||||
f.write(f"\n\nTotal: ({self.passed_tests})passed ({self.failed_tests})failed ({self.unknown_tests})unknown ({('%.10s' % (datetime.now() - self.total_start_time))})time consumed ")
|
||||
f.close()
|
||||
|
||||
def write_command_log(self):
|
||||
|
|
|
|||
|
|
@ -1,101 +0,0 @@
|
|||
// This is the unpowered netlist.
|
||||
module buff_flash_clkrst (in_n,
|
||||
in_s,
|
||||
out_n,
|
||||
out_s);
|
||||
input [11:0] in_n;
|
||||
input [2:0] in_s;
|
||||
output [2:0] out_n;
|
||||
output [11:0] out_s;
|
||||
|
||||
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[0] (.A(in_s[0]),
|
||||
.X(out_n[0]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[10] (.A(in_n[7]),
|
||||
.X(out_s[7]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[11] (.A(in_n[8]),
|
||||
.X(out_s[8]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[12] (.A(in_n[9]),
|
||||
.X(out_s[9]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[13] (.A(in_n[10]),
|
||||
.X(out_s[10]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[14] (.A(in_n[11]),
|
||||
.X(out_s[11]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[1] (.A(in_s[1]),
|
||||
.X(out_n[1]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[2] (.A(in_s[2]),
|
||||
.X(out_n[2]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[3] (.A(in_n[0]),
|
||||
.X(out_s[0]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[4] (.A(in_n[1]),
|
||||
.X(out_s[1]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[5] (.A(in_n[2]),
|
||||
.X(out_s[2]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[6] (.A(in_n[3]),
|
||||
.X(out_s[3]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[7] (.A(in_n[4]),
|
||||
.X(out_s[4]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[8] (.A(in_n[5]),
|
||||
.X(out_s[5]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[9] (.A(in_n[6]),
|
||||
.X(out_s[6]));
|
||||
sky130_fd_sc_hd__decap_3 PHY_0 ();
|
||||
sky130_fd_sc_hd__decap_3 PHY_1 ();
|
||||
sky130_fd_sc_hd__decap_3 PHY_2 ();
|
||||
sky130_fd_sc_hd__decap_3 PHY_3 ();
|
||||
sky130_fd_sc_hd__decap_3 PHY_4 ();
|
||||
sky130_fd_sc_hd__decap_3 PHY_5 ();
|
||||
sky130_fd_sc_hd__decap_3 PHY_6 ();
|
||||
sky130_fd_sc_hd__decap_3 PHY_7 ();
|
||||
sky130_fd_sc_hd__decap_3 PHY_8 ();
|
||||
sky130_fd_sc_hd__decap_3 PHY_9 ();
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 ();
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_11 ();
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_12 ();
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_13 ();
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_14 ();
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_15 ();
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_16 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_3 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_7 ();
|
||||
sky130_fd_sc_hd__decap_8 FILLER_0_19 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_27 ();
|
||||
sky130_ef_sc_hd__decap_12 FILLER_0_29 ();
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_41 ();
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_54 ();
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_57 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_70 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_74 ();
|
||||
sky130_fd_sc_hd__decap_3 FILLER_1_3 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_17 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_32 ();
|
||||
sky130_fd_sc_hd__decap_8 FILLER_1_47 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_55 ();
|
||||
sky130_fd_sc_hd__fill_2 FILLER_1_57 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_70 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_74 ();
|
||||
sky130_ef_sc_hd__decap_12 FILLER_2_3 ();
|
||||
sky130_fd_sc_hd__fill_2 FILLER_2_26 ();
|
||||
sky130_ef_sc_hd__decap_12 FILLER_2_29 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_2_52 ();
|
||||
sky130_fd_sc_hd__decap_8 FILLER_2_67 ();
|
||||
sky130_ef_sc_hd__decap_12 FILLER_3_3 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_15 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_3_27 ();
|
||||
sky130_ef_sc_hd__decap_12 FILLER_3_42 ();
|
||||
sky130_fd_sc_hd__fill_2 FILLER_3_54 ();
|
||||
sky130_fd_sc_hd__fill_2 FILLER_3_57 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_3_70 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_74 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_3 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_7 ();
|
||||
sky130_fd_sc_hd__decap_8 FILLER_4_19 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_27 ();
|
||||
sky130_ef_sc_hd__decap_12 FILLER_4_29 ();
|
||||
sky130_ef_sc_hd__decap_12 FILLER_4_41 ();
|
||||
sky130_fd_sc_hd__decap_3 FILLER_4_53 ();
|
||||
sky130_fd_sc_hd__fill_2 FILLER_4_57 ();
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_70 ();
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_74 ();
|
||||
endmodule
|
||||
|
||||
|
|
@ -0,0 +1,323 @@
|
|||
module buff_flash_clkrst (VPWR,
|
||||
VGND,
|
||||
in_n,
|
||||
in_s,
|
||||
out_n,
|
||||
out_s);
|
||||
input VPWR;
|
||||
input VGND;
|
||||
input [11:0] in_n;
|
||||
input [2:0] in_s;
|
||||
output [2:0] out_n;
|
||||
output [11:0] out_s;
|
||||
|
||||
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[0] (.A(in_s[0]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_n[0]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[10] (.A(in_n[7]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[7]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[11] (.A(in_n[8]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[8]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[12] (.A(in_n[9]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[9]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[13] (.A(in_n[10]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[10]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[14] (.A(in_n[11]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[11]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[1] (.A(in_s[1]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_n[1]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[2] (.A(in_s[2]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_n[2]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[3] (.A(in_n[0]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[0]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[4] (.A(in_n[1]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[1]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[5] (.A(in_n[2]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[2]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[6] (.A(in_n[3]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[3]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[7] (.A(in_n[4]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[4]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[8] (.A(in_n[5]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[5]));
|
||||
sky130_fd_sc_hd__clkbuf_8 \BUF[9] (.A(in_n[6]),
|
||||
.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR),
|
||||
.X(out_s[6]));
|
||||
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(VGND),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_11 (.VGND(VGND),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_12 (.VGND(VGND),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_13 (.VGND(VGND),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_14 (.VGND(VGND),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_15 (.VGND(VGND),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_16 (.VGND(VGND),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_3 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_7 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_0_19 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_27 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_0_29 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_41 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_54 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_0_57 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_70 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_74 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_1_3 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_17 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_32 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_1_47 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_55 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_1_57 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_70 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_74 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_2_3 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_2_26 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_2_29 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_2_52 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_2_67 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_3_3 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_15 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_3_27 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_3_42 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_3_54 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_3_57 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_3_70 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_74 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_3 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_7 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_4_19 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_27 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_4_29 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_ef_sc_hd__decap_12 FILLER_4_41 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_4_53 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_4_57 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_70 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_74 (.VGND(VGND),
|
||||
.VNB(VGND),
|
||||
.VPB(VPWR),
|
||||
.VPWR(VPWR));
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -103,10 +103,10 @@ module gpio_signal_buffering_alt (
|
|||
|
||||
/* Instantiate 48 + 48 + 6 = 101 buffers of size 8 */
|
||||
|
||||
wire [100:0] buf_in;
|
||||
wire [100:0] buf_out;
|
||||
wire [101:0] buf_in;
|
||||
wire [101:0] buf_out;
|
||||
|
||||
sky130_fd_sc_hd__buf_8 signal_buffers [100:0] (
|
||||
sky130_fd_sc_hd__buf_8 signal_buffers [101:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
|
|
@ -149,71 +149,71 @@ module gpio_signal_buffering_alt (
|
|||
// mgmt_io_in, left-hand side
|
||||
//----------------------------------------
|
||||
|
||||
assign buf_in[8] = mgmt_io_in_unbuf[8];
|
||||
assign buf_in[8] = mgmt_io_in_unbuf[7];
|
||||
assign buf_in[9] = buf_out[8];
|
||||
assign buf_in[10] = buf_out[9];
|
||||
assign buf_in[11] = buf_out[10];
|
||||
assign mgmt_io_in_buf[8] = buf_out[11];
|
||||
assign mgmt_io_in_buf[7] = buf_out[11];
|
||||
|
||||
assign buf_in[12] = mgmt_io_in_unbuf[9];
|
||||
assign buf_in[12] = mgmt_io_in_unbuf[8];
|
||||
assign buf_in[13] = buf_out[12];
|
||||
assign buf_in[14] = buf_out[13];
|
||||
assign buf_in[15] = buf_out[14];
|
||||
assign mgmt_io_in_buf[9] = buf_out[15];
|
||||
assign mgmt_io_in_buf[8] = buf_out[15];
|
||||
|
||||
assign buf_in[16] = mgmt_io_in_unbuf[10];
|
||||
assign buf_in[16] = mgmt_io_in_unbuf[9];
|
||||
assign buf_in[17] = buf_out[16];
|
||||
assign buf_in[18] = buf_out[17];
|
||||
assign buf_in[19] = buf_out[18];
|
||||
assign mgmt_io_in_buf[10] = buf_out[19];
|
||||
assign mgmt_io_in_buf[9] = buf_out[19];
|
||||
|
||||
assign buf_in[20] = mgmt_io_in_unbuf[11];
|
||||
assign buf_in[20] = mgmt_io_in_unbuf[10];
|
||||
assign buf_in[21] = buf_out[20];
|
||||
assign buf_in[22] = buf_out[21];
|
||||
assign buf_in[23] = buf_out[22];
|
||||
assign mgmt_io_in_buf[11] = buf_out[23];
|
||||
assign mgmt_io_in_buf[10] = buf_out[23];
|
||||
|
||||
assign buf_in[24] = mgmt_io_in_unbuf[12];
|
||||
assign buf_in[24] = mgmt_io_in_unbuf[11];
|
||||
assign buf_in[25] = buf_out[24];
|
||||
assign buf_in[26] = buf_out[25];
|
||||
assign buf_in[27] = buf_out[26];
|
||||
assign mgmt_io_in_buf[12] = buf_out[27];
|
||||
assign mgmt_io_in_buf[11] = buf_out[27];
|
||||
|
||||
assign buf_in[28] = mgmt_io_in_unbuf[13];
|
||||
assign buf_in[28] = mgmt_io_in_unbuf[12];
|
||||
assign buf_in[29] = buf_out[28];
|
||||
assign buf_in[30] = buf_out[29];
|
||||
assign mgmt_io_in_buf[13] = buf_out[30];
|
||||
assign mgmt_io_in_buf[12] = buf_out[30];
|
||||
|
||||
assign buf_in[31] = mgmt_io_in_unbuf[14];
|
||||
assign buf_in[31] = mgmt_io_in_unbuf[13];
|
||||
assign buf_in[32] = buf_out[31];
|
||||
assign buf_in[33] = buf_out[32];
|
||||
assign mgmt_io_in_buf[14] = buf_out[33];
|
||||
assign mgmt_io_in_buf[13] = buf_out[33];
|
||||
|
||||
assign buf_in[34] = mgmt_io_in_unbuf[15];
|
||||
assign buf_in[34] = mgmt_io_in_unbuf[14];
|
||||
assign buf_in[35] = buf_out[34];
|
||||
assign buf_in[36] = buf_out[35];
|
||||
assign mgmt_io_in_buf[15] = buf_out[36];
|
||||
assign mgmt_io_in_buf[14] = buf_out[36];
|
||||
|
||||
assign buf_in[37] = mgmt_io_in_unbuf[16];
|
||||
assign buf_in[37] = mgmt_io_in_unbuf[15];
|
||||
assign buf_in[38] = buf_out[37];
|
||||
assign buf_in[39] = buf_out[38];
|
||||
assign mgmt_io_in_buf[16] = buf_out[39];
|
||||
assign mgmt_io_in_buf[15] = buf_out[39];
|
||||
|
||||
assign buf_in[40] = mgmt_io_in_unbuf[17];
|
||||
assign buf_in[40] = mgmt_io_in_unbuf[16];
|
||||
assign buf_in[41] = buf_out[40];
|
||||
assign mgmt_io_in_buf[17] = buf_out[41];
|
||||
assign mgmt_io_in_buf[16] = buf_out[41];
|
||||
|
||||
assign buf_in[42] = mgmt_io_in_unbuf[18];
|
||||
assign buf_in[42] = mgmt_io_in_unbuf[17];
|
||||
assign buf_in[43] = buf_out[42];
|
||||
assign mgmt_io_in_buf[18] = buf_out[43];
|
||||
assign mgmt_io_in_buf[17] = buf_out[43];
|
||||
|
||||
assign buf_in[44] = mgmt_io_in_unbuf[19];
|
||||
assign buf_in[44] = mgmt_io_in_unbuf[18];
|
||||
assign buf_in[45] = buf_out[44];
|
||||
assign mgmt_io_in_buf[19] = buf_out[45];
|
||||
assign mgmt_io_in_buf[18] = buf_out[45];
|
||||
|
||||
assign buf_in[46] = mgmt_io_in_unbuf[20];
|
||||
assign buf_in[46] = mgmt_io_in_unbuf[19];
|
||||
assign buf_in[47] = buf_out[46];
|
||||
assign mgmt_io_in_buf[20] = buf_out[47];
|
||||
assign mgmt_io_in_buf[19] = buf_out[47];
|
||||
|
||||
//----------------------------------------
|
||||
// mgmt_io_out, right-hand side
|
||||
|
|
|
|||
Loading…
Reference in New Issue