mirror of https://github.com/efabless/caravel.git
[DATA] Update HK views (timing clean)
This commit is contained in:
manarabdelaty
parent
fe21089505
commit
05278ec738
5
Makefile
5
Makefile
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@ -464,7 +464,7 @@ help:
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# RCX Extraction
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BLOCKS = $(shell cd openlane && find * -maxdepth 0 -type d)
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RCX_BLOCKS = $(foreach block, $(BLOCKS), rcx-$(block))
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OPENLANE_IMAGE_NAME=efabless/openlane:2021.09.16_03.28.21
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OPENLANE_IMAGE_NAME=efabless/openlane:2021.11.23_01.42.34
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$(RCX_BLOCKS): rcx-% : ./def/%.def
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echo "Running RC Extraction on $*"
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mkdir -p ./def/tmp
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@ -520,8 +520,7 @@ $(RCX_BLOCKS): rcx-% : ./def/%.def
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};\
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set_cmd_units -time ns -capacitance pF -current mA -voltage V -resistance kOhm -distance um;\
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read_liberty $(PDK_ROOT)/sky130A/libs.ref/$(STD_CELL_LIBRARY)/lib/$(STD_CELL_LIBRARY)__tt_025C_1v80.lib;\
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read_verilog ./verilog/gl/$*.v;\
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link_design $*;\
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read_def ./def/$*.def;\
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read_spef ./def/tmp/$*.spef;\
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read_sdc -echo ./openlane/$*/base.sdc;\
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write_sdf $*.sdf;\
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318530
def/housekeeping.def
318530
def/housekeeping.def
File diff suppressed because it is too large
Load Diff
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@ -3215,7 +3215,7 @@ MACRO housekeeping
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RECT 1.905 38.440 300.080 42.480 ;
|
||||
RECT 1.445 38.440 300.080 42.480 ;
|
||||
RECT 4.400 37.040 295.830 38.440 ;
|
||||
RECT 1.905 33.680 300.080 37.040 ;
|
||||
RECT 1.445 33.680 300.080 37.040 ;
|
||||
RECT 4.400 32.280 300.080 33.680 ;
|
||||
RECT 1.905 30.280 300.080 32.280 ;
|
||||
RECT 1.905 28.880 295.830 30.280 ;
|
||||
RECT 1.905 28.240 300.080 28.880 ;
|
||||
RECT 1.445 30.280 300.080 32.280 ;
|
||||
RECT 1.445 28.880 295.830 30.280 ;
|
||||
RECT 1.445 28.240 300.080 28.880 ;
|
||||
RECT 4.400 26.840 300.080 28.240 ;
|
||||
RECT 1.905 23.480 300.080 26.840 ;
|
||||
RECT 1.445 23.480 300.080 26.840 ;
|
||||
RECT 4.400 22.080 300.080 23.480 ;
|
||||
RECT 1.905 21.440 300.080 22.080 ;
|
||||
RECT 1.905 20.040 295.830 21.440 ;
|
||||
RECT 1.905 18.040 300.080 20.040 ;
|
||||
RECT 1.445 21.440 300.080 22.080 ;
|
||||
RECT 1.445 20.040 295.830 21.440 ;
|
||||
RECT 1.445 18.040 300.080 20.040 ;
|
||||
RECT 4.400 16.640 300.080 18.040 ;
|
||||
RECT 1.905 13.280 300.080 16.640 ;
|
||||
RECT 1.445 13.280 300.080 16.640 ;
|
||||
RECT 4.400 11.880 295.830 13.280 ;
|
||||
RECT 1.905 7.840 300.080 11.880 ;
|
||||
RECT 1.445 7.840 300.080 11.880 ;
|
||||
RECT 4.400 6.440 300.080 7.840 ;
|
||||
RECT 1.905 5.120 300.080 6.440 ;
|
||||
RECT 1.905 3.720 295.830 5.120 ;
|
||||
RECT 1.905 3.080 300.080 3.720 ;
|
||||
RECT 4.400 2.230 300.080 3.080 ;
|
||||
RECT 1.445 5.120 300.080 6.440 ;
|
||||
RECT 1.445 3.720 295.830 5.120 ;
|
||||
RECT 1.445 3.080 300.080 3.720 ;
|
||||
RECT 4.400 2.215 300.080 3.080 ;
|
||||
LAYER met4 ;
|
||||
RECT 5.815 16.495 20.640 532.945 ;
|
||||
RECT 23.040 16.495 97.440 532.945 ;
|
||||
RECT 99.840 16.495 174.240 532.945 ;
|
||||
RECT 176.640 16.495 251.040 532.945 ;
|
||||
RECT 253.440 16.495 299.625 532.945 ;
|
||||
RECT 2.135 26.695 20.640 531.585 ;
|
||||
RECT 23.040 26.695 97.440 531.585 ;
|
||||
RECT 99.840 26.695 174.240 531.585 ;
|
||||
RECT 176.640 26.695 251.040 531.585 ;
|
||||
RECT 253.440 26.695 299.625 531.585 ;
|
||||
LAYER met5 ;
|
||||
RECT 16.220 194.700 140.180 196.300 ;
|
||||
RECT 83.380 266.100 208.260 277.900 ;
|
||||
END
|
||||
END housekeeping
|
||||
END LIBRARY
|
||||
|
|
|
|||
1003240
mag/housekeeping.mag
1003240
mag/housekeeping.mag
File diff suppressed because it is too large
Load Diff
|
|
@ -1,11 +1,11 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1637412622
|
||||
timestamp 1637788660
|
||||
<< obsli1 >>
|
||||
rect 1104 2159 58880 107729
|
||||
<< obsm1 >>
|
||||
rect 14 2128 60044 107976
|
||||
rect 14 2048 60044 107908
|
||||
<< metal2 >>
|
||||
rect 202 109390 258 110190
|
||||
rect 662 109390 718 110190
|
||||
|
|
@ -360,99 +360,99 @@ rect 58918 109334 59210 109426
|
|||
rect 59378 109334 59670 109426
|
||||
rect 59838 109334 60044 109426
|
||||
rect 20 856 60044 109334
|
||||
rect 20 800 238 856
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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||||
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||||
rect 54594 439 55070 856
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||||
rect 58458 439 58934 856
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||||
rect 59102 439 59578 856
|
||||
rect 59746 439 60044 856
|
||||
<< metal3 >>
|
||||
rect 0 109488 800 109608
|
||||
rect 59246 109216 60046 109336
|
||||
|
|
@ -630,342 +630,342 @@ rect 0 416 800 536
|
|||
<< obsm3 >>
|
||||
rect 880 109416 60016 109578
|
||||
rect 880 109408 59166 109416
|
||||
rect 381 109136 59166 109408
|
||||
rect 381 108736 60016 109136
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rect 289 109136 59166 109408
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rect 289 108736 60016 109136
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rect 880 108456 60016 108736
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||||
rect 381 107784 60016 108456
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||||
rect 381 107648 59166 107784
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||||
rect 289 107784 60016 108456
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||||
rect 289 107648 59166 107784
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||||
rect 880 107504 59166 107648
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||||
rect 880 107368 60016 107504
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||||
rect 381 106696 60016 107368
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||||
rect 289 106696 60016 107368
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||||
rect 880 106416 60016 106696
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||||
rect 381 106016 60016 106416
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rect 381 105736 59166 106016
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||||
rect 381 105608 60016 105736
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||||
rect 289 106016 60016 106416
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rect 289 105736 59166 106016
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||||
rect 289 105608 60016 105736
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||||
rect 880 105328 60016 105608
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rect 289 70928 60016 71736
|
||||
rect 880 70648 60016 70928
|
||||
rect 381 70384 60016 70648
|
||||
rect 381 70104 59166 70384
|
||||
rect 381 69976 60016 70104
|
||||
rect 289 70384 60016 70648
|
||||
rect 289 70104 59166 70384
|
||||
rect 289 69976 60016 70104
|
||||
rect 880 69696 60016 69976
|
||||
rect 381 68888 60016 69696
|
||||
rect 289 68888 60016 69696
|
||||
rect 880 68752 60016 68888
|
||||
rect 880 68608 59166 68752
|
||||
rect 381 68472 59166 68608
|
||||
rect 381 67936 60016 68472
|
||||
rect 289 68472 59166 68608
|
||||
rect 289 67936 60016 68472
|
||||
rect 880 67656 60016 67936
|
||||
rect 381 67120 60016 67656
|
||||
rect 381 66848 59166 67120
|
||||
rect 289 67120 60016 67656
|
||||
rect 289 66848 59166 67120
|
||||
rect 880 66840 59166 66848
|
||||
rect 880 66568 60016 66840
|
||||
rect 381 65896 60016 66568
|
||||
rect 289 65896 60016 66568
|
||||
rect 880 65616 60016 65896
|
||||
rect 381 65352 60016 65616
|
||||
rect 381 65072 59166 65352
|
||||
rect 381 64808 60016 65072
|
||||
rect 289 65352 60016 65616
|
||||
rect 289 65072 59166 65352
|
||||
rect 289 64808 60016 65072
|
||||
rect 880 64528 60016 64808
|
||||
rect 381 63856 60016 64528
|
||||
rect 289 63856 60016 64528
|
||||
rect 880 63720 60016 63856
|
||||
rect 880 63576 59166 63720
|
||||
rect 381 63440 59166 63576
|
||||
rect 381 62768 60016 63440
|
||||
rect 289 63440 59166 63576
|
||||
rect 289 62768 60016 63440
|
||||
rect 880 62488 60016 62768
|
||||
rect 381 61952 60016 62488
|
||||
rect 381 61816 59166 61952
|
||||
rect 289 61952 60016 62488
|
||||
rect 289 61816 59166 61952
|
||||
rect 880 61672 59166 61816
|
||||
rect 880 61536 60016 61672
|
||||
rect 381 60728 60016 61536
|
||||
rect 289 60728 60016 61536
|
||||
rect 880 60448 60016 60728
|
||||
rect 381 60320 60016 60448
|
||||
rect 381 60040 59166 60320
|
||||
rect 381 59776 60016 60040
|
||||
rect 289 60320 60016 60448
|
||||
rect 289 60040 59166 60320
|
||||
rect 289 59776 60016 60040
|
||||
rect 880 59496 60016 59776
|
||||
rect 381 58688 60016 59496
|
||||
rect 289 58688 60016 59496
|
||||
rect 880 58552 60016 58688
|
||||
rect 880 58408 59166 58552
|
||||
rect 381 58272 59166 58408
|
||||
rect 381 57736 60016 58272
|
||||
rect 289 58272 59166 58408
|
||||
rect 289 57736 60016 58272
|
||||
rect 880 57456 60016 57736
|
||||
rect 381 56920 60016 57456
|
||||
rect 381 56648 59166 56920
|
||||
rect 289 56920 60016 57456
|
||||
rect 289 56648 59166 56920
|
||||
rect 880 56640 59166 56648
|
||||
rect 880 56368 60016 56640
|
||||
rect 381 55696 60016 56368
|
||||
rect 289 55696 60016 56368
|
||||
rect 880 55416 60016 55696
|
||||
rect 381 55152 60016 55416
|
||||
rect 381 54872 59166 55152
|
||||
rect 381 54608 60016 54872
|
||||
rect 289 55152 60016 55416
|
||||
rect 289 54872 59166 55152
|
||||
rect 289 54608 60016 54872
|
||||
rect 880 54328 60016 54608
|
||||
rect 381 53656 60016 54328
|
||||
rect 289 53656 60016 54328
|
||||
rect 880 53520 60016 53656
|
||||
rect 880 53376 59166 53520
|
||||
rect 381 53240 59166 53376
|
||||
rect 381 52568 60016 53240
|
||||
rect 289 53240 59166 53376
|
||||
rect 289 52568 60016 53240
|
||||
rect 880 52288 60016 52568
|
||||
rect 381 51752 60016 52288
|
||||
rect 381 51616 59166 51752
|
||||
rect 289 51752 60016 52288
|
||||
rect 289 51616 59166 51752
|
||||
rect 880 51472 59166 51616
|
||||
rect 880 51336 60016 51472
|
||||
rect 381 50528 60016 51336
|
||||
rect 289 50528 60016 51336
|
||||
rect 880 50248 60016 50528
|
||||
rect 381 50120 60016 50248
|
||||
rect 381 49840 59166 50120
|
||||
rect 381 49576 60016 49840
|
||||
rect 289 50120 60016 50248
|
||||
rect 289 49840 59166 50120
|
||||
rect 289 49576 60016 49840
|
||||
rect 880 49296 60016 49576
|
||||
rect 381 48488 60016 49296
|
||||
rect 289 48488 60016 49296
|
||||
rect 880 48352 60016 48488
|
||||
rect 880 48208 59166 48352
|
||||
rect 381 48072 59166 48208
|
||||
rect 381 47536 60016 48072
|
||||
rect 289 48072 59166 48208
|
||||
rect 289 47536 60016 48072
|
||||
rect 880 47256 60016 47536
|
||||
rect 381 46720 60016 47256
|
||||
rect 381 46448 59166 46720
|
||||
rect 289 46720 60016 47256
|
||||
rect 289 46448 59166 46720
|
||||
rect 880 46440 59166 46448
|
||||
rect 880 46168 60016 46440
|
||||
rect 381 45496 60016 46168
|
||||
rect 289 45496 60016 46168
|
||||
rect 880 45216 60016 45496
|
||||
rect 381 45088 60016 45216
|
||||
rect 381 44808 59166 45088
|
||||
rect 381 44408 60016 44808
|
||||
rect 289 45088 60016 45216
|
||||
rect 289 44808 59166 45088
|
||||
rect 289 44408 60016 44808
|
||||
rect 880 44128 60016 44408
|
||||
rect 381 43456 60016 44128
|
||||
rect 289 43456 60016 44128
|
||||
rect 880 43320 60016 43456
|
||||
rect 880 43176 59166 43320
|
||||
rect 381 43040 59166 43176
|
||||
rect 381 42368 60016 43040
|
||||
rect 289 43040 59166 43176
|
||||
rect 289 42368 60016 43040
|
||||
rect 880 42088 60016 42368
|
||||
rect 381 41688 60016 42088
|
||||
rect 381 41416 59166 41688
|
||||
rect 289 41688 60016 42088
|
||||
rect 289 41416 59166 41688
|
||||
rect 880 41408 59166 41416
|
||||
rect 880 41136 60016 41408
|
||||
rect 381 40328 60016 41136
|
||||
rect 289 40328 60016 41136
|
||||
rect 880 40048 60016 40328
|
||||
rect 381 39920 60016 40048
|
||||
rect 381 39640 59166 39920
|
||||
rect 381 39376 60016 39640
|
||||
rect 289 39920 60016 40048
|
||||
rect 289 39640 59166 39920
|
||||
rect 289 39376 60016 39640
|
||||
rect 880 39096 60016 39376
|
||||
rect 381 38288 60016 39096
|
||||
rect 289 38288 60016 39096
|
||||
rect 880 38008 59166 38288
|
||||
rect 381 37336 60016 38008
|
||||
rect 289 37336 60016 38008
|
||||
rect 880 37056 60016 37336
|
||||
rect 381 36520 60016 37056
|
||||
rect 381 36248 59166 36520
|
||||
rect 289 36520 60016 37056
|
||||
rect 289 36248 59166 36520
|
||||
rect 880 36240 59166 36248
|
||||
rect 880 35968 60016 36240
|
||||
rect 381 35296 60016 35968
|
||||
rect 289 35296 60016 35968
|
||||
rect 880 35016 60016 35296
|
||||
rect 381 34888 60016 35016
|
||||
rect 381 34608 59166 34888
|
||||
rect 381 34208 60016 34608
|
||||
rect 289 34888 60016 35016
|
||||
rect 289 34608 59166 34888
|
||||
rect 289 34208 60016 34608
|
||||
rect 880 33928 60016 34208
|
||||
rect 381 33256 60016 33928
|
||||
rect 289 33256 60016 33928
|
||||
rect 880 33120 60016 33256
|
||||
rect 880 32976 59166 33120
|
||||
rect 381 32840 59166 32976
|
||||
rect 381 32168 60016 32840
|
||||
rect 289 32840 59166 32976
|
||||
rect 289 32168 60016 32840
|
||||
rect 880 31888 60016 32168
|
||||
rect 381 31488 60016 31888
|
||||
rect 381 31216 59166 31488
|
||||
rect 289 31488 60016 31888
|
||||
rect 289 31216 59166 31488
|
||||
rect 880 31208 59166 31216
|
||||
rect 880 30936 60016 31208
|
||||
rect 381 30128 60016 30936
|
||||
rect 289 30128 60016 30936
|
||||
rect 880 29848 60016 30128
|
||||
rect 381 29720 60016 29848
|
||||
rect 381 29440 59166 29720
|
||||
rect 381 29176 60016 29440
|
||||
rect 289 29720 60016 29848
|
||||
rect 289 29440 59166 29720
|
||||
rect 289 29176 60016 29440
|
||||
rect 880 28896 60016 29176
|
||||
rect 381 28088 60016 28896
|
||||
rect 289 28088 60016 28896
|
||||
rect 880 27808 59166 28088
|
||||
rect 381 27136 60016 27808
|
||||
rect 289 27136 60016 27808
|
||||
rect 880 26856 60016 27136
|
||||
rect 381 26320 60016 26856
|
||||
rect 381 26048 59166 26320
|
||||
rect 289 26320 60016 26856
|
||||
rect 289 26048 59166 26320
|
||||
rect 880 26040 59166 26048
|
||||
rect 880 25768 60016 26040
|
||||
rect 381 25096 60016 25768
|
||||
rect 289 25096 60016 25768
|
||||
rect 880 24816 60016 25096
|
||||
rect 381 24688 60016 24816
|
||||
rect 381 24408 59166 24688
|
||||
rect 381 24008 60016 24408
|
||||
rect 289 24688 60016 24816
|
||||
rect 289 24408 59166 24688
|
||||
rect 289 24008 60016 24408
|
||||
rect 880 23728 60016 24008
|
||||
rect 381 23056 60016 23728
|
||||
rect 289 23056 60016 23728
|
||||
rect 880 22776 59166 23056
|
||||
rect 381 21968 60016 22776
|
||||
rect 289 21968 60016 22776
|
||||
rect 880 21688 60016 21968
|
||||
rect 381 21288 60016 21688
|
||||
rect 381 21016 59166 21288
|
||||
rect 289 21288 60016 21688
|
||||
rect 289 21016 59166 21288
|
||||
rect 880 21008 59166 21016
|
||||
rect 880 20736 60016 21008
|
||||
rect 381 19928 60016 20736
|
||||
rect 289 19928 60016 20736
|
||||
rect 880 19656 60016 19928
|
||||
rect 880 19648 59166 19656
|
||||
rect 381 19376 59166 19648
|
||||
rect 381 18976 60016 19376
|
||||
rect 289 19376 59166 19648
|
||||
rect 289 18976 60016 19376
|
||||
rect 880 18696 60016 18976
|
||||
rect 381 17888 60016 18696
|
||||
rect 289 17888 60016 18696
|
||||
rect 880 17608 59166 17888
|
||||
rect 381 16936 60016 17608
|
||||
rect 289 16936 60016 17608
|
||||
rect 880 16656 60016 16936
|
||||
rect 381 16256 60016 16656
|
||||
rect 381 15976 59166 16256
|
||||
rect 381 15848 60016 15976
|
||||
rect 289 16256 60016 16656
|
||||
rect 289 15976 59166 16256
|
||||
rect 289 15848 60016 15976
|
||||
rect 880 15568 60016 15848
|
||||
rect 381 14896 60016 15568
|
||||
rect 289 14896 60016 15568
|
||||
rect 880 14616 60016 14896
|
||||
rect 381 14488 60016 14616
|
||||
rect 381 14208 59166 14488
|
||||
rect 381 13808 60016 14208
|
||||
rect 289 14488 60016 14616
|
||||
rect 289 14208 59166 14488
|
||||
rect 289 13808 60016 14208
|
||||
rect 880 13528 60016 13808
|
||||
rect 381 12856 60016 13528
|
||||
rect 289 12856 60016 13528
|
||||
rect 880 12576 59166 12856
|
||||
rect 381 11768 60016 12576
|
||||
rect 289 11768 60016 12576
|
||||
rect 880 11488 60016 11768
|
||||
rect 381 11088 60016 11488
|
||||
rect 381 10816 59166 11088
|
||||
rect 289 11088 60016 11488
|
||||
rect 289 10816 59166 11088
|
||||
rect 880 10808 59166 10816
|
||||
rect 880 10536 60016 10808
|
||||
rect 381 9728 60016 10536
|
||||
rect 289 9728 60016 10536
|
||||
rect 880 9456 60016 9728
|
||||
rect 880 9448 59166 9456
|
||||
rect 381 9176 59166 9448
|
||||
rect 381 8776 60016 9176
|
||||
rect 289 9176 59166 9448
|
||||
rect 289 8776 60016 9176
|
||||
rect 880 8496 60016 8776
|
||||
rect 381 7688 60016 8496
|
||||
rect 289 7688 60016 8496
|
||||
rect 880 7408 59166 7688
|
||||
rect 381 6736 60016 7408
|
||||
rect 289 6736 60016 7408
|
||||
rect 880 6456 60016 6736
|
||||
rect 381 6056 60016 6456
|
||||
rect 381 5776 59166 6056
|
||||
rect 381 5648 60016 5776
|
||||
rect 289 6056 60016 6456
|
||||
rect 289 5776 59166 6056
|
||||
rect 289 5648 60016 5776
|
||||
rect 880 5368 60016 5648
|
||||
rect 381 4696 60016 5368
|
||||
rect 289 4696 60016 5368
|
||||
rect 880 4416 60016 4696
|
||||
rect 381 4288 60016 4416
|
||||
rect 381 4008 59166 4288
|
||||
rect 381 3608 60016 4008
|
||||
rect 289 4288 60016 4416
|
||||
rect 289 4008 59166 4288
|
||||
rect 289 3608 60016 4008
|
||||
rect 880 3328 60016 3608
|
||||
rect 381 2656 60016 3328
|
||||
rect 289 2656 60016 3328
|
||||
rect 880 2376 59166 2656
|
||||
rect 381 1568 60016 2376
|
||||
rect 289 1568 60016 2376
|
||||
rect 880 1288 60016 1568
|
||||
rect 381 1024 60016 1288
|
||||
rect 381 744 59166 1024
|
||||
rect 381 616 60016 744
|
||||
rect 880 446 60016 616
|
||||
rect 289 1024 60016 1288
|
||||
rect 289 744 59166 1024
|
||||
rect 289 616 60016 744
|
||||
rect 880 443 60016 616
|
||||
<< metal4 >>
|
||||
rect 4208 2128 4528 107760
|
||||
rect 19568 2128 19888 107760
|
||||
rect 34928 2128 35248 107760
|
||||
rect 50288 2128 50608 107760
|
||||
<< obsm4 >>
|
||||
rect 1163 3299 4128 106589
|
||||
rect 4608 3299 19488 106589
|
||||
rect 19968 3299 34848 106589
|
||||
rect 35328 3299 50208 106589
|
||||
rect 50688 3299 59925 106589
|
||||
rect 427 5339 4128 106317
|
||||
rect 4608 5339 19488 106317
|
||||
rect 19968 5339 34848 106317
|
||||
rect 35328 5339 50208 106317
|
||||
rect 50688 5339 59925 106317
|
||||
<< metal5 >>
|
||||
rect 1104 97206 58880 97526
|
||||
rect 1104 81888 58880 82208
|
||||
|
|
@ -975,7 +975,7 @@ rect 1104 35934 58880 36254
|
|||
rect 1104 20616 58880 20936
|
||||
rect 1104 5298 58880 5618
|
||||
<< obsm5 >>
|
||||
rect 3244 38940 28036 39260
|
||||
rect 16676 53220 41652 55580
|
||||
<< labels >>
|
||||
rlabel metal5 s 1104 20616 58880 20936 6 VGND
|
||||
port 1 nsew ground input
|
||||
|
|
@ -1791,8 +1791,8 @@ port 396 nsew signal input
|
|||
string LEFclass BLOCK
|
||||
string FIXED_BBOX 0 0 60046 110190
|
||||
string LEFview TRUE
|
||||
string GDS_FILE /home/ma/ef/caravel_openframe/openlane/housekeeping/runs/housekeeping/results/magic/housekeeping.gds
|
||||
string GDS_END 22580570
|
||||
string GDS_START 1111786
|
||||
string GDS_FILE /home/ma/ef/caravel_openframe/openlane/housekeeping/runs/housekeeping/results/finishing/housekeeping.gds
|
||||
string GDS_END 21816938
|
||||
string GDS_START 1139396
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ BLOCKS = $(shell find * -maxdepth 0 -type d)
|
|||
CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
|
||||
CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
|
||||
|
||||
OPENLANE_TAG ?= v0.20
|
||||
OPENLANE_TAG ?= 2021.11.23_01.42.34
|
||||
OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
|
||||
OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
|
||||
OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -it -file ./$*/interactive.tcl"
|
||||
|
|
|
|||
|
|
@ -1,25 +1,38 @@
|
|||
set ::env(WB_CLK_PERIOD) 25
|
||||
set ::env(SCK_CLK_PERIOD) 100
|
||||
set ::env(RESET_PORT) "wb_rstn_i"
|
||||
|
||||
## MASTER CLOCKS
|
||||
create_clock [get_ports {"wb_clk_i"} ] -name "wb_clk_i" -period $::env(WB_CLK_PERIOD)
|
||||
create_clock [get_ports {"mgmt_gpio_in[4]"} ] -name "mgmt_gpio_in" -period $::env(SCK_CLK_PERIOD)
|
||||
|
||||
# change the csclk pin whenever the synthesis receipe changes
|
||||
create_generated_clock -name "csclk" -source [get_ports {"mgmt_gpio_in[4]"} ] -divide_by 1 [get_pins {"_8889_/X"} ]
|
||||
## GENERATED CLOCKS
|
||||
# NOTE: change the clock pins whenever the synthesis receipe changes
|
||||
create_generated_clock -name "wbbd_sck" -source [get_ports {"wb_clk_i"} ] -divide_by 1 [get_pins {"_9640_/Q"} ]
|
||||
create_generated_clock -name "csclk_fast" -source [get_pins {"_9640_/Q"}] -divide_by 1 [get_pins {"_8847_/X"} ]
|
||||
create_generated_clock -name "csclk_slow" -source [get_ports {"mgmt_gpio_in[4]"} ] -divide_by 1 [get_pins {"_8847_/X"} ]
|
||||
|
||||
# paths between wb_clk_i and mgmt_gpio_in shouldn't be timed
|
||||
set_clock_groups -logically_exclusive -group wb_clk_i -group mgmt_gpio_in
|
||||
# mux output is logically exclusive
|
||||
set_clock_groups -logically_exclusive -group csclk_fast -group csclk_slow
|
||||
|
||||
## FALSE PATHS
|
||||
set_false_path -from [get_ports $::env(RESET_PORT)]
|
||||
set_false_path -from [get_ports "porb"]
|
||||
|
||||
## INPUT/OUTPUT DELAYS
|
||||
set input_delay_value [expr $::env(WB_CLK_PERIOD) * $::env(IO_PCT)]
|
||||
set output_delay_value [expr $::env(WB_CLK_PERIOD) * $::env(IO_PCT)]
|
||||
puts "\[INFO\]: Setting output delay to: $output_delay_value"
|
||||
puts "\[INFO\]: Setting input delay to: $input_delay_value"
|
||||
|
||||
|
||||
set sck_clk_indx [lsearch [all_inputs] [get_port "mgmt_gpio_in[4]"]]
|
||||
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
|
||||
set all_inputs_wo_clk [lreplace [all_inputs] $sck_clk_indx $sck_clk_indx]
|
||||
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
|
||||
set all_inputs_wo_clk_rst $all_inputs_wo_clk
|
||||
|
||||
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
|
||||
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [all_outputs]
|
||||
|
||||
|
|
@ -29,16 +42,20 @@ set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
|
|||
puts "\[INFO\]: Setting load to: $cap_load"
|
||||
set_load $cap_load [all_outputs]
|
||||
|
||||
## TIMING DERATE
|
||||
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
|
||||
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
|
||||
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
|
||||
|
||||
## CLOCK UNCERTAINITY
|
||||
puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {wb_clk_i}]
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {csclk}]
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {mgmt_gpio_in}]
|
||||
|
||||
## CLOCK TRANSITION
|
||||
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {wb_clk_i}]
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {csclk}]
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {mgmt_gpio_in}]
|
||||
|
||||
## FANOUT
|
||||
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
|
||||
|
|
@ -13,6 +13,7 @@
|
|||
# limitations under the License.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# OR COMMIT: 182e733faa149c80f36cfd2198a83dcdeb7853ea
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
|
||||
set ::env(DESIGN_NAME) "housekeeping"
|
||||
|
|
@ -25,14 +26,15 @@ set ::env(VERILOG_FILES) "\
|
|||
$script_dir/../../verilog/rtl/housekeeping.v"
|
||||
|
||||
set ::env(CLOCK_PORT) "wb_clk_i"
|
||||
set ::env(CLOCK_NET) {wb_clk_i csclk mgmt_gpio_in[4]}
|
||||
set ::env(CLOCK_NET) "$::env(CLOCK_PORT) csclk mgmt_gpio_in\[4\]"
|
||||
|
||||
set ::env(BASE_SDC_FILE) $script_dir/base.sdc
|
||||
|
||||
## Synthesis
|
||||
set ::env(NO_SYNTH_CELL_LIST) $script_dir/no_synth.list
|
||||
set ::env(SYNTH_STRATEGY) "AREA 0"
|
||||
|
||||
set ::env(SYNTH_MAX_FANOUT) 10
|
||||
set ::env(SYNTH_MAX_FANOUT) 20
|
||||
|
||||
## Floorplan
|
||||
set ::env(FP_SIZING) absolute
|
||||
|
|
@ -45,7 +47,7 @@ set ::env(FP_IO_MIN_DISTANCE) 2
|
|||
set ::env(CELL_PAD) 0
|
||||
|
||||
## Routing
|
||||
set ::env(GLB_RT_ADJUSTMENT) 0.05
|
||||
set ::env(GLB_RT_ADJUSTMENT) 0.06
|
||||
set ::env(GLB_RT_OVERFLOW_ITERS) 100
|
||||
|
||||
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.17
|
||||
|
|
@ -58,15 +60,11 @@ set ::env(GLB_RT_OBS) "\
|
|||
li1 0 538.84500 300.2300 550.95000"
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.384
|
||||
set ::env(PL_TARGET_DENSITY) 0.378
|
||||
|
||||
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) .17
|
||||
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "30"
|
||||
|
||||
## Diode Insertion
|
||||
set ::env(DIODE_INSERTION_STRATEGY) "3"
|
||||
set ::env(GLB_RT_ANT_ITERS) "7"
|
||||
|
||||
# Disbale timing checks for now till the issue with the clock gating path is fixed
|
||||
# The timing reports show only one violating path from the mgmt_gpio_
|
||||
set ::env(QUIT_ON_TIMING_VIOLATIONS) 0
|
||||
set ::env(GLB_RT_ANT_ITERS) "7"
|
||||
|
|
@ -1 +1 @@
|
|||
openlane 2021.09.09_03.00.48-71-ge0e6fbc
|
||||
openlane 2021.11.23_01.42.34-4-gd30e8f0
|
||||
|
|
|
|||
|
|
@ -1,2 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/home/ma/ef/caravel_openframe/openlane/housekeeping,housekeeping,housekeeping,flow_completed,0h25m7s,-1,64928.89438180887,0.16541171850000005,32464.447190904433,37.52,976.58,5370,0,0,0,0,0,0,0,52,0,66,-1,454708,62134,-1.5,-11.43,-1,0.0,-1,-753.9,-6155.54,-1,0.0,-1,313455162.0,25.69,39.14,63.89,15.31,31.29,2.02,8469,9603,194,1275,0,0,0,9230,0,0,0,0,0,0,0,4,1066,991,49,388,2156,0,2544,90.9090909090909,11.0,10.0,AREA 0,10,50,1,153.6,153.18,0.384,0.05,sky130_fd_sc_hd,0,3
|
||||
0,/home/ma/ef/caravel_openframe/openlane/housekeeping,housekeeping,housekeeping,flow completed,0h41m37s0ms,0h39m53s0ms,64674.9825043381,0.16541171850000005,32337.49125216905,37.46,1665.97,5349,0,0,0,0,0,0,0,37,0,0,-1,450469,59541,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,309143746.0,31.94,38.9,62.05,15.68,33.81,1.61,8469,9603,194,1275,0,0,0,9230,0,0,0,0,0,0,0,4,1066,991,49,388,2156,0,2544,100.0,10.0,10.0,AREA 0,20,50,1,153.6,153.18,0.37799999999999995,0.06,sky130_fd_sc_hd,0,3
|
||||
|
|
|
|||
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue