mirror of https://github.com/efabless/caravel.git
harden gpio_control_block
This commit is contained in:
manarabdelaty
parent
8b055a380c
commit
cb9990f97e
File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,112 @@
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VERSION 5.8 ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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DESIGN gpio_logic_high ;
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UNITS DISTANCE MICRONS 1000 ;
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DIEAREA ( 0 0 ) ( 7000 16000 ) ;
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ROW ROW_0 unithd 0 0 N DO 15 BY 1 STEP 460 0 ;
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ROW ROW_1 unithd 0 2720 FS DO 15 BY 1 STEP 460 0 ;
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ROW ROW_2 unithd 0 5440 N DO 15 BY 1 STEP 460 0 ;
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ROW ROW_3 unithd 0 8160 FS DO 15 BY 1 STEP 460 0 ;
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ROW ROW_4 unithd 0 10880 N DO 15 BY 1 STEP 460 0 ;
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TRACKS X 230 DO 15 STEP 460 LAYER li1 ;
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TRACKS Y 170 DO 47 STEP 340 LAYER li1 ;
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TRACKS X 170 DO 21 STEP 340 LAYER met1 ;
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TRACKS Y 170 DO 47 STEP 340 LAYER met1 ;
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TRACKS X 230 DO 15 STEP 460 LAYER met2 ;
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TRACKS Y 230 DO 35 STEP 460 LAYER met2 ;
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TRACKS X 340 DO 10 STEP 680 LAYER met3 ;
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TRACKS Y 340 DO 24 STEP 680 LAYER met3 ;
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TRACKS X 460 DO 8 STEP 920 LAYER met4 ;
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TRACKS Y 460 DO 17 STEP 920 LAYER met4 ;
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TRACKS X 1700 DO 2 STEP 3400 LAYER met5 ;
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TRACKS Y 1700 DO 5 STEP 3400 LAYER met5 ;
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GCELLGRID X 0 DO 1 STEP 6900 ;
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GCELLGRID Y 0 DO 3 STEP 6900 ;
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VIAS 3 ;
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- via_1400x480 + VIARULE M1M2_PR + CUTSIZE 150 150 + LAYERS met1 via met2 + CUTSPACING 170 170 + ENCLOSURE 145 165 55 165 + ROWCOL 1 4 ;
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- via2_1400x480 + VIARULE M2M3_PR + CUTSIZE 200 200 + LAYERS met2 via2 met3 + CUTSPACING 200 200 + ENCLOSURE 40 140 200 65 + ROWCOL 1 3 ;
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- via3_1400x480 + VIARULE M3M4_PR + CUTSIZE 200 200 + LAYERS met3 via3 met4 + CUTSPACING 200 200 + ENCLOSURE 200 60 200 140 + ROWCOL 1 3 ;
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END VIAS
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COMPONENTS 26 ;
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- FILLER_0_3 sky130_fd_sc_hd__decap_4 + PLACED ( 1380 0 ) N ;
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- FILLER_0_7 sky130_fd_sc_hd__fill_1 + PLACED ( 3220 0 ) N ;
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- FILLER_0_9 sky130_fd_sc_hd__decap_3 + PLACED ( 4140 0 ) N ;
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- FILLER_1_11 sky130_fd_sc_hd__fill_1 + PLACED ( 5060 2720 ) FS ;
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- FILLER_1_3 sky130_fd_sc_hd__decap_8 + PLACED ( 1380 2720 ) FS ;
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- FILLER_2_3 sky130_fd_sc_hd__decap_4 + PLACED ( 1380 5440 ) N ;
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- FILLER_2_7 sky130_fd_sc_hd__fill_1 + PLACED ( 3220 5440 ) N ;
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- FILLER_2_9 sky130_fd_sc_hd__decap_3 + PLACED ( 4140 5440 ) N ;
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- FILLER_3_3 sky130_fd_sc_hd__decap_6 + PLACED ( 1380 8160 ) FS ;
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- FILLER_4_3 sky130_fd_sc_hd__decap_4 + PLACED ( 1380 10880 ) N ;
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- FILLER_4_7 sky130_fd_sc_hd__fill_1 + PLACED ( 3220 10880 ) N ;
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- FILLER_4_9 sky130_fd_sc_hd__decap_3 + PLACED ( 4140 10880 ) N ;
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- PHY_0 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 0 0 ) N ;
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- PHY_1 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 0 ) FN ;
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- PHY_2 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 0 2720 ) FS ;
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- PHY_3 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 2720 ) S ;
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- PHY_4 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 0 5440 ) N ;
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- PHY_5 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 5440 ) FN ;
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- PHY_6 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 0 8160 ) FS ;
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- PHY_7 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 8160 ) S ;
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- PHY_8 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 0 10880 ) N ;
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- PHY_9 sky130_fd_sc_hd__decap_3 + SOURCE DIST + FIXED ( 5520 10880 ) FN ;
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- TAP_10 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 3680 0 ) N ;
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- TAP_11 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 3680 5440 ) N ;
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- TAP_12 sky130_fd_sc_hd__tapvpwrvgnd_1 + SOURCE DIST + FIXED ( 3680 10880 ) N ;
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- gpio_logic_high sky130_fd_sc_hd__conb_1 + PLACED ( 4140 8160 ) S ;
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END COMPONENTS
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PINS 3 ;
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- gpio_logic1 + NET gpio_logic1 + DIRECTION OUTPUT + USE SIGNAL
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+ PORT
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+ LAYER met3 ( -2000 -300 ) ( 2000 300 )
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+ PLACED ( 5000 8500 ) N ;
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- vccd1 + NET vccd1 + SPECIAL + DIRECTION INPUT + USE POWER
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+ PORT
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+ LAYER met4 ( -700 -7040 ) ( 700 7040 )
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+ FIXED ( 1000 6800 ) N ;
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- vssd1 + NET vssd1 + SPECIAL + DIRECTION INPUT + USE GROUND
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+ PORT
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+ LAYER met4 ( -700 -7040 ) ( 700 7040 )
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+ FIXED ( 4700 6800 ) N ;
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END PINS
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SPECIALNETS 2 ;
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- vccd1 ( PIN vccd1 ) ( * VPB ) ( * VPWR ) + USE POWER
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+ ROUTED met3 0 + SHAPE STRIPE ( 1000 13600 ) via3_1400x480
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NEW met2 0 + SHAPE STRIPE ( 1000 13600 ) via2_1400x480
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NEW met1 0 + SHAPE STRIPE ( 1000 13600 ) via_1400x480
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NEW met3 0 + SHAPE STRIPE ( 1000 8160 ) via3_1400x480
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NEW met2 0 + SHAPE STRIPE ( 1000 8160 ) via2_1400x480
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NEW met1 0 + SHAPE STRIPE ( 1000 8160 ) via_1400x480
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NEW met3 0 + SHAPE STRIPE ( 1000 2720 ) via3_1400x480
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NEW met2 0 + SHAPE STRIPE ( 1000 2720 ) via2_1400x480
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NEW met1 0 + SHAPE STRIPE ( 1000 2720 ) via_1400x480
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NEW met4 1400 + SHAPE STRIPE ( 1000 -240 ) ( 1000 13840 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 0 13600 ) ( 6900 13600 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 0 8160 ) ( 6900 8160 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 0 2720 ) ( 6900 2720 ) ;
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- vssd1 ( PIN vssd1 ) ( * VNB ) ( * VGND ) + USE GROUND
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+ ROUTED met3 0 + SHAPE STRIPE ( 4700 10880 ) via3_1400x480
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NEW met2 0 + SHAPE STRIPE ( 4700 10880 ) via2_1400x480
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NEW met1 0 + SHAPE STRIPE ( 4700 10880 ) via_1400x480
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NEW met3 0 + SHAPE STRIPE ( 4700 5440 ) via3_1400x480
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NEW met2 0 + SHAPE STRIPE ( 4700 5440 ) via2_1400x480
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NEW met1 0 + SHAPE STRIPE ( 4700 5440 ) via_1400x480
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NEW met3 0 + SHAPE STRIPE ( 4700 0 ) via3_1400x480
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NEW met2 0 + SHAPE STRIPE ( 4700 0 ) via2_1400x480
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NEW met1 0 + SHAPE STRIPE ( 4700 0 ) via_1400x480
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NEW met4 1400 + SHAPE STRIPE ( 4700 -240 ) ( 4700 13840 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 0 10880 ) ( 6900 10880 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 0 5440 ) ( 6900 5440 )
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NEW met1 480 + SHAPE FOLLOWPIN ( 0 0 ) ( 6900 0 ) ;
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END SPECIALNETS
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NETS 1 ;
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- gpio_logic1 ( PIN gpio_logic1 ) ( gpio_logic_high HI ) + USE SIGNAL
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+ ROUTED met3 ( 2530 8500 ) ( 3220 * 0 )
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NEW met2 ( 2530 8500 ) ( * 9350 )
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NEW met1 ( 2530 9350 ) ( 5290 * )
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NEW met2 ( 2530 8500 ) M2M3_PR_M
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NEW met1 ( 2530 9350 ) M1M2_PR
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NEW li1 ( 5290 9350 ) L1M1_PR_MR ;
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END NETS
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END DESIGN
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Binary file not shown.
Binary file not shown.
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@ -0,0 +1,544 @@
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VERSION 5.7 ;
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NOWIREEXTENSIONATPIN ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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MACRO gpio_control_block
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CLASS BLOCK ;
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FOREIGN gpio_control_block ;
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ORIGIN 0.000 0.000 ;
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SIZE 170.000 BY 70.000 ;
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PIN gpio_defaults[0]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 8.200 170.000 8.800 ;
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END
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END gpio_defaults[0]
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PIN gpio_defaults[10]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 24.520 170.000 25.120 ;
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END
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END gpio_defaults[10]
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PIN gpio_defaults[11]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 26.560 170.000 27.160 ;
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END
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END gpio_defaults[11]
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PIN gpio_defaults[12]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 27.920 170.000 28.520 ;
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END
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END gpio_defaults[12]
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PIN gpio_defaults[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 10.240 170.000 10.840 ;
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END
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END gpio_defaults[1]
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PIN gpio_defaults[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 11.600 170.000 12.200 ;
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END
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END gpio_defaults[2]
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PIN gpio_defaults[3]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 13.640 170.000 14.240 ;
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END
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END gpio_defaults[3]
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PIN gpio_defaults[4]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 15.000 170.000 15.600 ;
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END
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END gpio_defaults[4]
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PIN gpio_defaults[5]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 16.360 170.000 16.960 ;
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END
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END gpio_defaults[5]
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PIN gpio_defaults[6]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 18.400 170.000 19.000 ;
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END
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END gpio_defaults[6]
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PIN gpio_defaults[7]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 19.760 170.000 20.360 ;
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END
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END gpio_defaults[7]
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PIN gpio_defaults[8]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 21.800 170.000 22.400 ;
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END
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END gpio_defaults[8]
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PIN gpio_defaults[9]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 23.160 170.000 23.760 ;
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END
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END gpio_defaults[9]
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PIN mgmt_gpio_in
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 3.440 170.000 4.040 ;
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END
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END mgmt_gpio_in
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PIN mgmt_gpio_oeb
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 5.480 170.000 6.080 ;
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END
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END mgmt_gpio_oeb
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PIN mgmt_gpio_out
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 6.840 170.000 7.440 ;
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END
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END mgmt_gpio_out
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PIN one
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 2.080 170.000 2.680 ;
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END
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END one
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PIN pad_gpio_ana_en
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 29.960 170.000 30.560 ;
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END
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END pad_gpio_ana_en
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PIN pad_gpio_ana_pol
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 31.320 170.000 31.920 ;
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END
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END pad_gpio_ana_pol
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PIN pad_gpio_ana_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 32.680 170.000 33.280 ;
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END
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END pad_gpio_ana_sel
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PIN pad_gpio_dm[0]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 34.720 170.000 35.320 ;
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END
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END pad_gpio_dm[0]
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PIN pad_gpio_dm[1]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 36.080 170.000 36.680 ;
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END
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END pad_gpio_dm[1]
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PIN pad_gpio_dm[2]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 38.120 170.000 38.720 ;
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END
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END pad_gpio_dm[2]
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PIN pad_gpio_holdover
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 39.480 170.000 40.080 ;
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END
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END pad_gpio_holdover
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PIN pad_gpio_ib_mode_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 40.840 170.000 41.440 ;
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END
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END pad_gpio_ib_mode_sel
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PIN pad_gpio_in
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 42.880 170.000 43.480 ;
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END
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END pad_gpio_in
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PIN pad_gpio_inenb
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 44.240 170.000 44.840 ;
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END
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END pad_gpio_inenb
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PIN pad_gpio_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 46.280 170.000 46.880 ;
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END
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END pad_gpio_out
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PIN pad_gpio_outenb
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 47.640 170.000 48.240 ;
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END
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END pad_gpio_outenb
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PIN pad_gpio_slow_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 49.000 170.000 49.600 ;
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END
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END pad_gpio_slow_sel
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PIN pad_gpio_vtrip_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 51.040 170.000 51.640 ;
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END
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END pad_gpio_vtrip_sel
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PIN resetn
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 52.400 170.000 53.000 ;
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END
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END resetn
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PIN resetn_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 54.440 170.000 55.040 ;
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END
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END resetn_out
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PIN serial_clock
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 55.800 170.000 56.400 ;
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END
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END serial_clock
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PIN serial_clock_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 57.160 170.000 57.760 ;
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END
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END serial_clock_out
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PIN serial_data_in
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 59.200 170.000 59.800 ;
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END
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END serial_data_in
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PIN serial_data_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 60.560 170.000 61.160 ;
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END
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END serial_data_out
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PIN serial_load
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 62.600 170.000 63.200 ;
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END
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END serial_load
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PIN serial_load_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
|
||||
LAYER met3 ;
|
||||
RECT 70.000 63.960 170.000 64.560 ;
|
||||
END
|
||||
END serial_load_out
|
||||
PIN user_gpio_in
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 70.000 65.320 170.000 65.920 ;
|
||||
END
|
||||
END user_gpio_in
|
||||
PIN user_gpio_oeb
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 70.000 67.360 170.000 67.960 ;
|
||||
END
|
||||
END user_gpio_oeb
|
||||
PIN user_gpio_out
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 70.000 68.720 170.000 69.320 ;
|
||||
END
|
||||
END user_gpio_out
|
||||
PIN vccd
|
||||
DIRECTION INPUT ;
|
||||
USE POWER ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 1.800 8.080 52.020 9.680 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 12.080 55.320 13.680 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 27.580 55.320 29.180 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 43.080 55.320 44.680 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 1.800 58.320 52.020 59.920 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 1.800 8.080 3.400 59.920 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 50.420 8.080 52.020 59.920 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 12.800 4.780 14.400 63.220 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 28.300 4.780 29.900 63.220 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 43.800 4.780 45.400 63.220 ;
|
||||
END
|
||||
END vccd
|
||||
PIN vccd1
|
||||
DIRECTION INPUT ;
|
||||
USE POWER ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -4.800 1.480 58.620 3.080 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 16.580 61.920 18.180 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 32.080 61.920 33.680 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 47.580 61.920 49.180 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -4.800 64.920 58.620 66.520 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT -4.800 1.480 -3.200 66.520 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 57.020 1.480 58.620 66.520 ;
|
||||
END
|
||||
END vccd1
|
||||
PIN vssd
|
||||
DIRECTION INPUT ;
|
||||
USE GROUND ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 4.780 55.320 6.380 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 19.830 55.320 21.430 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 35.330 55.320 36.930 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 50.830 55.320 52.430 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -1.500 61.620 55.320 63.220 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT -1.500 4.780 0.100 63.220 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 20.550 4.780 22.150 63.220 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 36.050 4.780 37.650 63.220 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 53.720 4.780 55.320 63.220 ;
|
||||
END
|
||||
END vssd
|
||||
PIN vssd1
|
||||
DIRECTION INPUT ;
|
||||
USE GROUND ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 -1.820 61.920 -0.220 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 24.330 61.920 25.930 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 39.830 61.920 41.430 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT -8.100 68.220 61.920 69.820 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT -8.100 -1.820 -6.500 69.820 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 60.320 -1.820 61.920 69.820 ;
|
||||
END
|
||||
END vssd1
|
||||
PIN zero
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 70.000 0.720 170.000 1.320 ;
|
||||
END
|
||||
END zero
|
||||
OBS
|
||||
LAYER li1 ;
|
||||
RECT 4.600 10.795 49.535 57.205 ;
|
||||
LAYER met1 ;
|
||||
RECT 4.600 9.900 114.010 59.800 ;
|
||||
LAYER met2 ;
|
||||
RECT 5.150 0.835 113.990 69.205 ;
|
||||
LAYER met3 ;
|
||||
RECT 5.125 66.960 69.600 69.185 ;
|
||||
RECT 5.125 66.320 70.000 66.960 ;
|
||||
RECT 5.125 62.200 69.600 66.320 ;
|
||||
RECT 5.125 61.560 70.000 62.200 ;
|
||||
RECT 5.125 58.800 69.600 61.560 ;
|
||||
RECT 5.125 58.160 70.000 58.800 ;
|
||||
RECT 5.125 54.040 69.600 58.160 ;
|
||||
RECT 5.125 53.400 70.000 54.040 ;
|
||||
RECT 5.125 50.640 69.600 53.400 ;
|
||||
RECT 5.125 50.000 70.000 50.640 ;
|
||||
RECT 5.125 45.880 69.600 50.000 ;
|
||||
RECT 5.125 45.240 70.000 45.880 ;
|
||||
RECT 5.125 42.480 69.600 45.240 ;
|
||||
RECT 5.125 41.840 70.000 42.480 ;
|
||||
RECT 5.125 37.720 69.600 41.840 ;
|
||||
RECT 5.125 37.080 70.000 37.720 ;
|
||||
RECT 5.125 34.320 69.600 37.080 ;
|
||||
RECT 5.125 33.680 70.000 34.320 ;
|
||||
RECT 5.125 29.560 69.600 33.680 ;
|
||||
RECT 5.125 28.920 70.000 29.560 ;
|
||||
RECT 5.125 26.160 69.600 28.920 ;
|
||||
RECT 5.125 25.520 70.000 26.160 ;
|
||||
RECT 5.125 21.400 69.600 25.520 ;
|
||||
RECT 5.125 20.760 70.000 21.400 ;
|
||||
RECT 5.125 18.000 69.600 20.760 ;
|
||||
RECT 5.125 17.360 70.000 18.000 ;
|
||||
RECT 5.125 13.240 69.600 17.360 ;
|
||||
RECT 5.125 12.600 70.000 13.240 ;
|
||||
RECT 5.125 9.840 69.600 12.600 ;
|
||||
RECT 5.125 9.200 70.000 9.840 ;
|
||||
RECT 5.125 5.080 69.600 9.200 ;
|
||||
RECT 5.125 4.440 70.000 5.080 ;
|
||||
RECT 5.125 0.855 69.600 4.440 ;
|
||||
LAYER met4 ;
|
||||
RECT 6.280 13.160 11.380 27.240 ;
|
||||
END
|
||||
END gpio_control_block
|
||||
END LIBRARY
|
||||
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
VERSION 5.7 ;
|
||||
NOWIREEXTENSIONATPIN ON ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
MACRO gpio_logic_high
|
||||
CLASS BLOCK ;
|
||||
FOREIGN gpio_logic_high ;
|
||||
ORIGIN 0.000 0.000 ;
|
||||
SIZE 7.000 BY 16.000 ;
|
||||
PIN gpio_logic1
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 3.000 8.200 7.000 8.800 ;
|
||||
END
|
||||
END gpio_logic1
|
||||
PIN vccd1
|
||||
DIRECTION INPUT ;
|
||||
USE POWER ;
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 0.300 -0.240 1.700 13.840 ;
|
||||
END
|
||||
END vccd1
|
||||
PIN vssd1
|
||||
DIRECTION INPUT ;
|
||||
USE GROUND ;
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 4.000 -0.240 5.400 13.840 ;
|
||||
END
|
||||
END vssd1
|
||||
OBS
|
||||
LAYER nwell ;
|
||||
RECT -0.190 12.185 7.090 13.790 ;
|
||||
RECT -0.190 6.745 7.090 9.575 ;
|
||||
RECT -0.190 1.305 7.090 4.135 ;
|
||||
LAYER pwell ;
|
||||
RECT 0.145 -0.085 0.315 0.085 ;
|
||||
RECT 1.525 -0.085 1.695 0.085 ;
|
||||
RECT 3.360 -0.055 3.480 0.055 ;
|
||||
RECT 4.285 -0.085 4.455 0.085 ;
|
||||
RECT 6.585 -0.085 6.755 0.085 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 0.085 6.900 13.685 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 -0.085 6.900 0.085 ;
|
||||
LAYER met1 ;
|
||||
RECT 0.000 -0.240 6.900 13.840 ;
|
||||
LAYER met2 ;
|
||||
RECT 0.390 0.000 5.310 13.840 ;
|
||||
RECT 4.090 -0.240 5.310 0.000 ;
|
||||
LAYER met3 ;
|
||||
RECT 0.300 9.200 5.400 13.765 ;
|
||||
RECT 0.300 7.800 2.600 9.200 ;
|
||||
RECT 0.300 0.000 5.400 7.800 ;
|
||||
RECT 4.000 -0.165 5.400 0.000 ;
|
||||
END
|
||||
END gpio_logic_high
|
||||
END LIBRARY
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,284 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1636035202
|
||||
<< obsli1 >>
|
||||
rect 920 2159 9907 11441
|
||||
<< obsm1 >>
|
||||
rect 920 1980 22802 11960
|
||||
<< obsm2 >>
|
||||
rect 1030 167 22798 13841
|
||||
<< metal3 >>
|
||||
rect 14000 13744 34000 13864
|
||||
rect 14000 13472 34000 13592
|
||||
rect 14000 13064 34000 13184
|
||||
rect 14000 12792 34000 12912
|
||||
rect 14000 12520 34000 12640
|
||||
rect 14000 12112 34000 12232
|
||||
rect 14000 11840 34000 11960
|
||||
rect 14000 11432 34000 11552
|
||||
rect 14000 11160 34000 11280
|
||||
rect 14000 10888 34000 11008
|
||||
rect 14000 10480 34000 10600
|
||||
rect 14000 10208 34000 10328
|
||||
rect 14000 9800 34000 9920
|
||||
rect 14000 9528 34000 9648
|
||||
rect 14000 9256 34000 9376
|
||||
rect 14000 8848 34000 8968
|
||||
rect 14000 8576 34000 8696
|
||||
rect 14000 8168 34000 8288
|
||||
rect 14000 7896 34000 8016
|
||||
rect 14000 7624 34000 7744
|
||||
rect 14000 7216 34000 7336
|
||||
rect 14000 6944 34000 7064
|
||||
rect 14000 6536 34000 6656
|
||||
rect 14000 6264 34000 6384
|
||||
rect 14000 5992 34000 6112
|
||||
rect 14000 5584 34000 5704
|
||||
rect 14000 5312 34000 5432
|
||||
rect 14000 4904 34000 5024
|
||||
rect 14000 4632 34000 4752
|
||||
rect 14000 4360 34000 4480
|
||||
rect 14000 3952 34000 4072
|
||||
rect 14000 3680 34000 3800
|
||||
rect 14000 3272 34000 3392
|
||||
rect 14000 3000 34000 3120
|
||||
rect 14000 2728 34000 2848
|
||||
rect 14000 2320 34000 2440
|
||||
rect 14000 2048 34000 2168
|
||||
rect 14000 1640 34000 1760
|
||||
rect 14000 1368 34000 1488
|
||||
rect 14000 1096 34000 1216
|
||||
rect 14000 688 34000 808
|
||||
rect 14000 416 34000 536
|
||||
rect 14000 144 34000 264
|
||||
<< obsm3 >>
|
||||
rect 1025 13392 13920 13837
|
||||
rect 1025 13264 14000 13392
|
||||
rect 1025 12440 13920 13264
|
||||
rect 1025 12312 14000 12440
|
||||
rect 1025 11760 13920 12312
|
||||
rect 1025 11632 14000 11760
|
||||
rect 1025 10808 13920 11632
|
||||
rect 1025 10680 14000 10808
|
||||
rect 1025 10128 13920 10680
|
||||
rect 1025 10000 14000 10128
|
||||
rect 1025 9176 13920 10000
|
||||
rect 1025 9048 14000 9176
|
||||
rect 1025 8496 13920 9048
|
||||
rect 1025 8368 14000 8496
|
||||
rect 1025 7544 13920 8368
|
||||
rect 1025 7416 14000 7544
|
||||
rect 1025 6864 13920 7416
|
||||
rect 1025 6736 14000 6864
|
||||
rect 1025 5912 13920 6736
|
||||
rect 1025 5784 14000 5912
|
||||
rect 1025 5232 13920 5784
|
||||
rect 1025 5104 14000 5232
|
||||
rect 1025 4280 13920 5104
|
||||
rect 1025 4152 14000 4280
|
||||
rect 1025 3600 13920 4152
|
||||
rect 1025 3472 14000 3600
|
||||
rect 1025 2648 13920 3472
|
||||
rect 1025 2520 14000 2648
|
||||
rect 1025 1968 13920 2520
|
||||
rect 1025 1840 14000 1968
|
||||
rect 1025 1016 13920 1840
|
||||
rect 1025 888 14000 1016
|
||||
rect 1025 171 13920 888
|
||||
<< metal4 >>
|
||||
rect -1620 -364 -1300 13964
|
||||
rect -960 296 -640 13304
|
||||
rect -300 956 20 12644
|
||||
rect 360 1616 680 11984
|
||||
rect 2560 956 2880 12644
|
||||
rect 4110 956 4430 12644
|
||||
rect 5660 956 5980 12644
|
||||
rect 7210 956 7530 12644
|
||||
rect 8760 956 9080 12644
|
||||
rect 10084 1616 10404 11984
|
||||
rect 10744 956 11064 12644
|
||||
rect 11404 296 11724 13304
|
||||
rect 12064 -364 12384 13964
|
||||
<< obsm4 >>
|
||||
rect 1256 2632 2276 5448
|
||||
<< metal5 >>
|
||||
rect -1620 13644 12384 13964
|
||||
rect -960 12984 11724 13304
|
||||
rect -300 12324 11064 12644
|
||||
rect 360 11664 10404 11984
|
||||
rect -300 10166 11064 10486
|
||||
rect -1620 9516 12384 9836
|
||||
rect -300 8616 11064 8936
|
||||
rect -1620 7966 12384 8286
|
||||
rect -300 7066 11064 7386
|
||||
rect -1620 6416 12384 6736
|
||||
rect -300 5516 11064 5836
|
||||
rect -1620 4866 12384 5186
|
||||
rect -300 3966 11064 4286
|
||||
rect -1620 3316 12384 3636
|
||||
rect -300 2416 11064 2736
|
||||
rect 360 1616 10404 1936
|
||||
rect -300 956 11064 1276
|
||||
rect -960 296 11724 616
|
||||
rect -1620 -364 12384 -44
|
||||
<< labels >>
|
||||
rlabel metal3 s 14000 1640 34000 1760 6 gpio_defaults[0]
|
||||
port 1 nsew signal input
|
||||
rlabel metal3 s 14000 4904 34000 5024 6 gpio_defaults[10]
|
||||
port 2 nsew signal input
|
||||
rlabel metal3 s 14000 5312 34000 5432 6 gpio_defaults[11]
|
||||
port 3 nsew signal input
|
||||
rlabel metal3 s 14000 5584 34000 5704 6 gpio_defaults[12]
|
||||
port 4 nsew signal input
|
||||
rlabel metal3 s 14000 2048 34000 2168 6 gpio_defaults[1]
|
||||
port 5 nsew signal input
|
||||
rlabel metal3 s 14000 2320 34000 2440 6 gpio_defaults[2]
|
||||
port 6 nsew signal input
|
||||
rlabel metal3 s 14000 2728 34000 2848 6 gpio_defaults[3]
|
||||
port 7 nsew signal input
|
||||
rlabel metal3 s 14000 3000 34000 3120 6 gpio_defaults[4]
|
||||
port 8 nsew signal input
|
||||
rlabel metal3 s 14000 3272 34000 3392 6 gpio_defaults[5]
|
||||
port 9 nsew signal input
|
||||
rlabel metal3 s 14000 3680 34000 3800 6 gpio_defaults[6]
|
||||
port 10 nsew signal input
|
||||
rlabel metal3 s 14000 3952 34000 4072 6 gpio_defaults[7]
|
||||
port 11 nsew signal input
|
||||
rlabel metal3 s 14000 4360 34000 4480 6 gpio_defaults[8]
|
||||
port 12 nsew signal input
|
||||
rlabel metal3 s 14000 4632 34000 4752 6 gpio_defaults[9]
|
||||
port 13 nsew signal input
|
||||
rlabel metal3 s 14000 688 34000 808 6 mgmt_gpio_in
|
||||
port 14 nsew signal output
|
||||
rlabel metal3 s 14000 1096 34000 1216 6 mgmt_gpio_oeb
|
||||
port 15 nsew signal input
|
||||
rlabel metal3 s 14000 1368 34000 1488 6 mgmt_gpio_out
|
||||
port 16 nsew signal input
|
||||
rlabel metal3 s 14000 416 34000 536 6 one
|
||||
port 17 nsew signal output
|
||||
rlabel metal3 s 14000 5992 34000 6112 6 pad_gpio_ana_en
|
||||
port 18 nsew signal output
|
||||
rlabel metal3 s 14000 6264 34000 6384 6 pad_gpio_ana_pol
|
||||
port 19 nsew signal output
|
||||
rlabel metal3 s 14000 6536 34000 6656 6 pad_gpio_ana_sel
|
||||
port 20 nsew signal output
|
||||
rlabel metal3 s 14000 6944 34000 7064 6 pad_gpio_dm[0]
|
||||
port 21 nsew signal output
|
||||
rlabel metal3 s 14000 7216 34000 7336 6 pad_gpio_dm[1]
|
||||
port 22 nsew signal output
|
||||
rlabel metal3 s 14000 7624 34000 7744 6 pad_gpio_dm[2]
|
||||
port 23 nsew signal output
|
||||
rlabel metal3 s 14000 7896 34000 8016 6 pad_gpio_holdover
|
||||
port 24 nsew signal output
|
||||
rlabel metal3 s 14000 8168 34000 8288 6 pad_gpio_ib_mode_sel
|
||||
port 25 nsew signal output
|
||||
rlabel metal3 s 14000 8576 34000 8696 6 pad_gpio_in
|
||||
port 26 nsew signal input
|
||||
rlabel metal3 s 14000 8848 34000 8968 6 pad_gpio_inenb
|
||||
port 27 nsew signal output
|
||||
rlabel metal3 s 14000 9256 34000 9376 6 pad_gpio_out
|
||||
port 28 nsew signal output
|
||||
rlabel metal3 s 14000 9528 34000 9648 6 pad_gpio_outenb
|
||||
port 29 nsew signal output
|
||||
rlabel metal3 s 14000 9800 34000 9920 6 pad_gpio_slow_sel
|
||||
port 30 nsew signal output
|
||||
rlabel metal3 s 14000 10208 34000 10328 6 pad_gpio_vtrip_sel
|
||||
port 31 nsew signal output
|
||||
rlabel metal3 s 14000 10480 34000 10600 6 resetn
|
||||
port 32 nsew signal input
|
||||
rlabel metal3 s 14000 10888 34000 11008 6 resetn_out
|
||||
port 33 nsew signal output
|
||||
rlabel metal3 s 14000 11160 34000 11280 6 serial_clock
|
||||
port 34 nsew signal input
|
||||
rlabel metal3 s 14000 11432 34000 11552 6 serial_clock_out
|
||||
port 35 nsew signal output
|
||||
rlabel metal3 s 14000 11840 34000 11960 6 serial_data_in
|
||||
port 36 nsew signal input
|
||||
rlabel metal3 s 14000 12112 34000 12232 6 serial_data_out
|
||||
port 37 nsew signal output
|
||||
rlabel metal3 s 14000 12520 34000 12640 6 serial_load
|
||||
port 38 nsew signal input
|
||||
rlabel metal3 s 14000 12792 34000 12912 6 serial_load_out
|
||||
port 39 nsew signal output
|
||||
rlabel metal3 s 14000 13064 34000 13184 6 user_gpio_in
|
||||
port 40 nsew signal output
|
||||
rlabel metal3 s 14000 13472 34000 13592 6 user_gpio_oeb
|
||||
port 41 nsew signal input
|
||||
rlabel metal3 s 14000 13744 34000 13864 6 user_gpio_out
|
||||
port 42 nsew signal input
|
||||
rlabel metal5 s 360 1616 10404 1936 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s -300 2416 11064 2736 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s -300 5516 11064 5836 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s -300 8616 11064 8936 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s 360 11664 10404 11984 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal4 s 360 1616 680 11984 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal4 s 10084 1616 10404 11984 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal4 s 2560 956 2880 12644 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal4 s 5660 956 5980 12644 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal4 s 8760 956 9080 12644 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s -960 296 11724 616 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal5 s -1620 3316 12384 3636 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal5 s -1620 6416 12384 6736 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal5 s -1620 9516 12384 9836 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal5 s -960 12984 11724 13304 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal4 s -960 296 -640 13304 4 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal4 s 11404 296 11724 13304 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal5 s -300 956 11064 1276 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal5 s -300 3966 11064 4286 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal5 s -300 7066 11064 7386 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal5 s -300 10166 11064 10486 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal5 s -300 12324 11064 12644 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal4 s -300 956 20 12644 4 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal4 s 4110 956 4430 12644 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal4 s 7210 956 7530 12644 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal4 s 10744 956 11064 12644 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal5 s -1620 -364 12384 -44 8 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal5 s -1620 4866 12384 5186 6 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal5 s -1620 7966 12384 8286 6 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal5 s -1620 13644 12384 13964 6 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal4 s -1620 -364 -1300 13964 4 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal4 s 12064 -364 12384 13964 6 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal3 s 14000 144 34000 264 6 zero
|
||||
port 47 nsew signal output
|
||||
<< properties >>
|
||||
string LEFclass BLOCK
|
||||
string FIXED_BBOX 0 0 34000 14000
|
||||
string LEFview TRUE
|
||||
string GDS_FILE ../gds/gpio_control_block.gds
|
||||
string GDS_END 596056
|
||||
string GDS_START 155690
|
||||
<< end >>
|
||||
|
||||
|
|
@ -0,0 +1,47 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1636033646
|
||||
<< nwell >>
|
||||
rect -38 2437 1418 2758
|
||||
rect -38 1349 1418 1915
|
||||
rect -38 261 1418 827
|
||||
<< pwell >>
|
||||
rect 29 -17 63 17
|
||||
rect 305 -17 339 17
|
||||
rect 672 -11 696 11
|
||||
rect 857 -17 891 17
|
||||
rect 1317 -17 1351 17
|
||||
<< obsli1 >>
|
||||
rect 0 -17 1380 2737
|
||||
<< obsm1 >>
|
||||
rect 0 -48 1380 2768
|
||||
<< obsm2 >>
|
||||
rect 78 0 1062 2768
|
||||
rect 818 -48 1062 0
|
||||
<< metal3 >>
|
||||
rect 600 1640 1400 1760
|
||||
<< obsm3 >>
|
||||
rect 60 1840 1080 2753
|
||||
rect 60 1560 520 1840
|
||||
rect 60 0 1080 1560
|
||||
rect 800 -33 1080 0
|
||||
<< metal4 >>
|
||||
rect 60 -48 340 2768
|
||||
rect 800 -48 1080 2768
|
||||
<< labels >>
|
||||
rlabel metal3 s 600 1640 1400 1760 6 gpio_logic1
|
||||
port 1 nsew signal output
|
||||
rlabel metal4 s 60 -48 340 2768 6 vccd1
|
||||
port 2 nsew power input
|
||||
rlabel metal4 s 800 -48 1080 2768 6 vssd1
|
||||
port 3 nsew ground input
|
||||
<< properties >>
|
||||
string LEFclass BLOCK
|
||||
string FIXED_BBOX 0 0 1400 3200
|
||||
string LEFview TRUE
|
||||
string GDS_FILE ../gds/gpio_logic_high.gds
|
||||
string GDS_END 27138
|
||||
string GDS_START 18568
|
||||
<< end >>
|
||||
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
|
||||
set ::env(DESIGN_NAME) gpio_control_block
|
||||
|
||||
set ::env(VERILOG_FILES) "\
|
||||
$script_dir/../../verilog/rtl/defines.v\
|
||||
$script_dir/../../verilog/rtl/gpio_control_block.v"
|
||||
|
||||
|
||||
set ::env(CLOCK_PORT) "serial_clock"
|
||||
set ::env(CLOCK_PERIOD) "25"
|
||||
|
||||
set ::env(VDD_NETS) "vccd vccd1"
|
||||
set ::env(GND_NETS) "vssd vssd1"
|
||||
|
||||
## Synthesis
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
|
||||
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
|
||||
|
||||
## Floorplan
|
||||
set ::env(FP_SIZING) absolute
|
||||
set ::env(DIE_AREA) "0 0 170 70"
|
||||
|
||||
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
|
||||
|
||||
set ::env(FP_IO_VEXTEND) 20
|
||||
set ::env(FP_IO_HLENGTH) 100
|
||||
|
||||
set ::env(RIGHT_MARGIN_MULT) 262
|
||||
set ::env(LEFT_MARGIN_MULT) 10
|
||||
set ::env(TOP_MARGIN_MULT) 4
|
||||
set ::env(BOTTOM_MARGIN_MULT) 4
|
||||
|
||||
set ::env(CELL_PAD) 0
|
||||
|
||||
## PDN
|
||||
set ::env(PDN_CFG) $script_dir/pdn.tcl
|
||||
set ::env(FP_PDN_AUTO_ADJUST) 0
|
||||
set ::env(FP_PDN_CORE_RING) 1
|
||||
|
||||
set ::env(FP_PDN_VWIDTH) 1.6
|
||||
set ::env(FP_PDN_HWIDTH) 1.6
|
||||
|
||||
set ::env(FP_HORIZONTAL_HALO) 2
|
||||
set ::env(FP_VERTICAL_HALO) 2
|
||||
|
||||
set ::env(FP_PDN_HOFFSET) 1.5
|
||||
set ::env(FP_PDN_VOFFSET) 8.5
|
||||
|
||||
set ::env(FP_PDN_HPITCH) 15.5
|
||||
set ::env(FP_PDN_VPITCH) 15.5
|
||||
|
||||
set ::env(FP_PDN_VSPACING) 3.4
|
||||
set ::env(FP_PDN_HSPACING) 3.4
|
||||
|
||||
set ::env(FP_PDN_CORE_RING_VOFFSET) 2
|
||||
set ::env(FP_PDN_CORE_RING_HOFFSET) 2
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.898
|
||||
# for some reason resizer is leaving a floating net after running repair_tie_fanout command
|
||||
set ::env(PL_RESZIER_REPIAR_TIE_FANOUT) 0
|
||||
|
||||
# mgmt_gpio_in is driven by a tristate cell
|
||||
set ::env(DONT_BUFFER_PORTS) "mgmt_gpio_in"
|
||||
|
||||
## Routing
|
||||
set ::env(GLB_RT_MINLAYER) 2
|
||||
set ::env(GLB_RT_MAXLAYER) 4
|
||||
set ::env(GLB_RT_ADJUSTMENT) 0.05
|
||||
|
||||
# Add obstructions on the areas that will lie underneath the padframe
|
||||
set ::env(GLB_RT_OBS) "\
|
||||
met5 67 0 170 70,
|
||||
met4 67 0 170 70,
|
||||
met2 120 0 170 70,
|
||||
met1 120 0 170 70"
|
||||
|
||||
## Internal macros
|
||||
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
|
||||
|
||||
set ::env(VERILOG_FILES_BLACKBOX) "\
|
||||
$script_dir/../../verilog/rtl/gpio_logic_high.v"
|
||||
|
||||
set ::env(EXTRA_LEFS) "\
|
||||
$script_dir/../../lef/gpio_logic_high.lef"
|
||||
|
||||
set ::env(EXTRA_GDS_FILES) "\
|
||||
$script_dir/../../gds/gpio_logic_high.gds"
|
||||
|
|
@ -0,0 +1 @@
|
|||
gpio_logic_high 5.98 13.40 N
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
# Power nets
|
||||
|
||||
if { ! [info exists ::env(VDD_NET)] } {
|
||||
set ::env(VDD_NET) $::env(VDD_PIN)
|
||||
}
|
||||
|
||||
if { ! [info exists ::env(GND_NET)] } {
|
||||
set ::env(GND_NET) $::env(GND_PIN)
|
||||
}
|
||||
|
||||
set ::power_nets $::env(VDD_NET)
|
||||
set ::ground_nets $::env(GND_NET)
|
||||
|
||||
if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
|
||||
if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
|
||||
foreach power_pin $::env(STD_CELL_POWER_PINS) {
|
||||
add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power
|
||||
}
|
||||
foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
|
||||
add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
|
||||
|
||||
# Assesses whether the deisgn is the core of the chip or not based on the
|
||||
# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
|
||||
if { $::env(VDD_NET) == "vccd1" } {
|
||||
# Used if the design is the core of the chip
|
||||
define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
|
||||
add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
} else {
|
||||
# Used if the design is the core of the chip
|
||||
define_pdn_grid -name stdcell_grid -starts_with POWER -voltage_domain CORE -pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_LOWER_LAYER) -width $::env(FP_PDN_VWIDTH) -pitch $::env(FP_PDN_VPITCH) -offset $::env(FP_PDN_VOFFSET) -starts_with POWER
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_UPPER_LAYER) -width $::env(FP_PDN_HWIDTH) -pitch $::env(FP_PDN_HPITCH) -offset $::env(FP_PDN_HOFFSET) -starts_with POWER
|
||||
add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
}
|
||||
|
||||
# Adds the standard cell rails if enabled.
|
||||
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
|
||||
add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
|
||||
}
|
||||
|
||||
|
||||
# Adds the core ring if enabled.
|
||||
if { $::env(FP_PDN_CORE_RING) == 1 } {
|
||||
add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
|
||||
-widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
|
||||
-spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
|
||||
-core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
|
||||
}
|
||||
|
||||
if { $::env(VDD_NET) == "vccd1" } {
|
||||
set macro {
|
||||
orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
power_pins "vccd1"
|
||||
ground_pins "vssd1"
|
||||
blockages $::env(MACRO_BLOCKAGES_LAYER)
|
||||
straps {
|
||||
}
|
||||
connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
|
||||
}
|
||||
set ::halo [list $::env(FP_HORIZONTAL_HALO) $::env(FP_VERTICAL_HALO)]
|
||||
pdngen::specify_grid macro [subst $macro]
|
||||
}
|
||||
|
||||
# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
|
||||
set ::rails_start_with "POWER" ;
|
||||
|
||||
# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
|
||||
set ::stripes_start_with "POWER" ;
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
#E
|
||||
zero
|
||||
one
|
||||
mgmt_.*
|
||||
gpio_defaults.*
|
||||
pad_gpio_ana_en.*
|
||||
pad_gpio_ana_pol.*
|
||||
pad_gpio_ana_sel.*
|
||||
pad_gpio_dm.*
|
||||
pad_gpio_holdover.*
|
||||
pad_gpio_ib_mode_sel.*
|
||||
pad_gpio_in.*
|
||||
pad_gpio_out.*
|
||||
pad_gpio_slow_sel.*
|
||||
pad_gpio_vtrip_sel.*
|
||||
resetn.*
|
||||
serial_clock.*
|
||||
serial_data_in.*
|
||||
serial_data_out.*
|
||||
serial_load.*
|
||||
user_gpio_in.*
|
||||
user_gpio_oeb.*
|
||||
user_gpio_out.*
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
|
||||
set ::env(DESIGN_NAME) gpio_logic_high
|
||||
set ::env(DESIGN_IS_CORE) 0
|
||||
|
||||
set ::env(VERILOG_FILES) "\
|
||||
$script_dir/../../verilog/rtl/defines.v\
|
||||
$script_dir/../../verilog/rtl/gpio_logic_high.v"
|
||||
|
||||
set ::env(CLOCK_PORT) ""
|
||||
set ::env(CLOCK_TREE_SYNTH) 0
|
||||
|
||||
## Synthesis
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
|
||||
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
|
||||
|
||||
## Floorplan
|
||||
set ::env(DIE_AREA) "0 0 7 16"
|
||||
set ::env(FP_SIZING) absolute
|
||||
|
||||
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
|
||||
|
||||
set ::env(FP_HORIZONTAL_HALO) 0
|
||||
set ::env(FP_VERTICAL_HALO) 0
|
||||
|
||||
set ::env(FP_TAPCELL_DIST) 4
|
||||
|
||||
set ::env(TOP_MARGIN_MULT) 0
|
||||
set ::env(BOTTOM_MARGIN_MULT) 0
|
||||
set ::env(LEFT_MARGIN_MULT) 0
|
||||
set ::env(RIGHT_MARGIN_MULT) 0
|
||||
|
||||
set ::env(CELL_PAD) 0
|
||||
|
||||
# Power nets
|
||||
set ::env(VDD_NETS) "vccd1"
|
||||
set ::env(GND_NETS) "vssd1"
|
||||
|
||||
## PDN Configuration
|
||||
set ::env(FP_PDN_AUTO_ADJUST) 0
|
||||
set ::env(FP_PDN_VWIDTH) 1.4
|
||||
set ::env(FP_PDN_VOFFSET) 1
|
||||
set ::env(FP_PDN_VPITCH) 7.4
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.8
|
||||
set ::env(PL_RANDOM_INITIAL_PLACEMENT) 1
|
||||
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
#E
|
||||
gpio_logic1
|
||||
|
|
@ -0,0 +1 @@
|
|||
openlane 2021.09.09_03.00.48-52-gc99f895
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
-ne openlane
|
||||
e6ba5d36a9b32a9f87626d49bf3c80cf3964ebeb
|
||||
-ne skywater-pdk
|
||||
c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
|
||||
-ne open_pdks
|
||||
f90a86bdd133bd629251d59eebb1aee8452c0f5c
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/project/openlane/gpio_control_block,gpio_control_block,gpio_control_block,flow_completed,0h1m57s,-1,21008.403361344535,0.0119,10504.201680672268,78.72,503.91,125,0,0,0,0,0,0,0,0,0,-1,-1,6738,1138,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,4693154.0,0.0,11.71,13.87,28.54,-1,17.24,81,109,48,76,0,0,0,66,0,0,0,0,0,0,0,4,24,44,4,34,25,0,59,38.46153846153846,26,25,AREA 0,5,50,1,15.5,15.5,0.898,0.05,sky130_fd_sc_hd,0,3
|
||||
|
|
|
@ -0,0 +1 @@
|
|||
openlane 2021.09.09_03.00.48-52-gc99f895
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
-ne openlane
|
||||
e6ba5d36a9b32a9f87626d49bf3c80cf3964ebeb
|
||||
-ne skywater-pdk
|
||||
c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
|
||||
-ne open_pdks
|
||||
f90a86bdd133bd629251d59eebb1aee8452c0f5c
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/project/openlane/gpio_logic_high,gpio_logic_high,gpio_logic_high,flow_completed,0h0m51s,-1,17857.14285714286,0.00011200000000000001,8928.57142857143,7.14,441.08,1,0,-1,-1,-1,-1,0,0,-1,0,0,-1,4,3,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,421.0,0.0,0.0,0.0,0.0,0.0,0.0,3,3,3,3,0,0,0,1,0,0,0,0,0,0,0,4,-1,-1,-1,10,3,0,13,90.9090909090909,11.0,10.0,AREA 0,5,50,1,7.4,153.18,0.8,0.0,sky130_fd_sc_hd,0,3
|
||||
|
|
|
@ -0,0 +1,417 @@
|
|||
* NGSPICE file created from gpio_control_block.ext - technology: sky130A
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfbbn_1 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkbuf_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2b_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2b_1 A B_N VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2_1 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2_1 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_1 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__einvp_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__einvp_2 A TE VGND VNB VPB VPWR Z
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkbuf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dlymetal6s2s_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dlymetal6s2s_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__ebufn_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__ebufn_1 A TE_B VGND VNB VPB VPWR Z
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkdlybuf4s25_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkdlybuf4s25_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__mux2_1 A0 A1 S VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for gpio_logic_high abstract view
|
||||
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_12 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_12 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_16 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkbuf_16 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
.subckt gpio_control_block gpio_defaults[0] gpio_defaults[10] gpio_defaults[11] gpio_defaults[12]
|
||||
+ gpio_defaults[1] gpio_defaults[2] gpio_defaults[3] gpio_defaults[4] gpio_defaults[5]
|
||||
+ gpio_defaults[6] gpio_defaults[7] gpio_defaults[8] gpio_defaults[9] mgmt_gpio_in
|
||||
+ mgmt_gpio_oeb mgmt_gpio_out one pad_gpio_ana_en pad_gpio_ana_pol pad_gpio_ana_sel
|
||||
+ pad_gpio_dm[0] pad_gpio_dm[1] pad_gpio_dm[2] pad_gpio_holdover pad_gpio_ib_mode_sel
|
||||
+ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
|
||||
+ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
|
||||
+ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
|
||||
XFILLER_3_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_200_ _162_/X _220_/D _166_/X _164_/X vssd vssd vccd vccd _200_/Q _200_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_0_46 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_131_ _131_/A vssd vssd vccd vccd _131_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_13_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XANTENNA_5 gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_114_ _190_/A _116_/B vssd vssd vccd vccd _115_/A sky130_fd_sc_hd__or2b_1
|
||||
Xoutput31 _202_/Q vssd vssd vccd vccd pad_gpio_inenb sky130_fd_sc_hd__buf_2
|
||||
X_130_ _130_/A vssd vssd vccd vccd _131_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_113_ _113_/A vssd vssd vccd vccd _113_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput32 _196_/X vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_6 gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_12_12 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_189_ _189_/A vssd vssd vccd vccd _189_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_0_59 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_7 gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_112_ _130_/A vssd vssd vccd vccd _113_/A sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput33 _193_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__buf_2
|
||||
XFILLER_3_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_15_9 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_188_ _188_/A vssd vssd vccd vccd _189_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_111_ _111_/A vssd vssd vccd vccd _111_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput34 _200_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_2
|
||||
XFILLER_15_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_8 gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput23 _208_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_2
|
||||
XFILLER_1_92 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_11_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_12_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_187_ _187_/A vssd vssd vccd vccd _187_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_110_ _190_/A _110_/B vssd vssd vccd vccd _111_/A sky130_fd_sc_hd__or2_1
|
||||
Xoutput35 _201_/Q vssd vssd vccd vccd pad_gpio_vtrip_sel sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_9 gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput24 _210_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_2
|
||||
X_186_ one _223_/Q vssd vssd vccd vccd _187_/A sky130_fd_sc_hd__and2_1
|
||||
XFILLER_9_16 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_169_ _190_/A _171_/B vssd vssd vccd vccd _170_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_1_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xoutput36 _190_/X vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_2
|
||||
XFILLER_7_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xoutput25 _209_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_2
|
||||
X_185_ _197_/A vssd vssd vccd vccd _185_/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_4_61 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_168_ _168_/A vssd vssd vccd vccd _168_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput26 _205_/Q vssd vssd vccd vccd pad_gpio_dm[0] sky130_fd_sc_hd__buf_2
|
||||
Xoutput37 _191_/X vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_184_ _184_/A vssd vssd vccd vccd _194_/S sky130_fd_sc_hd__clkbuf_1
|
||||
Xconst_source vssd vssd vccd vccd one zero sky130_fd_sc_hd__conb_1
|
||||
X_219_ _191_/A _219_/D _190_/A vssd vssd vccd vccd _220_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_167_ _188_/A vssd vssd vccd vccd _168_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_1_63 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xoutput38 _187_/X vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_2
|
||||
Xoutput27 _206_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_2
|
||||
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_166_ _166_/A vssd vssd vccd vccd _166_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_183_ _207_/Q _206_/Q vssd vssd vccd vccd _184_/A sky130_fd_sc_hd__or2b_1
|
||||
Xoutput28 _207_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_2
|
||||
Xoutput39 _192_/X vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__buf_2
|
||||
X_218_ _222_/CLK _218_/D _190_/A vssd vssd vccd vccd _219_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_149_ _161_/A vssd vssd vccd vccd _150_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_182_ _182_/A vssd vssd vccd vccd _182_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_165_ _190_/A _165_/B vssd vssd vccd vccd _166_/A sky130_fd_sc_hd__or2_1
|
||||
X_217_ _222_/CLK _217_/D _190_/A vssd vssd vccd vccd _218_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_148_ _148_/A vssd vssd vccd vccd _148_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput29 _199_/Q vssd vssd vccd vccd pad_gpio_holdover sky130_fd_sc_hd__buf_2
|
||||
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_164_ _164_/A vssd vssd vccd vccd _164_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_181_ _204_/Q _195_/S vssd vssd vccd vccd _182_/A sky130_fd_sc_hd__and2_1
|
||||
X_216_ _222_/CLK _216_/D _190_/A vssd vssd vccd vccd _217_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_147_ _190_/A _147_/B vssd vssd vccd vccd _148_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_16_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_180_ _180_/A vssd vssd vccd vccd _180_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_163_ _190_/A _165_/B vssd vssd vccd vccd _164_/A sky130_fd_sc_hd__or2b_1
|
||||
X_129_ _129_/A vssd vssd vccd vccd _129_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_7_77 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_215_ _222_/CLK _215_/D _190_/A vssd vssd vccd vccd _216_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_146_ _146_/A vssd vssd vccd vccd _146_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_162_ _162_/A vssd vssd vccd vccd _162_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput1 gpio_defaults[0] vssd vssd vccd vccd _177_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_145_ _190_/A _147_/B vssd vssd vccd vccd _146_/A sky130_fd_sc_hd__or2b_1
|
||||
X_214_ _222_/CLK _214_/D _190_/A vssd vssd vccd vccd _215_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_128_ _190_/A _128_/B vssd vssd vccd vccd _129_/A sky130_fd_sc_hd__or2_1
|
||||
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_13_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_13_22 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xgpio_in_buf _185_/Y gpio_in_buf/TE vssd vssd vccd vccd output40/A sky130_fd_sc_hd__einvp_2
|
||||
X_161_ _161_/A vssd vssd vccd vccd _162_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_10_23 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xinput2 gpio_defaults[10] vssd vssd vccd vccd _134_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_16_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_213_ _222_/CLK _213_/D _190_/A vssd vssd vccd vccd _214_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_144_ _144_/A vssd vssd vccd vccd _144_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_127_ _127_/A vssd vssd vccd vccd _127_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_16_77 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_16_11 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_160_ _160_/A vssd vssd vccd vccd _160_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_212_ _191_/A _212_/D _190_/A vssd vssd vccd vccd _213_/D sky130_fd_sc_hd__dfrtp_1
|
||||
Xinput3 gpio_defaults[11] vssd vssd vccd vccd _128_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_1_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_143_ _161_/A vssd vssd vccd vccd _144_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_126_ _190_/A _128_/B vssd vssd vccd vccd _127_/A sky130_fd_sc_hd__or2b_1
|
||||
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_109_ _109_/A vssd vssd vccd vccd _109_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput4 gpio_defaults[12] vssd vssd vccd vccd _122_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_211_ _191_/A _211_/D _190_/A vssd vssd vccd vccd _212_/D sky130_fd_sc_hd__dfrtp_1
|
||||
XANTENNA_20 user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_125_ _125_/A vssd vssd vccd vccd _125_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_142_ _142_/A vssd vssd vccd vccd _142_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_2_92 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_108_ _190_/A _110_/B vssd vssd vccd vccd _109_/A sky130_fd_sc_hd__or2b_1
|
||||
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_210_ _189_/X _219_/D _105_/X _103_/X vssd vssd vccd vccd _210_/Q _210_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
Xinput5 gpio_defaults[1] vssd vssd vccd vccd _141_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_141_ _190_/A _141_/B vssd vssd vccd vccd _142_/A sky130_fd_sc_hd__or2_1
|
||||
Xclkbuf_1_1_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _191_/A sky130_fd_sc_hd__clkbuf_2
|
||||
XANTENNA_21 serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_10 gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_124_ _130_/A vssd vssd vccd vccd _125_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_14_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
X_107_ _188_/A vssd vssd vccd vccd _130_/A sky130_fd_sc_hd__dlymetal6s2s_1
|
||||
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_10_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_11 gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xinput6 gpio_defaults[2] vssd vssd vccd vccd _171_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_140_ _140_/A vssd vssd vccd vccd _140_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_40 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_106_ _192_/A vssd vssd vccd vccd _188_/A sky130_fd_sc_hd__inv_2
|
||||
XFILLER_16_15 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_16_7 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xinput20 user_gpio_oeb vssd vssd vccd vccd _193_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
X_123_ _123_/A vssd vssd vccd vccd _123_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput7 gpio_defaults[3] vssd vssd vccd vccd _153_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_10_39 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XTAP_41 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_122_ _190_/A _122_/B vssd vssd vccd vccd _123_/A sky130_fd_sc_hd__or2_1
|
||||
Xinput21 user_gpio_out vssd vssd vccd vccd _196_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
XANTENNA_12 gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_199_ _168_/X _214_/D _172_/X _170_/X vssd vssd vccd vccd _199_/Q _199_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
Xinput10 gpio_defaults[6] vssd vssd vccd vccd _110_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_8_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_105_ _105_/A vssd vssd vccd vccd _105_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_14_82 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_198_ _174_/X _212_/D _178_/X _176_/X vssd vssd vccd vccd _198_/Q _198_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput8 gpio_defaults[4] vssd vssd vccd vccd _147_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_13 mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_121_ _121_/A vssd vssd vccd vccd _121_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_104_ _190_/A _104_/B vssd vssd vccd vccd _105_/A sky130_fd_sc_hd__or2_1
|
||||
Xinput11 gpio_defaults[7] vssd vssd vccd vccd _104_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput9 gpio_defaults[5] vssd vssd vccd vccd _116_/B sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_120_ _190_/A _122_/B vssd vssd vccd vccd _121_/A sky130_fd_sc_hd__or2b_1
|
||||
XANTENNA_14 mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xinput12 gpio_defaults[8] vssd vssd vccd vccd _165_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_197_ _197_/A _180_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_1
|
||||
XFILLER_14_7 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_103_ _103_/A vssd vssd vccd vccd _103_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_196_ _196_/A0 _195_/X _198_/Q vssd vssd vccd vccd _196_/X sky130_fd_sc_hd__mux2_1
|
||||
XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_15 one vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput13 gpio_defaults[9] vssd vssd vccd vccd _159_/B sky130_fd_sc_hd__clkbuf_1
|
||||
X_102_ _190_/A _104_/B vssd vssd vccd vccd _103_/A sky130_fd_sc_hd__or2b_1
|
||||
X_179_ _202_/Q _204_/Q vssd vssd vccd vccd _180_/A sky130_fd_sc_hd__or2b_1
|
||||
XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xgpio_logic_high gpio_in_buf/TE vccd1 vssd1 gpio_logic_high
|
||||
XTAP_34 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_32 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_195_ _195_/A0 _194_/X _195_/S vssd vssd vccd vccd _195_/X sky130_fd_sc_hd__mux2_1
|
||||
Xinput14 mgmt_gpio_oeb vssd vssd vccd vccd _195_/S sky130_fd_sc_hd__clkbuf_1
|
||||
XANTENNA_16 one vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_178_ _178_/A vssd vssd vccd vccd _178_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_10_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_194_ _194_/A0 _195_/A0 _194_/S vssd vssd vccd vccd _194_/X sky130_fd_sc_hd__mux2_1
|
||||
XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_35 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_177_ _177_/A _190_/A vssd vssd vccd vccd _178_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_11_54 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XANTENNA_17 pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xinput15 mgmt_gpio_out vssd vssd vccd vccd _195_/A0 sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_8_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_36 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_18 serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_193_ _193_/A0 _182_/X _198_/Q vssd vssd vccd vccd _193_/X sky130_fd_sc_hd__mux2_1
|
||||
XFILLER_11_11 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_176_ _176_/A vssd vssd vccd vccd _176_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_159_ _190_/A _159_/B vssd vssd vccd vccd _160_/A sky130_fd_sc_hd__or2_1
|
||||
Xinput16 pad_gpio_in vssd vssd vccd vccd _197_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_192_ _192_/A vssd vssd vccd vccd _192_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_48 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_37 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_19 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_175_ _190_/A _177_/A vssd vssd vccd vccd _176_/A sky130_fd_sc_hd__or2b_1
|
||||
Xinput17 resetn vssd vssd vccd vccd _190_/A sky130_fd_sc_hd__buf_12
|
||||
XFILLER_2_47 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_158_ _158_/A vssd vssd vccd vccd _158_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xclkbuf_1_0_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _222_/CLK sky130_fd_sc_hd__clkbuf_2
|
||||
XTAP_38 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_191_ _191_/A vssd vssd vccd vccd _191_/X sky130_fd_sc_hd__buf_2
|
||||
XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
|
||||
XFILLER_2_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_174_ _174_/A vssd vssd vccd vccd _174_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput18 serial_data_in vssd vssd vccd vccd _211_/D sky130_fd_sc_hd__clkbuf_1
|
||||
X_157_ _190_/A _159_/B vssd vssd vccd vccd _158_/A sky130_fd_sc_hd__or2b_1
|
||||
X_209_ _130_/A _218_/D _111_/X _109_/X vssd vssd vccd vccd _209_/Q _209_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_0_92 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XTAP_39 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_173_ _188_/A vssd vssd vccd vccd _174_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_190_ _190_/A vssd vssd vccd vccd _190_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xinput19 serial_load vssd vssd vccd vccd _192_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_156_ _156_/A vssd vssd vccd vccd _156_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_139_ _190_/A _141_/B vssd vssd vccd vccd _140_/A sky130_fd_sc_hd__or2b_1
|
||||
X_208_ _113_/X _217_/D _117_/X _115_/X vssd vssd vccd vccd _208_/Q _208_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_172_ _172_/A vssd vssd vccd vccd _172_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_155_ _161_/A vssd vssd vccd vccd _156_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_207_ _119_/X _223_/Q _123_/X _121_/X vssd vssd vccd vccd _207_/Q _207_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
XFILLER_0_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_138_ _138_/A vssd vssd vccd vccd _138_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_6_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_171_ _190_/A _171_/B vssd vssd vccd vccd _172_/A sky130_fd_sc_hd__or2_1
|
||||
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_223_ _191_/A hold1/X _190_/A vssd vssd vccd vccd _223_/Q sky130_fd_sc_hd__dfrtp_1
|
||||
X_154_ _154_/A vssd vssd vccd vccd _154_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_206_ _125_/X hold1/A _129_/X _127_/X vssd vssd vccd vccd _206_/Q _206_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_137_ _161_/A vssd vssd vccd vccd _138_/A sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_6_61 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_170_ _170_/A vssd vssd vccd vccd _170_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_136_ _188_/A vssd vssd vccd vccd _161_/A sky130_fd_sc_hd__dlymetal6s2s_1
|
||||
XFILLER_9_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_205_ _131_/X _222_/D _135_/X _133_/X vssd vssd vccd vccd _205_/Q _194_/A0 sky130_fd_sc_hd__dfbbn_1
|
||||
X_222_ _222_/CLK _222_/D _190_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_1
|
||||
XFILLER_0_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_153_ _190_/A _153_/B vssd vssd vccd vccd _154_/A sky130_fd_sc_hd__or2_1
|
||||
XFILLER_14_39 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_119_ _119_/A vssd vssd vccd vccd _119_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_15_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_0 gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_221_ _191_/A _221_/D _190_/A vssd vssd vccd vccd _222_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_152_ _152_/A vssd vssd vccd vccd _152_/X sky130_fd_sc_hd__clkbuf_1
|
||||
X_118_ _130_/A vssd vssd vccd vccd _119_/A sky130_fd_sc_hd__clkbuf_1
|
||||
X_204_ _138_/X _213_/D _142_/X _140_/X vssd vssd vccd vccd _204_/Q _204_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_135_ _135_/A vssd vssd vccd vccd _135_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_14_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_1 gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_3_64 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_220_ _191_/A _220_/D _190_/A vssd vssd vccd vccd _221_/D sky130_fd_sc_hd__dfrtp_1
|
||||
X_151_ _190_/A _153_/B vssd vssd vccd vccd _152_/A sky130_fd_sc_hd__or2b_1
|
||||
X_203_ _144_/X _216_/D _148_/X _146_/X vssd vssd vccd vccd _203_/Q _203_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_134_ _190_/A _134_/B vssd vssd vccd vccd _135_/A sky130_fd_sc_hd__or2_1
|
||||
X_117_ _117_/A vssd vssd vccd vccd _117_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_2 gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_150_ _150_/A vssd vssd vccd vccd _150_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_9_20 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_202_ _150_/X _215_/D _154_/X _152_/X vssd vssd vccd vccd _202_/Q _202_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_133_ _133_/A vssd vssd vccd vccd _133_/X sky130_fd_sc_hd__clkbuf_1
|
||||
XFILLER_0_77 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_3 gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_116_ _190_/A _116_/B vssd vssd vccd vccd _117_/A sky130_fd_sc_hd__or2_1
|
||||
Xoutput40 output40/A vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__buf_2
|
||||
XFILLER_12_75 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_201_ _156_/X _221_/D _160_/X _158_/X vssd vssd vccd vccd _201_/Q _201_/Q_N sky130_fd_sc_hd__dfbbn_1
|
||||
X_132_ _190_/A _134_/B vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__or2b_1
|
||||
XFILLER_9_54 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
X_115_ _115_/A vssd vssd vccd vccd _115_/X sky130_fd_sc_hd__clkbuf_1
|
||||
Xoutput30 _203_/Q vssd vssd vccd vccd pad_gpio_ib_mode_sel sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_4 gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
.ends
|
||||
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
* NGSPICE file created from gpio_logic_high.ext - technology: sky130A
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
|
||||
XFILLER_3_3 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_6
|
||||
XFILLER_1_3 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_8
|
||||
XPHY_0 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XPHY_1 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XPHY_2 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XPHY_4 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XPHY_3 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XPHY_5 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XFILLER_1_11 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__fill_1
|
||||
XPHY_6 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XPHY_7 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XPHY_8 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XPHY_9 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XFILLER_4_3 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_4
|
||||
XTAP_10 vssd1 vccd1 sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_11 vssd1 vccd1 sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_3 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_4
|
||||
XTAP_12 vssd1 vccd1 sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_4_7 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__fill_1
|
||||
Xgpio_logic_high vssd1 vssd1 vccd1 vccd1 gpio_logic1 gpio_logic_high/LO sky130_fd_sc_hd__conb_1
|
||||
XFILLER_4_9 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XFILLER_0_3 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_4
|
||||
XFILLER_2_7 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__fill_1
|
||||
XFILLER_2_9 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
XFILLER_0_7 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__fill_1
|
||||
XFILLER_0_9 vssd1 vssd1 vccd1 vccd1 sky130_fd_sc_hd__decap_3
|
||||
.ends
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,108 @@
|
|||
module gpio_logic_high (gpio_logic1,
|
||||
vccd1,
|
||||
vssd1);
|
||||
output gpio_logic1;
|
||||
input vccd1;
|
||||
input vssd1;
|
||||
|
||||
|
||||
sky130_fd_sc_hd__decap_4 FILLER_0_3 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_7 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_0_9 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_11 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_1_3 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_2_3 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_2_7 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_2_9 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_6 FILLER_3_3 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_4_3 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_7 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 FILLER_4_9 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_0 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_1 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_2 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_3 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_4 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_5 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_6 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_7 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_8 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__decap_3 PHY_9 (.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_10 (.VGND(vssd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_11 (.VGND(vssd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_12 (.VGND(vssd1),
|
||||
.VPWR(vccd1));
|
||||
sky130_fd_sc_hd__conb_1 gpio_logic_high (.HI(gpio_logic1),
|
||||
.VGND(vssd1),
|
||||
.VNB(vssd1),
|
||||
.VPB(vccd1),
|
||||
.VPWR(vccd1));
|
||||
endmodule
|
||||
Loading…
Reference in New Issue