Commit Graph

131 Commits

Author SHA1 Message Date
kareem aadfb57609 reharden: caravel_clocking
~ align pdn with top level
~ move spefs and sdfs output corners to signoff/*/openlane-signoff
2022-10-14 05:24:49 -07:00
Tim Edwards 46d44793e2 Added layout for the gpio_signal_buffering module, including GDS,
LEF, DEF, and magic views.
2022-10-13 21:59:10 -04:00
kareem 6452f14de0 reimplement caravel with latest blocks updates and a buffer macro 2022-10-13 13:34:47 -07:00
Marwan Abbas f7299933ee
Merge pull request #217 from mo-hosni/buff_flash_clkrst
Buff flash clkrst
2022-10-13 20:53:18 +02:00
Marwan Abbas 14856fea6d
Merge pull request #216 from mo-hosni/housekeeping_final_views
Housekeeping final views
2022-10-13 20:47:09 +02:00
Marwan Abbas e72f819020
Merge pull request #210 from mo-hosni/final_views
mgmt_protect final views
2022-10-13 20:33:57 +02:00
Marwan Abbas 08ac55bed8
Merge pull request #214 from efabless/caravel_clocking-buffering
Caravel clocking reharden
2022-10-13 20:13:45 +02:00
kareem c922241c3f reharden: caravel_clocking
+ add custom interactive script to insert a buffer on user_clk output
and have a large buffer on core_clk
~ change pdn config to match top level
~ change sdc
~ change openlane configuration
2022-10-13 10:54:04 -07:00
mo-hosni 889aa7e308 add buff_flash_clkrst 2022-10-13 10:35:51 -07:00
mo-hosni 0389423ea6 add housekeeping 2022-10-13 10:15:05 -07:00
mo-hosni 1aaebf5cbb add mgmt_protect 2022-10-13 10:11:45 -07:00
kareem 59743f4832 change buf16 to clkbuf16 and reimplement 2022-10-13 06:54:55 -07:00
kareem 0eed96f33f reharden: digital_pll
~ reimplement digital_pll using updated RTL
~ changes in config to generate same PDN
~ change deprecated variables
2022-10-13 06:21:08 -07:00
kareem 9ccb0ff2ed reharden!: caravel
~ reimplement based on updated views of the macros
~ change interactive script to call label_macro_pins
~ extract all spef and sdf corners using timing-scripts repo

!important same work arounds as before
2022-10-12 04:45:08 -07:00
Mohamed Shalan 98951388d0
Merge pull request #179 from efabless/chip_io_fix_ports
Fixes the .mag, LEF, DEF, and GDS views of chip_io and chip_io_alt
2022-10-12 11:37:24 +02:00
mo-hosni 76f8d37496 Rehardened housekeeping to fix Antenna violations. 2022-10-11 16:41:50 -07:00
Tim Edwards a2feddf714 Corrected the layout views of chip_io and chip_io_alt, which were
missing some of the labels for the power supplies (they were
accidentally erased during layout re-work).
2022-10-11 11:39:03 -04:00
Mohamed Hosni ee17bcf177
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-11 01:47:06 -07:00
mo-hosni df05079b6f update houskeepong powere netlst and fixed some antenna violations 2022-10-11 01:46:23 -07:00
Mohamed Shalan 344f806980
Merge pull request #166 from efabless/gpio_control_block-sparecell
gpio_control_block sparecell
2022-10-11 10:39:50 +02:00
kareem f4218ddde9 reharden!: gpio_control_block
- reimplement using a sparecell
- reimplement using newest open_pdks

!important using openlane pre odb with some local patches which
most if not all are merged in the current head of openlane however
still takes effort to update the interactive script to be latest
openlane compatible

!important override abstract lef generated by openlane. openlane
 generates lef and mag that contain def BLOCKAGE layers that cause
congestions during top level routing
2022-10-10 05:42:29 -07:00
Mohamed Hosni 40098f693e
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 05:08:33 -07:00
kareem 285ef6b642 reharden!: caravel
~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds

!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
2022-10-10 04:51:05 -07:00
Mohamed Hosni fa441babea
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-10 01:24:24 -07:00
mo-hosni 7a7690ba10 Update housekeeping 2022-10-10 01:21:51 -07:00
mo-hosni 7e5891dd9f Update mgmt_protect 2022-10-10 01:19:40 -07:00
Tim Edwards 2459b3583e Updated all views of chip_io and chip_io_alt based on the abstract
view of constant_block which was recently merged into the repository.
The constant_block instance positions and connections were modified
slightly to avoid routing over obstruction areas.
2022-10-09 14:20:43 -04:00
Mohamed Shalan 7538c8c776
Merge pull request #161 from efabless/chip_io_rework 2022-10-09 16:31:28 +02:00
Tim Edwards eceb71ee04 Added GDS, DEF, and LEF views of both chip_io and chip_io_alt. 2022-10-08 22:24:38 -04:00
mo-hosni dde6e034e0 added constant_block view 2022-10-08 12:05:53 -07:00
mo-hosni d6ca7f9091 rehardened housekeeping after rtl update, and fixed all hold and transition violations. 2022-10-07 16:59:01 -07:00
Mohamed Hosni 5c38e38767
Merge branch 'efabless:caravel_redesign' into caravel_redesign 2022-10-07 16:52:16 -07:00
kareem 6d1d618974 reharden!: gpio_control_block
- rtl updated
~ add one column to the right to pass placement congestion
~ density adjusted (probably has no effect)
+ manually add isosubstrate layer in mag and gds from older iterations

!important still need to run dynamic simulations
!important depends on some updates to openlane
!important need to be able to recreate using newer openlane versions
2022-10-07 05:02:14 -07:00
mo-hosni 9c850bf94b rehardened housekeeping 2022-10-05 12:35:03 -07:00
mo-hosni fcc009e65a rehardeneded mgmt_protect 2022-10-05 12:26:24 -07:00
R. Timothy Edwards 69240123c0
Merge branch 'caravel_redesign' into make_CSB_a_pullup 2022-10-05 10:18:35 -04:00
kareem aaa3b863e5 reharden!: gpio_control_clock
- add met5 obs to avoid drc with the top level pdn

!important: still need to use the latest openlane to replicate
2022-10-05 07:03:11 -07:00
R. Timothy Edwards cda2c87ae8
Merge branch 'caravel_redesign' into make_CSB_a_pullup 2022-10-03 17:39:24 -04:00
Tim Edwards aba145e0e2 Made modifications in support of changing the hard-coded default
configuration of GPIO 3 (CSB) from a standard input to a weak
pull-up input.
2022-09-27 20:58:57 -04:00
kareem 85f7f86c4e reharden!: gpio_control_block
- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition

- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
	- to add obstruction before pdn
	- to manually insert buffers on some ports
	- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn

- misc changes:
* fix openlane makefile to properly detect interactive script

!important still need to run dynamic simulations
!important depends on some updates to openlane
2022-09-27 07:09:26 -07:00
kareem c1e0d5ba06 openlane!: reharden gpio_control_block
update gpio_control_block config for new openlane versions:
- disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size
and fit the floorplan
- change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells
- disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and
enable `GLB_RESIZER_TIMING_OPTIMIZATIONS`
- remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement
- set `DECAP_CELL` to not use ef decaps.. i think that was for simulations?
- enable some turned off `QUIT_*` variables
- replace deprecated variables such as `GLB_RT_*`
- customize `pdn.tcl` to force pdn straps to follow the old pattern
- replace `$script_dir` with `$::env(DESIGN_DIR)`

!IMPORTANT - still need to run dynamic simulations
2022-09-14 11:06:23 -07:00
kareem ac1928a45b harden: gpio_control_block with updated rtl
TODO: run full verification
2022-08-15 02:29:01 -07:00
Anton Blanchard 1a96c0e34b
Remove gpio_defaults_block_*.def (#91)
These are no longer used and have errors in their vias.
2022-04-25 20:55:43 -07:00
Kareem Farid 9ddb806293
gpio_control_block constrains fix (#69)
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-15 11:50:54 -07:00
R. Timothy Edwards 71600440bc
Caravan top lvs (#67)
* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one

* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
  to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it

* Apply automatic changes to Manifest and README.rst

* add caravan power routing lef

* - update mag and def view of caravan
- add_macro_placement for fake cell

* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines.  Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag.  It may be
worth cherry-picking the files to merge and exclude those layouts.

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
2022-04-14 15:05:16 -07:00
Kareem Farid c84e1393e7
updates to top level caravel (#59)
* REVERT ME: temporarily match simple_por pin in verilog with lef

* - update configs
- add patch file for power routing def

* - update the following caravel toplevel views
    - gl
    - mag
    - def
- add caravel power routing def

* Apply automatic changes to Manifest and README.rst

* update gl mag and def for caravel

* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"

This reverts commit b70c27c69f.

* update caravel gds

* Apply automatic changes to Manifest and README.rst

* Added text and logo cells back into the caravel top level.  Put an
isolated ground marker layer on the xres_buf layout.  Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v.  Updated the copyright block text.
Corrected DRC errors in the top level routing.

Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
2022-04-08 09:31:33 -07:00
Kareem Farid dcebeed7e7
Mgmt protect update (#58)
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect

* mgmt_protect updated

* mgmt_protect updated

* remove some via3 to fix power shorts

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-04-08 09:29:49 -07:00
Kareem Farid e3b9a99154
- update gpio_control_block config (#57)
- update gpio_control_block views
- gitignore gds/*gds
2022-04-08 09:27:51 -07:00
manarabdelaty 981043cb7b [DATA] Update mgmt_protect/gpio_control_block to remove buffers after tri-state cells 2021-12-24 21:06:58 +02:00
manarabdelaty e60957d73b [DATA] Update sdf for chip_io to include pad delays 2021-12-16 15:58:58 +02:00
manarabdelaty bd88221d17 [DATA] Update caravel_clocking 2021-12-07 13:36:56 +02:00
manarabdelaty 966b1f22bb [DATA] Update digital_pll 2021-12-07 13:19:02 +02:00
manarabdelaty 3fa797bbf8 [DATA] Add sdc/spef/sdf files for the gpio_defaults_block/chip_io/mgmt_protect blocks 2021-12-05 19:48:02 +02:00
manarabdelaty aa766f9144 [DATA] Update caravel_clocking module 2021-12-05 19:44:28 +02:00
manarabdelaty ef1019b62a [DATA] Update caravel_clocking 2021-12-02 22:50:20 +02:00
manarabdelaty 0067bd5b7c [DATA] Update caravel_clocking/digital_pll/housekeeping 2021-12-02 21:09:43 +02:00
manarabdelaty c4efcec989 [DATA] Update housekeeping views 2021-11-30 13:00:33 +02:00
manarabdelaty 8b1c5df909 [DATA] Update caravel_clocking module (timing clean) 2021-11-25 15:23:01 +02:00
manarabdelaty 05278ec738 [DATA] Update HK views (timing clean) 2021-11-25 12:54:22 +02:00
manarabdelaty 83e150bf25 [DATA] Add spare_logic_block 2021-11-24 20:36:23 +02:00
manarabdelaty aeffe4756a [DATA] Add caravan layout 2021-11-22 23:10:25 +02:00
manarabdelaty 38f64d08a3 [DATA] Add user_analog_project_wrapper and chip_io_alt gds/lef views 2021-11-22 23:08:25 +02:00
manarabdelaty 1c18c1dae9 [DATA] Update caravel 2021-11-20 17:28:59 +02:00
manarabdelaty 331fdee2bb [DATA] Update HK module (li1 routing: 249um) 2021-11-20 15:13:16 +02:00
manarabdelaty 37fb2d6766 [DATA] update caravel_clocking module (removed long li1 routes, in total it used 8um from li1) 2021-11-20 13:07:23 +02:00
manarabdelaty ededa9ed35 [DATA] Update caravel layout with the latest views for the mgmt_protect and mgmt_core 2021-11-19 16:51:28 +02:00
manarabdelaty 581a22de6a [DATA] Update mgmt_protect (removed all li1 routing ) 2021-11-19 13:11:18 +02:00
manarabdelaty 2574eada93 [DATA] Add initial caravel layout 2021-11-19 01:37:10 +02:00
manarabdelaty 61bf3c651e [DATA] Update mgmt_protect pin placement 2021-11-19 01:33:11 +02:00
manarabdelaty 53b3a9013e [DATA] Update HK pin placement 2021-11-19 01:30:14 +02:00
manarabdelaty 37a07e291b [DATA] Update digital_pll pin placement to have it align with the HK 2021-11-19 01:28:40 +02:00
manarabdelaty 64bdd6230d [DATA] Update caravel_clocking module floorplan 2021-11-19 01:26:29 +02:00
manarabdelaty 1b300d7b59 [DATA] Add digital user project wrapper 2021-11-17 13:13:11 +02:00
manarabdelaty 72b2c724c9 [DATA] Add views for caravel_clocking and updated digital_pll clock after constraining clock to 150 MHz 2021-11-15 15:50:43 +02:00
manarabdelaty 56f672bbd8 [DATA] Add HK views 2021-11-15 13:23:54 +02:00
manarabdelaty 85a1ffc5aa [DATA] Add views for the mgmt_protect 2021-11-15 13:21:52 +02:00
manarabdelaty bee7b4ed78 Add initial config for the digital_pll 2021-11-08 13:34:59 +02:00
manarabdelaty 59076d499a Update gpio_defaults_block to align the pins with the gpio_control_block 2021-11-05 23:27:32 +02:00
manarabdelaty 53b09f43d1 Add gpio_defaults_block views 2021-11-05 12:33:36 +02:00
manarabdelaty 78ce7265c1 Update gpio_control block 2021-11-04 17:58:58 +02:00
manarabdelaty cb9990f97e harden gpio_control_block 2021-11-04 16:19:12 +02:00