mirror of https://github.com/efabless/caravel.git
Merge branch 'caravel_redesign' into make_CSB_a_pullup
This commit is contained in:
R. Timothy Edwards
GitHub
commit
69240123c0
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
Before Width: | Height: | Size: 258 KiB After Width: | Height: | Size: 80 KiB |
|
|
@ -112,7 +112,7 @@ Memory Mapped I/O summary
|
|||
- Trap output destination (:ref:`reg_trap_out_dest`)
|
||||
* - `0x 2f 00 00 08`
|
||||
- IRQ 7 input source (:ref:`reg_irq7_source`)
|
||||
* - `0x 30 00 00 0`
|
||||
* - `0x 30 00 00 00`
|
||||
- User area base.
|
||||
A user project may define additional Wishbone responder modules starting at this address.
|
||||
* - `0x 80 00 00 00`
|
||||
|
|
|
|||
Binary file not shown.
|
|
@ -356,19 +356,19 @@ MACRO gpio_control_block
|
|||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 5.900 51.760 7.500 ;
|
||||
RECT 4.360 5.900 50.000 7.500 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 22.800 51.760 24.400 ;
|
||||
RECT 4.360 22.800 50.000 24.400 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 39.700 51.760 41.300 ;
|
||||
RECT 4.360 39.700 50.000 41.300 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 56.600 51.760 58.200 ;
|
||||
RECT 4.360 56.600 50.000 58.200 ;
|
||||
END
|
||||
END vccd
|
||||
PIN vccd1
|
||||
|
|
@ -384,15 +384,15 @@ MACRO gpio_control_block
|
|||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 11.140 51.760 12.740 ;
|
||||
RECT 4.360 11.140 50.000 12.740 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 28.040 51.760 29.640 ;
|
||||
RECT 4.360 28.040 50.000 29.640 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 44.940 51.760 46.540 ;
|
||||
RECT 4.360 44.940 50.000 46.540 ;
|
||||
END
|
||||
END vccd1
|
||||
PIN vssd
|
||||
|
|
@ -404,15 +404,15 @@ MACRO gpio_control_block
|
|||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 14.350 51.760 15.950 ;
|
||||
RECT 4.360 14.350 50.000 15.950 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 31.250 51.760 32.850 ;
|
||||
RECT 4.360 31.250 50.000 32.850 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 48.150 51.760 49.750 ;
|
||||
RECT 4.360 48.150 50.000 49.750 ;
|
||||
END
|
||||
END vssd
|
||||
PIN vssd1
|
||||
|
|
@ -424,15 +424,15 @@ MACRO gpio_control_block
|
|||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 19.590 51.760 21.190 ;
|
||||
RECT 4.360 19.590 50.000 21.190 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 36.490 51.760 38.090 ;
|
||||
RECT 4.360 36.490 50.000 38.090 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 53.390 51.760 54.990 ;
|
||||
RECT 4.360 53.390 50.000 54.990 ;
|
||||
END
|
||||
END vssd1
|
||||
PIN zero
|
||||
|
|
@ -718,68 +718,68 @@ MACRO gpio_control_block
|
|||
RECT 28.250 60.720 29.710 65.000 ;
|
||||
RECT 30.550 60.720 32.010 65.000 ;
|
||||
RECT 32.850 60.720 170.000 65.000 ;
|
||||
RECT 4.700 0.000 170.000 60.720 ;
|
||||
RECT 4.690 0.000 170.000 60.720 ;
|
||||
LAYER met3 ;
|
||||
RECT 6.280 60.840 69.600 61.705 ;
|
||||
RECT 6.280 60.200 70.000 60.840 ;
|
||||
RECT 6.280 58.800 69.600 60.200 ;
|
||||
RECT 6.280 58.160 70.000 58.800 ;
|
||||
RECT 6.280 56.760 69.600 58.160 ;
|
||||
RECT 6.280 56.120 70.000 56.760 ;
|
||||
RECT 6.280 54.720 69.600 56.120 ;
|
||||
RECT 6.280 54.080 70.000 54.720 ;
|
||||
RECT 6.280 52.680 69.600 54.080 ;
|
||||
RECT 6.280 52.040 70.000 52.680 ;
|
||||
RECT 6.280 50.640 69.600 52.040 ;
|
||||
RECT 6.280 50.000 70.000 50.640 ;
|
||||
RECT 6.280 48.600 69.600 50.000 ;
|
||||
RECT 6.280 47.960 70.000 48.600 ;
|
||||
RECT 6.280 46.560 69.600 47.960 ;
|
||||
RECT 6.280 45.920 70.000 46.560 ;
|
||||
RECT 6.280 44.520 69.600 45.920 ;
|
||||
RECT 6.280 43.880 70.000 44.520 ;
|
||||
RECT 6.280 42.480 69.600 43.880 ;
|
||||
RECT 6.280 41.840 70.000 42.480 ;
|
||||
RECT 6.280 40.440 69.600 41.840 ;
|
||||
RECT 6.280 39.800 70.000 40.440 ;
|
||||
RECT 6.280 38.400 69.600 39.800 ;
|
||||
RECT 6.280 37.760 70.000 38.400 ;
|
||||
RECT 6.280 36.360 69.600 37.760 ;
|
||||
RECT 6.280 35.720 70.000 36.360 ;
|
||||
RECT 6.280 34.320 69.600 35.720 ;
|
||||
RECT 6.280 33.680 70.000 34.320 ;
|
||||
RECT 6.280 32.280 69.600 33.680 ;
|
||||
RECT 6.280 31.640 70.000 32.280 ;
|
||||
RECT 6.280 30.240 69.600 31.640 ;
|
||||
RECT 6.280 29.600 70.000 30.240 ;
|
||||
RECT 6.280 28.200 69.600 29.600 ;
|
||||
RECT 6.280 27.560 70.000 28.200 ;
|
||||
RECT 6.280 26.160 69.600 27.560 ;
|
||||
RECT 6.280 25.520 70.000 26.160 ;
|
||||
RECT 6.280 24.120 69.600 25.520 ;
|
||||
RECT 6.280 23.480 70.000 24.120 ;
|
||||
RECT 6.280 22.080 69.600 23.480 ;
|
||||
RECT 6.280 21.440 70.000 22.080 ;
|
||||
RECT 6.280 20.040 69.600 21.440 ;
|
||||
RECT 6.280 19.400 70.000 20.040 ;
|
||||
RECT 6.280 18.000 69.600 19.400 ;
|
||||
RECT 6.280 17.360 70.000 18.000 ;
|
||||
RECT 6.280 15.960 69.600 17.360 ;
|
||||
RECT 6.280 15.320 70.000 15.960 ;
|
||||
RECT 6.280 13.920 69.600 15.320 ;
|
||||
RECT 6.280 13.280 70.000 13.920 ;
|
||||
RECT 6.280 11.880 69.600 13.280 ;
|
||||
RECT 6.280 11.240 70.000 11.880 ;
|
||||
RECT 6.280 9.840 69.600 11.240 ;
|
||||
RECT 6.280 9.200 70.000 9.840 ;
|
||||
RECT 6.280 7.800 69.600 9.200 ;
|
||||
RECT 6.280 7.160 70.000 7.800 ;
|
||||
RECT 6.280 5.760 69.600 7.160 ;
|
||||
RECT 6.280 5.120 70.000 5.760 ;
|
||||
RECT 6.280 3.720 69.600 5.120 ;
|
||||
RECT 6.280 3.080 70.000 3.720 ;
|
||||
RECT 6.280 1.680 69.600 3.080 ;
|
||||
RECT 6.280 0.175 70.000 1.680 ;
|
||||
RECT 4.665 60.840 69.600 61.705 ;
|
||||
RECT 4.665 60.200 70.000 60.840 ;
|
||||
RECT 4.665 58.800 69.600 60.200 ;
|
||||
RECT 4.665 58.160 70.000 58.800 ;
|
||||
RECT 4.665 56.760 69.600 58.160 ;
|
||||
RECT 4.665 56.120 70.000 56.760 ;
|
||||
RECT 4.665 54.720 69.600 56.120 ;
|
||||
RECT 4.665 54.080 70.000 54.720 ;
|
||||
RECT 4.665 52.680 69.600 54.080 ;
|
||||
RECT 4.665 52.040 70.000 52.680 ;
|
||||
RECT 4.665 50.640 69.600 52.040 ;
|
||||
RECT 4.665 50.000 70.000 50.640 ;
|
||||
RECT 4.665 48.600 69.600 50.000 ;
|
||||
RECT 4.665 47.960 70.000 48.600 ;
|
||||
RECT 4.665 46.560 69.600 47.960 ;
|
||||
RECT 4.665 45.920 70.000 46.560 ;
|
||||
RECT 4.665 44.520 69.600 45.920 ;
|
||||
RECT 4.665 43.880 70.000 44.520 ;
|
||||
RECT 4.665 42.480 69.600 43.880 ;
|
||||
RECT 4.665 41.840 70.000 42.480 ;
|
||||
RECT 4.665 40.440 69.600 41.840 ;
|
||||
RECT 4.665 39.800 70.000 40.440 ;
|
||||
RECT 4.665 38.400 69.600 39.800 ;
|
||||
RECT 4.665 37.760 70.000 38.400 ;
|
||||
RECT 4.665 36.360 69.600 37.760 ;
|
||||
RECT 4.665 35.720 70.000 36.360 ;
|
||||
RECT 4.665 34.320 69.600 35.720 ;
|
||||
RECT 4.665 33.680 70.000 34.320 ;
|
||||
RECT 4.665 32.280 69.600 33.680 ;
|
||||
RECT 4.665 31.640 70.000 32.280 ;
|
||||
RECT 4.665 30.240 69.600 31.640 ;
|
||||
RECT 4.665 29.600 70.000 30.240 ;
|
||||
RECT 4.665 28.200 69.600 29.600 ;
|
||||
RECT 4.665 27.560 70.000 28.200 ;
|
||||
RECT 4.665 26.160 69.600 27.560 ;
|
||||
RECT 4.665 25.520 70.000 26.160 ;
|
||||
RECT 4.665 24.120 69.600 25.520 ;
|
||||
RECT 4.665 23.480 70.000 24.120 ;
|
||||
RECT 4.665 22.080 69.600 23.480 ;
|
||||
RECT 4.665 21.440 70.000 22.080 ;
|
||||
RECT 4.665 20.040 69.600 21.440 ;
|
||||
RECT 4.665 19.400 70.000 20.040 ;
|
||||
RECT 4.665 18.000 69.600 19.400 ;
|
||||
RECT 4.665 17.360 70.000 18.000 ;
|
||||
RECT 4.665 15.960 69.600 17.360 ;
|
||||
RECT 4.665 15.320 70.000 15.960 ;
|
||||
RECT 4.665 13.920 69.600 15.320 ;
|
||||
RECT 4.665 13.280 70.000 13.920 ;
|
||||
RECT 4.665 11.880 69.600 13.280 ;
|
||||
RECT 4.665 11.240 70.000 11.880 ;
|
||||
RECT 4.665 9.840 69.600 11.240 ;
|
||||
RECT 4.665 9.200 70.000 9.840 ;
|
||||
RECT 4.665 7.800 69.600 9.200 ;
|
||||
RECT 4.665 7.160 70.000 7.800 ;
|
||||
RECT 4.665 5.760 69.600 7.160 ;
|
||||
RECT 4.665 5.120 70.000 5.760 ;
|
||||
RECT 4.665 3.720 69.600 5.120 ;
|
||||
RECT 4.665 3.080 70.000 3.720 ;
|
||||
RECT 4.665 1.680 69.600 3.080 ;
|
||||
RECT 4.665 0.175 70.000 1.680 ;
|
||||
LAYER met4 ;
|
||||
RECT 6.280 60.480 170.000 65.000 ;
|
||||
RECT 6.280 2.080 12.400 60.480 ;
|
||||
|
|
@ -791,7 +791,21 @@ MACRO gpio_control_block
|
|||
RECT 44.800 2.080 170.000 60.480 ;
|
||||
RECT 6.280 0.000 170.000 2.080 ;
|
||||
LAYER met5 ;
|
||||
RECT 67.000 0.000 170.000 65.000 ;
|
||||
RECT 50.000 59.800 170.000 65.000 ;
|
||||
RECT 51.600 51.790 170.000 59.800 ;
|
||||
RECT 50.000 51.350 170.000 51.790 ;
|
||||
RECT 51.600 43.340 170.000 51.350 ;
|
||||
RECT 50.000 42.900 170.000 43.340 ;
|
||||
RECT 51.600 34.890 170.000 42.900 ;
|
||||
RECT 50.000 34.450 170.000 34.890 ;
|
||||
RECT 51.600 26.440 170.000 34.450 ;
|
||||
RECT 50.000 26.000 170.000 26.440 ;
|
||||
RECT 51.600 17.990 170.000 26.000 ;
|
||||
RECT 50.000 17.550 170.000 17.990 ;
|
||||
RECT 51.600 9.540 170.000 17.550 ;
|
||||
RECT 50.000 9.100 170.000 9.540 ;
|
||||
RECT 51.600 4.300 170.000 9.100 ;
|
||||
RECT 50.000 0.000 170.000 4.300 ;
|
||||
END
|
||||
END gpio_control_block
|
||||
END LIBRARY
|
||||
|
|
|
|||
|
|
@ -59098,7 +59098,7 @@ use gpio_defaults_block_0403 gpio_defaults_block_13
|
|||
timestamp 1638587925
|
||||
transform -1 0 709467 0 1 897800
|
||||
box -38 0 6018 2224
|
||||
use gpio_defaults_block_0403 gpio_defaults_block_14
|
||||
use gpio_defaults_block_0403 gpio_defaults_block_25
|
||||
timestamp 1638587925
|
||||
transform 1 0 8367 0 1 818400
|
||||
box -38 0 6018 2224
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1664286915
|
||||
timestamp 1664976471
|
||||
<< obsli1 >>
|
||||
rect 0 13000 853 13014
|
||||
rect 0 0 33962 13000
|
||||
|
|
@ -35,7 +35,7 @@ rect 5190 12144 5482 13000
|
|||
rect 5650 12144 5942 13000
|
||||
rect 6110 12144 6402 13000
|
||||
rect 6570 12144 34000 13000
|
||||
rect 940 0 34000 12144
|
||||
rect 938 0 34000 12144
|
||||
<< metal3 >>
|
||||
rect 14000 12248 34000 12368
|
||||
rect 14000 11840 34000 11960
|
||||
|
|
@ -68,66 +68,66 @@ rect 14000 1232 34000 1352
|
|||
rect 14000 824 34000 944
|
||||
rect 14000 416 34000 536
|
||||
<< obsm3 >>
|
||||
rect 1256 12168 13920 12341
|
||||
rect 1256 12040 14000 12168
|
||||
rect 1256 11760 13920 12040
|
||||
rect 1256 11632 14000 11760
|
||||
rect 1256 11352 13920 11632
|
||||
rect 1256 11224 14000 11352
|
||||
rect 1256 10944 13920 11224
|
||||
rect 1256 10816 14000 10944
|
||||
rect 1256 10536 13920 10816
|
||||
rect 1256 10408 14000 10536
|
||||
rect 1256 10128 13920 10408
|
||||
rect 1256 10000 14000 10128
|
||||
rect 1256 9720 13920 10000
|
||||
rect 1256 9592 14000 9720
|
||||
rect 1256 9312 13920 9592
|
||||
rect 1256 9184 14000 9312
|
||||
rect 1256 8904 13920 9184
|
||||
rect 1256 8776 14000 8904
|
||||
rect 1256 8496 13920 8776
|
||||
rect 1256 8368 14000 8496
|
||||
rect 1256 8088 13920 8368
|
||||
rect 1256 7960 14000 8088
|
||||
rect 1256 7680 13920 7960
|
||||
rect 1256 7552 14000 7680
|
||||
rect 1256 7272 13920 7552
|
||||
rect 1256 7144 14000 7272
|
||||
rect 1256 6864 13920 7144
|
||||
rect 1256 6736 14000 6864
|
||||
rect 1256 6456 13920 6736
|
||||
rect 1256 6328 14000 6456
|
||||
rect 1256 6048 13920 6328
|
||||
rect 1256 5920 14000 6048
|
||||
rect 1256 5640 13920 5920
|
||||
rect 1256 5512 14000 5640
|
||||
rect 1256 5232 13920 5512
|
||||
rect 1256 5104 14000 5232
|
||||
rect 1256 4824 13920 5104
|
||||
rect 1256 4696 14000 4824
|
||||
rect 1256 4416 13920 4696
|
||||
rect 1256 4288 14000 4416
|
||||
rect 1256 4008 13920 4288
|
||||
rect 1256 3880 14000 4008
|
||||
rect 1256 3600 13920 3880
|
||||
rect 1256 3472 14000 3600
|
||||
rect 1256 3192 13920 3472
|
||||
rect 1256 3064 14000 3192
|
||||
rect 1256 2784 13920 3064
|
||||
rect 1256 2656 14000 2784
|
||||
rect 1256 2376 13920 2656
|
||||
rect 1256 2248 14000 2376
|
||||
rect 1256 1968 13920 2248
|
||||
rect 1256 1840 14000 1968
|
||||
rect 1256 1560 13920 1840
|
||||
rect 1256 1432 14000 1560
|
||||
rect 1256 1152 13920 1432
|
||||
rect 1256 1024 14000 1152
|
||||
rect 1256 744 13920 1024
|
||||
rect 1256 616 14000 744
|
||||
rect 1256 336 13920 616
|
||||
rect 1256 35 14000 336
|
||||
rect 933 12168 13920 12341
|
||||
rect 933 12040 14000 12168
|
||||
rect 933 11760 13920 12040
|
||||
rect 933 11632 14000 11760
|
||||
rect 933 11352 13920 11632
|
||||
rect 933 11224 14000 11352
|
||||
rect 933 10944 13920 11224
|
||||
rect 933 10816 14000 10944
|
||||
rect 933 10536 13920 10816
|
||||
rect 933 10408 14000 10536
|
||||
rect 933 10128 13920 10408
|
||||
rect 933 10000 14000 10128
|
||||
rect 933 9720 13920 10000
|
||||
rect 933 9592 14000 9720
|
||||
rect 933 9312 13920 9592
|
||||
rect 933 9184 14000 9312
|
||||
rect 933 8904 13920 9184
|
||||
rect 933 8776 14000 8904
|
||||
rect 933 8496 13920 8776
|
||||
rect 933 8368 14000 8496
|
||||
rect 933 8088 13920 8368
|
||||
rect 933 7960 14000 8088
|
||||
rect 933 7680 13920 7960
|
||||
rect 933 7552 14000 7680
|
||||
rect 933 7272 13920 7552
|
||||
rect 933 7144 14000 7272
|
||||
rect 933 6864 13920 7144
|
||||
rect 933 6736 14000 6864
|
||||
rect 933 6456 13920 6736
|
||||
rect 933 6328 14000 6456
|
||||
rect 933 6048 13920 6328
|
||||
rect 933 5920 14000 6048
|
||||
rect 933 5640 13920 5920
|
||||
rect 933 5512 14000 5640
|
||||
rect 933 5232 13920 5512
|
||||
rect 933 5104 14000 5232
|
||||
rect 933 4824 13920 5104
|
||||
rect 933 4696 14000 4824
|
||||
rect 933 4416 13920 4696
|
||||
rect 933 4288 14000 4416
|
||||
rect 933 4008 13920 4288
|
||||
rect 933 3880 14000 4008
|
||||
rect 933 3600 13920 3880
|
||||
rect 933 3472 14000 3600
|
||||
rect 933 3192 13920 3472
|
||||
rect 933 3064 14000 3192
|
||||
rect 933 2784 13920 3064
|
||||
rect 933 2656 14000 2784
|
||||
rect 933 2376 13920 2656
|
||||
rect 933 2248 14000 2376
|
||||
rect 933 1968 13920 2248
|
||||
rect 933 1840 14000 1968
|
||||
rect 933 1560 13920 1840
|
||||
rect 933 1432 14000 1560
|
||||
rect 933 1152 13920 1432
|
||||
rect 933 1024 14000 1152
|
||||
rect 933 744 13920 1024
|
||||
rect 933 616 14000 744
|
||||
rect 933 336 13920 616
|
||||
rect 933 35 14000 336
|
||||
<< metal4 >>
|
||||
rect 2560 496 2880 12016
|
||||
rect 3560 496 3880 12016
|
||||
|
|
@ -146,21 +146,35 @@ rect 7960 416 8480 12096
|
|||
rect 8960 416 34000 12096
|
||||
rect 1256 0 34000 416
|
||||
<< metal5 >>
|
||||
rect 872 11320 10352 11640
|
||||
rect 872 10678 10352 10998
|
||||
rect 872 9630 10352 9950
|
||||
rect 872 8988 10352 9308
|
||||
rect 872 7940 10352 8260
|
||||
rect 872 7298 10352 7618
|
||||
rect 872 6250 10352 6570
|
||||
rect 872 5608 10352 5928
|
||||
rect 872 4560 10352 4880
|
||||
rect 872 3918 10352 4238
|
||||
rect 872 2870 10352 3190
|
||||
rect 872 2228 10352 2548
|
||||
rect 872 1180 10352 1500
|
||||
rect 872 11320 10000 11640
|
||||
rect 872 10678 10000 10998
|
||||
rect 872 9630 10000 9950
|
||||
rect 872 8988 10000 9308
|
||||
rect 872 7940 10000 8260
|
||||
rect 872 7298 10000 7618
|
||||
rect 872 6250 10000 6570
|
||||
rect 872 5608 10000 5928
|
||||
rect 872 4560 10000 4880
|
||||
rect 872 3918 10000 4238
|
||||
rect 872 2870 10000 3190
|
||||
rect 872 2228 10000 2548
|
||||
rect 872 1180 10000 1500
|
||||
<< obsm5 >>
|
||||
rect 13400 0 34000 13000
|
||||
rect 10000 11960 34000 13000
|
||||
rect 10320 10358 34000 11960
|
||||
rect 10000 10270 34000 10358
|
||||
rect 10320 8668 34000 10270
|
||||
rect 10000 8580 34000 8668
|
||||
rect 10320 6978 34000 8580
|
||||
rect 10000 6890 34000 6978
|
||||
rect 10320 5288 34000 6890
|
||||
rect 10000 5200 34000 5288
|
||||
rect 10320 3598 34000 5200
|
||||
rect 10000 3510 34000 3598
|
||||
rect 10320 1908 34000 3510
|
||||
rect 10000 1820 34000 1908
|
||||
rect 10320 860 34000 1820
|
||||
rect 10000 0 34000 860
|
||||
<< labels >>
|
||||
rlabel metal2 s 938 12200 994 13000 6 gpio_defaults[0]
|
||||
port 1 nsew signal input
|
||||
|
|
@ -250,39 +264,39 @@ rlabel metal4 s 2560 496 2880 12016 6 vccd
|
|||
port 43 nsew power bidirectional
|
||||
rlabel metal4 s 7560 496 7880 12016 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 1180 10352 1500 6 vccd
|
||||
rlabel metal5 s 872 1180 10000 1500 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 4560 10352 4880 6 vccd
|
||||
rlabel metal5 s 872 4560 10000 4880 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 7940 10352 8260 6 vccd
|
||||
rlabel metal5 s 872 7940 10000 8260 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 11320 10352 11640 6 vccd
|
||||
rlabel metal5 s 872 11320 10000 11640 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal4 s 3560 496 3880 12016 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal4 s 8560 496 8880 12016 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal5 s 872 2228 10352 2548 6 vccd1
|
||||
rlabel metal5 s 872 2228 10000 2548 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal5 s 872 5608 10352 5928 6 vccd1
|
||||
rlabel metal5 s 872 5608 10000 5928 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal5 s 872 8988 10352 9308 6 vccd1
|
||||
rlabel metal5 s 872 8988 10000 9308 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal4 s 5060 496 5380 12016 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal5 s 872 2870 10352 3190 6 vssd
|
||||
rlabel metal5 s 872 2870 10000 3190 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal5 s 872 6250 10352 6570 6 vssd
|
||||
rlabel metal5 s 872 6250 10000 6570 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal5 s 872 9630 10352 9950 6 vssd
|
||||
rlabel metal5 s 872 9630 10000 9950 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal4 s 6060 496 6380 12016 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal5 s 872 3918 10352 4238 6 vssd1
|
||||
rlabel metal5 s 872 3918 10000 4238 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal5 s 872 7298 10352 7618 6 vssd1
|
||||
rlabel metal5 s 872 7298 10000 7618 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal5 s 872 10678 10352 10998 6 vssd1
|
||||
rlabel metal5 s 872 10678 10000 10998 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal3 s 14000 416 34000 536 6 zero
|
||||
port 47 nsew signal output
|
||||
|
|
@ -290,8 +304,8 @@ port 47 nsew signal output
|
|||
string FIXED_BBOX 0 0 34000 13000
|
||||
string LEFclass BLOCK
|
||||
string LEFview TRUE
|
||||
string GDS_END 572784
|
||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_09_27_06_53/results/signoff/gpio_control_block.magic.gds
|
||||
string GDS_END 572912
|
||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_10_05_06_26/results/signoff/gpio_control_block.magic.gds
|
||||
string GDS_START 204218
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
6
manifest
6
manifest
|
|
@ -2,8 +2,8 @@
|
|||
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
|
||||
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
|
||||
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
|
||||
8e0935b6cf50919e944ec97074a98f545b515d43 verilog/rtl/caravan.v
|
||||
78d57857e9121ce22681e1a93e63f85058db38d5 verilog/rtl/caravan_netlists.v
|
||||
0e2cda74281c33da2f4e23d0ff5af91adcbcf32a verilog/rtl/caravan.v
|
||||
a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v
|
||||
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
|
||||
3f0bb1f4fedd16d0e675e937a6f9b3e834e671e7 verilog/rtl/caravel.v
|
||||
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
|
||||
|
|
@ -18,7 +18,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
|||
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
||||
b890e19f294294ee4aad4136b95c46e17d6f91dd verilog/rtl/housekeeping.v
|
||||
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
|
||||
0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v
|
||||
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
|
||||
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
|
||||
9816acedf3dc3edd193861cc217ec46180ac1cdd verilog/rtl/mprj2_logic_high.v
|
||||
9dd11188f3a6980537dd51d8dd1a827795ac70fc verilog/rtl/mprj_io.v
|
||||
|
|
|
|||
|
|
@ -97,7 +97,7 @@ set ::env(GRT_OBS) "\
|
|||
li1 4.21500 57.40500 49.81500 64.93000,
|
||||
li1 16.83000 0 49.41000 5.24000,
|
||||
li1 49.000 0 169.81000 64.84500,
|
||||
met5 67 0 170 65,
|
||||
met5 50 0 170 65,
|
||||
met4 49 0 170 65,
|
||||
met2 120 0 170 65,
|
||||
met1 120 0 170 65"
|
||||
|
|
|
|||
|
|
@ -55,9 +55,9 @@ proc custom_run_placement {args} {
|
|||
}
|
||||
|
||||
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
|
||||
prep -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 0
|
||||
prep -design $SCRIPT_DIR -tag $::env(TAG) -overwrite -verbose 0
|
||||
exec rm -rf $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
exec ln -sf $SCRIPT_DIR/runs/$::env(TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
run_synthesis
|
||||
|
||||
init_floorplan
|
||||
|
|
@ -69,7 +69,7 @@ tap_decap_or
|
|||
add_route_obs
|
||||
run_power_grid_generation
|
||||
|
||||
set dont_use_old ::env(DONT_USE_CELLS)
|
||||
set dont_use_old $::env(DONT_USE_CELLS)
|
||||
global_placement_or
|
||||
set ::env(DONT_USE_CELLS) "$::env(DONT_USE_CELLS) sky130_fd_sc_hd__buf_1"
|
||||
run_resizer_design
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Tue Sep 27 13:54:44 2022
|
||||
# Wed Oct 5 13:27:20 2022
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
###############################################################################
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -3832,7 +3832,7 @@ module caravan(vddio, vddio_2, vssio, vssio_2, vdda, vssa, vccd, vssd, vdda1, vd
|
|||
.VPWR(vccd_core),
|
||||
.gpio_defaults({ \gpio_defaults[181] , \gpio_defaults[180] , \gpio_defaults[179] , \gpio_defaults[178] , \gpio_defaults[177] , \gpio_defaults[176] , \gpio_defaults[175] , \gpio_defaults[174] , \gpio_defaults[173] , \gpio_defaults[172] , \gpio_defaults[171] , \gpio_defaults[170] , \gpio_defaults[169] })
|
||||
);
|
||||
gpio_defaults_block_0403 gpio_defaults_block_14 (
|
||||
gpio_defaults_block_0403 gpio_defaults_block_25 (
|
||||
.VGND(vssd_core),
|
||||
.VPWR(vccd_core),
|
||||
.gpio_defaults({ \gpio_defaults[194] , \gpio_defaults[193] , \gpio_defaults[192] , \gpio_defaults[191] , \gpio_defaults[190] , \gpio_defaults[189] , \gpio_defaults[188] , \gpio_defaults[187] , \gpio_defaults[186] , \gpio_defaults[185] , \gpio_defaults[184] , \gpio_defaults[183] , \gpio_defaults[182] })
|
||||
|
|
|
|||
|
|
@ -960,8 +960,8 @@ module caravan (
|
|||
);
|
||||
|
||||
gpio_defaults_block #(
|
||||
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_14_INIT)
|
||||
) gpio_defaults_block_14 (
|
||||
.GPIO_CONFIG_INIT(`USER_CONFIG_GPIO_25_INIT)
|
||||
) gpio_defaults_block_25 (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd_core),
|
||||
.VGND(vssd_core),
|
||||
|
|
|
|||
|
|
@ -28,6 +28,14 @@
|
|||
/* For the sake of placement/routing, one conb (logic 1) cell is used */
|
||||
/* for every buffer. */
|
||||
/*----------------------------------------------------------------------*/
|
||||
/* 10/3/2022: Removed tri-state buffers in favor of AND gates; i.e., */
|
||||
/* if the user project is powered down, then the outputs are grounded */
|
||||
/* rather than tristated. Other explicitly-referenced gates removed */
|
||||
/* with the assumption that all outputs will be buffered as needed by */
|
||||
/* the synthesis tools. Therefore the only restrictions needed on the */
|
||||
/* synthesis tools is the list of input signals that must not be */
|
||||
/* buffered because they are allowed to be floating. */
|
||||
/*----------------------------------------------------------------------*/
|
||||
|
||||
module mgmt_protect (
|
||||
`ifdef USE_POWER_PINS
|
||||
|
|
@ -154,17 +162,7 @@ module mgmt_protect (
|
|||
// data input to the management core to be a solid logic 0 when
|
||||
// the user project is powered down.
|
||||
|
||||
sky130_fd_sc_hd__and2_1 user_to_mprj_in_ena_buf [127:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.X(la_data_in_enable),
|
||||
.A(la_iena_mprj),
|
||||
.B(mprj_logic1[457:330])
|
||||
);
|
||||
assign la_data_in_enable = la_iena_mprj & mprj_logic1[457:330];
|
||||
|
||||
sky130_fd_sc_hd__nand2_4 user_to_mprj_in_gates [127:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
|
|
@ -174,34 +172,15 @@ module mgmt_protect (
|
|||
.VNB(vssd),
|
||||
`endif
|
||||
.Y(la_data_in_mprj_bar),
|
||||
.A(la_data_out_core),
|
||||
.A(la_data_out_core), // may be floating
|
||||
.B(la_data_in_enable)
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__inv_8 user_to_mprj_in_buffers [127:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Y(la_data_in_mprj),
|
||||
.A(la_data_in_mprj_bar)
|
||||
);
|
||||
assign la_data_in_mprj = ~la_data_in_mprj_bar;
|
||||
|
||||
// Protection, similar to the above, for the three user IRQ lines
|
||||
|
||||
sky130_fd_sc_hd__and2_1 user_irq_ena_buf [2:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.X(user_irq_enable),
|
||||
.A(user_irq_ena),
|
||||
.B(mprj_logic1[460:458])
|
||||
);
|
||||
assign user_irq_enable = user_irq_ena & mprj_logic1[460:458];
|
||||
|
||||
sky130_fd_sc_hd__nand2_4 user_irq_gates [2:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
|
|
@ -211,35 +190,16 @@ module mgmt_protect (
|
|||
.VNB(vssd),
|
||||
`endif
|
||||
.Y(user_irq_bar),
|
||||
.A(user_irq_core),
|
||||
.A(user_irq_core), // may be floating
|
||||
.B(user_irq_enable)
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__inv_8 user_irq_buffers [2:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Y(user_irq),
|
||||
.A(user_irq_bar)
|
||||
);
|
||||
assign user_irq = ~user_irq_bar;
|
||||
|
||||
// Protection, similar to the above, for the return
|
||||
// signals from user area to managment on the wishbone bus
|
||||
|
||||
sky130_fd_sc_hd__and2_1 user_to_mprj_wb_ena_buf (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.X(wb_in_enable),
|
||||
.A(mprj_iena_wb),
|
||||
.B(mprj_logic1[462])
|
||||
);
|
||||
assign wb_in_enable = mprj_iena_wb & mprj_logic1[462];
|
||||
|
||||
sky130_fd_sc_hd__nand2_4 user_wb_dat_gates [31:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
|
|
@ -249,20 +209,11 @@ module mgmt_protect (
|
|||
.VNB(vssd),
|
||||
`endif
|
||||
.Y(mprj_dat_i_core_bar),
|
||||
.A(mprj_dat_i_user),
|
||||
.A(mprj_dat_i_user), // may be floating
|
||||
.B(wb_in_enable)
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__inv_8 user_wb_dat_buffers [31:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Y(mprj_dat_i_core),
|
||||
.A(mprj_dat_i_core_bar)
|
||||
);
|
||||
assign mprj_dat_i_core = ~mprj_dat_i_core_bar;
|
||||
|
||||
sky130_fd_sc_hd__nand2_4 user_wb_ack_gate (
|
||||
`ifdef USE_POWER_PINS
|
||||
|
|
@ -272,223 +223,45 @@ module mgmt_protect (
|
|||
.VNB(vssd),
|
||||
`endif
|
||||
.Y(mprj_ack_i_core_bar),
|
||||
.A(mprj_ack_i_user),
|
||||
.A(mprj_ack_i_user), // may be floating
|
||||
.B(wb_in_enable)
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__inv_8 user_wb_ack_buffer (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Y(mprj_ack_i_core),
|
||||
.A(mprj_ack_i_core_bar)
|
||||
);
|
||||
assign mprj_ack_i_core = ~mprj_ack_i_core_bar;
|
||||
|
||||
// The remaining circuitry guards against the management
|
||||
// SoC dumping current into the user project area when
|
||||
// the user project area is powered down.
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 mprj_rstn_buf (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(user_reset),
|
||||
.A(caravel_rstn),
|
||||
.TE(mprj_logic1[0])
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 mprj_clk_buf (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(user_clock),
|
||||
.A(~caravel_clk),
|
||||
.TE(mprj_logic1[1])
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 mprj_clk2_buf (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(user_clock2),
|
||||
.A(~caravel_clk2),
|
||||
.TE(mprj_logic1[2])
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 mprj_cyc_buf (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(mprj_cyc_o_user),
|
||||
.A(~mprj_cyc_o_core),
|
||||
.TE(mprj_logic1[3])
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 mprj_stb_buf (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(mprj_stb_o_user),
|
||||
.A(~mprj_stb_o_core),
|
||||
.TE(mprj_logic1[4])
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 mprj_we_buf (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(mprj_we_o_user),
|
||||
.A(~mprj_we_o_core),
|
||||
.TE(mprj_logic1[5])
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 mprj_sel_buf [3:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(mprj_sel_o_user),
|
||||
.A(~mprj_sel_o_core),
|
||||
.TE(mprj_logic1[9:6])
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 mprj_adr_buf [31:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(mprj_adr_o_user),
|
||||
.A(~mprj_adr_o_core),
|
||||
.TE(mprj_logic1[41:10])
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 mprj_dat_buf [31:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(mprj_dat_o_user),
|
||||
.A(~mprj_dat_o_core),
|
||||
.TE(mprj_logic1[73:42])
|
||||
);
|
||||
|
||||
/* Create signal to tristate the outputs to the user project */
|
||||
|
||||
sky130_fd_sc_hd__and2b_1 la_buf_enable [127:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.X(la_data_out_enable),
|
||||
.A_N(la_oenb_mprj),
|
||||
.B(mprj_logic1[201:74])
|
||||
);
|
||||
assign user_reset = (~caravel_rstn) & mprj_logic1[0];
|
||||
assign user_clock = caravel_clk & mprj_logic1[1];
|
||||
assign user_clock2 = caravel_clk2 & mprj_logic1[2];
|
||||
assign mprj_cyc_o_user = mprj_cyc_o_core & mprj_logic1[3];
|
||||
assign mprj_stb_o_user = mprj_stb_o_core & mprj_logic1[4];
|
||||
assign mprj_we_o_user = mprj_we_o_core & mprj_logic1[5];
|
||||
assign mprj_sel_o_user = mprj_sel_o_core & mprj_logic1[9:6];
|
||||
assign mprj_adr_o_user = mprj_adr_o_core & mprj_logic1[41:10];
|
||||
assign mprj_dat_o_user = mprj_dat_o_core & mprj_logic1[73:42];
|
||||
|
||||
/* Project data out from the managment side to the user project */
|
||||
/* area when the user project is powered down. */
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 la_buf [127:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(la_data_in_core),
|
||||
.A(~la_data_out_mprj),
|
||||
.TE(la_data_out_enable)
|
||||
);
|
||||
assign la_data_out_enable = (~la_oenb_mprj) & mprj_logic1[201:74];
|
||||
assign la_data_in_core = la_data_out_mprj & la_data_out_enable;
|
||||
|
||||
/* Project data out enable (bar) from the managment side to the */
|
||||
/* user project area when the user project is powered down. */
|
||||
|
||||
sky130_fd_sc_hd__einvp_8 user_to_mprj_oen_buffers [127:0] (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.Z(la_oenb_core),
|
||||
.A(~la_oenb_mprj),
|
||||
.TE(mprj_logic1[329:202])
|
||||
);
|
||||
assign la_oenb_core = la_oenb_mprj & mprj_logic1[329:202];
|
||||
|
||||
/* The conb cell output is a resistive connection directly to */
|
||||
/* the power supply, so when returning the user1_powergood */
|
||||
/* signal, make sure that it is buffered properly. */
|
||||
|
||||
sky130_fd_sc_hd__buf_8 mprj_pwrgood (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.A(mprj_logic1[461]),
|
||||
.X(user1_vcc_powergood)
|
||||
);
|
||||
assign user1_vcc_powergood = mprj_logic1[461];
|
||||
assign user2_vcc_powergood = mprj2_logic1;
|
||||
assign user1_vdd_powergood = mprj_vdd_logic1;
|
||||
assign user2_vdd_powergood = mprj2_vdd_logic1;
|
||||
|
||||
sky130_fd_sc_hd__buf_8 mprj2_pwrgood (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.A(mprj2_logic1),
|
||||
.X(user2_vcc_powergood)
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__buf_8 mprj_vdd_pwrgood (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.A(mprj_vdd_logic1),
|
||||
.X(user1_vdd_powergood)
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__buf_8 mprj2_vdd_pwrgood (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.A(mprj2_vdd_logic1),
|
||||
.X(user2_vdd_powergood)
|
||||
);
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
|
|
|
|||
Loading…
Reference in New Issue