mirror of https://github.com/efabless/caravel.git
Merge branch 'efabless:caravel_redesign' into caravel_redesign
This commit is contained in:
Mohamed Hosni
GitHub
commit
ee17bcf177
File diff suppressed because it is too large
Load Diff
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@ -8,344 +8,258 @@ MACRO gpio_control_block
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ORIGIN 0.000 0.000 ;
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SIZE 170.000 BY 65.000 ;
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PIN gpio_defaults[0]
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||||
DIRECTION INPUT ;
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||||
USE SIGNAL ;
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||||
PORT
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||||
LAYER met2 ;
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RECT 4.690 61.000 4.970 65.000 ;
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||||
END
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END gpio_defaults[0]
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||||
PIN gpio_defaults[10]
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||||
DIRECTION INPUT ;
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||||
USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 27.690 61.000 27.970 65.000 ;
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||||
END
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END gpio_defaults[10]
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PIN gpio_defaults[11]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 29.990 61.000 30.270 65.000 ;
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END
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END gpio_defaults[11]
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PIN gpio_defaults[12]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 32.290 61.000 32.570 65.000 ;
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END
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END gpio_defaults[12]
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PIN gpio_defaults[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 6.990 61.000 7.270 65.000 ;
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END
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END gpio_defaults[1]
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PIN gpio_defaults[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 9.290 61.000 9.570 65.000 ;
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END
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END gpio_defaults[2]
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PIN gpio_defaults[3]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 11.590 61.000 11.870 65.000 ;
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END
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END gpio_defaults[3]
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PIN gpio_defaults[4]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 13.890 61.000 14.170 65.000 ;
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END
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END gpio_defaults[4]
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PIN gpio_defaults[5]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 16.190 61.000 16.470 65.000 ;
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END
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END gpio_defaults[5]
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PIN gpio_defaults[6]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 18.490 61.000 18.770 65.000 ;
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END
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END gpio_defaults[6]
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PIN gpio_defaults[7]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 20.790 61.000 21.070 65.000 ;
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END
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END gpio_defaults[7]
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PIN gpio_defaults[8]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 23.090 61.000 23.370 65.000 ;
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END
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END gpio_defaults[8]
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PIN gpio_defaults[9]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 25.390 61.000 25.670 65.000 ;
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END
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END gpio_defaults[9]
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PIN mgmt_gpio_in
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 4.120 170.000 4.720 ;
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END
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END mgmt_gpio_in
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PIN mgmt_gpio_oeb
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 8.200 170.000 8.800 ;
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END
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END mgmt_gpio_oeb
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PIN mgmt_gpio_out
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 10.240 170.000 10.840 ;
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END
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END mgmt_gpio_out
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PIN one
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 6.160 170.000 6.760 ;
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END
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END one
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PIN pad_gpio_ana_en
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 12.280 170.000 12.880 ;
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END
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END pad_gpio_ana_en
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PIN pad_gpio_ana_pol
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 14.320 170.000 14.920 ;
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END
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END pad_gpio_ana_pol
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PIN pad_gpio_ana_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 16.360 170.000 16.960 ;
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END
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END pad_gpio_ana_sel
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PIN pad_gpio_dm[0]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 18.400 170.000 19.000 ;
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END
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END pad_gpio_dm[0]
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PIN pad_gpio_dm[1]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 20.440 170.000 21.040 ;
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END
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END pad_gpio_dm[1]
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PIN pad_gpio_dm[2]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 22.480 170.000 23.080 ;
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END
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END pad_gpio_dm[2]
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PIN pad_gpio_holdover
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 24.520 170.000 25.120 ;
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END
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END pad_gpio_holdover
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PIN pad_gpio_ib_mode_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 26.560 170.000 27.160 ;
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END
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END pad_gpio_ib_mode_sel
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PIN pad_gpio_in
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 28.600 170.000 29.200 ;
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END
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END pad_gpio_in
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PIN pad_gpio_inenb
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 30.640 170.000 31.240 ;
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END
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END pad_gpio_inenb
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PIN pad_gpio_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 32.680 170.000 33.280 ;
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END
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END pad_gpio_out
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PIN pad_gpio_outenb
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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||||
RECT 70.000 34.720 170.000 35.320 ;
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END
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END pad_gpio_outenb
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PIN pad_gpio_slow_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 36.760 170.000 37.360 ;
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END
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END pad_gpio_slow_sel
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PIN pad_gpio_vtrip_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 38.800 170.000 39.400 ;
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END
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END pad_gpio_vtrip_sel
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PIN resetn
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 40.840 170.000 41.440 ;
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END
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END resetn
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PIN resetn_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 42.880 170.000 43.480 ;
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END
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END resetn_out
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PIN serial_clock
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 44.920 170.000 45.520 ;
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END
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END serial_clock
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PIN serial_clock_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 46.960 170.000 47.560 ;
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||||
END
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END serial_clock_out
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PIN serial_data_in
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 49.000 170.000 49.600 ;
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END
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END serial_data_in
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PIN serial_data_out
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DIRECTION OUTPUT TRISTATE ;
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||||
USE SIGNAL ;
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PORT
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LAYER met3 ;
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||||
RECT 70.000 51.040 170.000 51.640 ;
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||||
END
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END serial_data_out
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||||
PIN serial_load
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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||||
LAYER met3 ;
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||||
RECT 70.000 53.080 170.000 53.680 ;
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||||
END
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END serial_load
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PIN serial_load_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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||||
LAYER met3 ;
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||||
RECT 70.000 55.120 170.000 55.720 ;
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END
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END serial_load_out
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PIN user_gpio_in
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DIRECTION OUTPUT TRISTATE ;
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||||
USE SIGNAL ;
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PORT
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LAYER met3 ;
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||||
RECT 70.000 57.160 170.000 57.760 ;
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END
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END user_gpio_in
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||||
PIN user_gpio_oeb
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DIRECTION INPUT ;
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||||
USE SIGNAL ;
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PORT
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||||
LAYER met3 ;
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||||
RECT 70.000 59.200 170.000 59.800 ;
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||||
END
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||||
END user_gpio_oeb
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||||
PIN user_gpio_out
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DIRECTION INPUT ;
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||||
USE SIGNAL ;
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||||
PORT
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||||
LAYER met3 ;
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||||
RECT 70.000 61.240 170.000 61.840 ;
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||||
END
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||||
END user_gpio_out
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||||
PIN vccd
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||||
DIRECTION INOUT ;
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||||
USE POWER ;
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||||
PORT
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||||
LAYER met4 ;
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||||
RECT 12.800 2.480 14.400 60.080 ;
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||||
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|
@ -372,8 +286,6 @@ MACRO gpio_control_block
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|||
END
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||||
END vccd
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||||
PIN vccd1
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||||
DIRECTION INOUT ;
|
||||
USE POWER ;
|
||||
PORT
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||||
LAYER met4 ;
|
||||
RECT 17.800 2.480 19.400 60.080 ;
|
||||
|
|
@ -396,8 +308,6 @@ MACRO gpio_control_block
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|||
END
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||||
END vccd1
|
||||
PIN vssd
|
||||
DIRECTION INOUT ;
|
||||
USE GROUND ;
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 25.300 2.480 26.900 60.080 ;
|
||||
|
|
@ -416,8 +326,6 @@ MACRO gpio_control_block
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|||
END
|
||||
END vssd
|
||||
PIN vssd1
|
||||
DIRECTION INOUT ;
|
||||
USE GROUND ;
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 30.300 2.480 31.900 60.080 ;
|
||||
|
|
@ -436,8 +344,6 @@ MACRO gpio_control_block
|
|||
END
|
||||
END vssd1
|
||||
PIN zero
|
||||
DIRECTION OUTPUT TRISTATE ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER met3 ;
|
||||
RECT 70.000 2.080 170.000 2.680 ;
|
||||
|
|
@ -445,272 +351,24 @@ MACRO gpio_control_block
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|||
END zero
|
||||
OBS
|
||||
LAYER li1 ;
|
||||
RECT 0.000 64.930 4.265 65.070 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.265 64.930 169.810 65.000 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 64.845 49.815 64.930 ;
|
||||
LAYER li1 ;
|
||||
RECT 49.815 64.845 169.810 64.930 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 59.925 169.810 64.845 ;
|
||||
RECT 0.000 59.755 4.745 59.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 59.755 169.810 59.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 59.585 169.810 59.755 ;
|
||||
RECT 0.000 58.605 6.505 59.585 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.505 58.605 169.810 59.585 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 58.445 6.585 58.605 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.585 58.445 169.810 58.605 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 58.195 6.085 58.445 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.085 58.195 169.810 58.445 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 58.005 6.585 58.195 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.585 58.005 169.810 58.195 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 57.405 6.505 58.005 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.505 57.405 169.810 58.005 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 30.025 4.265 57.405 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.265 30.025 169.810 57.405 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 30.005 16.795 30.025 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 30.005 169.810 30.025 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.835 4.745 30.005 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 29.835 169.810 30.005 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.655 16.795 29.835 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 29.655 169.810 29.835 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.640 16.910 29.655 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.910 29.640 169.810 29.655 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.395 8.925 29.640 ;
|
||||
LAYER li1 ;
|
||||
RECT 8.925 29.395 169.810 29.640 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.095 7.545 29.395 ;
|
||||
LAYER li1 ;
|
||||
RECT 7.545 29.095 169.810 29.395 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 28.925 7.845 29.095 ;
|
||||
LAYER li1 ;
|
||||
RECT 7.845 28.925 169.810 29.095 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 28.305 6.125 28.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.125 28.305 169.810 28.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 27.785 7.845 28.305 ;
|
||||
LAYER li1 ;
|
||||
RECT 7.845 27.785 169.810 28.305 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 27.455 7.625 27.785 ;
|
||||
LAYER li1 ;
|
||||
RECT 7.625 27.455 169.810 27.785 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 27.285 16.795 27.455 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 27.285 169.810 27.455 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 27.115 4.745 27.285 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 27.115 169.810 27.285 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 26.095 16.795 27.115 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 26.095 169.810 27.115 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 25.475 16.705 26.095 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.705 25.475 169.810 26.095 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 24.565 16.795 25.475 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 24.565 169.810 25.475 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 24.395 15.325 24.565 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 24.395 169.810 24.565 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 21.845 16.795 24.395 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 21.845 169.810 24.395 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 21.675 15.325 21.845 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 21.675 169.810 21.845 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 20.865 16.950 21.675 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.950 20.865 169.810 21.675 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 20.365 16.795 20.865 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 20.365 169.810 20.865 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 19.805 16.645 20.365 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.645 19.805 169.810 20.365 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 19.635 16.795 19.805 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 19.635 169.810 19.805 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 19.125 16.950 19.635 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.950 19.125 169.810 19.635 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 18.955 15.325 19.125 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 18.955 169.810 19.125 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 16.405 16.795 18.955 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 16.405 169.810 18.955 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 16.235 15.325 16.405 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 16.235 169.810 16.405 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 15.425 16.950 16.235 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.950 15.425 169.810 16.235 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 14.925 16.795 15.425 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 14.925 169.810 15.425 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 14.365 16.645 14.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.645 14.365 169.810 14.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 14.195 16.795 14.365 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 14.195 169.810 14.365 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 13.685 16.950 14.195 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.950 13.685 169.810 14.195 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 13.515 15.325 13.685 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 13.515 169.810 13.685 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 12.675 16.910 13.515 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.910 12.675 169.810 13.515 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 12.115 16.795 12.675 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 12.115 169.810 12.675 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 10.965 16.910 12.115 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.910 10.965 169.810 12.115 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 10.795 15.325 10.965 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 10.795 169.810 10.965 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 10.625 16.795 10.795 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 10.625 169.810 10.795 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 8.415 16.645 10.625 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.645 8.415 169.810 10.625 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 8.245 16.795 8.415 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 8.245 169.810 8.415 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 8.075 15.325 8.245 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 8.075 169.810 8.245 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 7.905 16.795 8.075 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 7.905 169.810 8.075 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 5.695 16.645 7.905 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.645 5.695 169.810 7.905 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 5.525 16.795 5.695 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 5.525 169.810 5.695 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 5.355 4.745 5.525 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 5.355 169.810 5.525 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 5.185 16.795 5.355 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 5.185 169.810 5.355 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 4.205 6.505 5.185 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.505 4.205 169.810 5.185 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 4.045 6.585 4.205 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.585 4.045 169.810 4.205 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 3.795 6.085 4.045 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.085 3.795 169.810 4.045 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 3.605 6.585 3.795 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.585 3.605 169.810 3.795 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 2.975 6.505 3.605 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.505 2.975 169.810 3.605 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 2.805 16.795 2.975 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 2.805 169.810 2.975 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 2.635 4.745 2.805 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 2.635 169.810 2.805 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 0.000 16.795 2.635 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 0.000 169.810 2.635 ;
|
||||
RECT 4.600 2.635 51.980 59.925 ;
|
||||
LAYER met1 ;
|
||||
RECT 4.600 0.000 170.000 65.000 ;
|
||||
RECT 4.600 2.480 103.890 60.480 ;
|
||||
LAYER met2 ;
|
||||
RECT 5.250 60.720 6.710 65.000 ;
|
||||
RECT 7.550 60.720 9.010 65.000 ;
|
||||
RECT 9.850 60.720 11.310 65.000 ;
|
||||
RECT 12.150 60.720 13.610 65.000 ;
|
||||
RECT 14.450 60.720 15.910 65.000 ;
|
||||
RECT 16.750 60.720 18.210 65.000 ;
|
||||
RECT 19.050 60.720 20.510 65.000 ;
|
||||
RECT 21.350 60.720 22.810 65.000 ;
|
||||
RECT 23.650 60.720 25.110 65.000 ;
|
||||
RECT 25.950 60.720 27.410 65.000 ;
|
||||
RECT 28.250 60.720 29.710 65.000 ;
|
||||
RECT 30.550 60.720 32.010 65.000 ;
|
||||
RECT 32.850 60.720 170.000 65.000 ;
|
||||
RECT 4.970 0.000 170.000 60.720 ;
|
||||
RECT 5.250 60.720 6.710 61.725 ;
|
||||
RECT 7.550 60.720 9.010 61.725 ;
|
||||
RECT 9.850 60.720 11.310 61.725 ;
|
||||
RECT 12.150 60.720 13.610 61.725 ;
|
||||
RECT 14.450 60.720 15.910 61.725 ;
|
||||
RECT 16.750 60.720 18.210 61.725 ;
|
||||
RECT 19.050 60.720 20.510 61.725 ;
|
||||
RECT 21.350 60.720 22.810 61.725 ;
|
||||
RECT 23.650 60.720 25.110 61.725 ;
|
||||
RECT 25.950 60.720 27.410 61.725 ;
|
||||
RECT 28.250 60.720 29.710 61.725 ;
|
||||
RECT 30.550 60.720 32.010 61.725 ;
|
||||
RECT 32.850 60.720 103.870 61.725 ;
|
||||
RECT 4.970 2.195 103.870 60.720 ;
|
||||
LAYER met3 ;
|
||||
RECT 6.045 60.840 69.600 61.705 ;
|
||||
RECT 6.045 60.200 70.000 60.840 ;
|
||||
|
|
@ -772,31 +430,13 @@ MACRO gpio_control_block
|
|||
RECT 6.045 3.080 70.000 3.720 ;
|
||||
RECT 6.045 2.215 69.600 3.080 ;
|
||||
LAYER met4 ;
|
||||
RECT 6.280 60.480 170.000 65.000 ;
|
||||
RECT 6.280 2.080 12.400 60.480 ;
|
||||
RECT 14.800 2.080 17.400 60.480 ;
|
||||
RECT 19.800 2.080 24.900 60.480 ;
|
||||
RECT 27.300 2.080 29.900 60.480 ;
|
||||
RECT 32.300 2.080 37.400 60.480 ;
|
||||
RECT 39.800 2.080 42.400 60.480 ;
|
||||
RECT 44.800 2.080 170.000 60.480 ;
|
||||
RECT 6.280 0.000 170.000 2.080 ;
|
||||
LAYER met5 ;
|
||||
RECT 50.000 59.800 170.000 65.000 ;
|
||||
RECT 51.600 51.790 170.000 59.800 ;
|
||||
RECT 50.000 51.350 170.000 51.790 ;
|
||||
RECT 51.600 43.340 170.000 51.350 ;
|
||||
RECT 50.000 42.900 170.000 43.340 ;
|
||||
RECT 51.600 34.890 170.000 42.900 ;
|
||||
RECT 50.000 34.450 170.000 34.890 ;
|
||||
RECT 51.600 26.440 170.000 34.450 ;
|
||||
RECT 50.000 26.000 170.000 26.440 ;
|
||||
RECT 51.600 17.990 170.000 26.000 ;
|
||||
RECT 50.000 17.550 170.000 17.990 ;
|
||||
RECT 51.600 9.540 170.000 17.550 ;
|
||||
RECT 50.000 9.100 170.000 9.540 ;
|
||||
RECT 51.600 4.300 170.000 9.100 ;
|
||||
RECT 50.000 0.000 170.000 4.300 ;
|
||||
RECT 6.280 8.160 12.400 52.185 ;
|
||||
RECT 14.800 8.160 17.400 52.185 ;
|
||||
RECT 19.800 8.160 24.900 52.185 ;
|
||||
RECT 27.300 8.160 29.900 52.185 ;
|
||||
RECT 32.300 8.160 37.400 52.185 ;
|
||||
RECT 39.800 8.160 42.400 52.185 ;
|
||||
RECT 44.800 8.160 45.705 52.185 ;
|
||||
END
|
||||
END gpio_control_block
|
||||
END LIBRARY
|
||||
|
|
|
|||
1226
lef/simple_por.lef
1226
lef/simple_por.lef
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1665142206
|
||||
timestamp 1665359486
|
||||
<< obsli1 >>
|
||||
rect 0 13000 853 13014
|
||||
rect 0 0 33962 13000
|
||||
|
|
@ -303,8 +303,8 @@ port 47 nsew signal output
|
|||
string FIXED_BBOX 0 0 34000 13000
|
||||
string LEFclass BLOCK
|
||||
string LEFview TRUE
|
||||
string GDS_END 560298
|
||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_10_07_04_28/results/signoff/gpio_control_block.magic.gds
|
||||
string GDS_START 184426
|
||||
string GDS_END 562744
|
||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_10_09_16_50/results/signoff/gpio_control_block.magic.gds
|
||||
string GDS_START 196838
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
9
manifest
9
manifest
|
|
@ -1,7 +1,9 @@
|
|||
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
|
||||
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
|
||||
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
|
||||
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
|
||||
1315c3df4decc1a015ec78dfb7df174eb3a74e9a verilog/rtl/__user_project_gpio_example.v
|
||||
5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v
|
||||
ef356bbc8938fef0c1866a709a3bf846d8c7e1e4 verilog/rtl/__user_project_wrapper.v
|
||||
f93c57988b0044d2bff4470a84b5eddc158f2094 verilog/rtl/caravan.v
|
||||
1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v
|
||||
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
|
||||
|
|
@ -13,12 +15,13 @@ d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
|
|||
97c958944dd74a87f75d9fe2309837e567468722 verilog/rtl/chip_io_alt.v
|
||||
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
|
||||
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
|
||||
653b230c7cbf092a6210ba7820bc942f312e53f3 verilog/rtl/debug_regs.v
|
||||
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
|
||||
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
||||
1f894f1c43d42017c157d8dd7d2e4674c1a43303 verilog/rtl/gpio_control_block.v
|
||||
00d2c61e4f424dfce3635f96a1c1bfdeaf7d0cf8 verilog/rtl/gpio_control_block.v
|
||||
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
|
||||
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
||||
9b602cb0e7f0e6b7e21d87d3a2bd30cb631302c4 verilog/rtl/housekeeping.v
|
||||
4290fcaf6bbcff701c2c47c7a23ce4fd4698e888 verilog/rtl/housekeeping.v
|
||||
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
|
||||
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
|
||||
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ set ::env(FP_PDN_VSPACING) 3.4
|
|||
set ::env(FP_PDN_HSPACING) 3.4
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.9
|
||||
set ::env(PL_TARGET_DENSITY) 0.95
|
||||
# for some reason resizer is leaving a floating net after running repair_tie_fanout command
|
||||
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 0
|
||||
|
||||
|
|
@ -155,3 +155,4 @@ set ::env(DRC_EXCLUDE_CELL_LIST) $::env(DESIGN_DIR)/drc_exclude_list.txt
|
|||
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) $::env(DESIGN_DIR)/drc_exclude_list.txt
|
||||
set ::env(RSZ_DONT_TOUCH) "user_gpio_out user_gpio_oeb serial_clock_out serial_load_out gpio_defaults*"
|
||||
set ::env(FP_PDN_SKIPTRIM) 1
|
||||
set ::env(MAGIC_NO_DEF_BLOCKAGES) 1
|
||||
|
|
|
|||
|
|
@ -55,9 +55,9 @@ proc custom_run_placement {args} {
|
|||
}
|
||||
|
||||
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
|
||||
prep -design $SCRIPT_DIR -tag $::env(TAG) -overwrite -verbose 0
|
||||
prep -ignore_mismatches -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 0
|
||||
exec rm -rf $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
exec ln -sf $SCRIPT_DIR/runs/$::env(TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
run_synthesis
|
||||
|
||||
init_floorplan
|
||||
|
|
@ -107,7 +107,7 @@ run_antenna_check
|
|||
run_lef_cvc
|
||||
calc_total_runtime
|
||||
save_final_views
|
||||
save_final_views -save_path .. -tag $::env(RUN_TAG)
|
||||
save_final_views -save_path .. -tag $::env(RUN_OPENLANE_RUN_TAG)
|
||||
save_state
|
||||
generate_final_summary_report
|
||||
check_timing_violations
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Fri Oct 7 11:29:34 2022
|
||||
# Sun Oct 9 23:50:57 2022
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
###############################################################################
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1 +1 @@
|
|||
open_pdks fa87f8f4bbcc7255b6f0c0fb506960f531ae2392
|
||||
open_pdks de752ec0ba4da0ecb1fbcd309eeec4993d88f5bc
|
||||
|
|
|
|||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_design_area
|
||||
============================================================================
|
||||
Design area 2408 u^2 89% utilization.
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
|
||||
===========================================================================
|
||||
report_clock_skew
|
||||
============================================================================
|
||||
Clock serial_clock
|
||||
Latency CRPR Skew
|
||||
_122_/CLK ^
|
||||
0.85
|
||||
_123_/CLK ^
|
||||
0.76 -0.06 0.02
|
||||
|
||||
Clock serial_load
|
||||
No launch/capture paths found.
|
||||
|
||||
|
|
@ -0,0 +1,679 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -path_delay max (Setup)
|
||||
============================================================================
|
||||
Startpoint: gpio_defaults[12] (input port clocked by serial_clock)
|
||||
Endpoint: _115_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[12] (in)
|
||||
4 0.02 gpio_defaults[12] (net)
|
||||
5.00 0.00 10.00 v _087_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.73 1.27 11.27 ^ _087_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _020_ (net)
|
||||
0.73 0.00 11.27 ^ _115_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.27 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.82 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.03 0.00 50.82 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.05 50.37 library recovery time
|
||||
50.37 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.37 data required time
|
||||
-11.27 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.11 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[4] (input port clocked by serial_clock)
|
||||
Endpoint: _111_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[4] (in)
|
||||
4 0.03 gpio_defaults[4] (net)
|
||||
5.00 0.00 10.00 v _079_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.70 1.22 11.22 ^ _079_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _012_ (net)
|
||||
0.70 0.00 11.22 ^ _111_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.22 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.18 50.77 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 50.77 ^ _098__6/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.80 v _098__6/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net37 (net)
|
||||
0.03 0.00 50.81 v _111_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.41 clock uncertainty
|
||||
0.00 50.41 clock reconvergence pessimism
|
||||
-0.05 50.36 library recovery time
|
||||
50.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.36 data required time
|
||||
-11.22 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.14 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[5] (input port clocked by serial_clock)
|
||||
Endpoint: _116_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[5] (in)
|
||||
4 0.02 gpio_defaults[5] (net)
|
||||
5.00 0.00 10.00 v _089_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.68 1.20 11.20 ^ _089_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _022_ (net)
|
||||
0.68 0.00 11.20 ^ _116_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.20 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.18 50.77 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 50.77 ^ _103__11/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 50.80 v _103__11/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net42 (net)
|
||||
0.02 0.00 50.80 v _116_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.40 clock uncertainty
|
||||
0.00 50.40 clock reconvergence pessimism
|
||||
-0.05 50.36 library recovery time
|
||||
50.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.36 data required time
|
||||
-11.20 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.16 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[11] (input port clocked by serial_clock)
|
||||
Endpoint: _114_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[11] (in)
|
||||
4 0.02 gpio_defaults[11] (net)
|
||||
5.00 0.00 10.00 v _085_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.70 1.22 11.22 ^ _085_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _018_ (net)
|
||||
0.70 0.00 11.22 ^ _114_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.22 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _101__9/A (sky130_fd_sc_hd__inv_2)
|
||||
0.04 0.05 50.83 v _101__9/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net40 (net)
|
||||
0.04 0.00 50.83 v _114_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.43 clock uncertainty
|
||||
0.00 50.43 clock reconvergence pessimism
|
||||
-0.04 50.38 library recovery time
|
||||
50.38 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.38 data required time
|
||||
-11.22 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.16 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[3] (input port clocked by serial_clock)
|
||||
Endpoint: _110_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[3] (in)
|
||||
4 0.02 gpio_defaults[3] (net)
|
||||
5.00 0.00 10.00 v _077_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.68 1.20 11.20 ^ _077_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _010_ (net)
|
||||
0.68 0.00 11.20 ^ _110_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.20 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _097__5/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _097__5/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net36 (net)
|
||||
0.03 0.00 50.82 v _110_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.04 50.38 library recovery time
|
||||
50.38 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.38 data required time
|
||||
-11.20 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.18 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.22 26.77 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 26.77 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.07 26.84 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.05 0.00 26.84 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.10 0.41 27.25 ^ _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.10 0.00 27.25 ^ output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.27 0.29 27.54 ^ output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.27 0.01 27.55 ^ serial_data_out (out)
|
||||
27.55 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.55 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.05 slack (MET)
|
||||
|
||||
|
||||
Startpoint: serial_load (clock source 'serial_load')
|
||||
Endpoint: serial_load_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_load (fall edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.23 26.77 v clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.06 0.00 26.77 v serial_load_out_buffer/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.26 27.03 v serial_load_out_buffer/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
1 0.25 serial_load_out (net)
|
||||
0.18 0.03 27.06 v serial_load_out (out)
|
||||
27.06 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.06 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.54 slack (MET)
|
||||
|
||||
|
||||
Startpoint: serial_clock (clock source 'serial_clock')
|
||||
Endpoint: serial_clock_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock (fall edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.22 26.76 v clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.04 0.00 26.76 v serial_clock_out_buffer/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.26 27.03 v serial_clock_out_buffer/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
1 0.25 serial_clock_out (net)
|
||||
0.18 0.02 27.04 v serial_clock_out (out)
|
||||
27.04 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.04 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.56 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _131_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.19 0.84 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.84 ^ _131_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.50 1.34 v _131_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
2 0.01 shift_register[12] (net)
|
||||
0.06 0.00 1.34 v _132_/D (sky130_fd_sc_hd__dfrtp_2)
|
||||
1.34 data arrival time
|
||||
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.40 26.40 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.40 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.20 26.60 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 26.60 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.06 26.66 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.05 0.00 26.66 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
-0.40 26.26 clock uncertainty
|
||||
0.06 26.32 clock reconvergence pessimism
|
||||
-0.12 26.20 library setup time
|
||||
26.20 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
26.20 data required time
|
||||
-1.34 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
24.86 slack (MET)
|
||||
|
||||
|
||||
Startpoint: mgmt_gpio_oeb (input port clocked by serial_clock)
|
||||
Endpoint: pad_gpio_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v mgmt_gpio_oeb (in)
|
||||
2 0.01 mgmt_gpio_oeb (net)
|
||||
5.00 0.00 10.00 v input1/A (sky130_fd_sc_hd__buf_2)
|
||||
0.16 1.31 11.31 v input1/X (sky130_fd_sc_hd__buf_2)
|
||||
2 0.01 net1 (net)
|
||||
0.16 0.00 11.31 v _063_/C (sky130_fd_sc_hd__and3b_2)
|
||||
0.06 0.30 11.62 v _063_/X (sky130_fd_sc_hd__and3b_2)
|
||||
2 0.01 _043_ (net)
|
||||
0.06 0.00 11.62 v _064_/B (sky130_fd_sc_hd__and2b_2)
|
||||
0.05 0.23 11.85 v _064_/X (sky130_fd_sc_hd__and2b_2)
|
||||
1 0.01 _044_ (net)
|
||||
0.05 0.00 11.85 v _066_/A1 (sky130_fd_sc_hd__o21ai_4)
|
||||
0.17 0.20 12.04 ^ _066_/Y (sky130_fd_sc_hd__o21ai_4)
|
||||
1 0.02 net16 (net)
|
||||
0.17 0.00 12.04 ^ output16/A (sky130_fd_sc_hd__buf_16)
|
||||
0.27 0.31 12.35 ^ output16/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 pad_gpio_out (net)
|
||||
0.27 0.01 12.36 ^ pad_gpio_out (out)
|
||||
12.36 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-12.36 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
27.24 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.50 1.35 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.06 0.00 1.35 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.09 0.64 1.98 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.09 0.00 1.98 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.98 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 50.82 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.25 library setup time
|
||||
50.25 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.25 data required time
|
||||
-1.98 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _129_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _113_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.19 0.84 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.84 ^ _129_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.48 1.32 v _129_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[10] (net)
|
||||
0.05 0.00 1.32 v hold9/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.09 0.63 1.95 v hold9/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net54 (net)
|
||||
0.09 0.00 1.95 v _113_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.95 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.18 50.77 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 50.77 ^ _100__8/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.03 50.80 v _100__8/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net39 (net)
|
||||
0.02 0.00 50.80 v _113_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.40 clock uncertainty
|
||||
0.00 50.40 clock reconvergence pessimism
|
||||
-0.18 50.22 library setup time
|
||||
50.22 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.22 data required time
|
||||
-1.95 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _120_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _112_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _120_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.49 1.34 v _120_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[1] (net)
|
||||
0.06 0.00 1.34 v hold6/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.63 1.97 v hold6/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net51 (net)
|
||||
0.08 0.00 1.97 v _112_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.97 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _099__7/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.82 v _099__7/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net38 (net)
|
||||
0.03 0.00 50.82 v _112_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.24 library setup time
|
||||
50.24 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.24 data required time
|
||||
-1.97 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _122_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _110_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _122_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.49 1.34 v _122_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[3] (net)
|
||||
0.06 0.00 1.34 v hold7/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.63 1.96 v hold7/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net52 (net)
|
||||
0.08 0.00 1.96 v _110_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.96 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _097__5/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _097__5/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net36 (net)
|
||||
0.03 0.00 50.82 v _110_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.25 library setup time
|
||||
50.25 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.25 data required time
|
||||
-1.96 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.29 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _124_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _116_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _124_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.48 1.32 v _124_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[5] (net)
|
||||
0.05 0.00 1.32 v hold13/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.61 1.94 v hold13/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net58 (net)
|
||||
0.08 0.00 1.94 v _116_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.94 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.18 50.77 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 50.77 ^ _103__11/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 50.80 v _103__11/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net42 (net)
|
||||
0.02 0.00 50.80 v _116_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.40 clock uncertainty
|
||||
0.00 50.40 clock reconvergence pessimism
|
||||
-0.17 50.23 library setup time
|
||||
50.23 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.23 data required time
|
||||
-1.94 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.30 slack (MET)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,714 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -path_delay min (Hold)
|
||||
============================================================================
|
||||
Startpoint: gpio_defaults[0] (input port clocked by serial_clock)
|
||||
Endpoint: _106_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[0] (in)
|
||||
4 0.03 gpio_defaults[0] (net)
|
||||
5.00 0.00 10.00 ^ _068_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.07 0.29 10.29 ^ _068_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _001_ (net)
|
||||
0.07 0.00 10.29 ^ _106_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.29 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _058__1/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 0.91 v _058__1/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net32 (net)
|
||||
0.03 0.00 0.91 v _106_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.07 1.38 library removal time
|
||||
1.38 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.38 data required time
|
||||
-10.29 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[10] (input port clocked by serial_clock)
|
||||
Endpoint: _113_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[10] (in)
|
||||
4 0.02 gpio_defaults[10] (net)
|
||||
5.00 0.00 10.00 ^ _082_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.06 0.28 10.28 ^ _082_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _015_ (net)
|
||||
0.06 0.00 10.28 ^ _113_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.28 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _100__8/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 0.89 v _100__8/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net39 (net)
|
||||
0.02 0.00 0.89 v _113_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.29 clock uncertainty
|
||||
0.00 1.29 clock reconvergence pessimism
|
||||
0.07 1.36 library removal time
|
||||
1.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.36 data required time
|
||||
-10.28 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[2] (input port clocked by serial_clock)
|
||||
Endpoint: _107_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[2] (in)
|
||||
4 0.02 gpio_defaults[2] (net)
|
||||
5.00 0.00 10.00 ^ _070_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.08 0.30 10.30 ^ _070_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _003_ (net)
|
||||
0.08 0.00 10.30 ^ _107_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.30 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 0.91 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 0.91 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.07 1.38 library removal time
|
||||
1.38 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.38 data required time
|
||||
-10.30 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[7] (input port clocked by serial_clock)
|
||||
Endpoint: _118_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[7] (in)
|
||||
4 0.02 gpio_defaults[7] (net)
|
||||
5.00 0.00 10.00 ^ _092_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.06 0.28 10.28 ^ _092_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _025_ (net)
|
||||
0.06 0.00 10.28 ^ _118_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.28 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _105__13/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 0.88 v _105__13/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.00 net44 (net)
|
||||
0.02 0.00 0.88 v _118_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.28 clock uncertainty
|
||||
0.00 1.28 clock reconvergence pessimism
|
||||
0.07 1.35 library removal time
|
||||
1.35 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.35 data required time
|
||||
-10.28 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.93 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[6] (input port clocked by serial_clock)
|
||||
Endpoint: _117_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[6] (in)
|
||||
4 0.02 gpio_defaults[6] (net)
|
||||
5.00 0.00 10.00 ^ _090_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.07 0.29 10.29 ^ _090_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _023_ (net)
|
||||
0.07 0.00 10.29 ^ _117_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.29 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _104__12/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 0.88 v _104__12/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.00 net43 (net)
|
||||
0.02 0.00 0.88 v _117_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.28 clock uncertainty
|
||||
0.00 1.28 clock reconvergence pessimism
|
||||
0.07 1.35 library removal time
|
||||
1.35 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.35 data required time
|
||||
-10.29 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.94 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _123_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _124_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _123_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _123_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[4] (net)
|
||||
0.05 0.00 1.13 ^ hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.66 ^ hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net53 (net)
|
||||
0.08 0.00 1.66 ^ _124_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _124_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.25 clock uncertainty
|
||||
-0.06 1.18 clock reconvergence pessimism
|
||||
-0.04 1.14 library hold time
|
||||
1.14 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.14 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.52 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _130_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _131_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _130_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _130_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[11] (net)
|
||||
0.05 0.00 1.13 ^ hold4/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.07 0.53 1.66 ^ hold4/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net49 (net)
|
||||
0.07 0.00 1.66 ^ _131_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.19 0.84 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.84 ^ _131_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.24 clock uncertainty
|
||||
-0.06 1.18 clock reconvergence pessimism
|
||||
-0.04 1.14 library hold time
|
||||
1.14 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.14 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.52 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _127_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _128_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _127_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.14 ^ _127_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[8] (net)
|
||||
0.05 0.00 1.14 ^ hold10/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.67 ^ hold10/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net55 (net)
|
||||
0.08 0.00 1.67 ^ _128_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.67 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.19 0.84 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.84 ^ _128_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.24 clock uncertainty
|
||||
-0.06 1.18 clock reconvergence pessimism
|
||||
-0.04 1.14 library hold time
|
||||
1.14 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.14 data required time
|
||||
-1.67 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.53 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _119_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _120_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _119_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.04 0.36 1.12 ^ _119_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[0] (net)
|
||||
0.04 0.00 1.12 ^ hold1/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.11 0.55 1.68 ^ hold1/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net46 (net)
|
||||
0.11 0.00 1.68 ^ _120_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.68 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _120_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.25 clock uncertainty
|
||||
-0.06 1.19 clock reconvergence pessimism
|
||||
-0.05 1.14 library hold time
|
||||
1.14 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.14 data required time
|
||||
-1.68 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.54 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _125_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _126_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _125_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _125_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[6] (net)
|
||||
0.05 0.00 1.13 ^ hold12/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.67 ^ hold12/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net57 (net)
|
||||
0.08 0.00 1.67 ^ _126_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.67 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _126_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.25 clock uncertainty
|
||||
-0.08 1.17 clock reconvergence pessimism
|
||||
-0.04 1.13 library hold time
|
||||
1.13 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.13 data required time
|
||||
-1.67 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.54 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _130_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _114_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _130_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _130_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[11] (net)
|
||||
0.05 0.00 1.13 ^ hold4/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.07 0.53 1.66 ^ hold4/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net49 (net)
|
||||
0.07 0.00 1.66 ^ _114_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _101__9/A (sky130_fd_sc_hd__inv_2)
|
||||
0.04 0.05 0.91 v _101__9/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net40 (net)
|
||||
0.04 0.00 0.91 v _114_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.04 1.36 library hold time
|
||||
1.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.36 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.30 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _131_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _115_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _131_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.39 1.15 ^ _131_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
2 0.01 shift_register[12] (net)
|
||||
0.06 0.00 1.15 ^ hold3/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.05 0.51 1.66 ^ hold3/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
1 0.00 net48 (net)
|
||||
0.05 0.00 1.66 ^ _115_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 0.91 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.03 0.00 0.91 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.05 1.36 library hold time
|
||||
1.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.36 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.31 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _123_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _111_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _123_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _123_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[4] (net)
|
||||
0.05 0.00 1.13 ^ hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.66 ^ hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net53 (net)
|
||||
0.08 0.00 1.66 ^ _111_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _098__6/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 0.89 v _098__6/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net37 (net)
|
||||
0.03 0.00 0.89 v _111_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.29 clock uncertainty
|
||||
0.00 1.29 clock reconvergence pessimism
|
||||
0.04 1.33 library hold time
|
||||
1.33 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.33 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.33 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _119_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _106_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _119_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.04 0.36 1.12 ^ _119_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[0] (net)
|
||||
0.04 0.00 1.12 ^ hold1/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.11 0.55 1.68 ^ hold1/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net46 (net)
|
||||
0.11 0.00 1.68 ^ _106_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.68 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _058__1/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 0.91 v _058__1/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net32 (net)
|
||||
0.03 0.00 0.91 v _106_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.03 1.34 library hold time
|
||||
1.34 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.34 data required time
|
||||
-1.68 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.33 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _127_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _108_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _127_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.14 ^ _127_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[8] (net)
|
||||
0.05 0.00 1.14 ^ hold10/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.67 ^ hold10/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net55 (net)
|
||||
0.08 0.00 1.67 ^ _108_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.67 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _095__3/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 0.89 v _095__3/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net34 (net)
|
||||
0.03 0.00 0.89 v _108_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.29 clock uncertainty
|
||||
0.00 1.29 clock reconvergence pessimism
|
||||
0.04 1.33 library hold time
|
||||
1.33 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.33 data required time
|
||||
-1.67 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.34 slack (MET)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
|
||||
===========================================================================
|
||||
report_power
|
||||
============================================================================
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 2.58e-05 1.05e-06 2.17e-10 2.68e-05 20.0%
|
||||
Combinational 3.88e-05 6.84e-05 7.83e-10 1.07e-04 80.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 6.46e-05 6.95e-05 1.00e-09 1.34e-04 100.0%
|
||||
48.2% 51.8% 0.0%
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -unconstrained
|
||||
============================================================================
|
||||
Startpoint: gpio_defaults[12] (input port clocked by serial_clock)
|
||||
Endpoint: _115_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[12] (in)
|
||||
4 0.02 gpio_defaults[12] (net)
|
||||
5.00 0.00 10.00 v _087_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.73 1.27 11.27 ^ _087_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _020_ (net)
|
||||
0.73 0.00 11.27 ^ _115_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.27 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.82 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.03 0.00 50.82 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.05 50.37 library recovery time
|
||||
50.37 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.37 data required time
|
||||
-11.27 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.11 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.22 26.77 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 26.77 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.07 26.84 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.05 0.00 26.84 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.10 0.41 27.25 ^ _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.10 0.00 27.25 ^ output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.27 0.29 27.54 ^ output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.27 0.01 27.55 ^ serial_data_out (out)
|
||||
27.55 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.55 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.05 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.50 1.35 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.06 0.00 1.35 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.09 0.64 1.98 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.09 0.00 1.98 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.98 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 50.82 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.25 library setup time
|
||||
50.25 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.25 data required time
|
||||
-1.98 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
|
||||
===========================================================================
|
||||
report_checks --slack_max -0.01
|
||||
============================================================================
|
||||
No paths found.
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
|
||||
===========================================================================
|
||||
report_check_types -max_slew -max_cap -max_fanout -violators
|
||||
============================================================================
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
ANTENNA__080__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__081__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_081_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__061__A0/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_087_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__089__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__088__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__084__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__085__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_089_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_086_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_084_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__087__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_085_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__068__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_061_/A0 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__077__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_069_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_079_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__076__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_074_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__074__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__078__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_076_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__086__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__069__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_075_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__062__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_077_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_078_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__091__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_088_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_091_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__090__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__092__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__082__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_082_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_083_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__072__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_073_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_092_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_080_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__079__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__083__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_093_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__093__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_clock_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_clock/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input2_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_071_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_090_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input3_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__075__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__073__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__070__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_068_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input3/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
_070_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input5_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
input2/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_load/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input5/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input4/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input4_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_062_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_load_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input1_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__071__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_072_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input1/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[0] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[10] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[11] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[12] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[1] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[2] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[3] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[4] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[5] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[6] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[7] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[8] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[9] 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
pad_gpio_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
resetn 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_clock 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_data_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_load 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
clkbuf_1_0__f_serial_clock/X 7 9 -2 (VIOLATED)
|
||||
clkbuf_1_1__f_serial_load/X 7 8 (VIOLATED)
|
||||
fanout30/X 7 8 (VIOLATED)
|
||||
|
||||
|
||||
===========================================================================
|
||||
max slew violation count 92
|
||||
max fanout violation count 3
|
||||
max cap violation count 0
|
||||
============================================================================
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_tns
|
||||
============================================================================
|
||||
tns 0.00
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_wns
|
||||
============================================================================
|
||||
wns 0.00
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
===========================================================================
|
||||
report_worst_slack -max (Setup)
|
||||
============================================================================
|
||||
worst slack 12.05
|
||||
|
||||
===========================================================================
|
||||
report_worst_slack -min (Hold)
|
||||
============================================================================
|
||||
worst slack 0.30
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_design_area
|
||||
============================================================================
|
||||
Design area 2408 u^2 89% utilization.
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
|
||||
===========================================================================
|
||||
report_clock_skew
|
||||
============================================================================
|
||||
|
||||
======================== Slowest Corner ==================================
|
||||
|
||||
Clock serial_clock
|
||||
Latency CRPR Skew
|
||||
_122_/CLK ^
|
||||
1.62
|
||||
_123_/CLK ^
|
||||
1.46 -0.12 0.04
|
||||
|
||||
Clock serial_load
|
||||
No launch/capture paths found.
|
||||
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
Clock serial_clock
|
||||
Latency CRPR Skew
|
||||
_122_/CLK ^
|
||||
0.85
|
||||
_123_/CLK ^
|
||||
0.76 -0.06 0.02
|
||||
|
||||
Clock serial_load
|
||||
No launch/capture paths found.
|
||||
|
||||
|
||||
======================= Fastest Corner ===================================
|
||||
|
||||
Clock serial_clock
|
||||
Latency CRPR Skew
|
||||
_122_/CLK ^
|
||||
0.12
|
||||
_123_/CLK ^
|
||||
0.11 -0.00 0.01
|
||||
|
||||
Clock serial_load
|
||||
No launch/capture paths found.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,45 @@
|
|||
|
||||
===========================================================================
|
||||
report_power
|
||||
============================================================================
|
||||
|
||||
|
||||
======================= Slowest Corner =================================
|
||||
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.96e-05 8.16e-07 4.03e-07 2.08e-05 19.8%
|
||||
Combinational 2.99e-05 5.39e-05 9.49e-07 8.47e-05 80.2%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 4.95e-05 5.47e-05 1.35e-06 1.06e-04 100.0%
|
||||
46.9% 51.8% 1.3%
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 2.58e-05 1.05e-06 2.17e-10 2.68e-05 20.0%
|
||||
Combinational 3.88e-05 6.84e-05 3.83e-09 1.07e-04 80.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 6.46e-05 6.95e-05 4.05e-09 1.34e-04 100.0%
|
||||
48.2% 51.8% 0.0%
|
||||
|
||||
|
||||
======================= Fastest Corner =================================
|
||||
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 2.99e-05 1.25e-06 5.32e-10 3.11e-05 18.8%
|
||||
Combinational 5.36e-05 8.05e-05 5.86e-09 1.34e-04 81.2%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 8.35e-05 8.18e-05 6.39e-09 1.65e-04 100.0%
|
||||
50.5% 49.5% 0.0%
|
||||
|
|
@ -0,0 +1,446 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -unconstrained
|
||||
============================================================================
|
||||
|
||||
======================= Slowest Corner ===================================
|
||||
|
||||
Startpoint: gpio_defaults[8] (input port clocked by serial_clock)
|
||||
Endpoint: _108_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
Corner: ss
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[8] (in)
|
||||
4 0.02 gpio_defaults[8] (net)
|
||||
5.00 0.00 10.00 ^ _072_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.29 1.06 11.06 ^ _072_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.01 _005_ (net)
|
||||
0.29 0.00 11.07 ^ _108_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.07 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.18 1.18 51.18 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.18 0.00 51.18 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.10 0.29 51.47 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.10 0.00 51.47 ^ _095__3/A (sky130_fd_sc_hd__inv_2)
|
||||
0.04 0.08 51.55 v _095__3/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net34 (net)
|
||||
0.04 0.00 51.55 v _108_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 51.15 clock uncertainty
|
||||
0.00 51.15 clock reconvergence pessimism
|
||||
-0.18 50.96 library recovery time
|
||||
50.96 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.96 data required time
|
||||
-11.07 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.90 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
Corner: ss
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 1.68 26.68 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 26.68 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.07 0.34 27.01 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.07 0.00 27.02 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.09 0.11 27.13 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.09 0.00 27.13 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.13 0.93 28.05 v _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.13 0.00 28.05 v output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.22 0.42 28.48 v output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.22 0.01 28.48 v serial_data_out (out)
|
||||
28.48 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-28.48 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
11.12 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
Corner: ss
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.18 1.31 1.31 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.18 0.00 1.31 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.09 0.31 1.62 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.09 0.00 1.62 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.12 1.05 2.67 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.12 0.00 2.67 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.18 1.31 3.98 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.18 0.00 3.98 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
3.98 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.18 1.18 51.18 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.18 0.00 51.18 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.12 0.30 51.49 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.12 0.00 51.49 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.09 51.58 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.05 0.00 51.58 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 51.18 clock uncertainty
|
||||
0.00 51.18 clock reconvergence pessimism
|
||||
-0.41 50.77 library setup time
|
||||
50.77 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.77 data required time
|
||||
-3.98 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
46.79 slack (MET)
|
||||
|
||||
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
Startpoint: gpio_defaults[12] (input port clocked by serial_clock)
|
||||
Endpoint: _115_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
Corner: tt
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[12] (in)
|
||||
4 0.02 gpio_defaults[12] (net)
|
||||
5.00 0.00 10.00 v _087_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.73 1.27 11.27 ^ _087_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _020_ (net)
|
||||
0.73 0.00 11.27 ^ _115_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.27 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.82 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.03 0.00 50.82 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.05 50.37 library recovery time
|
||||
50.37 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.37 data required time
|
||||
-11.27 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.11 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
Corner: tt
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.22 26.77 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 26.77 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.07 26.84 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.05 0.00 26.84 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.10 0.41 27.25 ^ _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.10 0.00 27.25 ^ output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.27 0.29 27.54 ^ output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.27 0.01 27.55 ^ serial_data_out (out)
|
||||
27.55 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.55 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.05 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
Corner: tt
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.50 1.35 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.06 0.00 1.35 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.09 0.64 1.98 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.09 0.00 1.98 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.98 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 50.82 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.25 library setup time
|
||||
50.25 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.25 data required time
|
||||
-1.98 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
|
||||
======================= Fastest Corner ===================================
|
||||
|
||||
Startpoint: gpio_defaults[12] (input port clocked by serial_clock)
|
||||
Endpoint: _115_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
Corner: ff
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[12] (in)
|
||||
4 0.02 gpio_defaults[12] (net)
|
||||
5.00 0.00 10.00 v _087_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.56 1.16 11.16 ^ _087_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _020_ (net)
|
||||
0.56 0.00 11.16 ^ _115_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.16 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.13 -0.01 49.99 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.13 0.00 49.99 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.13 50.12 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.06 0.00 50.12 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.03 50.14 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.02 0.00 50.14 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 49.74 clock uncertainty
|
||||
0.00 49.74 clock reconvergence pessimism
|
||||
0.00 49.75 library recovery time
|
||||
49.75 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
49.75 data required time
|
||||
-11.16 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
38.58 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
Corner: ff
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.13 1.22 26.22 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.13 0.00 26.22 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.03 0.16 26.38 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.03 0.00 26.38 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.04 0.05 26.43 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.04 0.00 26.43 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.07 0.26 26.69 ^ _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.07 0.00 26.69 ^ output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.21 0.21 26.90 ^ output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.21 0.01 26.91 ^ serial_data_out (out)
|
||||
26.91 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-26.91 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.69 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
Corner: ff
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.13 -0.01 -0.01 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.13 0.00 -0.01 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.13 0.12 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 0.12 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.31 0.43 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.05 0.00 0.43 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.06 0.42 0.86 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.06 0.00 0.86 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.86 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.13 -0.01 49.99 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.13 0.00 49.99 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.13 50.12 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.06 0.00 50.12 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.03 50.14 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 50.14 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 49.74 clock uncertainty
|
||||
0.00 49.74 clock reconvergence pessimism
|
||||
-0.10 49.65 library setup time
|
||||
49.65 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
49.65 data required time
|
||||
-0.86 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.79 slack (MET)
|
||||
|
||||
|
||||
|
||||
===========================================================================
|
||||
report_checks --slack_max -0.01
|
||||
============================================================================
|
||||
|
||||
======================= Slowest Corner ===================================
|
||||
|
||||
No paths found.
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
No paths found.
|
||||
|
||||
======================= Fastest Corner ===================================
|
||||
|
||||
No paths found.
|
||||
|
|
@ -0,0 +1,334 @@
|
|||
|
||||
===========================================================================
|
||||
report_check_types -max_slew -max_cap -max_fanout -violators
|
||||
============================================================================
|
||||
|
||||
======================= Slowest Corner ===================================
|
||||
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
ANTENNA__080__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__081__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_081_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__061__A0/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_087_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__089__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__088__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__084__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__085__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_089_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_086_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_084_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__087__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_085_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__068__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_061_/A0 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__077__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_069_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__076__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_079_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_074_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__074__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__078__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_076_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__086__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__069__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__062__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_075_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_077_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_078_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__091__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_088_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__090__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_091_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__092__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__082__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_082_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__072__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_083_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_092_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_073_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_080_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__079__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__083__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_093_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_clock_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__093__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_clock/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input2_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_071_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_090_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input3_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__075__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__073__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__070__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_068_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input3/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input5_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_070_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input2/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_load/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input5/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input4/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input4_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_062_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_load_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input1_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__071__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_072_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input1/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[0] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[10] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[11] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[12] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[1] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[2] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[3] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[4] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[5] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[6] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[7] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[8] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[9] 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
pad_gpio_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
resetn 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_clock 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_data_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_load 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
clkbuf_1_0__f_serial_clock/X 7 9 -2 (VIOLATED)
|
||||
clkbuf_1_1__f_serial_load/X 7 8 (VIOLATED)
|
||||
fanout30/X 7 8 (VIOLATED)
|
||||
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
ANTENNA__080__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__081__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_081_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__061__A0/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_087_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__089__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__088__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__084__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__085__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_089_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_086_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_084_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__087__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_085_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__068__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_061_/A0 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__077__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_069_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_079_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__076__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_074_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__074__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__078__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_076_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__086__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__069__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_075_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__062__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_077_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_078_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__091__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_088_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_091_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__090__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__092__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__082__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_082_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_083_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__072__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_073_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_092_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_080_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__079__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__083__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_093_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__093__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_clock_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_clock/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input2_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_071_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_090_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input3_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__075__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__073__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__070__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_068_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input3/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
_070_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input5_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
input2/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_load/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input5/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input4/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input4_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_062_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_load_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input1_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__071__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_072_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input1/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[0] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[10] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[11] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[12] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[1] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[2] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[3] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[4] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[5] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[6] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[7] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[8] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[9] 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
pad_gpio_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
resetn 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_clock 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_data_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_load 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
clkbuf_1_0__f_serial_clock/X 7 9 -2 (VIOLATED)
|
||||
clkbuf_1_1__f_serial_load/X 7 8 (VIOLATED)
|
||||
fanout30/X 7 8 (VIOLATED)
|
||||
|
||||
|
||||
======================= Fastest Corner ===================================
|
||||
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
ANTENNA__080__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__081__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_081_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__061__A0/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_087_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__089__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__084__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__085__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__088__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_086_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_089_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_084_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__087__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_085_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__068__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_061_/A0 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__077__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_069_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_079_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__076__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_074_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__074__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__078__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_076_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__086__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__069__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_075_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__062__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_077_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_078_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_088_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__091__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_091_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__090__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__092__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__082__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_082_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_083_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_092_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_073_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__072__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_080_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__079__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__083__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_093_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__093__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_clock_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_clock/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
_071_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input2_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_090_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input3_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__075__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__073__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_068_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__070__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
input3/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
_070_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input5_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
input2/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_load/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input5/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input4/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input4_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_062_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_load_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input1_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__071__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_072_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input1/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[0] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[10] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[11] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[12] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[1] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[2] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[3] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[4] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[5] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[6] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[7] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[8] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[9] 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
pad_gpio_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
resetn 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_clock 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_data_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_load 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
clkbuf_1_0__f_serial_clock/X 7 9 -2 (VIOLATED)
|
||||
clkbuf_1_1__f_serial_load/X 7 8 (VIOLATED)
|
||||
fanout30/X 7 8 (VIOLATED)
|
||||
|
||||
|
||||
===========================================================================
|
||||
max slew violation count 92
|
||||
max fanout violation count 3
|
||||
max cap violation count 0
|
||||
============================================================================
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_tns
|
||||
============================================================================
|
||||
tns 0.00
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_wns
|
||||
============================================================================
|
||||
wns 0.00
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
===========================================================================
|
||||
report_worst_slack -max (Setup)
|
||||
============================================================================
|
||||
worst slack 11.12
|
||||
|
||||
===========================================================================
|
||||
report_worst_slack -min (Hold)
|
||||
============================================================================
|
||||
worst slack 0.11
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
Instance name, X location, Y location, Voltage
|
||||
_131_, 38.6, 59.84, 1.8
|
||||
_071_, 38.6, 54.4, 1.8
|
||||
_115_, 38.6, 54.4, 1.8
|
||||
hold3, 38.6, 54.4, 1.8
|
||||
_114_, 38.6, 48.96, 1.8
|
||||
hold5, 38.6, 48.96, 1.8
|
||||
hold6, 38.6, 48.96, 1.8
|
||||
hold7, 38.6, 48.96, 1.8
|
||||
_100__8, 38.6, 43.52, 1.8
|
||||
_109_, 38.6, 43.52, 1.8
|
||||
hold10, 38.6, 43.52, 1.8
|
||||
hold2, 38.6, 43.52, 1.8
|
||||
ANTENNA__070__B, 38.6, 38.08, 1.8
|
||||
_108_, 38.6, 38.08, 1.8
|
||||
_129_, 38.6, 38.08, 1.8
|
||||
hold9, 38.6, 38.08, 1.8
|
||||
ANTENNA__093__B, 38.6, 32.64, 1.8
|
||||
_061_, 38.6, 32.64, 1.8
|
||||
_096__4, 38.6, 32.64, 1.8
|
||||
_113_, 38.6, 32.64, 1.8
|
||||
ANTENNA__083__B, 38.6, 27.2, 1.8
|
||||
_066_, 38.6, 27.2, 1.8
|
||||
_082_, 38.6, 27.2, 1.8
|
||||
_083_, 38.6, 27.2, 1.8
|
||||
output17, 38.6, 27.2, 1.8
|
||||
ANTENNA__069__B, 38.6, 21.76, 1.8
|
||||
ANTENNA__092__B, 38.6, 21.76, 1.8
|
||||
_069_, 38.6, 21.76, 1.8
|
||||
_074_, 38.6, 21.76, 1.8
|
||||
_085_, 38.6, 21.76, 1.8
|
||||
output16, 38.6, 21.76, 1.8
|
||||
ANTENNA__074__B, 38.6, 16.32, 1.8
|
||||
_058__1, 38.6, 16.32, 1.8
|
||||
_067_, 38.6, 16.32, 1.8
|
||||
_084_, 38.6, 16.32, 1.8
|
||||
_102__10, 38.6, 16.32, 1.8
|
||||
output15, 38.6, 16.32, 1.8
|
||||
spare_cell, 38.6, 16.32, 1.8
|
||||
_133_, 38.6, 10.88, 1.8
|
||||
fanout31, 38.6, 10.88, 1.8
|
||||
ANTENNA__081__B, 38.6, 5.44, 1.8
|
||||
ANTENNA__082__A, 38.6, 5.44, 1.8
|
||||
ANTENNA__084__B, 38.6, 5.44, 1.8
|
||||
ANTENNA__085__B, 38.6, 5.44, 1.8
|
||||
ANTENNA__087__B, 38.6, 5.44, 1.8
|
||||
ANTENNA_input5_A, 38.6, 5.44, 1.8
|
||||
input1, 38.6, 5.44, 1.8
|
||||
output12, 38.6, 5.44, 1.8
|
||||
output7, 38.6, 5.44, 1.8
|
||||
_072_, 13.6, 54.4, 1.8
|
||||
_107_, 13.6, 54.4, 1.8
|
||||
_110_, 13.6, 48.96, 1.8
|
||||
_119_, 13.6, 48.96, 1.8
|
||||
fanout26, 13.6, 48.96, 1.8
|
||||
_130_, 13.6, 43.52, 1.8
|
||||
hold8, 13.6, 43.52, 1.8
|
||||
output20, 13.6, 43.52, 1.8
|
||||
_111_, 13.6, 38.08, 1.8
|
||||
_123_, 13.6, 38.08, 1.8
|
||||
_116_, 13.6, 32.64, 1.8
|
||||
hold12, 13.6, 32.64, 1.8
|
||||
_126_, 13.6, 27.2, 1.8
|
||||
clkbuf_1_1__f_serial_clock, 13.6, 27.2, 1.8
|
||||
fanout23, 13.6, 27.2, 1.8
|
||||
ANTENNA__077__B, 13.6, 5.44, 1.8
|
||||
ANTENNA__078__B, 13.6, 5.44, 1.8
|
||||
ANTENNA__080__B, 13.6, 5.44, 1.8
|
||||
ANTENNA_fanout27_A, 13.6, 5.44, 1.8
|
||||
ANTENNA_input2_A, 13.6, 5.44, 1.8
|
||||
PHY_2, 13.6, 5.44, 1.8
|
||||
_059__14, 13.6, 5.44, 1.8
|
||||
_098__6, 13.6, 5.44, 1.8
|
||||
PHY_12, 15.18, 21.76, 1.8
|
||||
PHY_14, 15.18, 21.76, 1.8
|
||||
PHY_16, 15.18, 21.76, 1.8
|
||||
_077_, 15.18, 21.76, 1.8
|
||||
_090_, 15.18, 21.76, 1.8
|
||||
clkbuf_1_0__f_serial_load, 15.18, 21.76, 1.8
|
||||
fanout25, 15.18, 21.76, 1.8
|
||||
PHY_13, 51.98, 21.76, 1.8
|
||||
PHY_15, 51.98, 21.76, 1.8
|
||||
_064_, 51.98, 21.76, 1.8
|
||||
input5, 51.98, 21.76, 1.8
|
||||
_117_, 26.89, 21.76, 1.8
|
||||
_134_, 26.89, 21.76, 1.8
|
||||
output18, 26.89, 21.76, 1.8
|
||||
ANTENNA_clkbuf_0_serial_clock_A, 15.18, 16.32, 1.8
|
||||
PHY_10, 15.18, 16.32, 1.8
|
||||
PHY_8, 15.18, 16.32, 1.8
|
||||
_091_, 15.18, 16.32, 1.8
|
||||
output10, 15.18, 16.32, 1.8
|
||||
serial_load_out_buffer, 15.18, 16.32, 1.8
|
||||
PHY_11, 51.98, 16.32, 1.8
|
||||
PHY_9, 51.98, 16.32, 1.8
|
||||
_087_, 51.98, 16.32, 1.8
|
||||
_076_, 26.89, 16.32, 1.8
|
||||
input4, 26.89, 16.32, 1.8
|
||||
output13, 26.89, 16.32, 1.8
|
||||
output14, 26.89, 16.32, 1.8
|
||||
ANTENNA__090__B, 15.18, 10.88, 1.8
|
||||
PHY_4, 15.18, 10.88, 1.8
|
||||
PHY_6, 15.18, 10.88, 1.8
|
||||
_089_, 15.18, 10.88, 1.8
|
||||
_094__2, 15.18, 10.88, 1.8
|
||||
_097__5, 15.18, 10.88, 1.8
|
||||
fanout28, 15.18, 10.88, 1.8
|
||||
serial_clock_out_buffer, 15.18, 10.88, 1.8
|
||||
zero_buffer, 15.18, 10.88, 1.8
|
||||
PHY_5, 51.98, 10.88, 1.8
|
||||
PHY_7, 51.98, 10.88, 1.8
|
||||
_086_, 51.98, 10.88, 1.8
|
||||
input3, 51.98, 10.88, 1.8
|
||||
ANTENNA__061__A0, 26.89, 10.88, 1.8
|
||||
ANTENNA__062__B, 26.89, 10.88, 1.8
|
||||
ANTENNA__076__B, 26.89, 10.88, 1.8
|
||||
ANTENNA__086__B, 26.89, 10.88, 1.8
|
||||
ANTENNA_input3_A, 26.89, 10.88, 1.8
|
||||
ANTENNA_input4_A, 26.89, 10.88, 1.8
|
||||
_103__11, 26.89, 10.88, 1.8
|
||||
_104__12, 26.89, 10.88, 1.8
|
||||
_105__13, 26.89, 10.88, 1.8
|
||||
output11, 26.89, 10.88, 1.8
|
||||
output9, 26.89, 10.88, 1.8
|
||||
PHY_40, 4.6, 59.84, 1.8
|
||||
PHY_41, 51.98, 59.84, 1.8
|
||||
_065_, 51.98, 59.84, 1.8
|
||||
output21, 26.1, 59.84, 1.8
|
||||
PHY_36, 4.6, 54.4, 1.8
|
||||
PHY_38, 4.6, 54.4, 1.8
|
||||
_099__7, 4.6, 54.4, 1.8
|
||||
_132_, 4.6, 54.4, 1.8
|
||||
fanout27, 4.6, 54.4, 1.8
|
||||
output22, 4.6, 54.4, 1.8
|
||||
PHY_37, 51.98, 54.4, 1.8
|
||||
PHY_39, 51.98, 54.4, 1.8
|
||||
_062_, 51.98, 54.4, 1.8
|
||||
fanout24, 26.1, 54.4, 1.8
|
||||
hold1, 26.1, 54.4, 1.8
|
||||
ANTENNA__071__B, 4.6, 48.96, 1.8
|
||||
ANTENNA_clkbuf_0_serial_load_A, 4.6, 48.96, 1.8
|
||||
PHY_32, 4.6, 48.96, 1.8
|
||||
PHY_34, 4.6, 48.96, 1.8
|
||||
_120_, 4.6, 48.96, 1.8
|
||||
_122_, 4.6, 48.96, 1.8
|
||||
PHY_33, 51.98, 48.96, 1.8
|
||||
PHY_35, 51.98, 48.96, 1.8
|
||||
_068_, 51.98, 48.96, 1.8
|
||||
_081_, 51.98, 48.96, 1.8
|
||||
_106_, 26.1, 48.96, 1.8
|
||||
_112_, 26.1, 48.96, 1.8
|
||||
hold4, 26.1, 48.96, 1.8
|
||||
ANTENNA__079__B, 4.6, 43.52, 1.8
|
||||
PHY_28, 4.6, 43.52, 1.8
|
||||
PHY_30, 4.6, 43.52, 1.8
|
||||
_121_, 4.6, 43.52, 1.8
|
||||
hold13, 4.6, 43.52, 1.8
|
||||
PHY_29, 51.98, 43.52, 1.8
|
||||
PHY_31, 51.98, 43.52, 1.8
|
||||
_079_, 51.98, 43.52, 1.8
|
||||
_070_, 26.1, 43.52, 1.8
|
||||
PHY_24, 4.6, 38.08, 1.8
|
||||
PHY_26, 4.6, 38.08, 1.8
|
||||
_080_, 4.6, 38.08, 1.8
|
||||
_095__3, 4.6, 38.08, 1.8
|
||||
clkbuf_0_serial_load, 4.6, 38.08, 1.8
|
||||
output19, 4.6, 38.08, 1.8
|
||||
PHY_25, 51.98, 38.08, 1.8
|
||||
PHY_27, 51.98, 38.08, 1.8
|
||||
_075_, 51.98, 38.08, 1.8
|
||||
_073_, 26.1, 38.08, 1.8
|
||||
_093_, 26.1, 38.08, 1.8
|
||||
_127_, 26.1, 38.08, 1.8
|
||||
_128_, 26.1, 38.08, 1.8
|
||||
ANTENNA__073__B, 4.6, 32.64, 1.8
|
||||
ANTENNA__075__B, 4.6, 32.64, 1.8
|
||||
PHY_20, 4.6, 32.64, 1.8
|
||||
PHY_22, 4.6, 32.64, 1.8
|
||||
_124_, 4.6, 32.64, 1.8
|
||||
_125_, 4.6, 32.64, 1.8
|
||||
PHY_21, 51.98, 32.64, 1.8
|
||||
PHY_23, 51.98, 32.64, 1.8
|
||||
_060_, 51.98, 32.64, 1.8
|
||||
hold11, 26.1, 32.64, 1.8
|
||||
PHY_18, 4.6, 27.2, 1.8
|
||||
_078_, 4.6, 27.2, 1.8
|
||||
_088_, 4.6, 27.2, 1.8
|
||||
clkbuf_0_serial_clock, 4.6, 27.2, 1.8
|
||||
clkbuf_1_1__f_serial_load, 4.6, 27.2, 1.8
|
||||
ANTENNA__082__B, 51.98, 27.2, 1.8
|
||||
PHY_17, 51.98, 27.2, 1.8
|
||||
PHY_19, 51.98, 27.2, 1.8
|
||||
_063_, 51.98, 27.2, 1.8
|
||||
_092_, 26.1, 27.2, 1.8
|
||||
_118_, 26.1, 27.2, 1.8
|
||||
PHY_0, 4.6, 5.44, 1.8
|
||||
clkbuf_1_0__f_serial_clock, 4.6, 5.44, 1.8
|
||||
ANTENNA__068__B, 51.98, 5.44, 1.8
|
||||
PHY_1, 51.98, 5.44, 1.8
|
||||
PHY_3, 51.98, 5.44, 1.8
|
||||
const_source, 51.98, 5.44, 1.8
|
||||
fanout29, 51.98, 5.44, 1.8
|
||||
fanout30, 51.98, 5.44, 1.8
|
||||
input2, 51.98, 5.44, 1.8
|
||||
ANTENNA__072__B, 26.1, 5.44, 1.8
|
||||
ANTENNA__088__B, 26.1, 5.44, 1.8
|
||||
ANTENNA__089__B, 26.1, 5.44, 1.8
|
||||
ANTENNA__091__B, 26.1, 5.44, 1.8
|
||||
ANTENNA_fanout28_A, 26.1, 5.44, 1.8
|
||||
ANTENNA_fanout29_A, 26.1, 5.44, 1.8
|
||||
ANTENNA_input1_A, 26.1, 5.44, 1.8
|
||||
_101__9, 26.1, 5.44, 1.8
|
||||
one_buffer, 26.1, 5.44, 1.8
|
||||
output6, 26.1, 5.44, 1.8
|
||||
output8, 26.1, 5.44, 1.8
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" ?>
|
||||
<report-database>
|
||||
<categories/>
|
||||
<cells>
|
||||
<cell>
|
||||
<name>gpio_control_block</name>
|
||||
</cell>
|
||||
</cells>
|
||||
<items/>
|
||||
</report-database>
|
||||
|
|
@ -0,0 +1 @@
|
|||
$gpio_control_block 100
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
gpio_control_block
|
||||
----------------------------------------
|
||||
[INFO]: COUNT: 0
|
||||
[INFO]: Should be divided by 3 or 4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,9 +1,5 @@
|
|||
* NGSPICE file created from gpio_control_block.ext - technology: sky130A
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_4 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
|
@ -12,6 +8,10 @@
|
|||
.subckt sky130_fd_sc_hd__nand2b_2 A_N B VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_4 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfbbn_2 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
|
||||
.ends
|
||||
|
|
@ -52,10 +52,6 @@
|
|||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
|
@ -68,18 +64,14 @@
|
|||
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__macro_sparecell abstract view
|
||||
.subckt sky130_fd_sc_hd__macro_sparecell VGND VNB VPB VPWR LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for gpio_logic_high abstract view
|
||||
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2_2 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
|
@ -112,40 +104,43 @@
|
|||
+ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
|
||||
+ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
|
||||
+ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
|
||||
X_131_ _131_/CLK hold1/X _086_/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_4
|
||||
XFILLER_9_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_3_89 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_062_ _106_/Q user_gpio_out vssd vssd vccd vccd _062_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_131_ _131_/CLK hold4/X _086_/A vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_4
|
||||
XFILLER_0_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_114_ _101__9/Y hold1/X _084_/X _085_/Y vssd vssd vccd vccd _114_/Q _114_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_114_ _101__9/Y hold4/X _084_/X _085_/Y vssd vssd vccd vccd _114_/Q _114_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xoutput20 _134_/X vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_16
|
||||
Xoutput7 _116_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_16
|
||||
X_104__12 _100__8/A vssd vssd vccd vccd _104__12/Y sky130_fd_sc_hd__inv_2
|
||||
X_130_ _131_/CLK hold9/X _086_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_4
|
||||
Xoutput7 _116_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_16
|
||||
X_130_ _130_/CLK hold9/X _086_/A vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_094__2 _101__9/A vssd vssd vccd vccd _094__2/Y sky130_fd_sc_hd__inv_2
|
||||
X_061_ user_gpio_oeb _060_/X _106_/Q vssd vssd vccd vccd _061_/X sky130_fd_sc_hd__mux2_4
|
||||
X_113_ _100__8/Y hold9/X _082_/X _083_/Y vssd vssd vccd vccd _113_/Q _113_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xclkbuf_1_0__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _100__8/A sky130_fd_sc_hd__clkbuf_16
|
||||
X_059__14 _126_/CLK vssd vssd vccd vccd _132_/CLK sky130_fd_sc_hd__inv_2
|
||||
X_059__14 _130_/CLK vssd vssd vccd vccd _132_/CLK sky130_fd_sc_hd__inv_2
|
||||
Xoutput21 _132_/Q vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_16
|
||||
Xoutput8 _118_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_16
|
||||
Xoutput10 _113_/Q vssd vssd vccd vccd pad_gpio_dm[0] sky130_fd_sc_hd__buf_16
|
||||
X_060_ _112_/Q _063_/C vssd vssd vccd vccd _060_/X sky130_fd_sc_hd__and2_0
|
||||
X_112_ _099__7/Y hold3/X _080_/X _081_/Y vssd vssd vccd vccd _112_/Q _112_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold10 _123_/Q vssd vssd vccd vccd _124_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
X_112_ _099__7/Y hold6/X _080_/X _081_/Y vssd vssd vccd vccd _112_/Q _112_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold10 _127_/Q vssd vssd vccd vccd _128_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xoutput22 _067_/X vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__buf_16
|
||||
Xoutput11 _114_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_16
|
||||
Xoutput9 _117_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_16
|
||||
X_111_ _098__6/Y _124_/D _078_/X _079_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xoutput11 _114_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_16
|
||||
X_111_ _098__6/Y hold8/X _078_/X _079_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XFILLER_0_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_15_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold11 _126_/Q vssd vssd vccd vccd _127_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xoutput12 _115_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_16
|
||||
XANTENNA__072__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_110_ _097__5/Y hold6/X _076_/X _077_/Y vssd vssd vccd vccd _110_/Q _110_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_110_ _097__5/Y hold7/X _076_/X _077_/Y vssd vssd vccd vccd _110_/Q _110_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold12 _125_/Q vssd vssd vccd vccd _126_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA_fanout29_A _082_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__072__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_097__5 _101__9/A vssd vssd vccd vccd _097__5/Y sky130_fd_sc_hd__inv_2
|
||||
Xoutput13 _107_/Q vssd vssd vccd vccd pad_gpio_holdover sky130_fd_sc_hd__buf_16
|
||||
XANTENNA__080__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__075__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_4_60 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold13 _124_/Q vssd vssd vccd vccd _125_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA__083__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput14 _111_/Q vssd vssd vccd vccd pad_gpio_ib_mode_sel sky130_fd_sc_hd__buf_16
|
||||
|
|
@ -153,123 +148,115 @@ XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
|||
XANTENNA__078__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__091__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__086__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xoutput15 _110_/Q vssd vssd vccd vccd pad_gpio_inenb sky130_fd_sc_hd__buf_16
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__089__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xconst_source vssd vssd vccd vccd one_buffer/A zero_buffer/A sky130_fd_sc_hd__conb_1
|
||||
XFILLER_10_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_1_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XANTENNA_fanout27_A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_fanout27_A _082_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput16 _066_/Y vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__buf_16
|
||||
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_12_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xoutput17 _061_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__buf_16
|
||||
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xfanout30 input4/X vssd vssd vccd vccd fanout30/X sky130_fd_sc_hd__buf_2
|
||||
Xoutput18 _108_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_16
|
||||
Xfanout30 fanout31/X vssd vssd vccd vccd _082_/A sky130_fd_sc_hd__buf_2
|
||||
X_079_ _088_/A gpio_defaults[4] vssd vssd vccd vccd _079_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xoutput18 _108_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_16
|
||||
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_serial_load_out_buffer_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_100__8 _100__8/A vssd vssd vccd vccd _100__8/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA_input4_A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xfanout31 input4/X vssd vssd vccd vccd fanout31/X sky130_fd_sc_hd__buf_2
|
||||
Xoutput19 _109_/Q vssd vssd vccd vccd pad_gpio_vtrip_sel sky130_fd_sc_hd__buf_16
|
||||
XANTENNA__061__A0 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_103__11 _100__8/A vssd vssd vccd vccd _103__11/Y sky130_fd_sc_hd__inv_2
|
||||
X_078_ _088_/A gpio_defaults[4] vssd vssd vccd vccd _078_/X sky130_fd_sc_hd__or2_0
|
||||
XANTENNA__097__5_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_103__11 _100__8/A vssd vssd vccd vccd _103__11/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__061__A0 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__058__1_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_1_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_129_ _131_/CLK hold4/X _074_/A vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_129_ _131_/CLK hold2/X _074_/A vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_077_ _076_/A gpio_defaults[3] vssd vssd vccd vccd _077_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_093_ _092_/A gpio_defaults[7] vssd vssd vccd vccd _093_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_076_ _076_/A gpio_defaults[3] vssd vssd vccd vccd _076_/X sky130_fd_sc_hd__or2_0
|
||||
Xinput1 mgmt_gpio_oeb vssd vssd vccd vccd _063_/C sky130_fd_sc_hd__buf_2
|
||||
X_128_ _131_/CLK hold7/X _074_/A vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_128_ _131_/CLK _128_/D _074_/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_13_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xfanout23 _092_/A vssd vssd vccd vccd _088_/A sky130_fd_sc_hd__buf_2
|
||||
X_092_ _092_/A gpio_defaults[7] vssd vssd vccd vccd _092_/X sky130_fd_sc_hd__or2_0
|
||||
Xinput2 mgmt_gpio_out vssd vssd vccd vccd input2/X sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_input2_A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_075_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _075_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_127_ _131_/CLK _127_/D _092_/A vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_4
|
||||
Xinput2 mgmt_gpio_out vssd vssd vccd vccd input2/X sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_clkbuf_0_serial_load_A serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_075_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _075_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_127_ _130_/CLK _127_/D _092_/A vssd vssd vccd vccd _127_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xfanout24 fanout31/X vssd vssd vccd vccd _092_/A sky130_fd_sc_hd__buf_2
|
||||
X_095__3 _100__8/A vssd vssd vccd vccd _095__3/Y sky130_fd_sc_hd__inv_2
|
||||
Xfanout24 fanout30/X vssd vssd vccd vccd _092_/A sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__102__10_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_074_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _074_/X sky130_fd_sc_hd__or2_0
|
||||
XTAP_70 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput3 pad_gpio_in vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__buf_2
|
||||
X_074_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _074_/X sky130_fd_sc_hd__or2_0
|
||||
X_091_ _088_/A gpio_defaults[6] vssd vssd vccd vccd _091_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_126_ _126_/CLK _126_/D _088_/A vssd vssd vccd vccd _126_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
Xinput3 pad_gpio_in vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__buf_2
|
||||
X_126_ _130_/CLK _126_/D _088_/A vssd vssd vccd vccd _126_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_109_ _096__4/Y hold4/X _074_/X _075_/Y vssd vssd vccd vccd _109_/Q _109_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_109_ _096__4/Y hold2/X _074_/X _075_/Y vssd vssd vccd vccd _109_/Q _109_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xfanout25 _080_/A vssd vssd vccd vccd _076_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_71 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_60 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_090_ _092_/A gpio_defaults[6] vssd vssd vccd vccd _090_/X sky130_fd_sc_hd__or2_0
|
||||
Xinput4 resetn vssd vssd vccd vccd input4/X sky130_fd_sc_hd__buf_2
|
||||
X_090_ _092_/A gpio_defaults[6] vssd vssd vccd vccd _090_/X sky130_fd_sc_hd__or2_0
|
||||
XFILLER_5_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_073_ _074_/A gpio_defaults[8] vssd vssd vccd vccd _073_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_125_ _126_/CLK _125_/D _088_/A vssd vssd vccd vccd _125_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XFILLER_7_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_125_ _130_/CLK _125_/D _088_/A vssd vssd vccd vccd _125_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__062__B user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_108_ _095__3/Y hold7/X _072_/X _073_/Y vssd vssd vccd vccd _108_/Q _108_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA__070__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__098__6_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xfanout26 fanout30/X vssd vssd vccd vccd _080_/A sky130_fd_sc_hd__buf_2
|
||||
X_108_ _095__3/Y _128_/D _072_/X _073_/Y vssd vssd vccd vccd _108_/Q _108_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xfanout26 fanout31/X vssd vssd vccd vccd _080_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_72 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_072_ _074_/A gpio_defaults[8] vssd vssd vccd vccd _072_/X sky130_fd_sc_hd__or2_0
|
||||
XTAP_61 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput5 serial_data_in vssd vssd vccd vccd _119_/D sky130_fd_sc_hd__buf_2
|
||||
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA__073__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_124_ _126_/CLK _124_/D _092_/A vssd vssd vccd vccd _124_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__101__9_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_124_ _130_/CLK hold8/X _092_/A vssd vssd vccd vccd _124_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__068__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_107_ _094__2/Y hold8/X _070_/X _071_/Y vssd vssd vccd vccd _107_/Q _107_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xfanout27 _134_/A vssd vssd vccd vccd _074_/A sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__081__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_107_ _094__2/Y hold5/X _070_/X _071_/Y vssd vssd vccd vccd _107_/Q _107_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xfanout27 _082_/A vssd vssd vccd vccd _074_/A sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__076__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__081__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_73 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_071_ _076_/A gpio_defaults[2] vssd vssd vccd vccd _071_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XTAP_62 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_106_ _058__1/Y hold5/X _068_/X _069_/Y vssd vssd vccd vccd _106_/Q _106_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_123_ _126_/CLK hold6/X _092_/A vssd vssd vccd vccd _123_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
X_098__6 _101__9/A vssd vssd vccd vccd _098__6/Y sky130_fd_sc_hd__inv_2
|
||||
X_106_ _058__1/Y hold1/X _068_/X _069_/Y vssd vssd vccd vccd _106_/Q _106_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_123_ _131_/CLK hold7/X _092_/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_098__6 _100__8/A vssd vssd vccd vccd _098__6/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__084__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__079__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xfanout28 _134_/A vssd vssd vccd vccd _086_/A sky130_fd_sc_hd__buf_2
|
||||
Xfanout28 _082_/A vssd vssd vccd vccd _086_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_63 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_070_ _076_/A gpio_defaults[2] vssd vssd vccd vccd _070_/X sky130_fd_sc_hd__or2_0
|
||||
XANTENNA__092__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA__087__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_122_ _126_/CLK hold8/X _076_/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_4
|
||||
Xserial_clock_out_buffer _126_/CLK vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_16
|
||||
Xfanout29 fanout30/X vssd vssd vccd vccd _134_/A sky130_fd_sc_hd__buf_2
|
||||
X_122_ _130_/CLK hold5/X _076_/A vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_4
|
||||
Xspare_cell vssd vssd vccd vccd spare_cell/LO sky130_fd_sc_hd__macro_sparecell
|
||||
Xserial_clock_out_buffer _131_/CLK vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_16
|
||||
Xfanout29 _082_/A vssd vssd vccd vccd _134_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_64 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
X_121_ _126_/CLK hold3/X _080_/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_121_ _130_/CLK hold6/X _076_/A vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_4
|
||||
XTAP_65 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_120_ _126_/CLK hold5/X _076_/A vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_120_ _130_/CLK hold1/X _076_/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_102__10 _101__9/A vssd vssd vccd vccd _102__10/Y sky130_fd_sc_hd__inv_2
|
||||
X_058__1 _101__9/A vssd vssd vccd vccd _058__1/Y sky130_fd_sc_hd__inv_2
|
||||
Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA__099__7_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_66 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_32 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xclkbuf_0_serial_load serial_load vssd vssd vccd vccd clkbuf_0_serial_load/X sky130_fd_sc_hd__clkbuf_16
|
||||
Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _126_/CLK
|
||||
Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _130_/CLK
|
||||
+ sky130_fd_sc_hd__clkbuf_16
|
||||
XTAP_67 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
|
|
@ -277,24 +264,21 @@ Xgpio_logic_high _067_/A vccd1 vssd1 gpio_logic_high
|
|||
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_40 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xone_buffer one_buffer/A vssd vssd vccd vccd one sky130_fd_sc_hd__buf_16
|
||||
XFILLER_8_65 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold3 hold3/A vssd vssd vccd vccd hold3/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_5_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_101__9 _101__9/A vssd vssd vccd vccd _101__9/Y sky130_fd_sc_hd__inv_2
|
||||
XTAP_68 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_101__9 _101__9/A vssd vssd vccd vccd _101__9/Y sky130_fd_sc_hd__inv_2
|
||||
XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_fanout28_A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_fanout28_A _082_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_8_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_69 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__134__A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold5 hold5/A vssd vssd vccd vccd hold5/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_59 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
|
|
@ -307,88 +291,85 @@ X_089_ _088_/A gpio_defaults[5] vssd vssd vccd vccd _089_/Y sky130_fd_sc_hd__nan
|
|||
Xzero_buffer zero_buffer/A vssd vssd vccd vccd zero sky130_fd_sc_hd__buf_16
|
||||
XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
|
||||
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
|
||||
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_input5_A serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_105__13 _100__8/A vssd vssd vccd vccd _105__13/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA_input5_A serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_088_ _088_/A gpio_defaults[5] vssd vssd vccd vccd _088_/X sky130_fd_sc_hd__or2_0
|
||||
XFILLER_3_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold7 hold7/A vssd vssd vccd vccd hold7/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_5_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_096__4 _100__8/A vssd vssd vccd vccd _096__4/Y sky130_fd_sc_hd__inv_2
|
||||
X_096__4 _101__9/A vssd vssd vccd vccd _096__4/Y sky130_fd_sc_hd__inv_2
|
||||
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_2_49 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_17_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_087_ _086_/A gpio_defaults[12] vssd vssd vccd vccd _087_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xclkbuf_1_1__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _101__9/A sky130_fd_sc_hd__clkbuf_16
|
||||
XANTENNA__082__A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_087_ _134_/A gpio_defaults[12] vssd vssd vccd vccd _087_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XANTENNA__071__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__082__A _082_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_1_1__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _131_/CLK
|
||||
+ sky130_fd_sc_hd__clkbuf_16
|
||||
X_086_ _086_/A gpio_defaults[12] vssd vssd vccd vccd _086_/X sky130_fd_sc_hd__or2_0
|
||||
XANTENNA__074__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_069_ _080_/A gpio_defaults[0] vssd vssd vccd vccd _069_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_086_ _086_/A gpio_defaults[12] vssd vssd vccd vccd _086_/X sky130_fd_sc_hd__or2_0
|
||||
Xhold9 hold9/A vssd vssd vccd vccd hold9/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA__069__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_069_ _086_/A gpio_defaults[0] vssd vssd vccd vccd _069_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XANTENNA__082__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__077__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__132__RESET_B _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__077__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_input3_A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_085_ _086_/A gpio_defaults[11] vssd vssd vccd vccd _085_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XANTENNA__090__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__085__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_068_ _086_/A gpio_defaults[0] vssd vssd vccd vccd _068_/X sky130_fd_sc_hd__or2_0
|
||||
XFILLER_0_95 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_37 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__093__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__093__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__088__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__094__2_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_3_84 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_084_ _086_/A gpio_defaults[11] vssd vssd vccd vccd _084_/X sky130_fd_sc_hd__or2_0
|
||||
X_099__7 _101__9/A vssd vssd vccd vccd _099__7/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_0_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_084_ _086_/A gpio_defaults[11] vssd vssd vccd vccd _084_/X sky130_fd_sc_hd__or2_0
|
||||
X_067_ _067_/A _133_/A vssd vssd vccd vccd _067_/X sky130_fd_sc_hd__and2_2
|
||||
X_119_ _126_/CLK _119_/D _080_/A vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_119_ _131_/CLK _119_/D _080_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_15_71 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_083_ _074_/A gpio_defaults[10] vssd vssd vccd vccd _083_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XFILLER_3_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_066_ _064_/X _065_/Y _062_/Y vssd vssd vccd vccd _066_/Y sky130_fd_sc_hd__o21ai_4
|
||||
X_118_ _105__13/Y _127_/D _092_/X _093_/Y vssd vssd vccd vccd _118_/Q _118_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XFILLER_0_31 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_39 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_15_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_065_ input2/X _064_/B _106_/Q vssd vssd vccd vccd _065_/Y sky130_fd_sc_hd__o21ai_2
|
||||
X_082_ _134_/A gpio_defaults[10] vssd vssd vccd vccd _082_/X sky130_fd_sc_hd__or2_0
|
||||
X_082_ _082_/A gpio_defaults[10] vssd vssd vccd vccd _082_/X sky130_fd_sc_hd__or2_0
|
||||
X_134_ _134_/A vssd vssd vccd vccd _134_/X sky130_fd_sc_hd__buf_2
|
||||
Xserial_load_out_buffer _101__9/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__clkbuf_16
|
||||
XANTENNA_input1_A mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_117_ _104__12/Y _126_/D _090_/X _091_/Y vssd vssd vccd vccd _117_/Q _117_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_081_ _076_/A gpio_defaults[1] vssd vssd vccd vccd _081_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XFILLER_3_43 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_081_ _080_/A gpio_defaults[1] vssd vssd vccd vccd _081_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_064_ _113_/Q_N _064_/B vssd vssd vccd vccd _064_/X sky130_fd_sc_hd__and2b_2
|
||||
XFILLER_0_33 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_133_ _133_/A vssd vssd vccd vccd _133_/X sky130_fd_sc_hd__buf_2
|
||||
X_116_ _103__11/Y _125_/D _088_/X _089_/Y vssd vssd vccd vccd _116_/Q _116_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_clkbuf_0_serial_clock_A serial_clock vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_132_ _132_/CLK hold2/A _134_/A vssd vssd vccd vccd _132_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
X_063_ _115_/Q _114_/Q _063_/C vssd vssd vccd vccd _064_/B sky130_fd_sc_hd__and3b_2
|
||||
XFILLER_3_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_132_ _132_/CLK hold3/A _134_/A vssd vssd vccd vccd _132_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
X_080_ _080_/A gpio_defaults[1] vssd vssd vccd vccd _080_/X sky130_fd_sc_hd__or2_0
|
||||
X_115_ _102__10/Y hold2/X _086_/X _087_/Y vssd vssd vccd vccd _115_/Q _115_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_063_ _115_/Q _114_/Q _063_/C vssd vssd vccd vccd _064_/B sky130_fd_sc_hd__and3b_2
|
||||
X_115_ _102__10/Y hold3/X _086_/X _087_/Y vssd vssd vccd vccd _115_/Q _115_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xoutput6 _133_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__buf_16
|
||||
.ends
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,11 @@
|
|||
*.log
|
||||
sim_build
|
||||
sim
|
||||
__pycache__
|
||||
*.
|
||||
./wb_models/housekeepingWB/__pycache__
|
||||
*.xml
|
||||
*.yml
|
||||
*.hex*
|
||||
*.elf
|
||||
AN.DB
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
# SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
|
||||
PWDD := $(shell pwd)
|
||||
BLOCKS := $(shell basename $(PWDD))
|
||||
|
||||
# ---- Include Partitioned Makefiles ----
|
||||
CONFIG = caravel_user_project
|
||||
# TestName = temp_partial
|
||||
# export COCOTB_ANSI_OUTPUT=0 # disable color in termianl
|
||||
export GUI=1
|
||||
export COCOTB_REDUCED_LOG_FMT=1
|
||||
# Change this line if you want to use existing cocotb test modules:
|
||||
# export PYTHONPATH := $(DESIGNS)/verilog/rtl/<your design python tests>
|
||||
# export LIBPYTHON_LOC=$(cocotb-config --libpython)
|
||||
#export VERILOG_PATH = ../../../
|
||||
#export CARAVEL_PATH = ../../../../../caravel/verilog/
|
||||
# include $(MCW_ROOT)/verilog/dv/make/env.makefile
|
||||
# #export VERILOG_PATH = ../../../
|
||||
# include $(MCW_ROOT)/verilog/dv/make/var.makefile
|
||||
# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
|
||||
# include $(MCW_ROOT)/verilog/dv/make/sim.makefile
|
||||
TESTCASE=$(TestName)
|
||||
|
||||
MODULE=caravel_tests
|
||||
$(info $$MODULE is [$(MODULE)])
|
||||
cocotb:
|
||||
rm -rf sim_build/
|
||||
mkdir sim_build/
|
||||
# change project_tb.v to match your testbench
|
||||
#RTL
|
||||
iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
|
||||
-DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
|
||||
-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
|
||||
-o sim_build/sim.vvp $(CARAVEL_PATH)/rtl/__user_project_wrapper.v $(CARAVEL_PATH)/rtl/debug_regs.v caravel_top.sv
|
||||
#GL
|
||||
# iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
|
||||
# -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
|
||||
# -f$(VERILOG_PATH)/includes/includes.gl.caravel \
|
||||
# -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv
|
||||
#CVC
|
||||
|
||||
|
||||
# TESTCASE=$(TestName) MODULE=caravel_tests cvc64 +interp +acc+2 \
|
||||
# +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap\
|
||||
# +change_port_type +maxerrors 1\
|
||||
# +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY=#0 \
|
||||
# +define+TESTNAME=\"$(TestName)\" +define+RUNTAG=\"$(RUNTAG)\" +define+COCOTB_SIM=1\
|
||||
# -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
|
||||
# -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) -o sim_build/sim.vvp
|
||||
|
||||
|
||||
|
||||
# verilator --vpi --public-flat-rw --prefix Vtop \
|
||||
# -LDFLAGS "-Wl,-rpath,$(cocotb-config --prefix)/cocotb/libs \
|
||||
# -L$(cocotb-config --prefix)/cocotb/libs \
|
||||
# -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils" \
|
||||
# $(cocotb-config --share)/lib/verilator/verilator.cpp\
|
||||
# -y $(VERILOG_PATH)/includes/includes.rtl.caravel \
|
||||
# -y $(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) --cc -o sim_build/sim.vvp caravel_top.sv
|
||||
# change this line to choose the comma separated test cases and the name of your python test module
|
||||
|
||||
TESTCASE=$(TestName) MODULE=caravel_tests vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
|
||||
! grep failure results.xml
|
||||
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
Overview
|
||||
========
|
||||
Cocotb environment (CTN) is a dynamic simulation testing environment. It's purpose is to speed testing simulation time and get coverage data. The environment is developed using cocotb, an open source coroutine-based co simulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. CTN has 2 main layers: tests and whitebox models. Tests layer contain multiple tests and sequences that can communicate with the caravel (dut) through drivers shown in read at fig 1. Whitebox models layer contain multiple models that should mimic the behavior of each main block inside caravel see fig1. Model is supposed to check if the model is working as expected, if its registers contain the expected values all the time and report coverage of features provided by this block if it’s tested or not.
|
||||
|
||||
|
||||
<img src="doc/CTN.png" alt="Alt text" title="fig1. caravel testbench environment (read lines are drivers )">
|
||||
|
||||
fig1. caravel testbench environment (read lines are drivers )
|
||||
|
||||
Prerequisites
|
||||
=============================
|
||||
|
||||
- Docker: [Linux](https://hub.docker.com/search?q=&type=edition&offering=community&operating_system=linux&utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Windows](https://desktop.docker.com/win/main/amd64/Docker%20Desktop%20Installer.exe?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with Intel Chip](https://desktop.docker.com/mac/main/amd64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with M1 Chip](https://desktop.docker.com/mac/main/arm64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header)
|
||||
- Python 3.6+ with PIP
|
||||
- cocotb
|
||||
```
|
||||
apt update && apt install python3 python3-pip
|
||||
pip3 install cocotb
|
||||
pip3 install cocotb_coverage
|
||||
pip3 install coverage
|
||||
pip3 install cocotb-bus
|
||||
```
|
||||
- iverilog or vcs
|
||||
|
||||
run a test
|
||||
=============================
|
||||
|
||||
Use script verify_cocotb.py
|
||||
|
||||
```
|
||||
-h, --help show this help message and exit
|
||||
|
||||
-regression REGRESSION, -r REGRESSION
|
||||
name of regression can found in tests.json
|
||||
|
||||
-test TEST [TEST ...], -t TEST [TEST ...]
|
||||
name of test if no --sim provided RTL will be run
|
||||
<takes list as input>
|
||||
|
||||
-sim SIM [SIM ...] Simulation type to be run RTL,GL&GL_SDF provided only
|
||||
when run -test <takes list as input>
|
||||
|
||||
-testlist TESTLIST, -tl TESTLIST
|
||||
path of testlist to be run
|
||||
|
||||
-tag TAG provide tag of the run default would be regression
|
||||
name and if no regression is provided would be
|
||||
run_<random float>_<timestamp>_
|
||||
|
||||
-maxerr MAXERR max number of errors for every test before simulation
|
||||
breaks default = 3
|
||||
|
||||
-vcs, -v use vcs as compiler if not used iverilog would be used
|
||||
|
||||
-cov, -c enable code coverage
|
||||
|
||||
```
|
||||
|
||||
|
||||
Tests
|
||||
===============
|
||||
|
||||
Refer to [tests.json](tests.json) for tests list
|
||||
|
||||
Directories names fixed for now
|
||||
===============
|
||||
>repo
|
||||
>>caravel_mgmt_soc_litex/
|
||||
|
||||
>>caravel
|
||||
>>>verilog
|
||||
>>>>dv
|
||||
>>>>cocotb
|
||||
|
||||
cocotb directory tree
|
||||
===============
|
||||
```
|
||||
├── caravel.py -> contains driving and mentoring functions for caravel interface
|
||||
├── caravel_top.sv -> testbench top level
|
||||
├── cpu.py -> contains driving and mentoring functions for wishbone when disable the cpu
|
||||
├── hex_files -> folder that contains hex files
|
||||
├── verify_cocotb.py -> script that run tests and regressions
|
||||
├── sim -> directory get generate when run a test
|
||||
│ └── <tag> -> tag of the run
|
||||
│ ├── <sim type>-<test name> -> test result directory contain all logs and wave related to the test
|
||||
│ ├── command.log -> command use for this run
|
||||
│ └── runs.log -> contains status of the run fails and passes tests
|
||||
├── tests -> directory contains all the tests
|
||||
├── tests.json -> test list have all the tests, regressions and contain small description about every test
|
||||
└── wb_models -> contains checkers and models for some caravel blocks
|
||||
|
||||
```
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
import cocotb.simulator
|
||||
from cocotb.handle import SimHandleBase
|
||||
from cocotb.handle import Force
|
||||
from cocotb_coverage.coverage import *
|
||||
from cocotb.binary import BinaryValue
|
||||
import enum
|
||||
from cocotb.handle import (
|
||||
ConstantObject,
|
||||
HierarchyArrayObject,
|
||||
HierarchyObject,
|
||||
ModifiableObject,
|
||||
NonHierarchyIndexableObject,
|
||||
SimHandle,
|
||||
)
|
||||
|
||||
from itertools import groupby, product
|
||||
|
||||
import interfaces.common as common
|
||||
from common import GPIO_MODE
|
||||
from common import MASK_GPIO_CTRL
|
||||
from common import Macros
|
||||
|
||||
def gpio_mode(gpios_values:list):
|
||||
gpios=[]
|
||||
for array in gpios_values:
|
||||
gpio_value = GPIO_MODE(array[1]).name
|
||||
for gpio in array[0]:
|
||||
gpios.append((gpio,gpio_value))
|
||||
cocotb.log.info(f'[caravel][gpio_mode] gpios {gpios}')
|
||||
return gpios
|
||||
|
||||
Carvel_Coverage = coverage_section (
|
||||
|
||||
CoverPoint("top.caravel.gpio", vname="gpios mode", xf = lambda gpio ,gpio_mode: (gpio,gpio_mode) ,
|
||||
bins = list(product(range(38),[e.name for e in GPIO_MODE])))
|
||||
|
||||
)
|
||||
|
||||
class Caravel_env:
|
||||
def __init__(self,dut:SimHandleBase):
|
||||
self.dut = dut
|
||||
self.clk = dut.clock_tb
|
||||
self.caravel_hdl = dut.uut
|
||||
self.hk_hdl = dut.uut.housekeeping
|
||||
|
||||
"""start carvel by insert power then reset"""
|
||||
async def start_up(self):
|
||||
await self.power_up()
|
||||
# await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup
|
||||
await self.reset()
|
||||
await self.disable_bins()
|
||||
common.fill_macros(self.dut.macros) # get macros value
|
||||
|
||||
async def disable_bins(self):
|
||||
for i in range(38):
|
||||
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
|
||||
|
||||
"""setup the vdd and vcc power bins"""
|
||||
async def power_up(self):
|
||||
cocotb.log.info(f' [caravel] start powering up')
|
||||
self.set_vdd(0)
|
||||
self.set_vcc(0)
|
||||
await ClockCycles(self.clk, 10)
|
||||
cocotb.log.info(f' [caravel] power up -> connect vdd' )
|
||||
self.set_vdd(1)
|
||||
# await ClockCycles(self.clk, 10)
|
||||
cocotb.log.info(f' [caravel] power up -> connect vcc' )
|
||||
self.set_vcc(1)
|
||||
await ClockCycles(self.clk, 10)
|
||||
|
||||
""""reset caravel"""
|
||||
async def reset(self):
|
||||
cocotb.log.info(f' [caravel] start resetting')
|
||||
self.dut.resetb_tb.value = 0
|
||||
await ClockCycles(self.clk, 20)
|
||||
self.dut.resetb_tb.value = 1
|
||||
await ClockCycles(self.clk, 1)
|
||||
cocotb.log.info(f' [caravel] finish resetting')
|
||||
|
||||
|
||||
def set_vdd(self,value:bool):
|
||||
self.dut.vddio_tb.value = value
|
||||
self.dut.vssio_tb.value = 0
|
||||
self.dut.vddio_2_tb.value = value
|
||||
self.dut.vssio_2_tb.value = 0
|
||||
self.dut.vdda_tb.value = value
|
||||
self.dut.vssa_tb.value = 0
|
||||
self.dut.vdda1_tb.value = value
|
||||
self.dut.vssa1_tb.value = 0
|
||||
self.dut.vdda1_2_tb.value = value
|
||||
self.dut.vssa1_2_tb.value = 0
|
||||
self.dut.vdda2_tb.value = value
|
||||
self.dut.vssa2_tb.value = 0
|
||||
|
||||
def set_vcc(self , value:bool):
|
||||
self.dut.vccd_tb.value = value
|
||||
self.dut.vssd_tb.value = 0
|
||||
self.dut.vccd1_tb.value = value
|
||||
self.dut.vssd1_tb.value = 0
|
||||
self.dut.vccd2_tb.value = value
|
||||
self.dut.vssd2_tb.value = 0
|
||||
|
||||
"""drive csb signal bin E8 mprj[3]"""
|
||||
async def drive_csb(self,bit):
|
||||
self.drive_gpio_in((3,3),bit)
|
||||
self.drive_gpio_in((2,2),0)
|
||||
await ClockCycles(self.clk, 1)
|
||||
|
||||
|
||||
"""set the spi vsb signal high to disable housekeeping spi transmission bin E8 mprj[3]"""
|
||||
async def disable_csb(self ):
|
||||
cocotb.log.info(f' [caravel] disable housekeeping spi transmission')
|
||||
await self.drive_csb(1)
|
||||
|
||||
"""set the spi vsb signal high impedance """
|
||||
async def release_csb(self ):
|
||||
cocotb.log.info(f' [caravel] release housekeeping spi transmission')
|
||||
self.release_gpio(3)
|
||||
self.release_gpio(2)
|
||||
await ClockCycles(self.clk, 1)
|
||||
|
||||
"""set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]"""
|
||||
async def enable_csb(self ):
|
||||
cocotb.log.info(f' [caravel] enable housekeeping spi transmission')
|
||||
await self.drive_csb(0)
|
||||
|
||||
|
||||
"""return the value of mprj in bits used tp monitor the output gpios value"""
|
||||
def monitor_gpio(self,bits:tuple):
|
||||
mprj = self.dut.mprj_io_tb.value
|
||||
size =mprj.n_bits -1 #size of bins array
|
||||
mprj_out= self.dut.mprj_io_tb.value[size - bits[0]:size - bits[1]]
|
||||
if(mprj_out.is_resolvable):
|
||||
cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {hex(mprj_out)}')
|
||||
else:
|
||||
cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {mprj_out}')
|
||||
return mprj_out
|
||||
|
||||
"""return the value of management gpio"""
|
||||
def monitor_mgmt_gpio(self):
|
||||
data = self.dut.gpio_tb.value
|
||||
cocotb.log.debug(f' [caravel] Monitor mgmt gpio = {data}')
|
||||
return data
|
||||
|
||||
"""change the configration of the gpios by overwrite their defaults value then reset
|
||||
need to take at least 1 cycle for reset """
|
||||
### dont use back door accessing
|
||||
async def configure_gpio_defaults(self,gpios_values: list):
|
||||
gpio_defaults = self.caravel_hdl.gpio_defaults.value
|
||||
cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
|
||||
size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
|
||||
# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
|
||||
for array in gpios_values:
|
||||
gpio_value = array[1]
|
||||
for gpio in array[0]:
|
||||
self.cov_configure_gpios(gpio,gpio_value.name)
|
||||
gpio_defaults[size - (gpio*13 + 12): size -gpio*13] = gpio_value.value
|
||||
#cocotb.log.info(f' [caravel] gpio_defaults[{size - (gpio*13 + 12)}:{size -gpio*13}] = {gpio_value.value} ')
|
||||
self.caravel_hdl.gpio_defaults.value = gpio_defaults
|
||||
#reset
|
||||
self.caravel_hdl.gpio_resetn_1_shifted.value = 0
|
||||
self.caravel_hdl.gpio_resetn_2_shifted.value = 0
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.caravel_hdl.gpio_resetn_1_shifted.value = 1
|
||||
self.caravel_hdl.gpio_resetn_2_shifted.value = 1
|
||||
cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
|
||||
self.print_gpios_ctrl_val()
|
||||
|
||||
"""change the configration of the gpios by overwrite the register value
|
||||
in control registers and housekeeping regs, don't consume simulation cycles"""
|
||||
### dont use back door accessing
|
||||
def configure_gpios_regs(self,gpios_values: list):
|
||||
cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
|
||||
control_modules = self.control_blocks_paths()
|
||||
# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
|
||||
for array in gpios_values:
|
||||
gpio_value = array[1]
|
||||
for gpio in array[0]:
|
||||
self.cov_configure_gpios(gpio,gpio_value.name)
|
||||
self.gpio_control_reg_write(control_modules[gpio],gpio_value.value) # for control blocks regs
|
||||
self.caravel_hdl.housekeeping.gpio_configure[gpio].value = gpio_value.value # for house keeping regs
|
||||
cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
|
||||
self.print_gpios_ctrl_val()
|
||||
self.print_gpios_HW_val()
|
||||
|
||||
"""dummy function for coverage sampling"""
|
||||
@Carvel_Coverage
|
||||
def cov_configure_gpios(self,gpio,gpio_mode):
|
||||
cocotb.log.debug(f' [caravel] gpio [{gpio}] = {gpio_mode} ')
|
||||
pass
|
||||
|
||||
def print_gpios_default_val(self,print=1):
|
||||
gpio_defaults = self.caravel_hdl.gpio_defaults.value
|
||||
size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
|
||||
gpios = []
|
||||
for gpio in range(Macros['MPRJ_IO_PADS']):
|
||||
gpio_value = gpio_defaults[size - (gpio*13 + 12): size -gpio*13]
|
||||
gpio_enum = GPIO_MODE(gpio_value.integer)
|
||||
gpios.append((gpio,gpio_enum))
|
||||
group_bins = groupby(gpios,key=lambda x: x[1])
|
||||
for key,value in group_bins:
|
||||
gpios=[]
|
||||
for gpio in list(value):
|
||||
gpios.append(gpio[0])
|
||||
if (print):
|
||||
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
|
||||
return gpios
|
||||
|
||||
"""print the values return in the gpio of control block mode in GPIO Mode format"""
|
||||
def print_gpios_ctrl_val(self, print=1):
|
||||
control_modules = self.control_blocks_paths()
|
||||
gpios = []
|
||||
for i , gpio in enumerate(control_modules):
|
||||
gpios.append((i,self.gpio_control_reg_read(gpio)))
|
||||
group_bins = groupby(gpios,key=lambda x: x[1])
|
||||
for key,value in group_bins:
|
||||
gpios=[]
|
||||
for gpio in list(value):
|
||||
gpios.append(gpio[0])
|
||||
if (print):
|
||||
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
|
||||
return gpios
|
||||
|
||||
def _check_gpio_ctrl_eq_HW(self):
|
||||
assert self.print_gpios_ctrl_val(1) == self.print_gpios_HW_val(1), f'there is an issue while configuration the control block register value isn\'t the same as the house keeping gpio register'
|
||||
|
||||
"""print the values return in the gpio of housekeeping block mode in GPIO Mode format"""
|
||||
def print_gpios_HW_val(self,print=1):
|
||||
gpios = []
|
||||
for pin in range(Macros['MPRJ_IO_PADS']):
|
||||
gpios.append((pin,GPIO_MODE(self.caravel_hdl.housekeeping.gpio_configure[pin].value)))
|
||||
group_bins = groupby(gpios,key=lambda x: x[1])
|
||||
for key,value in group_bins:
|
||||
gpios=[]
|
||||
for gpio in list(value):
|
||||
gpios.append(gpio[0])
|
||||
if (print):
|
||||
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
|
||||
return gpios
|
||||
|
||||
|
||||
"""return the paths of the control blocks"""
|
||||
def control_blocks_paths(self)-> list:
|
||||
car = self.caravel_hdl
|
||||
control_modules =[car._id("gpio_control_bidir_1[0]",False),car._id("gpio_control_bidir_1[1]",False)]
|
||||
#add gpio_control_in_1a (GPIO 2 to 7)
|
||||
for i in range(6):
|
||||
control_modules.append(car._id(f'gpio_control_in_1a[{i}]',False))
|
||||
#add gpio_control_in_1 (GPIO 8 to 18)
|
||||
for i in range(Macros['MPRJ_IO_PADS_1']-9+1):
|
||||
control_modules.append(car._id(f'gpio_control_in_1[{i}]',False))
|
||||
#add gpio_control_in_2 (GPIO 19 to 34)
|
||||
for i in range(Macros['MPRJ_IO_PADS_2']-4+1):
|
||||
control_modules.append(car._id(f'gpio_control_in_2[{i}]',False))
|
||||
# Last three GPIOs (spi_sdo, flash_io2, and flash_io3) gpio_control_bidir_2
|
||||
for i in range(3):
|
||||
control_modules.append(car._id(f'gpio_control_bidir_2[{i}]',False))
|
||||
return control_modules
|
||||
|
||||
"""read the control register and return a GPIO Mode it takes the path to the control reg"""
|
||||
def gpio_control_reg_read(self,path:SimHandleBase) -> GPIO_MODE:
|
||||
gpio_mgmt_en = path.mgmt_ena.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value
|
||||
gpio_out_dis = path.gpio_outenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value
|
||||
gpio_holdover = path.gpio_holdover.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value
|
||||
gpio_in_dis = path.gpio_inenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value
|
||||
gpio_mode_sel = path.gpio_ib_mode_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value
|
||||
gpio_anlg_en = path.gpio_ana_en.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value
|
||||
gpio_anlg_sel = path.gpio_ana_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value
|
||||
gpio_anlg_pol = path.gpio_ana_pol.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value
|
||||
gpio_slow_sel = path.gpio_slow_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value
|
||||
gpio_vtrip_sel = path.gpio_vtrip_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value
|
||||
gpio_dgtl_mode = path.gpio_dm.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value
|
||||
control_reg = (gpio_mgmt_en | gpio_out_dis | gpio_holdover| gpio_in_dis | gpio_mode_sel | gpio_anlg_en
|
||||
|gpio_anlg_sel|gpio_anlg_pol|gpio_slow_sel|gpio_vtrip_sel|gpio_dgtl_mode)
|
||||
return(GPIO_MODE(control_reg))
|
||||
|
||||
"""read the control register and return a GPIO Mode it takes the path to the control reg"""
|
||||
def gpio_control_reg_write(self,path:SimHandleBase,data) :
|
||||
bits =common.int_to_bin_list(data,14)
|
||||
path.mgmt_ena.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value]
|
||||
path.gpio_outenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value]
|
||||
path.gpio_holdover.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value]
|
||||
path.gpio_inenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value]
|
||||
path.gpio_ib_mode_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value]
|
||||
path.gpio_ana_en.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value]
|
||||
path.gpio_ana_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value]
|
||||
path.gpio_ana_pol.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value]
|
||||
path.gpio_slow_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value]
|
||||
path.gpio_vtrip_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value]
|
||||
gpio_dm =bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value:MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value+3]
|
||||
gpio_dm =sum(d * 2**i for i, d in enumerate(gpio_dm)) # convert list to binary int
|
||||
path.gpio_dm.value = gpio_dm
|
||||
|
||||
# """drive the value of mprj bits with spicific data from input pad at the top"""
|
||||
# def release_gpio(self):
|
||||
# io = self.caravel_hdl.padframe.mprj_pads.io
|
||||
# mprj , n_bits = common.signal_valueZ_size(io)
|
||||
# io.value = mprj
|
||||
# cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
|
||||
|
||||
"""drive the value of mprj bits with spicific data from input pad at the top"""
|
||||
def drive_gpio_in(self,bits,data):
|
||||
# io = self.caravel_hdl.padframe.mprj_pads.io
|
||||
# mprj , n_bits = common.signal_value_size(io)
|
||||
# cocotb.log.debug(f' [caravel] before mprj with {mprj} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
|
||||
# mprj[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
# io.value = mprj
|
||||
# cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
|
||||
data_bits = []
|
||||
is_list = isinstance(bits, (list,tuple))
|
||||
if is_list :
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
|
||||
data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0]<bits[1]))
|
||||
for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
|
||||
self.dut._id(f"bin{bits2}",False).value = data_bits[i]
|
||||
self.dut._id(f"bin{bits2}_en",False).value = 1
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits2} with {data_bits[i]} and bin{bits2}_en with 1')
|
||||
else:
|
||||
self.dut._id(f'bin{bits}',False).value = data
|
||||
self.dut._id(f'bin{bits}_en',False).value = 1
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1')
|
||||
|
||||
""" release driving the value of mprj bits """
|
||||
def release_gpio(self,bits):
|
||||
data_bits = []
|
||||
is_list = isinstance(bits, (list,tuple))
|
||||
if is_list :
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_disable] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
|
||||
for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
|
||||
self.dut._id(f"bin{bits2}_en",False).value = 0
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits2}')
|
||||
else:
|
||||
self.dut._id(f'bin{bits}_en',False).value = 0
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits}')
|
||||
|
||||
|
||||
"""drive the value of gpio management"""
|
||||
def drive_mgmt_gpio(self,data):
|
||||
mgmt_io = self.dut.gpio_tb
|
||||
mgmt_io.value = data
|
||||
cocotb.log.info(f' [caravel] drive_mgmt_gpio through management area mprj with {data}')
|
||||
|
||||
"""update the value of mprj bits with spicific data then after certain number of cycle drive z to free the signal"""
|
||||
async def drive_gpio_in_with_cycles(self,bits,data,num_cycles):
|
||||
self.drive_gpio_in(bits,data)
|
||||
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
|
||||
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
|
||||
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
|
||||
|
||||
"""drive the value of mprj bits with spicific data from management area then after certain number of cycle drive z to free the signal"""
|
||||
async def drive_mgmt_gpio_with_cycles(self,bits,data,num_cycles):
|
||||
self.drive_mgmt_gpio(bits,data)
|
||||
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
|
||||
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
|
||||
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
|
||||
|
||||
async def wait_then_undrive(self,bits,num_cycles):
|
||||
await ClockCycles(self.clk, num_cycles)
|
||||
n_bits = bits[0]-bits[1]+1
|
||||
self.drive_gpio_in(bits, (n_bits)* 'z')
|
||||
cocotb.log.info(f' [caravel] finish wait_then_drive ')
|
||||
|
||||
async def hk_write_byte(self, data):
|
||||
self.path = self.dut.mprj_io_tb
|
||||
data_bit = BinaryValue(value = data , n_bits = 8,bigEndian=False)
|
||||
for i in range(7,-1,-1):
|
||||
await FallingEdge(self.clk)
|
||||
#common.drive_hdl(self.path,[(4,4),(2,2)],[0,int(data_bit[i])]) # 2 = SDI 4 = SCK
|
||||
self.drive_gpio_in((2,2),int(data_bit[i]))
|
||||
self.drive_gpio_in((4,4),0)
|
||||
|
||||
await RisingEdge(self.clk)
|
||||
self.drive_gpio_in((4,4),1)
|
||||
await FallingEdge(self.clk)
|
||||
|
||||
""" read byte using housekeeping spi
|
||||
when writing to SCK we can't use mprj[4] as there is a limitation in cocotb for accessing pack array #2587
|
||||
so use back door access to write the clock then read the output from the SDO mprj[1] value"""
|
||||
async def hk_read_byte(self,last_read= False):
|
||||
read_data =''
|
||||
for i in range(8,0,-1):
|
||||
self.drive_gpio_in((4,4),1)# SCK
|
||||
await FallingEdge(self.clk)
|
||||
self.drive_gpio_in((4,4),0)# SCK
|
||||
await RisingEdge(self.clk)
|
||||
read_data= f'{read_data}{self.dut.mprj_io_tb.value[37-1]}'
|
||||
await FallingEdge(self.clk)
|
||||
self.drive_gpio_in((4,4),0) # SCK
|
||||
# if (last_read):
|
||||
# common.drive_hdl(self.dut.bin4_en,(0,0),'z') #4 = SCK
|
||||
# common.drive_hdl(self.path,[(1,1)],'z')
|
||||
|
||||
return int(read_data,2)
|
||||
|
||||
"""write to the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
|
||||
async def hk_write_backdoor(self,addr, data):
|
||||
await RisingEdge(self.dut.wb_clk_i)
|
||||
self.hk_hdl.wb_stb_i.value = 1
|
||||
self.hk_hdl.wb_cyc_i.value = 1
|
||||
self.hk_hdl.wb_sel_i.value = 0xF
|
||||
self.hk_hdl.wb_we_i.value = 1
|
||||
self.hk_hdl.wb_adr_i.value = addr
|
||||
self.hk_hdl.wb_dat_i.value = data
|
||||
cocotb.log.info(f'Monitor: Start Writing to {hex(addr)} -> {data}')
|
||||
await FallingEdge(self.dut.wb_ack_o) # wait for acknowledge
|
||||
self.hk_hdl.wb_stb_i.value = 0
|
||||
self.hk_hdl.wb_cyc_i.value = 0
|
||||
cocotb.log.info(f'Monitor: End writing {hex(addr)} -> {data}')
|
||||
|
||||
|
||||
"""read from the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
|
||||
async def hk_read_backdoor(self,addr):
|
||||
await RisingEdge(self.clk)
|
||||
self.hk_hdl.wb_stb_i.value = 1
|
||||
self.hk_hdl.wb_cyc_i.value = 1
|
||||
self.hk_hdl.wb_sel_i.value = 0
|
||||
self.hk_hdl.wb_we_i.value = 0
|
||||
self.hk_hdl.wb_adr_i.value = addr
|
||||
cocotb.log.info(f' [housekeeping] Monitor: Start reading from {hex(addr)}')
|
||||
await FallingEdge(self.hk_hdl.wb_ack_o)
|
||||
self.hk_hdl.wb_stb_i.value = 0
|
||||
self.hk_hdl.wb_cyc_i.value = 0
|
||||
cocotb.log.info(f' [housekeeping] Monitor: read from {hex(addr)} value {(self.hk_hdl.wb_dat_o.value)}')
|
||||
return self.hk_hdl.wb_dat_o.value
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
from cgitb import handler
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
import cocotb.simulator
|
||||
from cocotb_coverage.coverage import *
|
||||
from cocotb.binary import BinaryValue
|
||||
import interfaces.caravel
|
||||
from interfaces.logic_analyzer import LA
|
||||
from interfaces.caravel import GPIO_MODE, Caravel_env
|
||||
from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox
|
||||
import interfaces.common as common
|
||||
import logging
|
||||
from interfaces.cpu import RiskV
|
||||
from cocotb.log import SimTimeContextFilter
|
||||
from cocotb.log import SimLogFormatter
|
||||
from interfaces.defsParser import Regs
|
||||
from tests.common_functions.Timeout import Timeout
|
||||
from cocotb.result import TestSuccess
|
||||
import inspect
|
||||
import os
|
||||
# tests
|
||||
from tests.bitbang.bitbang_tests import *
|
||||
from tests.bitbang.bitbang_tests_cpu import *
|
||||
from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import *
|
||||
from tests.housekeeping.housekeeping_spi.user_pass_thru import *
|
||||
from tests.housekeeping.general.pll import *
|
||||
from tests.housekeeping.general.sys_ctrl import *
|
||||
from tests.temp_partial_test.partial import *
|
||||
from tests.hello_world.helloWorld import *
|
||||
from tests.cpu.cpu_stress import *
|
||||
from tests.mem.mem_stress import *
|
||||
from tests.irq.IRQ_external import *
|
||||
from tests.irq.IRQ_timer import *
|
||||
from tests.irq.IRQ_uart import *
|
||||
from tests.gpio.gpio import *
|
||||
from tests.gpio.gpio_user import *
|
||||
from tests.mgmt_gpio.mgmt_gpio import *
|
||||
from tests.timer.timer import *
|
||||
from tests.uart.uart import *
|
||||
from tests.spi_master.spi_master import *
|
||||
from tests.logicAnalyzer.la import *
|
||||
|
||||
|
||||
|
||||
# archive tests
|
||||
@cocotb.test()
|
||||
async def cpu_drive(dut):
|
||||
TestName = inspect.stack()[0][3]
|
||||
if not os.path.exists(f'sim/{TestName}'):
|
||||
os.mkdir(f'sim/{TestName}') # create test folder
|
||||
cocotb.log.setLevel(logging.INFO)
|
||||
handler = logging.FileHandler(f"sim/{TestName}/{TestName}.log",mode='w')
|
||||
handler.addFilter(SimTimeContextFilter())
|
||||
handler.setFormatter(SimLogFormatter())
|
||||
cocotb.log.addHandler(handler)
|
||||
caravelEnv = caravel.Caravel_env(dut)
|
||||
Timeout(caravelEnv.clk,1000000,0.1)
|
||||
la = LA(dut)
|
||||
clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
|
||||
cocotb.start_soon(clock.start()) # Start the clock
|
||||
|
||||
await caravelEnv.start_up()
|
||||
hk = HK_whiteBox(dut)
|
||||
|
||||
reg = Regs()
|
||||
time_out_count =0
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
address = reg.get_addr('reg_wb_enable')
|
||||
await cpu.drive_data2address(address,1)
|
||||
address = reg.get_addr('reg_debug_2')
|
||||
await cpu.drive_data2address(address,0xdFF0)
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
cpu.cpu_release_reset()
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
||||
raise TestSuccess(f" TEST {TestName} passed")
|
||||
|
||||
while True:
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
if (cpu.read_debug_reg1() == 0xFFF0):
|
||||
break
|
||||
cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xFFF0")
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
address = reg.get_addr('reg_debug_2')
|
||||
await cpu.drive_data2address(address,0xdFF0)
|
||||
await ClockCycles(caravelEnv.clk, 50)
|
||||
# address = reg.get_addr('reg_mprj_io_0')
|
||||
# await cpu.drive_data2address(address,0x0c03)
|
||||
cocotb.log.info(f"[TEST][cpu_drive] wait debug reg1 = 0xddd0")
|
||||
while True:
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
if (cpu.read_debug_reg1() == 0xddd0):
|
||||
break
|
||||
cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xddd0")
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
||||
caravelEnv.print_gpios_HW_val()
|
||||
coverage_db.export_to_yaml(filename="coverage.yalm")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
async def spi_drive(dut):
|
||||
cocotb.log.setLevel(logging.INFO)
|
||||
handler = logging.FileHandler(f"test.log",mode='w')
|
||||
handler.addFilter(SimTimeContextFilter())
|
||||
handler.setFormatter(SimLogFormatter())
|
||||
cocotb.log.addHandler(handler)
|
||||
caravelEnv = caravel.Caravel_env(dut)
|
||||
|
||||
|
||||
la = LA(dut)
|
||||
clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk
|
||||
cocotb.start_soon(clock.start()) # Start the clock
|
||||
await caravelEnv.start_up()
|
||||
hk = HK_whiteBox(dut,True)
|
||||
|
||||
caravelEnv.enable_csb()
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
# caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]])
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
await caravelEnv.hk_write_byte(0x40) # read command
|
||||
# await caravelEnv.hk_write_byte(0x80) # command write
|
||||
await caravelEnv.hk_write_byte(0x0) # address
|
||||
# await caravelEnv.hk_write_byte(0x03) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
print(read_data)
|
||||
read_data = await caravelEnv.hk_read_byte(True) # read value
|
||||
caravelEnv.disable_csb()
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
caravelEnv.enable_csb()
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
# caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]])
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
await caravelEnv.hk_write_byte(0x40) # read command
|
||||
# await caravelEnv.hk_write_byte(0x80) # command write
|
||||
await caravelEnv.hk_write_byte(0x8) # address
|
||||
# await caravelEnv.hk_write_byte(0x03) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
# await caravelEnv.hk_write_byte(0xaa) # data
|
||||
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
read_data = await caravelEnv.hk_read_byte() # read value
|
||||
|
||||
# caravelEnv.drive_gpio_in([5,5],1)
|
||||
await ClockCycles(caravelEnv.clk,40)
|
||||
coverage_db.export_to_yaml(filename="coverage.yml")
|
||||
coverage_db.export_to_xml(filename="coverage.xml")
|
||||
return
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,358 @@
|
|||
`ifdef VCS
|
||||
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
|
||||
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
|
||||
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
|
||||
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
|
||||
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
|
||||
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
|
||||
`endif
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
module caravel_top ;
|
||||
|
||||
// parameter FILENAME = {"hex_files/",`TESTNAME,".hex"};
|
||||
parameter FILENAME={"hex_files/",`TESTNAME,".hex"};
|
||||
initial begin
|
||||
`ifdef VCS
|
||||
`ifdef ENABLE_SDF
|
||||
$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME , `SDF_POSTFIX, ".vpd"});
|
||||
`else
|
||||
$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME ,".vpd"});
|
||||
`endif
|
||||
$vcdpluson();
|
||||
`else
|
||||
$dumpfile ({"sim/",`TAG,"/",`SIM,"-",`TESTNAME,"/",`SIM,"-",`TESTNAME,".vcd"});
|
||||
$dumpvars (0, caravel_top);
|
||||
`endif
|
||||
end
|
||||
|
||||
wire vddio_tb; // Common 3.3V padframe/ESD power
|
||||
wire vddio_2_tb; // Common 3.3V padframe/ESD power
|
||||
wire vssio_tb; // Common padframe/ESD ground
|
||||
wire vssio_2_tb; // Common padframe/ESD ground
|
||||
wire vdda_tb; // Management 3.3V power
|
||||
wire vssa_tb; // Common analog ground
|
||||
wire vccd_tb; // Management/Common 1.8V power
|
||||
wire vssd_tb; // Common digital ground
|
||||
wire vdda1_tb; // User area 1 3.3V power
|
||||
wire vdda1_2_tb; // User area 1 3.3V power
|
||||
wire vdda2_tb; // User area 2 3.3V power
|
||||
wire vssa1_tb; // User area 1 analog ground
|
||||
wire vssa1_2_tb; // User area 1 analog ground
|
||||
wire vssa2_tb; // User area 2 analog ground
|
||||
wire vccd1_tb; // User area 1 1.8V power
|
||||
wire vccd2_tb; // User area 2 1.8V power
|
||||
wire vssd1_tb; // User area 1 digital ground
|
||||
wire vssd2_tb; // User area 2 digital ground
|
||||
|
||||
wire gpio_tb; // Used for external LDO control
|
||||
wire [38-1:0] mprj_io_tb;
|
||||
reg clock_tb; // CMOS core clock input; not a crystal
|
||||
wire resetb_tb; // Reset input (sense inverted)
|
||||
|
||||
// Note that only two flash data pins are dedicated to the
|
||||
// management SoC wrapper. The management SoC exports the
|
||||
// quad SPI mode status to make use of the top two mprj_io
|
||||
// pins for io2 and io3.
|
||||
|
||||
wire flash_csb_tb;
|
||||
wire flash_clk_tb;
|
||||
wire flash_io0_tb;
|
||||
wire flash_io1_tb;
|
||||
|
||||
|
||||
|
||||
caravel uut (
|
||||
.vddio (vddio_tb),
|
||||
.vddio_2 (vddio_2_tb),
|
||||
.vssio (vssio_tb),
|
||||
.vssio_2 (vssio_2_tb),
|
||||
.vdda (vdda_tb),
|
||||
.vssa (vssa_tb),
|
||||
.vccd (vccd_tb),
|
||||
.vssd (vssd_tb),
|
||||
.vdda1 (vdda1_tb),
|
||||
.vdda1_2 (vdda1_2_tb),
|
||||
.vdda2 (vdda2_tb),
|
||||
.vssa1 (vssa1_tb),
|
||||
.vssa1_2 (vssa1_2_tb),
|
||||
.vssa2 (vssa2_tb),
|
||||
.vccd1 (vccd1_tb),
|
||||
.vccd2 (vccd2_tb),
|
||||
.vssd1 (vssd1_tb),
|
||||
.vssd2 (vssd2_tb),
|
||||
.clock (clock_tb),
|
||||
.gpio (gpio_tb),
|
||||
.mprj_io (mprj_io_tb),
|
||||
.flash_csb(flash_csb_tb),
|
||||
.flash_clk(flash_clk_tb),
|
||||
.flash_io0(flash_io0_tb),
|
||||
.flash_io1(flash_io1_tb),
|
||||
.resetb (resetb_tb)
|
||||
);
|
||||
|
||||
spiflash #(
|
||||
FILENAME
|
||||
) spiflash (
|
||||
.csb(flash_csb_tb),
|
||||
.clk(flash_clk_tb),
|
||||
.io0(flash_io0_tb),
|
||||
.io1(flash_io1_tb),
|
||||
.io2(), // not used
|
||||
.io3() // not used
|
||||
);
|
||||
|
||||
mac macros();
|
||||
|
||||
|
||||
// make speical variables for the mprj input to assign the input without writing to the output gpios
|
||||
// cocotb limitation #2587: iverilog deal with array as 1 object not multiple of objects so can't write to only 1 element
|
||||
wire bin0;
|
||||
wire bin0_en;
|
||||
wire bin1;
|
||||
wire bin1_en;
|
||||
wire bin2;
|
||||
wire bin2_en;
|
||||
wire bin3;
|
||||
wire bin3_en;
|
||||
wire bin4;
|
||||
wire bin4_en;
|
||||
wire bin5;
|
||||
wire bin5_en;
|
||||
wire bin6;
|
||||
wire bin6_en;
|
||||
wire bin7;
|
||||
wire bin7_en;
|
||||
wire bin8;
|
||||
wire bin8_en;
|
||||
wire bin9;
|
||||
wire bin9_en;
|
||||
wire bin10;
|
||||
wire bin10_en;
|
||||
wire bin11;
|
||||
wire bin11_en;
|
||||
wire bin12;
|
||||
wire bin12_en;
|
||||
wire bin13;
|
||||
wire bin13_en;
|
||||
wire bin14;
|
||||
wire bin14_en;
|
||||
wire bin15;
|
||||
wire bin15_en;
|
||||
wire bin16;
|
||||
wire bin16_en;
|
||||
wire bin17;
|
||||
wire bin17_en;
|
||||
wire bin18;
|
||||
wire bin18_en;
|
||||
wire bin19;
|
||||
wire bin19_en;
|
||||
wire bin20;
|
||||
wire bin20_en;
|
||||
wire bin21;
|
||||
wire bin21_en;
|
||||
wire bin22;
|
||||
wire bin22_en;
|
||||
wire bin23;
|
||||
wire bin23_en;
|
||||
wire bin24;
|
||||
wire bin24_en;
|
||||
wire bin25;
|
||||
wire bin25_en;
|
||||
wire bin26;
|
||||
wire bin26_en;
|
||||
wire bin27;
|
||||
wire bin27_en;
|
||||
wire bin28;
|
||||
wire bin28_en;
|
||||
wire bin29;
|
||||
wire bin29_en;
|
||||
wire bin30;
|
||||
wire bin30_en;
|
||||
wire bin31;
|
||||
wire bin31_en;
|
||||
wire bin32;
|
||||
wire bin32_en;
|
||||
wire bin33;
|
||||
wire bin33_en;
|
||||
wire bin34;
|
||||
wire bin34_en;
|
||||
wire bin35;
|
||||
wire bin35_en;
|
||||
wire bin36;
|
||||
wire bin36_en;
|
||||
wire bin37;
|
||||
wire bin37_en;
|
||||
|
||||
|
||||
assign mprj_io_tb[0] = (bin0_en) ? bin0 : 1'bz;
|
||||
assign mprj_io_tb[1] = (bin1_en) ? bin1 : 1'bz;
|
||||
assign mprj_io_tb[2] = (bin2_en) ? bin2 : 1'bz;
|
||||
assign mprj_io_tb[3] = (bin3_en) ? bin3 : 1'bz;
|
||||
assign mprj_io_tb[4] = (bin4_en) ? bin4 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[5] = (bin5_en) ? bin5 : 1'bz;
|
||||
assign mprj_io_tb[6] = (bin6_en) ? bin6 : 1'bz;
|
||||
assign mprj_io_tb[7] = (bin7_en) ? bin7 : 1'bz;
|
||||
assign mprj_io_tb[8] = (bin8_en) ? bin8 : 1'bz;
|
||||
assign mprj_io_tb[9] = (bin9_en) ? bin9 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[10] = (bin10_en) ? bin10 : 1'bz;
|
||||
assign mprj_io_tb[11] = (bin11_en) ? bin11 : 1'bz;
|
||||
assign mprj_io_tb[12] = (bin12_en) ? bin12 : 1'bz;
|
||||
assign mprj_io_tb[13] = (bin13_en) ? bin13 : 1'bz;
|
||||
assign mprj_io_tb[14] = (bin14_en) ? bin14 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[15] = (bin15_en) ? bin15 : 1'bz;
|
||||
assign mprj_io_tb[16] = (bin16_en) ? bin16 : 1'bz;
|
||||
assign mprj_io_tb[17] = (bin17_en) ? bin17 : 1'bz;
|
||||
assign mprj_io_tb[18] = (bin18_en) ? bin18 : 1'bz;
|
||||
assign mprj_io_tb[19] = (bin19_en) ? bin19 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[20] = (bin20_en) ? bin20 : 1'bz;
|
||||
assign mprj_io_tb[21] = (bin21_en) ? bin21 : 1'bz;
|
||||
assign mprj_io_tb[22] = (bin22_en) ? bin22 : 1'bz;
|
||||
assign mprj_io_tb[23] = (bin23_en) ? bin23 : 1'bz;
|
||||
assign mprj_io_tb[24] = (bin24_en) ? bin24 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[25] = (bin25_en) ? bin25 : 1'bz;
|
||||
assign mprj_io_tb[26] = (bin26_en) ? bin26 : 1'bz;
|
||||
assign mprj_io_tb[27] = (bin27_en) ? bin27 : 1'bz;
|
||||
assign mprj_io_tb[28] = (bin28_en) ? bin28 : 1'bz;
|
||||
assign mprj_io_tb[29] = (bin29_en) ? bin29 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[30] = (bin30_en) ? bin30 : 1'bz;
|
||||
assign mprj_io_tb[31] = (bin31_en) ? bin31 : 1'bz;
|
||||
assign mprj_io_tb[32] = (bin32_en) ? bin32 : 1'bz;
|
||||
assign mprj_io_tb[33] = (bin33_en) ? bin33 : 1'bz;
|
||||
assign mprj_io_tb[34] = (bin34_en) ? bin34 : 1'bz;
|
||||
|
||||
assign mprj_io_tb[35] = (bin35_en) ? bin35 : 1'bz;
|
||||
assign mprj_io_tb[36] = (bin36_en) ? bin36 : 1'bz;
|
||||
assign mprj_io_tb[37] = (bin37_en) ? bin37 : 1'bz;
|
||||
|
||||
|
||||
|
||||
// to read from mprj array with iverilog
|
||||
wire bin0_monitor;
|
||||
wire bin1_monitor;
|
||||
wire bin2_monitor;
|
||||
wire bin3_monitor;
|
||||
wire bin4_monitor;
|
||||
wire bin5_monitor;
|
||||
wire bin6_monitor;
|
||||
wire bin7_monitor;
|
||||
wire bin8_monitor;
|
||||
wire bin9_monitor;
|
||||
wire bin10_monitor;
|
||||
wire bin11_monitor;
|
||||
wire bin12_monitor;
|
||||
wire bin13_monitor;
|
||||
wire bin14_monitor;
|
||||
wire bin15_monitor;
|
||||
wire bin16_monitor;
|
||||
wire bin17_monitor;
|
||||
wire bin18_monitor;
|
||||
wire bin19_monitor;
|
||||
wire bin20_monitor;
|
||||
wire bin21_monitor;
|
||||
wire bin22_monitor;
|
||||
wire bin23_monitor;
|
||||
wire bin24_monitor;
|
||||
wire bin25_monitor;
|
||||
wire bin26_monitor;
|
||||
wire bin27_monitor;
|
||||
wire bin28_monitor;
|
||||
wire bin29_monitor;
|
||||
wire bin30_monitor;
|
||||
wire bin31_monitor;
|
||||
wire bin32_monitor;
|
||||
wire bin33_monitor;
|
||||
wire bin34_monitor;
|
||||
wire bin35_monitor;
|
||||
wire bin36_monitor;
|
||||
wire bin37_monitor;
|
||||
|
||||
assign bin0_monitor = mprj_io_tb[0];
|
||||
assign bin1_monitor = mprj_io_tb[1];
|
||||
assign bin2_monitor = mprj_io_tb[2];
|
||||
assign bin3_monitor = mprj_io_tb[3];
|
||||
assign bin4_monitor = mprj_io_tb[4];
|
||||
assign bin5_monitor = mprj_io_tb[5];
|
||||
assign bin6_monitor = mprj_io_tb[6];
|
||||
assign bin7_monitor = mprj_io_tb[7];
|
||||
assign bin8_monitor = mprj_io_tb[8];
|
||||
assign bin9_monitor = mprj_io_tb[9];
|
||||
assign bin10_monitor = mprj_io_tb[10];
|
||||
assign bin11_monitor = mprj_io_tb[11];
|
||||
assign bin12_monitor = mprj_io_tb[12];
|
||||
assign bin13_monitor = mprj_io_tb[13];
|
||||
assign bin14_monitor = mprj_io_tb[14];
|
||||
assign bin15_monitor = mprj_io_tb[15];
|
||||
assign bin16_monitor = mprj_io_tb[16];
|
||||
assign bin17_monitor = mprj_io_tb[17];
|
||||
assign bin18_monitor = mprj_io_tb[18];
|
||||
assign bin19_monitor = mprj_io_tb[19];
|
||||
assign bin20_monitor = mprj_io_tb[20];
|
||||
assign bin21_monitor = mprj_io_tb[21];
|
||||
assign bin22_monitor = mprj_io_tb[22];
|
||||
assign bin23_monitor = mprj_io_tb[23];
|
||||
assign bin24_monitor = mprj_io_tb[24];
|
||||
assign bin25_monitor = mprj_io_tb[25];
|
||||
assign bin26_monitor = mprj_io_tb[26];
|
||||
assign bin27_monitor = mprj_io_tb[27];
|
||||
assign bin28_monitor = mprj_io_tb[28];
|
||||
assign bin29_monitor = mprj_io_tb[29];
|
||||
assign bin30_monitor = mprj_io_tb[30];
|
||||
assign bin31_monitor = mprj_io_tb[31];
|
||||
assign bin32_monitor = mprj_io_tb[32];
|
||||
assign bin33_monitor = mprj_io_tb[33];
|
||||
assign bin34_monitor = mprj_io_tb[34];
|
||||
assign bin35_monitor = mprj_io_tb[35];
|
||||
assign bin36_monitor = mprj_io_tb[36];
|
||||
assign bin37_monitor = mprj_io_tb[37];
|
||||
|
||||
endmodule
|
||||
|
||||
// module that has all needed macros by cocotb
|
||||
module mac;
|
||||
|
||||
reg [7:0] MPRJ_IO_PADS_1 = `ifdef MPRJ_IO_PADS_1 `MPRJ_IO_PADS_1 `else 0 `endif; /* number of user GPIO pads on user1 side */
|
||||
reg [7:0] MPRJ_IO_PADS_2 = `ifdef MPRJ_IO_PADS_2 `MPRJ_IO_PADS_2 `else 0 `endif; /* number of user GPIO pads on user2 side */
|
||||
reg [7:0] MPRJ_IO_PADS = `ifdef MPRJ_IO_PADS `MPRJ_IO_PADS `else 0 `endif;
|
||||
reg [7:0] MPRJ_PWR_PADS_1 =`ifdef MPRJ_PWR_PADS_1 `MPRJ_PWR_PADS_1 `else 0 `endif; /* vdda1, vccd1 enable/disable control */
|
||||
reg [7:0] MPRJ_PWR_PADS_2 = `ifdef MPRJ_PWR_PADS_2 `MPRJ_PWR_PADS_2 `else 0 `endif; /* vdda2, vccd2 enable/disable control */
|
||||
reg [7:0] MPRJ_PWR_PADS =`ifdef MPRJ_PWR_PADS `MPRJ_PWR_PADS `else 0 `endif;
|
||||
// Analog pads are only used by the "caravan" module and associated
|
||||
// modules such as user_analog_project_wrapper and chip_io_alt.
|
||||
reg [7:0] ANALOG_PADS_1 = `ifdef ANALOG_PADS_1 `ANALOG_PADS_1 `else 0 `endif;
|
||||
reg [7:0] ANALOG_PADS_2 = `ifdef ANALOG_PADS_2 `ANALOG_PADS_2 `else 0 `endif;
|
||||
reg [7:0] ANALOG_PADS = `ifdef ANALOG_PADS `ANALOG_PADS `else 0 `endif;
|
||||
|
||||
// Type and size of soc_mem
|
||||
reg USE_CUSTOM_DFFRAM = `ifdef USE_CUSTOM_DFFRAM 1 `else 0 `endif;
|
||||
// don't change the following without double checking addr widths
|
||||
reg [7:0] MEM_WORDS = `ifdef MEM_WORDS `MEM_WORDS `else 0 `endif;
|
||||
// Number of columns in the custom memory; takes one of three values:
|
||||
// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
|
||||
reg [7:0] DFFRAM_WSIZE = `ifdef DFFRAM_WSIZE `DFFRAM_WSIZE `else 0 `endif;
|
||||
reg [7:0] DFFRAM_USE_LATCH = `ifdef DFFRAM_USE_LATCH `DFFRAM_USE_LATCH `else 0 `endif;
|
||||
|
||||
// not really parameterized but just to easily keep track of the number
|
||||
// of ram_block across different modules
|
||||
reg [7:0] RAM_BLOCKS = `ifdef RAM_BLOCKS `RAM_BLOCKS `else 0 `endif;
|
||||
|
||||
// Clock divisor default value
|
||||
reg [7:0] CLK_DIV = `ifdef CLK_DIV `CLK_DIV `else 0 `endif;
|
||||
|
||||
// GPIO control default mode and enable for most I/Os
|
||||
// Most I/Os set to be user bidirectional pins on power-up.
|
||||
reg [7:0] MGMT_INIT = `ifdef MGMT_INIT `MGMT_INIT `else 0 `endif;
|
||||
reg [7:0] OENB_INIT = `ifdef OENB_INIT `OENB_INIT `else 0 `endif;
|
||||
reg [7:0] DM_INIT = `ifdef DM_INIT `DM_INIT `else 0 `endif;
|
||||
|
||||
// GL
|
||||
|
||||
reg GL = `ifdef GL 1 `else 0 `endif;
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
from operator import add
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
import cocotb.simulator
|
||||
from cocotb.handle import SimHandleBase
|
||||
from cocotb.handle import Force
|
||||
from cocotb_coverage.coverage import *
|
||||
from cocotb.binary import BinaryValue
|
||||
import enum
|
||||
from cocotb.handle import (
|
||||
ConstantObject,
|
||||
HierarchyArrayObject,
|
||||
HierarchyObject,
|
||||
ModifiableObject,
|
||||
NonHierarchyIndexableObject,
|
||||
SimHandle,
|
||||
)
|
||||
|
||||
from itertools import groupby, product
|
||||
|
||||
import interfaces.common as common
|
||||
from common import GPIO_MODE
|
||||
from common import MASK_GPIO_CTRL
|
||||
from common import Macros
|
||||
|
||||
class RiskV:
|
||||
def __init__(self,dut:SimHandleBase):
|
||||
self.dut = dut
|
||||
self.clk = dut.clock_tb
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl = dut.uut.soc.core.VexRiscv
|
||||
else:
|
||||
self.cpu_hdl = dut.uut.soc.core
|
||||
self.debug_hdl = dut.uut.mprj.debug
|
||||
self.force_reset = 0
|
||||
cocotb.scheduler.add(self.force_reset_fun())
|
||||
|
||||
|
||||
""" """
|
||||
async def drive_data_with_address(self,address,data,SEL=0xF):
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = 1
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = 0
|
||||
self.cpu_hdl.dBusWishbone_STB.value = 1
|
||||
self.cpu_hdl.dBusWishbone_WE.value = 1
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = SEL
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
|
||||
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.dBusWishbone_STB.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.dBusWishbone_WE.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = BinaryValue(value = 'zzzz')
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_ADR)[0]
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_DAT_MOSI)[0]
|
||||
|
||||
""" """
|
||||
async def drive_data2address(self,address,data,SEL=0xF):
|
||||
cocotb.log.info(f"[RiskV][drive_data2address] start driving address {hex(address)} with {hex(data)}")
|
||||
# print(dir(self.cpu_hdl))
|
||||
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
|
||||
if not Macros['GL']:
|
||||
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
|
||||
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
|
||||
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
|
||||
else:
|
||||
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
|
||||
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
|
||||
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
|
||||
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
|
||||
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = 1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = 0
|
||||
self.cpu_hdl.dBusWishbone_STB.value = 1
|
||||
self.cpu_hdl.dBusWishbone_WE.value = 1
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = SEL
|
||||
else:
|
||||
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
|
||||
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
|
||||
self.cpu_hdl.net848.value = (SEL >>2 ) &1
|
||||
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
|
||||
else:
|
||||
address_temp = address >> 2
|
||||
for i in range(30):
|
||||
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
|
||||
else:
|
||||
for i in range(32):
|
||||
self.cpu_hdl._id(f'dBusWishbone_DAT_MOSI[{i}]',False).value = (data >> i) & 1
|
||||
|
||||
if not Macros['GL']:
|
||||
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
|
||||
else:
|
||||
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
|
||||
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
|
||||
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
|
||||
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
cocotb.log.info(f"[RiskV][drive_data2address] finish driving address {hex(address)} with {hex(data)}")
|
||||
|
||||
""" """
|
||||
async def read_address(self,address,SEL=0xF):
|
||||
cocotb.log.info(f"[RiskV][read_address] start reading address {hex(address)}")
|
||||
# print(dir(self.cpu_hdl))
|
||||
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
|
||||
if not Macros['GL']:
|
||||
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
|
||||
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
|
||||
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
|
||||
else:
|
||||
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
|
||||
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
|
||||
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
|
||||
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
|
||||
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = 1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = 0
|
||||
self.cpu_hdl.dBusWishbone_STB.value = 1
|
||||
self.cpu_hdl.dBusWishbone_WE.value = 0
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = SEL
|
||||
else:
|
||||
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
|
||||
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
|
||||
self.cpu_hdl.net848.value = (SEL >>2 ) &1
|
||||
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
|
||||
else:
|
||||
address_temp = address >> 2
|
||||
for i in range(30):
|
||||
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
|
||||
|
||||
|
||||
if not Macros['GL']:
|
||||
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
|
||||
else:
|
||||
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
|
||||
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
|
||||
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
|
||||
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
|
||||
data = self.cpu_hdl.dBusWishbone_DAT_MISO.value
|
||||
await ClockCycles(self.clk, 1)
|
||||
cocotb.log.info(f"[RiskV][read_address] finish reading address {hex(address)} data = {data}")
|
||||
|
||||
# return data
|
||||
return int(str(bin(data.integer)[2:]).zfill(32),2)
|
||||
# return int(str(bin(data.integer)[2:]).zfill(32)[::-1],2)
|
||||
|
||||
|
||||
def read_debug_reg1(self):
|
||||
return self.debug_hdl.debug_reg_1.value.integer
|
||||
def read_debug_reg2(self):
|
||||
return self.debug_hdl.debug_reg_2.value.integer
|
||||
|
||||
# writing debug registers using backdoor because in GL cpu can't be disabled for now because of different netlist names
|
||||
def write_debug_reg1_backdoor(self,data):
|
||||
self.debug_hdl.debug_reg_1.value = data
|
||||
def write_debug_reg2_backdoor(self,data):
|
||||
self.debug_hdl.debug_reg_2.value = data
|
||||
|
||||
async def force_reset_fun(self):
|
||||
first_time_force = True
|
||||
first_time_release = True
|
||||
while True:
|
||||
if self.force_reset:
|
||||
if first_time_force:
|
||||
cocotb.log.info(f"[RiskV][force_reset_fun] Force CPU reset")
|
||||
first_time_force = False
|
||||
first_time_release = True
|
||||
self.cpu_hdl.reset.value =1
|
||||
if not Macros['GL']:
|
||||
common.drive_hdl(self.cpu_hdl.reset,(0,0),1)
|
||||
else:
|
||||
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),1)
|
||||
else:
|
||||
if first_time_release:
|
||||
first_time_force = True
|
||||
first_time_release = False
|
||||
|
||||
if not Macros['GL']:
|
||||
common.drive_hdl(self.cpu_hdl.reset,(0,0),0)
|
||||
else:
|
||||
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),0)
|
||||
cocotb.log.info(f"[RiskV][force_reset_fun] release CPU reset")
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
def cpu_force_reset(self):
|
||||
self.force_reset = True
|
||||
|
||||
def cpu_release_reset(self):
|
||||
self.force_reset = False
|
||||
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 45 KiB |
|
|
@ -0,0 +1 @@
|
|||
|
||||
|
|
@ -0,0 +1,432 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
import cocotb.simulator
|
||||
from cocotb.handle import SimHandleBase
|
||||
from cocotb.handle import Force
|
||||
from cocotb_coverage.coverage import *
|
||||
from cocotb.binary import BinaryValue
|
||||
import enum
|
||||
from cocotb.handle import (
|
||||
ConstantObject,
|
||||
HierarchyArrayObject,
|
||||
HierarchyObject,
|
||||
ModifiableObject,
|
||||
NonHierarchyIndexableObject,
|
||||
SimHandle,
|
||||
)
|
||||
|
||||
from itertools import groupby, product
|
||||
|
||||
import interfaces.common as common
|
||||
from interfaces.common import GPIO_MODE
|
||||
from interfaces.common import MASK_GPIO_CTRL
|
||||
from interfaces.common import Macros
|
||||
|
||||
def gpio_mode(gpios_values:list):
|
||||
gpios=[]
|
||||
for array in gpios_values:
|
||||
gpio_value = GPIO_MODE(array[1]).name
|
||||
for gpio in array[0]:
|
||||
gpios.append((gpio,gpio_value))
|
||||
cocotb.log.info(f'[caravel][gpio_mode] gpios {gpios}')
|
||||
return gpios
|
||||
|
||||
Carvel_Coverage = coverage_section (
|
||||
|
||||
CoverPoint("top.caravel.gpio", vname="gpios mode", xf = lambda gpio ,gpio_mode: (gpio,gpio_mode) ,
|
||||
bins = list(product(range(38),[e.name for e in GPIO_MODE])))
|
||||
|
||||
)
|
||||
|
||||
class Caravel_env:
|
||||
def __init__(self,dut:SimHandleBase):
|
||||
self.dut = dut
|
||||
self.clk = dut.clock_tb
|
||||
self.caravel_hdl = dut.uut
|
||||
self.hk_hdl = dut.uut.housekeeping
|
||||
|
||||
"""start carvel by insert power then reset"""
|
||||
async def start_up(self):
|
||||
await self.power_up()
|
||||
# await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup
|
||||
await self.reset()
|
||||
await self.disable_bins()
|
||||
common.fill_macros(self.dut.macros) # get macros value
|
||||
|
||||
async def disable_bins(self):
|
||||
for i in range(38):
|
||||
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
|
||||
|
||||
"""setup the vdd and vcc power bins"""
|
||||
async def power_up(self):
|
||||
cocotb.log.info(f' [caravel] start powering up')
|
||||
self.set_vdd(0)
|
||||
self.set_vcc(0)
|
||||
await ClockCycles(self.clk, 10)
|
||||
cocotb.log.info(f' [caravel] power up -> connect vdd' )
|
||||
self.set_vdd(1)
|
||||
# await ClockCycles(self.clk, 10)
|
||||
cocotb.log.info(f' [caravel] power up -> connect vcc' )
|
||||
self.set_vcc(1)
|
||||
await ClockCycles(self.clk, 10)
|
||||
|
||||
""""reset caravel"""
|
||||
async def reset(self):
|
||||
cocotb.log.info(f' [caravel] start resetting')
|
||||
self.dut.resetb_tb.value = 0
|
||||
await ClockCycles(self.clk, 20)
|
||||
self.dut.resetb_tb.value = 1
|
||||
await ClockCycles(self.clk, 1)
|
||||
cocotb.log.info(f' [caravel] finish resetting')
|
||||
|
||||
|
||||
def set_vdd(self,value:bool):
|
||||
self.dut.vddio_tb.value = value
|
||||
self.dut.vssio_tb.value = 0
|
||||
self.dut.vddio_2_tb.value = value
|
||||
self.dut.vssio_2_tb.value = 0
|
||||
self.dut.vdda_tb.value = value
|
||||
self.dut.vssa_tb.value = 0
|
||||
self.dut.vdda1_tb.value = value
|
||||
self.dut.vssa1_tb.value = 0
|
||||
self.dut.vdda1_2_tb.value = value
|
||||
self.dut.vssa1_2_tb.value = 0
|
||||
self.dut.vdda2_tb.value = value
|
||||
self.dut.vssa2_tb.value = 0
|
||||
|
||||
def set_vcc(self , value:bool):
|
||||
self.dut.vccd_tb.value = value
|
||||
self.dut.vssd_tb.value = 0
|
||||
self.dut.vccd1_tb.value = value
|
||||
self.dut.vssd1_tb.value = 0
|
||||
self.dut.vccd2_tb.value = value
|
||||
self.dut.vssd2_tb.value = 0
|
||||
|
||||
"""drive csb signal bin E8 mprj[3]"""
|
||||
async def drive_csb(self,bit):
|
||||
self.drive_gpio_in((3,3),bit)
|
||||
self.drive_gpio_in((2,2),0)
|
||||
await ClockCycles(self.clk, 1)
|
||||
|
||||
|
||||
"""set the spi vsb signal high to disable housekeeping spi transmission bin E8 mprj[3]"""
|
||||
async def disable_csb(self ):
|
||||
cocotb.log.info(f' [caravel] disable housekeeping spi transmission')
|
||||
await self.drive_csb(1)
|
||||
|
||||
"""set the spi vsb signal high impedance """
|
||||
async def release_csb(self ):
|
||||
cocotb.log.info(f' [caravel] release housekeeping spi transmission')
|
||||
self.release_gpio(3)
|
||||
self.release_gpio(2)
|
||||
await ClockCycles(self.clk, 1)
|
||||
|
||||
"""set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]"""
|
||||
async def enable_csb(self ):
|
||||
cocotb.log.info(f' [caravel] enable housekeeping spi transmission')
|
||||
await self.drive_csb(0)
|
||||
|
||||
|
||||
"""return the value of mprj in bits used tp monitor the output gpios value"""
|
||||
def monitor_gpio(self,bits:tuple):
|
||||
mprj = self.dut.mprj_io_tb.value
|
||||
size =mprj.n_bits -1 #size of bins array
|
||||
mprj_out= self.dut.mprj_io_tb.value[size - bits[0]:size - bits[1]]
|
||||
if(mprj_out.is_resolvable):
|
||||
cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {hex(mprj_out)}')
|
||||
else:
|
||||
cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {mprj_out}')
|
||||
return mprj_out
|
||||
|
||||
"""return the value of management gpio"""
|
||||
def monitor_mgmt_gpio(self):
|
||||
data = self.dut.gpio_tb.value
|
||||
cocotb.log.debug(f' [caravel] Monitor mgmt gpio = {data}')
|
||||
return data
|
||||
|
||||
"""change the configration of the gpios by overwrite their defaults value then reset
|
||||
need to take at least 1 cycle for reset """
|
||||
### dont use back door accessing
|
||||
async def configure_gpio_defaults(self,gpios_values: list):
|
||||
gpio_defaults = self.caravel_hdl.gpio_defaults.value
|
||||
cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
|
||||
size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
|
||||
# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
|
||||
for array in gpios_values:
|
||||
gpio_value = array[1]
|
||||
for gpio in array[0]:
|
||||
self.cov_configure_gpios(gpio,gpio_value.name)
|
||||
gpio_defaults[size - (gpio*13 + 12): size -gpio*13] = gpio_value.value
|
||||
#cocotb.log.info(f' [caravel] gpio_defaults[{size - (gpio*13 + 12)}:{size -gpio*13}] = {gpio_value.value} ')
|
||||
self.caravel_hdl.gpio_defaults.value = gpio_defaults
|
||||
#reset
|
||||
self.caravel_hdl.gpio_resetn_1_shifted.value = 0
|
||||
self.caravel_hdl.gpio_resetn_2_shifted.value = 0
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.caravel_hdl.gpio_resetn_1_shifted.value = 1
|
||||
self.caravel_hdl.gpio_resetn_2_shifted.value = 1
|
||||
cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
|
||||
self.print_gpios_ctrl_val()
|
||||
|
||||
"""change the configration of the gpios by overwrite the register value
|
||||
in control registers and housekeeping regs, don't consume simulation cycles"""
|
||||
### dont use back door accessing
|
||||
def configure_gpios_regs(self,gpios_values: list):
|
||||
cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
|
||||
control_modules = self.control_blocks_paths()
|
||||
# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
|
||||
for array in gpios_values:
|
||||
gpio_value = array[1]
|
||||
for gpio in array[0]:
|
||||
self.cov_configure_gpios(gpio,gpio_value.name)
|
||||
self.gpio_control_reg_write(control_modules[gpio],gpio_value.value) # for control blocks regs
|
||||
self.caravel_hdl.housekeeping.gpio_configure[gpio].value = gpio_value.value # for house keeping regs
|
||||
cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
|
||||
self.print_gpios_ctrl_val()
|
||||
self.print_gpios_HW_val()
|
||||
|
||||
"""dummy function for coverage sampling"""
|
||||
@Carvel_Coverage
|
||||
def cov_configure_gpios(self,gpio,gpio_mode):
|
||||
cocotb.log.debug(f' [caravel] gpio [{gpio}] = {gpio_mode} ')
|
||||
pass
|
||||
|
||||
def print_gpios_default_val(self,print=1):
|
||||
gpio_defaults = self.caravel_hdl.gpio_defaults.value
|
||||
size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
|
||||
gpios = []
|
||||
for gpio in range(Macros['MPRJ_IO_PADS']):
|
||||
gpio_value = gpio_defaults[size - (gpio*13 + 12): size -gpio*13]
|
||||
gpio_enum = GPIO_MODE(gpio_value.integer)
|
||||
gpios.append((gpio,gpio_enum))
|
||||
group_bins = groupby(gpios,key=lambda x: x[1])
|
||||
for key,value in group_bins:
|
||||
gpios=[]
|
||||
for gpio in list(value):
|
||||
gpios.append(gpio[0])
|
||||
if (print):
|
||||
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
|
||||
return gpios
|
||||
|
||||
"""print the values return in the gpio of control block mode in GPIO Mode format"""
|
||||
def print_gpios_ctrl_val(self, print=1):
|
||||
control_modules = self.control_blocks_paths()
|
||||
gpios = []
|
||||
for i , gpio in enumerate(control_modules):
|
||||
gpios.append((i,self.gpio_control_reg_read(gpio)))
|
||||
group_bins = groupby(gpios,key=lambda x: x[1])
|
||||
for key,value in group_bins:
|
||||
gpios=[]
|
||||
for gpio in list(value):
|
||||
gpios.append(gpio[0])
|
||||
if (print):
|
||||
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
|
||||
return gpios
|
||||
|
||||
def _check_gpio_ctrl_eq_HW(self):
|
||||
assert self.print_gpios_ctrl_val(1) == self.print_gpios_HW_val(1), f'there is an issue while configuration the control block register value isn\'t the same as the house keeping gpio register'
|
||||
|
||||
"""print the values return in the gpio of housekeeping block mode in GPIO Mode format"""
|
||||
def print_gpios_HW_val(self,print=1):
|
||||
gpios = []
|
||||
for pin in range(Macros['MPRJ_IO_PADS']):
|
||||
gpios.append((pin,GPIO_MODE(self.caravel_hdl.housekeeping.gpio_configure[pin].value)))
|
||||
group_bins = groupby(gpios,key=lambda x: x[1])
|
||||
for key,value in group_bins:
|
||||
gpios=[]
|
||||
for gpio in list(value):
|
||||
gpios.append(gpio[0])
|
||||
if (print):
|
||||
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
|
||||
return gpios
|
||||
|
||||
|
||||
"""return the paths of the control blocks"""
|
||||
def control_blocks_paths(self)-> list:
|
||||
car = self.caravel_hdl
|
||||
control_modules =[car._id("gpio_control_bidir_1[0]",False),car._id("gpio_control_bidir_1[1]",False)]
|
||||
#add gpio_control_in_1a (GPIO 2 to 7)
|
||||
for i in range(6):
|
||||
control_modules.append(car._id(f'gpio_control_in_1a[{i}]',False))
|
||||
#add gpio_control_in_1 (GPIO 8 to 18)
|
||||
for i in range(Macros['MPRJ_IO_PADS_1']-9+1):
|
||||
control_modules.append(car._id(f'gpio_control_in_1[{i}]',False))
|
||||
#add gpio_control_in_2 (GPIO 19 to 34)
|
||||
for i in range(Macros['MPRJ_IO_PADS_2']-4+1):
|
||||
control_modules.append(car._id(f'gpio_control_in_2[{i}]',False))
|
||||
# Last three GPIOs (spi_sdo, flash_io2, and flash_io3) gpio_control_bidir_2
|
||||
for i in range(3):
|
||||
control_modules.append(car._id(f'gpio_control_bidir_2[{i}]',False))
|
||||
return control_modules
|
||||
|
||||
"""read the control register and return a GPIO Mode it takes the path to the control reg"""
|
||||
def gpio_control_reg_read(self,path:SimHandleBase) -> GPIO_MODE:
|
||||
gpio_mgmt_en = path.mgmt_ena.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value
|
||||
gpio_out_dis = path.gpio_outenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value
|
||||
gpio_holdover = path.gpio_holdover.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value
|
||||
gpio_in_dis = path.gpio_inenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value
|
||||
gpio_mode_sel = path.gpio_ib_mode_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value
|
||||
gpio_anlg_en = path.gpio_ana_en.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value
|
||||
gpio_anlg_sel = path.gpio_ana_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value
|
||||
gpio_anlg_pol = path.gpio_ana_pol.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value
|
||||
gpio_slow_sel = path.gpio_slow_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value
|
||||
gpio_vtrip_sel = path.gpio_vtrip_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value
|
||||
gpio_dgtl_mode = path.gpio_dm.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value
|
||||
control_reg = (gpio_mgmt_en | gpio_out_dis | gpio_holdover| gpio_in_dis | gpio_mode_sel | gpio_anlg_en
|
||||
|gpio_anlg_sel|gpio_anlg_pol|gpio_slow_sel|gpio_vtrip_sel|gpio_dgtl_mode)
|
||||
return(GPIO_MODE(control_reg))
|
||||
|
||||
"""read the control register and return a GPIO Mode it takes the path to the control reg"""
|
||||
def gpio_control_reg_write(self,path:SimHandleBase,data) :
|
||||
bits =common.int_to_bin_list(data,14)
|
||||
path.mgmt_ena.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value]
|
||||
path.gpio_outenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value]
|
||||
path.gpio_holdover.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value]
|
||||
path.gpio_inenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value]
|
||||
path.gpio_ib_mode_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value]
|
||||
path.gpio_ana_en.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value]
|
||||
path.gpio_ana_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value]
|
||||
path.gpio_ana_pol.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value]
|
||||
path.gpio_slow_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value]
|
||||
path.gpio_vtrip_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value]
|
||||
gpio_dm =bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value:MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value+3]
|
||||
gpio_dm =sum(d * 2**i for i, d in enumerate(gpio_dm)) # convert list to binary int
|
||||
path.gpio_dm.value = gpio_dm
|
||||
|
||||
# """drive the value of mprj bits with spicific data from input pad at the top"""
|
||||
# def release_gpio(self):
|
||||
# io = self.caravel_hdl.padframe.mprj_pads.io
|
||||
# mprj , n_bits = common.signal_valueZ_size(io)
|
||||
# io.value = mprj
|
||||
# cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
|
||||
|
||||
"""drive the value of mprj bits with spicific data from input pad at the top"""
|
||||
def drive_gpio_in(self,bits,data):
|
||||
# io = self.caravel_hdl.padframe.mprj_pads.io
|
||||
# mprj , n_bits = common.signal_value_size(io)
|
||||
# cocotb.log.debug(f' [caravel] before mprj with {mprj} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
|
||||
# mprj[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
# io.value = mprj
|
||||
# cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
|
||||
data_bits = []
|
||||
is_list = isinstance(bits, (list,tuple))
|
||||
if is_list :
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
|
||||
data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0]<bits[1]))
|
||||
for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
|
||||
self.dut._id(f"bin{bits2}",False).value = data_bits[i]
|
||||
self.dut._id(f"bin{bits2}_en",False).value = 1
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits2} with {data_bits[i]} and bin{bits2}_en with 1')
|
||||
else:
|
||||
self.dut._id(f'bin{bits}',False).value = data
|
||||
self.dut._id(f'bin{bits}_en',False).value = 1
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1')
|
||||
|
||||
""" release driving the value of mprj bits """
|
||||
def release_gpio(self,bits):
|
||||
data_bits = []
|
||||
is_list = isinstance(bits, (list,tuple))
|
||||
if is_list :
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_disable] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
|
||||
for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
|
||||
self.dut._id(f"bin{bits2}_en",False).value = 0
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits2}')
|
||||
else:
|
||||
self.dut._id(f'bin{bits}_en',False).value = 0
|
||||
cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits}')
|
||||
|
||||
|
||||
"""drive the value of gpio management"""
|
||||
def drive_mgmt_gpio(self,data):
|
||||
mgmt_io = self.dut.gpio_tb
|
||||
mgmt_io.value = data
|
||||
cocotb.log.info(f' [caravel] drive_mgmt_gpio through management area mprj with {data}')
|
||||
|
||||
"""update the value of mprj bits with spicific data then after certain number of cycle drive z to free the signal"""
|
||||
async def drive_gpio_in_with_cycles(self,bits,data,num_cycles):
|
||||
self.drive_gpio_in(bits,data)
|
||||
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
|
||||
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
|
||||
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
|
||||
|
||||
"""drive the value of mprj bits with spicific data from management area then after certain number of cycle drive z to free the signal"""
|
||||
async def drive_mgmt_gpio_with_cycles(self,bits,data,num_cycles):
|
||||
self.drive_mgmt_gpio(bits,data)
|
||||
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
|
||||
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
|
||||
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
|
||||
|
||||
async def wait_then_undrive(self,bits,num_cycles):
|
||||
await ClockCycles(self.clk, num_cycles)
|
||||
n_bits = bits[0]-bits[1]+1
|
||||
self.drive_gpio_in(bits, (n_bits)* 'z')
|
||||
cocotb.log.info(f' [caravel] finish wait_then_drive ')
|
||||
|
||||
async def hk_write_byte(self, data):
|
||||
self.path = self.dut.mprj_io_tb
|
||||
data_bit = BinaryValue(value = data , n_bits = 8,bigEndian=False)
|
||||
for i in range(7,-1,-1):
|
||||
await FallingEdge(self.clk)
|
||||
#common.drive_hdl(self.path,[(4,4),(2,2)],[0,int(data_bit[i])]) # 2 = SDI 4 = SCK
|
||||
self.drive_gpio_in((2,2),int(data_bit[i]))
|
||||
self.drive_gpio_in((4,4),0)
|
||||
|
||||
await RisingEdge(self.clk)
|
||||
self.drive_gpio_in((4,4),1)
|
||||
await FallingEdge(self.clk)
|
||||
|
||||
""" read byte using housekeeping spi
|
||||
when writing to SCK we can't use mprj[4] as there is a limitation in cocotb for accessing pack array #2587
|
||||
so use back door access to write the clock then read the output from the SDO mprj[1] value"""
|
||||
async def hk_read_byte(self,last_read= False):
|
||||
read_data =''
|
||||
for i in range(8,0,-1):
|
||||
self.drive_gpio_in((4,4),1)# SCK
|
||||
await FallingEdge(self.clk)
|
||||
self.drive_gpio_in((4,4),0)# SCK
|
||||
await RisingEdge(self.clk)
|
||||
read_data= f'{read_data}{self.dut.mprj_io_tb.value[37-1]}'
|
||||
await FallingEdge(self.clk)
|
||||
self.drive_gpio_in((4,4),0) # SCK
|
||||
# if (last_read):
|
||||
# common.drive_hdl(self.dut.bin4_en,(0,0),'z') #4 = SCK
|
||||
# common.drive_hdl(self.path,[(1,1)],'z')
|
||||
|
||||
return int(read_data,2)
|
||||
|
||||
"""write to the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
|
||||
async def hk_write_backdoor(self,addr, data):
|
||||
await RisingEdge(self.dut.wb_clk_i)
|
||||
self.hk_hdl.wb_stb_i.value = 1
|
||||
self.hk_hdl.wb_cyc_i.value = 1
|
||||
self.hk_hdl.wb_sel_i.value = 0xF
|
||||
self.hk_hdl.wb_we_i.value = 1
|
||||
self.hk_hdl.wb_adr_i.value = addr
|
||||
self.hk_hdl.wb_dat_i.value = data
|
||||
cocotb.log.info(f'Monitor: Start Writing to {hex(addr)} -> {data}')
|
||||
await FallingEdge(self.dut.wb_ack_o) # wait for acknowledge
|
||||
self.hk_hdl.wb_stb_i.value = 0
|
||||
self.hk_hdl.wb_cyc_i.value = 0
|
||||
cocotb.log.info(f'Monitor: End writing {hex(addr)} -> {data}')
|
||||
|
||||
|
||||
"""read from the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
|
||||
async def hk_read_backdoor(self,addr):
|
||||
await RisingEdge(self.clk)
|
||||
self.hk_hdl.wb_stb_i.value = 1
|
||||
self.hk_hdl.wb_cyc_i.value = 1
|
||||
self.hk_hdl.wb_sel_i.value = 0
|
||||
self.hk_hdl.wb_we_i.value = 0
|
||||
self.hk_hdl.wb_adr_i.value = addr
|
||||
cocotb.log.info(f' [housekeeping] Monitor: Start reading from {hex(addr)}')
|
||||
await FallingEdge(self.hk_hdl.wb_ack_o)
|
||||
self.hk_hdl.wb_stb_i.value = 0
|
||||
self.hk_hdl.wb_cyc_i.value = 0
|
||||
cocotb.log.info(f' [housekeeping] Monitor: read from {hex(addr)} value {(self.hk_hdl.wb_dat_o.value)}')
|
||||
return self.hk_hdl.wb_dat_o.value
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
from cocotb.handle import SimHandleBase
|
||||
from cocotb.binary import BinaryValue
|
||||
from enum import Enum
|
||||
import cocotb
|
||||
"""return the value and the size of the signal"""
|
||||
def signal_value_size(path:SimHandleBase):
|
||||
value = path.value
|
||||
size = value.n_bits
|
||||
return value, size
|
||||
|
||||
|
||||
"""
|
||||
Create a binaryValue object with all Z that helps when drive to drive only the bits needed
|
||||
return value with all z and the size
|
||||
"""
|
||||
def signal_valueZ_size(path:SimHandleBase):
|
||||
value = path.value
|
||||
size = value.n_bits
|
||||
value = BinaryValue(value = int(size) * 'z',n_bits=size)
|
||||
return value, size
|
||||
|
||||
def int_to_bin_list(number:bin,number_of_bits)-> list:
|
||||
data = bin(number)
|
||||
data = data[2:].zfill(number_of_bits)[::-1]
|
||||
bits = [int(bit) for bit in data]
|
||||
return bits
|
||||
|
||||
def drive_hdl(path,bits,data):
|
||||
hdl , n_bits = signal_value_size(path)
|
||||
is_list_of_lists = all(isinstance(x, list) for x in bits)
|
||||
is_list_of_tuples = all(isinstance(x, tuple) for x in bits)
|
||||
if is_list_of_lists | is_list_of_tuples:
|
||||
for i,bits2 in enumerate(bits):
|
||||
hdl[n_bits-1-bits2[0]:n_bits-1-bits2[1]] = data[i]
|
||||
else:
|
||||
hdl[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
path.value = hdl
|
||||
cocotb.log.debug(f' [common] drive { path._path } with {hdl}')
|
||||
|
||||
"""Enum for GPIO modes valus used to configured the pins"""
|
||||
class GPIO_MODE(Enum):
|
||||
GPIO_MODE_MGMT_STD_INPUT_NOPULL = 0x0403
|
||||
GPIO_MODE_MGMT_STD_INPUT_PULLDOWN = 0x0803
|
||||
GPIO_MODE_MGMT_STD_INPUT_PULLUP = 0x0c03
|
||||
GPIO_MODE_MGMT_STD_OUTPUT = 0x1809
|
||||
GPIO_MODE_MGMT_STD_INPUT = 0x1803 # TODO: ask if this legal the default value for first 2 bin is like that
|
||||
GPIO_MODE_MGMT_STD_BIDIRECTIONAL = 0x1801
|
||||
GPIO_MODE_MGMT_STD_ANALOG = 0x000b
|
||||
GPIO_MODE_USER_STD_INPUT_NOPULL = 0x0402
|
||||
GPIO_MODE_USER_STD_INPUT_PULLDOWN = 0x0802
|
||||
GPIO_MODE_USER_STD_INPUT_PULLUP = 0x0c02
|
||||
GPIO_MODE_USER_STD_OUTPUT = 0x1808
|
||||
GPIO_MODE_USER_STD_BIDIRECTIONAL = 0x1800
|
||||
GPIO_MODE_USER_STD_OUT_MONITORED = 0x1802
|
||||
GPIO_MODE_USER_STD_ANALOG = 0x000a
|
||||
|
||||
class MASK_GPIO_CTRL(Enum):
|
||||
MASK_GPIO_CTRL_MGMT_EN = 0
|
||||
MASK_GPIO_CTRL_OUT_DIS = 1
|
||||
MASK_GPIO_CTRL_OVERRIDE = 2
|
||||
MASK_GPIO_CTRL_INP_DIS = 3
|
||||
MASK_GPIO_CTRL_MOD_SEL = 4
|
||||
MASK_GPIO_CTRL_ANLG_EN = 5
|
||||
MASK_GPIO_CTRL_ANLG_SEL = 6
|
||||
MASK_GPIO_CTRL_ANLG_POL = 7
|
||||
MASK_GPIO_CTRL_SLOW = 8
|
||||
MASK_GPIO_CTRL_TRIP = 9
|
||||
MASK_GPIO_CTRL_DGTL_MODE = 10
|
||||
|
||||
Macros= {}
|
||||
|
||||
def fill_macros(macros_hdl):
|
||||
Macros['MPRJ_IO_PADS_1'] = macros_hdl.MPRJ_IO_PADS_1.value.integer
|
||||
Macros['MPRJ_IO_PADS_2'] = macros_hdl.MPRJ_IO_PADS_2.value.integer
|
||||
Macros['MPRJ_IO_PADS'] = macros_hdl.MPRJ_IO_PADS.value.integer
|
||||
Macros['GL'] = macros_hdl.GL.value.integer
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,232 @@
|
|||
from operator import add
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
import cocotb.simulator
|
||||
from cocotb.handle import SimHandleBase
|
||||
from cocotb.handle import Force
|
||||
from cocotb_coverage.coverage import *
|
||||
from cocotb.binary import BinaryValue
|
||||
import enum
|
||||
from cocotb.handle import (
|
||||
ConstantObject,
|
||||
HierarchyArrayObject,
|
||||
HierarchyObject,
|
||||
ModifiableObject,
|
||||
NonHierarchyIndexableObject,
|
||||
SimHandle,
|
||||
)
|
||||
|
||||
from itertools import groupby, product
|
||||
|
||||
import interfaces.common as common
|
||||
from interfaces.common import GPIO_MODE
|
||||
from interfaces.common import MASK_GPIO_CTRL
|
||||
from interfaces.common import Macros
|
||||
|
||||
class RiskV:
|
||||
def __init__(self,dut:SimHandleBase):
|
||||
self.dut = dut
|
||||
self.clk = dut.clock_tb
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl = dut.uut.soc.core.VexRiscv
|
||||
else:
|
||||
self.cpu_hdl = dut.uut.soc.core
|
||||
self.debug_hdl = dut.uut.mprj.debug
|
||||
self.force_reset = 0
|
||||
cocotb.scheduler.add(self.force_reset_fun())
|
||||
|
||||
|
||||
""" """
|
||||
async def drive_data_with_address(self,address,data,SEL=0xF):
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = 1
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = 0
|
||||
self.cpu_hdl.dBusWishbone_STB.value = 1
|
||||
self.cpu_hdl.dBusWishbone_WE.value = 1
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = SEL
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
|
||||
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.dBusWishbone_STB.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.dBusWishbone_WE.value = BinaryValue(value = 'z')
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = BinaryValue(value = 'zzzz')
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_ADR)[0]
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_DAT_MOSI)[0]
|
||||
|
||||
""" """
|
||||
async def drive_data2address(self,address,data,SEL=0xF):
|
||||
cocotb.log.info(f"[RiskV][drive_data2address] start driving address {hex(address)} with {hex(data)}")
|
||||
# print(dir(self.cpu_hdl))
|
||||
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
|
||||
if not Macros['GL']:
|
||||
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
|
||||
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
|
||||
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
|
||||
else:
|
||||
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
|
||||
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
|
||||
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
|
||||
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
|
||||
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = 1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = 0
|
||||
self.cpu_hdl.dBusWishbone_STB.value = 1
|
||||
self.cpu_hdl.dBusWishbone_WE.value = 1
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = SEL
|
||||
else:
|
||||
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
|
||||
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
|
||||
self.cpu_hdl.net848.value = (SEL >>2 ) &1
|
||||
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
|
||||
else:
|
||||
address_temp = address >> 2
|
||||
for i in range(30):
|
||||
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
|
||||
else:
|
||||
for i in range(32):
|
||||
self.cpu_hdl._id(f'dBusWishbone_DAT_MOSI[{i}]',False).value = (data >> i) & 1
|
||||
|
||||
if not Macros['GL']:
|
||||
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
|
||||
else:
|
||||
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
|
||||
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
|
||||
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
|
||||
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
cocotb.log.info(f"[RiskV][drive_data2address] finish driving address {hex(address)} with {hex(data)}")
|
||||
|
||||
""" """
|
||||
async def read_address(self,address,SEL=0xF):
|
||||
cocotb.log.info(f"[RiskV][read_address] start reading address {hex(address)}")
|
||||
# print(dir(self.cpu_hdl))
|
||||
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
|
||||
if not Macros['GL']:
|
||||
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
|
||||
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
|
||||
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
|
||||
else:
|
||||
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
|
||||
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
|
||||
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
|
||||
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
|
||||
if not Macros['GL']:
|
||||
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
|
||||
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = 1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = 0
|
||||
self.cpu_hdl.dBusWishbone_STB.value = 1
|
||||
self.cpu_hdl.dBusWishbone_WE.value = 0
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = SEL
|
||||
else:
|
||||
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
|
||||
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
|
||||
self.cpu_hdl.net848.value = (SEL >>2 ) &1
|
||||
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
|
||||
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
|
||||
else:
|
||||
address_temp = address >> 2
|
||||
for i in range(30):
|
||||
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
|
||||
|
||||
|
||||
if not Macros['GL']:
|
||||
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
|
||||
else:
|
||||
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
|
||||
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
|
||||
if not Macros['GL']:
|
||||
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
|
||||
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
|
||||
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
|
||||
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
|
||||
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
|
||||
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
|
||||
data = self.cpu_hdl.dBusWishbone_DAT_MISO.value
|
||||
await ClockCycles(self.clk, 1)
|
||||
cocotb.log.info(f"[RiskV][read_address] finish reading address {hex(address)} data = {data}")
|
||||
|
||||
# return data
|
||||
return int(str(bin(data.integer)[2:]).zfill(32),2)
|
||||
# return int(str(bin(data.integer)[2:]).zfill(32)[::-1],2)
|
||||
|
||||
|
||||
def read_debug_reg1(self):
|
||||
return self.debug_hdl.debug_reg_1.value.integer
|
||||
def read_debug_reg2(self):
|
||||
return self.debug_hdl.debug_reg_2.value.integer
|
||||
|
||||
# writing debug registers using backdoor because in GL cpu can't be disabled for now because of different netlist names
|
||||
def write_debug_reg1_backdoor(self,data):
|
||||
self.debug_hdl.debug_reg_1.value = data
|
||||
def write_debug_reg2_backdoor(self,data):
|
||||
self.debug_hdl.debug_reg_2.value = data
|
||||
|
||||
async def force_reset_fun(self):
|
||||
first_time_force = True
|
||||
first_time_release = True
|
||||
while True:
|
||||
if self.force_reset:
|
||||
if first_time_force:
|
||||
cocotb.log.info(f"[RiskV][force_reset_fun] Force CPU reset")
|
||||
first_time_force = False
|
||||
first_time_release = True
|
||||
self.cpu_hdl.reset.value =1
|
||||
if not Macros['GL']:
|
||||
common.drive_hdl(self.cpu_hdl.reset,(0,0),1)
|
||||
else:
|
||||
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),1)
|
||||
else:
|
||||
if first_time_release:
|
||||
first_time_force = True
|
||||
first_time_release = False
|
||||
|
||||
if not Macros['GL']:
|
||||
common.drive_hdl(self.cpu_hdl.reset,(0,0),0)
|
||||
else:
|
||||
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),0)
|
||||
cocotb.log.info(f"[RiskV][force_reset_fun] release CPU reset")
|
||||
|
||||
await ClockCycles(self.clk, 1)
|
||||
def cpu_force_reset(self):
|
||||
self.force_reset = True
|
||||
|
||||
def cpu_release_reset(self):
|
||||
self.force_reset = False
|
||||
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
import re
|
||||
import sys
|
||||
from tokenize import group
|
||||
from unittest.util import _MIN_COMMON_LEN
|
||||
import string
|
||||
import cocotb
|
||||
import os
|
||||
class Regs:
|
||||
def __init__(self):
|
||||
pass
|
||||
|
||||
def get_addr(self,reg):
|
||||
search1 = self.get_add_defs(reg)
|
||||
# if all(c in string.hexdigits for c in search1[2:]):
|
||||
return int(search1,16)
|
||||
# return hex(self.get_hexa(search1))
|
||||
|
||||
|
||||
"""get address from defs.h"""
|
||||
def get_add_defs(self,reg):
|
||||
pattern = re.compile(rf'#define {reg}\s*\(\*\(volatile uint32_t\*\)\s*(.*)\s*\)')
|
||||
with open(f'{os.getenv("FIRMWARE_PATH")}/defs.h') as f:
|
||||
for line in f:
|
||||
m= re.search(pattern,line)
|
||||
if m:
|
||||
break
|
||||
if m:
|
||||
if not all(c in string.hexdigits for c in m.group(1)):
|
||||
return hex(self.get_hexa(m.group(1)))
|
||||
else:
|
||||
return m.group(1)
|
||||
else:
|
||||
cocotb.log.info(f" [defsParser] can't find {reg} inside defs")
|
||||
sys.exit()
|
||||
|
||||
"""get address from defs.h"""
|
||||
def get_add_csr(self,reg):
|
||||
pattern1 = re.compile(rf'#define {reg}\s*\(\*\(volatile uint32_t\*\)\s*(.*)\s*\)')
|
||||
pattern2 = re.compile(rf'#define {reg}\s*(.*)')
|
||||
m = False
|
||||
with open(f'{os.getenv("FIRMWARE_PATH")}/../generated/csr.h') as f:
|
||||
for line in f:
|
||||
m1= re.search(pattern1,line)
|
||||
m2= re.search(pattern2,line)
|
||||
if m1:
|
||||
m = m1
|
||||
break
|
||||
if m2:
|
||||
m=m2
|
||||
break
|
||||
if m:
|
||||
matched_str= m.group(1)
|
||||
if matched_str[-1] == "L" and matched_str[-2].isnumeric:
|
||||
matched_str = matched_str[:-1]
|
||||
if not all(c in string.hexdigits for c in matched_str[2:]):
|
||||
matched_str= hex(self.get_hexa(matched_str))
|
||||
|
||||
return matched_str
|
||||
else:
|
||||
cocotb.log.info(f" [defsParser] can't find {reg} inside csr")
|
||||
sys.exit()
|
||||
|
||||
|
||||
def get_hexa(self,s:string):
|
||||
pattern2 = re.compile(r'\((.*)\s*\+\s*(.*)\)')
|
||||
search_match = re.search(pattern2,s)
|
||||
if search_match :
|
||||
matches = [search_match.group(1),search_match.group(2)]
|
||||
else:
|
||||
matches = [s]
|
||||
nothex = 1
|
||||
while nothex:
|
||||
nothex = 0
|
||||
for i,match in enumerate(matches):
|
||||
if not all(c in string.hexdigits for c in match[2:-1]):
|
||||
matches[i]=self.get_add_csr(match)
|
||||
nothex = 0
|
||||
else:
|
||||
if match[-1] == "L" and match[-2].isnumeric:
|
||||
matches[i]=matches[i][:-1]
|
||||
|
||||
if len(matches) ==2:
|
||||
return int(matches[0],16) + int(matches[1],16)
|
||||
else:
|
||||
return int(matches[0],16)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,84 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
import cocotb.simulator
|
||||
from cocotb.handle import SimHandleBase
|
||||
from cocotb.handle import Force
|
||||
from cocotb_coverage.coverage import *
|
||||
from cocotb.binary import BinaryValue
|
||||
import enum
|
||||
from cocotb.handle import (
|
||||
ConstantObject,
|
||||
HierarchyArrayObject,
|
||||
HierarchyObject,
|
||||
ModifiableObject,
|
||||
NonHierarchyIndexableObject,
|
||||
SimHandle,
|
||||
)
|
||||
|
||||
from itertools import groupby, product
|
||||
|
||||
import interfaces.common as common
|
||||
from interfaces.common import GPIO_MODE
|
||||
from interfaces.common import MASK_GPIO_CTRL
|
||||
from interfaces.common import Macros
|
||||
|
||||
class LA:
|
||||
def __init__(self,dut:SimHandleBase):
|
||||
self.dut = dut
|
||||
self.clk = dut.clock_tb
|
||||
self.core_hdl = dut.uut.soc.core
|
||||
|
||||
|
||||
""" Configure the value of LA probes [0:127]
|
||||
writing 1 to any bit means bit acts as outputs from the cpu
|
||||
writing 0 to any bit means bit acts as inputs to the cpu """
|
||||
async def configure_la_en(self, bits,data):
|
||||
self.__drive_la_iena(bits,data)
|
||||
self.__drive_la_oenb(bits,data)
|
||||
await ClockCycles(self.clk, 1)
|
||||
|
||||
|
||||
|
||||
def __drive_la_iena(self, bits,data):
|
||||
iena , n_bits = common.signal_value_size(self.core_hdl.la_ien_storage)
|
||||
cocotb.log.debug(f' [LA] before change iena with {iena} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
|
||||
iena[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
self.core_hdl.la_ien_storage.value = iena
|
||||
cocotb.log.info(f' [LA] drive reg_la_iena with {hex(iena)}')
|
||||
|
||||
def __drive_la_oenb(self, bits,data):
|
||||
oenb , n_bits = common.signal_value_size(self.core_hdl.la_oe_storage)
|
||||
cocotb.log.debug(f' [LA] before change oenb with {oenb} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
|
||||
oenb[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
self.core_hdl.la_oe_storage.value = oenb
|
||||
cocotb.log.info(f' [LA] drive reg_la_oenb with {hex(oenb)}')
|
||||
|
||||
""" update the value of LA data input from cpu to user project """
|
||||
def drive_la_data_to_user(self,bits,data):
|
||||
la , n_bits = common.signal_value_size(self.core_hdl.la_out_storage)
|
||||
cocotb.log.debug(f' [LA] before la data update with LA ={la} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
|
||||
la[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
|
||||
self.core_hdl.la_out_storage.value = la
|
||||
cocotb.log.info(f' [LA] drive_la_data_to_user: drive data {hex(la)} to user project')
|
||||
|
||||
"""return the value of LA data output from user project tp cpu"""
|
||||
def check_la_user_out(self):
|
||||
LA_out = self.core_hdl.la_input.value
|
||||
if(LA_out.is_resolvable):
|
||||
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}')
|
||||
else:
|
||||
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}')
|
||||
return LA_out
|
||||
|
||||
|
||||
"""return the value of LA data output from user project tp cpu"""
|
||||
def check_la_ctrl_reg(self):
|
||||
LA_out = self.dut.uut.la_oenb_mprj.value
|
||||
if(LA_out.is_resolvable):
|
||||
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}')
|
||||
else:
|
||||
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}')
|
||||
return LA_out
|
||||
|
|
@ -0,0 +1 @@
|
|||
acc+=rw,wn:*
|
||||
|
|
@ -0,0 +1,263 @@
|
|||
{
|
||||
"Tests": {
|
||||
"_comment0" :"level is priorty of the test low is better, SW spcify if the test uses SW, RTL regressions run this test in RTL ",
|
||||
"_comment1" :"GL regressions run this test in gatelevel, GL_SDF regression run this test with SDF included"
|
||||
|
||||
,"bitbang_no_cpu_all_o" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"test disable CPU and control the wishbone to configure gpio[4:37] as mgmt output using bitbang and check them"}
|
||||
,"bitbang_cpu_all_o" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt output using bitbang and check them"}
|
||||
,"gpio_all_o" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt output using automatic approach firmware and check them"}
|
||||
,"gpio_all_o_user" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as user output using automatic approach firmware and check them"}
|
||||
,"gpio_all_i" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt input using automatic approach firmware and check them"}
|
||||
,"gpio_all_i_pu" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them"}
|
||||
,"gpio_all_i_pd" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them"}
|
||||
,"gpio_all_bidir" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"configure all gpios as mgmt bidir using automatic approach firmware and check them"}
|
||||
,"bitbang_cpu_all_10" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 10"}
|
||||
,"bitbang_cpu_all_01" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 01"}
|
||||
,"bitbang_cpu_all_1100" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 1100"}
|
||||
,"bitbang_cpu_all_0011" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"shift all the register with 0011"}
|
||||
,"bitbang_no_cpu_all_i" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"test disable CPU and control the wishbone to configure gpio[0:31] as mgmt input using bitbang and check them"}
|
||||
,"bitbang_cpu_all_i" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":" configure gpio[0:37] as mgmt input using bitbang and check them"}
|
||||
|
||||
,"bitbang_spi_o" :{"level":0,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"SW":true,
|
||||
"description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"}
|
||||
|
||||
,"bitbang_spi_i" :{"level":0,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"SW":true,
|
||||
"description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"}
|
||||
,"hk_regs_wr_wb_cpu" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"bit bash test for housekeeping registers"}
|
||||
,"hk_regs_wr_wb" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"write then read (the written value) from random housekeeping registers through the firmware but without using CPU, the SPI and system regs can't be read using firmware so the test only GPIO regs inside housekeeping "}
|
||||
,"hk_regs_wr_spi" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"write then read(the written value) from random housekeeping registers through the SPI housekeeping"}
|
||||
,"hk_regs_rst_spi" :{"level":0,
|
||||
"SW":false,
|
||||
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check reset value of house keeping registers by reading them trough the spi housekeeping"}
|
||||
,"helloWorld" :{"level":3,
|
||||
"SW":false,
|
||||
"RTL":[],
|
||||
"GL":[],
|
||||
"GL_SDF":[],
|
||||
"description":"hello world test"}
|
||||
|
||||
,"cpu_stress" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"stress the cpu with heavy processing"}
|
||||
,"mem_stress" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"Memory stress tests write and read from 800 bytes 200 words and 400 half words"}
|
||||
,"IRQ_external" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test external interrupt by mprj 7"}
|
||||
,"IRQ_timer" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test timer0 interrupt"}
|
||||
,"IRQ_uart" :{"level":2,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test timer0 interrupt"}
|
||||
,"mgmt_gpio_out" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"tests blinking of mgmt gpio bit as an output"}
|
||||
,"mgmt_gpio_in" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"tests blinking of mgmt gpio bit as an output"}
|
||||
,"mgmt_gpio_bidir" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"send random number of blinks through mgmt_gpio and expect to recieve the same number back "}
|
||||
,"timer0_oneshot" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check timer0 oneshot mode"}
|
||||
,"timer0_periodic" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check timer0 periodic mode"}
|
||||
,"uart_tx" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test uart transmit"}
|
||||
,"uart_rx" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test uart reception"}
|
||||
,"uart_loopback" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"test uart in loopback mode input and output is shorted"}
|
||||
,"spi_master_rd" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"using SPI master for reading from external memory"}
|
||||
|
||||
,"spi_master_temp" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"To be deleted"}
|
||||
|
||||
,"user_pass_thru_rd" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"use the housekeeping spi in user pass thru mode to read from external mem"}
|
||||
|
||||
|
||||
,"pll" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"Check pll diffrent configuration"}
|
||||
|
||||
,"clock_redirect" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check clock redirect is working as expected"}
|
||||
|
||||
,"hk_disable" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check Housekeeping SPI disable register is working"}
|
||||
|
||||
,"la" :{"level":0,
|
||||
"SW":true,
|
||||
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
|
||||
"GL":["r_gl","nightly","weekly","tape_out"],
|
||||
"GL_SDF":["r_sdf","weekly","tape_out"],
|
||||
"description":"check logic analyzer input and output enable"}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
for(int i =0;i<19*13;i++){
|
||||
clock00();
|
||||
clock00();
|
||||
clock11();
|
||||
clock11();
|
||||
}
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
for(int i =0;i<19*13;i++){
|
||||
clock00();
|
||||
clock11();
|
||||
}
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
for(int i =0;i<19*13;i++){
|
||||
clock11();
|
||||
clock00();
|
||||
}
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
for(int i =0;i<19*13;i++){
|
||||
clock11();
|
||||
clock11();
|
||||
clock00();
|
||||
clock00();
|
||||
}
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = 0x1803;
|
||||
reg_mprj_io_36 = 0x1803;
|
||||
reg_mprj_io_35 = 0x1803;
|
||||
reg_mprj_io_34 = 0x1803;
|
||||
reg_mprj_io_33 = 0x1803;
|
||||
reg_mprj_io_32 = 0x1803;
|
||||
reg_mprj_io_31 = 0x1803;
|
||||
reg_mprj_io_30 = 0x1803;
|
||||
reg_mprj_io_29 = 0x1803;
|
||||
reg_mprj_io_28 = 0x1803;
|
||||
reg_mprj_io_27 = 0x1803;
|
||||
reg_mprj_io_26 = 0x1803;
|
||||
reg_mprj_io_25 = 0x1803;
|
||||
reg_mprj_io_24 = 0x1803;
|
||||
reg_mprj_io_23 = 0x1803;
|
||||
reg_mprj_io_22 = 0x1803;
|
||||
reg_mprj_io_21 = 0x1803;
|
||||
reg_mprj_io_20 = 0x1803;
|
||||
reg_mprj_io_19 = 0x1803;
|
||||
reg_mprj_io_18 = 0x1803;
|
||||
reg_mprj_io_17 = 0x1803;
|
||||
reg_mprj_io_16 = 0x1803;
|
||||
reg_mprj_io_15 = 0x1803;
|
||||
reg_mprj_io_14 = 0x1803;
|
||||
reg_mprj_io_13 = 0x1803;
|
||||
reg_mprj_io_12 = 0x1803;
|
||||
reg_mprj_io_11 = 0x1803;
|
||||
reg_mprj_io_10 = 0x1803;
|
||||
reg_mprj_io_9 = 0x1803;
|
||||
reg_mprj_io_8 = 0x1803;
|
||||
reg_mprj_io_7 = 0x1803;
|
||||
reg_mprj_io_6 = 0x1803;
|
||||
reg_mprj_io_5 = 0x1803;
|
||||
reg_mprj_io_4 = 0x1803;
|
||||
reg_mprj_io_3 = 0x1803;
|
||||
reg_mprj_io_2 = 0x1803;
|
||||
reg_mprj_io_1 = 0x1803;
|
||||
reg_mprj_io_0 = 0x1803;
|
||||
reg_mprj_io_0 = 0x1803;
|
||||
|
||||
// bitbang
|
||||
//Configure all as input except reg_mprj_io_3
|
||||
clock_in_right_i_left_i_standard(0); // 18 and 19
|
||||
clock_in_right_i_left_i_standard(0); // 17 and 20
|
||||
clock_in_right_i_left_i_standard(0); // 16 and 21
|
||||
clock_in_right_i_left_i_standard(0); // 15 and 22
|
||||
clock_in_right_i_left_i_standard(0); // 14 and 23
|
||||
clock_in_right_i_left_i_standard(0); // 13 and 24
|
||||
clock_in_right_i_left_i_standard(0); // 12 and 25
|
||||
clock_in_right_i_left_i_standard(0); // 11 and 26
|
||||
clock_in_right_i_left_i_standard(0); // 10 and 27
|
||||
clock_in_right_i_left_i_standard(0); // 9 and 28
|
||||
clock_in_right_i_left_i_standard(0); // 8 and 29
|
||||
clock_in_right_i_left_i_standard(0); // 7 and 30
|
||||
clock_in_right_i_left_i_standard(0); // 6 and 31
|
||||
clock_in_right_i_left_i_standard(0); // 5 and 32
|
||||
clock_in_right_i_left_i_standard(0); // 4 and 33
|
||||
clock_in_right_i_left_i_standard(0); // 3 and 34
|
||||
clock_in_right_i_left_i_standard(0); // 2 and 35
|
||||
clock_in_right_i_left_i_standard(0); // 1 and 36
|
||||
clock_in_right_i_left_i_standard(0); // 0 and 37
|
||||
load(); // load
|
||||
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0x8F66FD7B);
|
||||
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xFFA88C5A);
|
||||
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xC9536346);
|
||||
reg_debug_1 = 0XD1;
|
||||
while (reg_mprj_datah != 0x3F);
|
||||
reg_debug_1 = 0XD2;
|
||||
while (reg_mprj_datah != 0x0);
|
||||
reg_debug_1 = 0XD3;
|
||||
while (reg_mprj_datah != 0x15);
|
||||
reg_debug_1 = 0XD4;
|
||||
while (reg_mprj_datah != 0x2A);
|
||||
|
||||
reg_debug_2 = 0xFF;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,99 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = 0x1803 ;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
// bitbang
|
||||
// Configure all as output except reg_mprj_io_3
|
||||
clock_in_right_o_left_o_standard(0); // 18 and 19
|
||||
clock_in_right_o_left_o_standard(0); // 17 and 20
|
||||
clock_in_right_o_left_o_standard(0); // 16 and 21
|
||||
clock_in_right_o_left_o_standard(0); // 15 and 22
|
||||
clock_in_right_o_left_o_standard(0); // 14 and 23
|
||||
clock_in_right_o_left_o_standard(0); // 13 and 24
|
||||
clock_in_right_o_left_o_standard(0); // 12 and 25
|
||||
clock_in_right_o_left_o_standard(0); // 11 and 26
|
||||
clock_in_right_o_left_o_standard(0); // 10 and 27
|
||||
clock_in_right_o_left_o_standard(0); // 9 and 28
|
||||
clock_in_right_o_left_o_standard(0); // 8 and 29
|
||||
clock_in_right_o_left_o_standard(0); // 7 and 30
|
||||
clock_in_right_o_left_o_standard(0); // 6 and 31
|
||||
clock_in_right_o_left_o_standard(0); // 5 and 32
|
||||
clock_in_right_o_left_o_standard(0); // 4 and 33
|
||||
clock_in_right_o_left_i_standard(0); // 3 and 34
|
||||
clock_in_right_o_left_o_standard(0); // 2 and 35
|
||||
clock_in_right_o_left_o_standard(0); // 1 and 36
|
||||
clock_in_right_o_left_o_standard(0); // 0 and 37
|
||||
load();
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
reg_mprj_datal = 0x0;
|
||||
reg_mprj_datah = 0x0;
|
||||
i = 0x20;
|
||||
for (j = 0; j < 5; j++) {
|
||||
reg_mprj_datah = i;
|
||||
reg_debug_2 = 37-j;
|
||||
reg_mprj_datah = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x20;
|
||||
}
|
||||
i = 0x80000000;
|
||||
for (j = 0; j < 32; j++) {
|
||||
reg_mprj_datah = 0x3f;
|
||||
reg_mprj_datal = i;
|
||||
reg_debug_2 = 32-j;
|
||||
reg_mprj_datah = 0x00;
|
||||
reg_mprj_datal = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x80000000;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,325 @@
|
|||
|
||||
|
||||
void clock11()
|
||||
{
|
||||
reg_mprj_xfer = 0x66; reg_mprj_xfer = 0x76;
|
||||
}
|
||||
|
||||
void clock00()
|
||||
{
|
||||
reg_mprj_xfer = 0x06; reg_mprj_xfer = 0x16;
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
|
||||
void clock10()
|
||||
{
|
||||
reg_mprj_xfer = 0x46; reg_mprj_xfer = 0x56;
|
||||
}
|
||||
|
||||
void clock01()
|
||||
{
|
||||
reg_mprj_xfer = 0x26; reg_mprj_xfer = 0x36;
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Load registers
|
||||
// --------------------------------------------------------
|
||||
|
||||
void load()
|
||||
{
|
||||
reg_mprj_xfer = 0x06;
|
||||
reg_mprj_xfer = 0x0e; reg_mprj_xfer = 0x06; // Apply load
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Enable bit-bang mode and clear registers
|
||||
// --------------------------------------------------------
|
||||
|
||||
void clear_registers()
|
||||
{
|
||||
reg_mprj_xfer = 0x06; // Enable bit-bang mode
|
||||
reg_mprj_xfer = 0x04; reg_mprj_xfer = 0x06; // Pulse reset
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Clock in an input + output configuration. The value
|
||||
// passed in "ddhold" is the number of data-dependent hold
|
||||
// violations up to this point.
|
||||
// --------------------------------------------------------
|
||||
|
||||
/* Clock in data on the left side. Assume standard hold
|
||||
* violation, so clock in12 times and assume that the
|
||||
* next data to be clocked will start with "1", enforced
|
||||
* by the code.
|
||||
*
|
||||
* Left side = GPIOs 37 to19
|
||||
*/
|
||||
|
||||
void clock_in_left_short(uint32_t ddhold)
|
||||
{
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock10();
|
||||
clock10();
|
||||
|
||||
for (count = 0; count < 9; count++) {
|
||||
if (holds != 0) {
|
||||
clock10();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock00();
|
||||
}
|
||||
|
||||
/* Clock in data on the right side. Assume standard hold
|
||||
* violation, so clock in12 times and assume that the
|
||||
* next data to be clocked will start with "1", enforced
|
||||
* by the code.
|
||||
*
|
||||
* Right side = GPIOs 0 to18
|
||||
*/
|
||||
|
||||
void clock_in_right_short(uint32_t ddhold)
|
||||
{
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock01();
|
||||
clock01();
|
||||
|
||||
for (count = 0; count < 9; count++) {
|
||||
if (holds != 0) {
|
||||
clock01();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock00();
|
||||
}
|
||||
|
||||
/* Clock in data on the left side. Clock the normal13 times,
|
||||
* which is correct for no hold violation or for a data-
|
||||
* dependent hold violation (for the latter, ddhold must be
|
||||
* incremented before calling the subroutine).
|
||||
*
|
||||
* Left side = GPIOs 37 to19
|
||||
*/
|
||||
|
||||
void clock_in_left_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock10();
|
||||
clock10();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock10();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock10();
|
||||
clock00();
|
||||
clock00();
|
||||
clock10();
|
||||
}
|
||||
void clock_in_right_o_left_o_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock11();
|
||||
clock00();
|
||||
clock00();
|
||||
clock11();
|
||||
}
|
||||
|
||||
void clock_in_right_o_left_i_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock10();
|
||||
clock00();
|
||||
clock01();
|
||||
clock11();
|
||||
}
|
||||
|
||||
void clock_in_right_i_left_o_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock01();
|
||||
clock00();
|
||||
clock10();
|
||||
clock11();
|
||||
}
|
||||
|
||||
void clock_in_right_i_left_i_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock00();
|
||||
clock00();
|
||||
clock11();
|
||||
clock11();
|
||||
}
|
||||
|
||||
/* Clock in data on the right side. Clock the normal13 times,
|
||||
* which is correct for no hold violation or for a data-
|
||||
* dependent hold violation (for the latter, ddhold must be
|
||||
* incremented before calling the subroutine).
|
||||
*
|
||||
* Right side = GPIOs 0 to18
|
||||
*/
|
||||
|
||||
void clock_in_right_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock01();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock10();
|
||||
clock00();
|
||||
clock01();
|
||||
clock11();
|
||||
}
|
||||
|
||||
void clock_in_right_i_left_io_standard(uint32_t ddhold){
|
||||
uint32_t count;
|
||||
uint32_t holds = ddhold;
|
||||
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
for (count = 0; count < 7; count++) {
|
||||
if (holds != 0) {
|
||||
clock11();
|
||||
holds--;
|
||||
}
|
||||
else
|
||||
clock00();
|
||||
}
|
||||
|
||||
clock01();
|
||||
clock00();
|
||||
clock11();
|
||||
clock11();
|
||||
}
|
||||
// --------------------------------------------------------
|
||||
// Clock in data for GPIO 0 and 37 (fixed) and apply load.
|
||||
// --------------------------------------------------------
|
||||
|
||||
void clock_in_end(){
|
||||
// Right side: GPIO 0 configured disabled
|
||||
// Left side: GPIO 37 configured as input
|
||||
clock11();
|
||||
clock10();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock01();
|
||||
clock00();
|
||||
clock11();
|
||||
clock11();
|
||||
|
||||
load();
|
||||
}
|
||||
|
||||
// --------------------------------------------------------
|
||||
// Same as above, except that GPIO is configured as an
|
||||
// output for a quick sanity check.
|
||||
// --------------------------------------------------------
|
||||
|
||||
void clock_in_end_output()
|
||||
{
|
||||
// Right side: GPIO 0 configured disabled
|
||||
// Left side: GPIO 37 configured as output
|
||||
clock11();
|
||||
clock10();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock00();
|
||||
clock01();
|
||||
clock00();
|
||||
clock01();
|
||||
clock11();
|
||||
|
||||
load();
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
}
|
||||
|
|
@ -0,0 +1,355 @@
|
|||
from interfaces.defsParser import Regs
|
||||
|
||||
reg = Regs()
|
||||
|
||||
|
||||
"""
|
||||
reg_mprj_xfer contain
|
||||
bit 0 : busy
|
||||
bit 1 : bitbang enable
|
||||
bit 2 : bitbang reset active low
|
||||
bit 3 : bitbang load registers
|
||||
bit 4 : bitbang clock
|
||||
bit 5 : serial data 1
|
||||
bit 6 : serial data 2
|
||||
"""
|
||||
|
||||
"""shift the 2 registers with 2 ones"""
|
||||
async def clock11(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x66) # 0110_0110
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x76) # 0111_0110
|
||||
|
||||
"""shift the 2 registers with 2 zeros"""
|
||||
async def clock00(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # 0000_0110
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x16) # 0001_0110
|
||||
|
||||
"""shift the 2 registers with 1 in the left side and zero in right side"""
|
||||
async def clock01(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x26) # 0010_0110
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x36) # 0011_0110
|
||||
|
||||
"""shift the 2 registers with 1 in the left side and zero in right side"""
|
||||
async def clock10(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x46) # 0100_0110
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x56) # 0101_0110
|
||||
|
||||
"""enable the serial loader bit to load registers"""
|
||||
async def load(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x0e) # enable loader
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
|
||||
|
||||
"""Enable bit-bang mode and clear registers"""
|
||||
async def clear_registers(cpu):
|
||||
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x04) # reset
|
||||
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
|
||||
|
||||
"""
|
||||
--------------------------------------------------------
|
||||
Clock in an input + output configuration. The value
|
||||
passed in "ddhold" is the number of data-dependent hold
|
||||
violations up to this point.
|
||||
--------------------------------------------------------
|
||||
|
||||
* Clock in data on the left side. Assume standard hold
|
||||
* violation, so clock in 12 times and assume that the
|
||||
* next data to be clocked will start with "1", enforced
|
||||
* by the code.
|
||||
*
|
||||
* Left side = GPIOs 37 to 19
|
||||
|
||||
"""
|
||||
async def clock_in_left_short(cpu,ddhold):
|
||||
await clock10(cpu)
|
||||
await clock10(cpu)
|
||||
|
||||
for i in range(9):
|
||||
if ddhold != 0:
|
||||
await clock10(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock00(cpu)
|
||||
|
||||
async def clock_in_right_short(cpu,ddhold):
|
||||
await clock01(cpu)
|
||||
await clock01(cpu)
|
||||
|
||||
for i in range(9):
|
||||
if ddhold != 0:
|
||||
await clock01(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock00(cpu)
|
||||
|
||||
async def clock_in_left_standard(cpu,ddhold):
|
||||
await clock10(cpu)
|
||||
await clock10(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock10(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock10(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock10(cpu)
|
||||
|
||||
"""right output left input"""
|
||||
async def clock_in_right_o_left_i_standard(cpu,ddhold):
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock10(cpu)
|
||||
await clock00(cpu)
|
||||
await clock01(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
"""right input left output"""
|
||||
async def clock_in_right_i_left_o_standard(cpu,ddhold):
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock10(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock01(cpu)
|
||||
await clock00(cpu)
|
||||
await clock10(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
"""right input left output"""
|
||||
async def clock_in_right_i_left_i_standard(cpu,ddhold):
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
"""right output left output"""
|
||||
async def clock_in_right_o_left_o_standard(cpu,ddhold):
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01(cpu)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00(cpu)
|
||||
|
||||
await clock11(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock11(cpu)
|
||||
|
||||
async def clock_in_end_output(cpu):
|
||||
# Right side: GPIO 0 configured disabled
|
||||
# /Left side: GPIO 37 configured as output
|
||||
await clock11(cpu)
|
||||
await clock11(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock00(cpu)
|
||||
await clock01(cpu)
|
||||
await clock11(cpu)
|
||||
await load(cpu)
|
||||
reg_mprj_io_37_addr = reg.get_addr('reg_mprj_io_37')
|
||||
await cpu.drive_data2address(reg_mprj_io_37_addr,0x1809)
|
||||
|
||||
|
||||
async def clock11_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x66) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x76) # 11
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
async def clock00_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x06) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x16) # 00
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
async def clock01_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x26) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x36) # 01
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
async def clock10_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x46) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x56) # 10
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
async def load_spi(caravelEnv):
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x0e) # load enable
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(0x16) # 00
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
"""right output left input"""
|
||||
async def clock_in_right_o_left_i_standard_spi(caravelEnv,ddhold):
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01_spi(caravelEnv)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00_spi(caravelEnv)
|
||||
|
||||
await clock10_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock01_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
"""right input left output"""
|
||||
async def clock_in_right_i_left_o_standard_spi(caravelEnv,ddhold):
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock10_spi(caravelEnv)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00_spi(caravelEnv)
|
||||
|
||||
await clock01_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock10_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
"""right input left output"""
|
||||
async def clock_in_right_i_left_i_standard_spi(caravelEnv,ddhold):
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01_spi(caravelEnv)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00_spi(caravelEnv)
|
||||
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
"""right output left output"""
|
||||
async def clock_in_right_o_left_o_standard_spi(caravelEnv,ddhold):
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
for i in range(7):
|
||||
if ddhold != 0:
|
||||
await clock01_spi(caravelEnv)
|
||||
ddhold -=1
|
||||
else:
|
||||
await clock00_spi(caravelEnv)
|
||||
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
|
||||
async def clock_in_end_output_spi(caravelEnv):
|
||||
# Right side: GPIO 0 configured disabled
|
||||
# /Left side: GPIO 37 configured as output
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock00_spi(caravelEnv)
|
||||
await clock01_spi(caravelEnv)
|
||||
await clock11_spi(caravelEnv)
|
||||
await load_spi(caravelEnv)
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
int i,j;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
|
||||
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0x8F66FD7B);
|
||||
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xFFA88C5A);
|
||||
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xC9536346);
|
||||
reg_debug_1 = 0XD1;
|
||||
while (reg_mprj_datah != 0x3F);
|
||||
reg_debug_1 = 0XD2;
|
||||
while (reg_mprj_datah != 0x0);
|
||||
reg_debug_1 = 0XD3;
|
||||
while (reg_mprj_datah != 0x15);
|
||||
reg_debug_1 = 0XD4;
|
||||
while (reg_mprj_datah != 0x2A);
|
||||
|
||||
reg_debug_2 = 0xFF;
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
int i,j;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = 0x1803;
|
||||
reg_mprj_io_3 = 0x1803;
|
||||
reg_mprj_io_2 = 0x1803;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
reg_debug_1 = 0xFF; // finish configuration
|
||||
while (reg_debug_2 != 0xFF); // finish bit bang
|
||||
reg_mprj_datal = 0x0;
|
||||
reg_mprj_datah = 0x0;
|
||||
i = 0x20;
|
||||
for (j = 0; j < 5; j++) {
|
||||
reg_mprj_datah = i;
|
||||
reg_debug_2 = 37-j;
|
||||
reg_mprj_datah = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x20;
|
||||
}
|
||||
i = 0x80000000;
|
||||
for (j = 0; j < 32; j++) {
|
||||
reg_mprj_datah = 0x3f;
|
||||
reg_mprj_datal = i;
|
||||
reg_debug_2 = 32-j;
|
||||
reg_mprj_datah = 0x00;
|
||||
reg_mprj_datal = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x80000000;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,258 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from interfaces.caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_no_cpu_all_o(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=10206)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
|
||||
|
||||
#Configure all as output except reg_mprj_io_3
|
||||
await clear_registers(cpu)
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 18 and 19
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 17 and 20
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 16 and 21
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 15 and 22
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 14 and 23
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 13 and 24
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 12 and 25
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 11 and 26
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 10 and 27
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 9 and 28
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 8 and 29
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 7 and 30
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 6 and 31
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 5 and 32
|
||||
await clock_in_right_o_left_o_standard(cpu,0) # 4 and 33
|
||||
await clock_in_right_o_left_i_standard(cpu,0) # 3 and 34
|
||||
await clock_in_right_o_left_i_standard(cpu,0) # 2 and 35
|
||||
await clock_in_right_o_left_i_standard(cpu,0) # 1 and 36
|
||||
await clock_in_end_output(cpu) # 0 and 37 and load
|
||||
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),i)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} int {caravelEnv.monitor_gpio((37,4)).integer} i = {i}')
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
|
||||
# for k in range(250):
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0)
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3f)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),i)
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)}')
|
||||
if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {i>>4}')
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} type {int(caravelEnv.monitor_gpio((37,4)))} i = {i}')
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
|
||||
# await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
|
||||
await ClockCycles(caravelEnv.clk, 1)
|
||||
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 1000)
|
||||
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_no_cpu_all_i(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=8005)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
|
||||
|
||||
|
||||
#Configure all as input except reg_mprj_io_3
|
||||
await clear_registers(cpu)
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 18 and 19
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 17 and 20
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 16 and 21
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 15 and 22
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 14 and 23
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 13 and 24
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 12 and 25
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 11 and 26
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 10 and 27
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 9 and 28
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 8 and 29
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 7 and 30
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 6 and 31
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 5 and 32
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 4 and 33
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 3 and 34
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 2 and 35
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 1 and 36
|
||||
await clock_in_right_i_left_i_standard(cpu,0) # 0 and 37
|
||||
await load(cpu) # load
|
||||
|
||||
caravelEnv.drive_gpio_in((31,0),0x8F66FD7B)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
|
||||
# value_masked = reg_mprj_datal & mask_input
|
||||
if reg_mprj_datal == 0x8F66FD7B:
|
||||
cocotb.log.info(f'[TEST] Passed with value 0x8F66FD7B')
|
||||
else:
|
||||
cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0x8F66FD7B)}')
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x1B)
|
||||
x = caravelEnv.monitor_gpio((37,32))
|
||||
print(f"xxxxxxxx {x}")
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
|
||||
caravelEnv.drive_gpio_in((31,0),0xFFA88C5A)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
|
||||
# value_masked = reg_mprj_datal & mask_input
|
||||
if reg_mprj_datal == 0xFFA88C5A:
|
||||
cocotb.log.info(f'[TEST] Passed with value 0xFFA88C5A')
|
||||
else:
|
||||
cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xFFA88C5A)}')
|
||||
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x2B)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
|
||||
caravelEnv.drive_gpio_in((31,0),0xC9536346)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
|
||||
# value_masked = reg_mprj_datal & mask_input
|
||||
if reg_mprj_datal == 0xC9536346:
|
||||
cocotb.log.info(f'[TEST] Passed with value 0xC9536346')
|
||||
else:
|
||||
cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xC9536346)}')
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3B)
|
||||
await ClockCycles(caravelEnv.clk, 100)
|
||||
|
||||
|
||||
|
||||
|
||||
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def io_ports(dut):
|
||||
caravelEnv,clock = await test_configure(dut)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
|
||||
|
||||
# Apply configuration
|
||||
await cpu.drive_data2address(reg.get_addr('reg_mprj_xfer'),1)
|
||||
|
||||
while True:
|
||||
if await cpu.read_address(reg.get_addr('reg_mprj_xfer')) != 1 :
|
||||
break
|
||||
|
|
@ -0,0 +1,356 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from interfaces.caravel import GPIO_MODE
|
||||
from interfaces.common import Macros
|
||||
|
||||
reg = Regs()
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_o(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=2075459)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
cocotb.log.info("[TEST] finish configuring using bitbang")
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await wait_reg2(cpu,caravelEnv,37-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await wait_reg2(cpu,caravelEnv,32-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
|
||||
if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,4)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_10(dut):
|
||||
caravelEnv = await test_configure(dut,timeout_cycles=2863378)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = True # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift(uut._id(gpio,False),type)
|
||||
type = not type
|
||||
type = True # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift(uut._id(gpio,False),type)
|
||||
type = not type
|
||||
|
||||
|
||||
def shift(gpio,shift_type):
|
||||
if shift_type:
|
||||
bits = "0101010101010"
|
||||
else:
|
||||
bits = "1010101010101"
|
||||
fail = False
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
|
||||
for i in range(13):
|
||||
if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
|
||||
fail = True
|
||||
cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
|
||||
if not fail:
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} passed")
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_01(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=2863378)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = False # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift(uut._id(gpio,False),type)
|
||||
type = not type
|
||||
type = False # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift(uut._id(gpio,False),type)
|
||||
type = not type
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_0011(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = 0 # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
type = (type + 1) %4
|
||||
type = 0 # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
type = (type + 1) %4
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_1100(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=10000000000)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xFF)
|
||||
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
|
||||
|
||||
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
|
||||
type = 2 # type of shifting 01 or 10
|
||||
for gpio in gpios_l:
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
type = (type + 1) %4
|
||||
type = 2 # type of shifting 01 or 10
|
||||
for gpio in reversed(gpios_h):
|
||||
shift_2(uut._id(gpio,False),type)
|
||||
type = (type + 1) %4
|
||||
|
||||
def shift_2(gpio,shift_type):
|
||||
if shift_type == 0:
|
||||
bits = "1001100110011"
|
||||
elif shift_type == 1:
|
||||
bits = "1100110011001"
|
||||
elif shift_type == 2:
|
||||
bits = "0110011001100"
|
||||
elif shift_type == 3:
|
||||
bits = "0011001100110"
|
||||
fail = False
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
|
||||
for i in range(13):
|
||||
if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
|
||||
fail = True
|
||||
cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
|
||||
if not fail:
|
||||
cocotb.log.info(f"[TEST] gpio {gpio} passed")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_cpu_all_i(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=1691295)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xAA)
|
||||
cocotb.log.info(f"[TEST] configuration finished")
|
||||
data_in = 0x8F66FD7B
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xBB)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
data_in = 0xFFA88C5A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xCC)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
data_in = 0xC9536346
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD1)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
data_in = 0x3F
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD2)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
|
||||
data_in = 0x0
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD3)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
|
||||
data_in = 0x15
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD4)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
|
||||
data_in = 0x2A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
|
||||
await wait_reg2(cpu,caravelEnv,0xFF)
|
||||
cocotb.log.info(f"[TEST] finish")
|
||||
|
||||
|
||||
|
||||
"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as output."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_spi_o(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=639757)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured
|
||||
#Configure all as output except reg_mprj_io_3
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 18 and 19
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 17 and 20
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 16 and 21
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 15 and 22
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 14 and 23
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 13 and 24
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 12 and 25
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 11 and 26
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 10 and 27
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 9 and 28
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 8 and 29
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 7 and 30
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 6 and 31
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 5 and 32
|
||||
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 4 and 33
|
||||
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 3 and 34
|
||||
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 2 and 35
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 1 and 36
|
||||
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 0 and 37
|
||||
await load_spi(caravelEnv) # load
|
||||
|
||||
cpu.write_debug_reg2_backdoor(0xFF)
|
||||
cocotb.log.info("[TEST] finish configuring using bitbang")
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await wait_reg2(cpu,caravelEnv,37-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,5)).integer != i << 27:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,5))} instead of {bin(i << 28)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,5)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await wait_reg2(cpu,caravelEnv,32-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
|
||||
if caravelEnv.monitor_gpio((31,5)).integer != i>>5 :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,5)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
||||
|
||||
"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as input."""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def bitbang_spi_i(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=56703)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured
|
||||
#Configure all as output except reg_mprj_io_3
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 18 and 19
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 17 and 20
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 16 and 21
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 15 and 22
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 14 and 23
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 13 and 24
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 12 and 25
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 11 and 26
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 10 and 27
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 9 and 28
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 8 and 29
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 7 and 30
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 6 and 31
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 5 and 32
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 4 and 33
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 3 and 34
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 2 and 35
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 1 and 36
|
||||
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 0 and 37
|
||||
await load_spi(caravelEnv) # load
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xAA)
|
||||
cocotb.log.info(f"[TEST] configuration finished")
|
||||
data_in = 0x8F66FD7B
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xBB)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
data_in = 0xFFA88C5A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xCC)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
data_in = 0xC9536346
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD1)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
data_in = 0x3F
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD2)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
|
||||
data_in = 0x0
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD3)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
|
||||
data_in = 0x15
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD4)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
|
||||
data_in = 0x2A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg2(cpu,caravelEnv,0xFF)
|
||||
cocotb.log.info(f"[TEST] finish")
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
|
||||
# from turtle import st
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from cocotb.result import SimTimeoutError
|
||||
import cocotb
|
||||
import time
|
||||
"""class to handle timeout inside the tests. after the provided number of cycles (cycle_num) are exceeded test would fail
|
||||
precision would determine when to log timeout warning for example if cycle_num=1000 and percision = 10% so after each 1000*10% = 100 cycle log would be printed
|
||||
"""
|
||||
class Timeout:
|
||||
def __init__(self,clk,cycle_num,precision=0.20):
|
||||
self.clk = clk
|
||||
self.cycle_num = cycle_num
|
||||
self.cycle_precision = precision * cycle_num
|
||||
cocotb.scheduler.add(self._timeout_check())
|
||||
|
||||
|
||||
async def _timeout_check(self):
|
||||
number_of_cycles = 0
|
||||
for i in range(0,self.cycle_num):
|
||||
await ClockCycles(self.clk,1)
|
||||
number_of_cycles +=1
|
||||
if number_of_cycles %self.cycle_precision ==0:
|
||||
cocotb.log.warning(f"simulation are only {self.cycle_num-number_of_cycles} cycles away from TIMEOUT ")
|
||||
|
||||
raise SimTimeoutError(f"simulation exceeds the max number of cycles {self.cycle_num}")
|
||||
|
||||
pass
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.clock import Clock
|
||||
import cocotb.log
|
||||
import interfaces.caravel as caravel
|
||||
from interfaces.logic_analyzer import LA
|
||||
from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox
|
||||
import interfaces.common as common
|
||||
import logging
|
||||
from interfaces.cpu import RiskV
|
||||
from cocotb.log import SimTimeContextFilter
|
||||
from cocotb.log import SimLogFormatter
|
||||
from tests.common_functions.Timeout import Timeout
|
||||
import os
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
|
||||
"""configure the test log file location and log verbosity
|
||||
configure the test clock
|
||||
configure the test timeout
|
||||
configure whitbox models
|
||||
start up the test connecting power vdd to the design then reset and disable the CSB bit
|
||||
return the caravel environmnet with clock and start up
|
||||
"""
|
||||
async def test_configure(dut,timeout_cycles=1000000,clk=25,timeout_precision=0.2,num_error=3):
|
||||
caravelEnv = caravel.Caravel_env(dut)
|
||||
Timeout(caravelEnv.clk,timeout_cycles,timeout_precision)
|
||||
if os.getenv('ERRORMAX') != 'None':
|
||||
num_error = int(os.getenv('ERRORMAX'))
|
||||
cocotb.scheduler.add(max_num_error(num_error,caravelEnv.clk))
|
||||
clock = Clock(caravelEnv.clk, clk, units="ns") # Create a 10ns period clock on port clk
|
||||
cocotb.start_soon(clock.start()) # Start the clock
|
||||
await caravelEnv.start_up()
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
# HK_whiteBox(dut)
|
||||
return caravelEnv,clock
|
||||
|
||||
class CallCounted:
|
||||
"""Decorator to determine number of calls for a method"""
|
||||
|
||||
def __init__(self,method):
|
||||
self.method=method
|
||||
self.counter=0
|
||||
|
||||
def __call__(self,*args,**kwargs):
|
||||
self.counter+=1
|
||||
return self.method(*args,**kwargs)
|
||||
|
||||
|
||||
def repot_test(func):
|
||||
async def wrapper_func(*args, **kwargs):
|
||||
## configure logging
|
||||
COCOTB_ANSI_OUTPUT=0
|
||||
|
||||
TestName = func.__name__
|
||||
cocotb.log.setLevel(logging.INFO)
|
||||
cocotb.log.error = CallCounted(cocotb.log.error)
|
||||
cocotb.log.critical = CallCounted(cocotb.log.critical)
|
||||
cocotb.log.warning = CallCounted(cocotb.log.warning)
|
||||
handler = logging.FileHandler(f"sim/{os.getenv('RUNTAG')}/{os.getenv('SIM')}-{TestName}/{TestName}.log",mode='w')
|
||||
handler.addFilter(SimTimeContextFilter())
|
||||
handler.setFormatter(SimLogFormatter())
|
||||
cocotb.log.addHandler(handler)
|
||||
## call test
|
||||
await func(*args, **kwargs)
|
||||
## report after finish simulation
|
||||
msg = f'with ({cocotb.log.critical.counter})criticals ({cocotb.log.error.counter})errors ({cocotb.log.warning.counter})warnings '
|
||||
if cocotb.log.error.counter > 0 or cocotb.log.critical.counter >0:
|
||||
raise cocotb.result.TestComplete(f'Test failed {msg}')
|
||||
else:
|
||||
raise cocotb.result.TestComplete(f'Test passed {msg}')
|
||||
return retval
|
||||
return wrapper_func
|
||||
|
||||
async def max_num_error(num_error,clk):
|
||||
while True:
|
||||
await ClockCycles(clk,1)
|
||||
if cocotb.log.error.counter + cocotb.log.critical.counter > num_error:
|
||||
msg = f'Test failed with max number of errors {num_error} ({cocotb.log.critical.counter})criticals ({cocotb.log.error.counter})errors ({cocotb.log.warning.counter})warnings '
|
||||
raise cocotb.result.TestFailure(msg)
|
||||
|
||||
|
||||
async def wait_reg1(cpu,caravelEnv,data):
|
||||
while (True):
|
||||
if cpu.read_debug_reg1() == data:
|
||||
return
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
|
||||
async def wait_reg2(cpu,caravelEnv,data):
|
||||
while (True):
|
||||
if cpu.read_debug_reg2() == data:
|
||||
return
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
|
|
@ -0,0 +1,156 @@
|
|||
#include <defs.h>
|
||||
|
||||
int A[]={1, 40, 2, 5, 22, 11, 90, 200, 10, 20, 25};
|
||||
|
||||
// int factorial(int n) {
|
||||
// int fac=1;
|
||||
// for(int i=1; i<=n;++i){
|
||||
// fac = fac * i;
|
||||
// }
|
||||
// return fac;
|
||||
// }
|
||||
|
||||
int fibbonacci(int n) {
|
||||
if(n == 0){
|
||||
return 0;
|
||||
} else if(n == 1) {
|
||||
return 1;
|
||||
} else {
|
||||
return (fibbonacci(n-1) + fibbonacci(n-2));
|
||||
}
|
||||
}
|
||||
|
||||
void recursiveInsertionSort(int arr[], int n){
|
||||
if (n <= 1)
|
||||
return;
|
||||
recursiveInsertionSort( arr, n-1 );
|
||||
int nth = arr[n-1];
|
||||
int j = n-2;
|
||||
while (j >= 0 && arr[j] > nth){
|
||||
arr[j+1] = arr[j];
|
||||
j--;
|
||||
}
|
||||
arr[j+1] = nth;
|
||||
}
|
||||
|
||||
|
||||
void quick_sort(int number[],int first,int last){
|
||||
int i, j, pivot, temp;
|
||||
|
||||
if(first<last){
|
||||
pivot=first;
|
||||
i=first;
|
||||
j=last;
|
||||
|
||||
while(i<j){
|
||||
while(number[i]<=number[pivot]&&i<last)
|
||||
i++;
|
||||
while(number[j]>number[pivot])
|
||||
j--;
|
||||
if(i<j){
|
||||
temp=number[i];
|
||||
number[i]=number[j];
|
||||
number[j]=temp;
|
||||
}
|
||||
}
|
||||
|
||||
temp=number[pivot];
|
||||
number[pivot]=number[j];
|
||||
number[j]=temp;
|
||||
quick_sort(number,first,j-1);
|
||||
quick_sort(number,j+1,last);
|
||||
|
||||
}
|
||||
}
|
||||
int f4(int a, int b, int c, int d){
|
||||
return a + b + c + d;
|
||||
}
|
||||
|
||||
int f5(int a, int b, int c, int d, int e){
|
||||
return e + f4(a, b, c, d);
|
||||
}
|
||||
|
||||
int f6(int a, int b, int c, int d, int e, int f){
|
||||
return f + f5(a, b, c, d, e);
|
||||
}
|
||||
|
||||
int f7(int a, int b, int c, int d, int e, int f, int g){
|
||||
return g + f6(a, b, c, d, e, f);
|
||||
}
|
||||
int f8(int a, int b, int c, int d, int e, int f, int g, int h){
|
||||
return h + f7(a, b, c, d, e, f, g);
|
||||
}
|
||||
/*
|
||||
Stress the cpu with heavy processing
|
||||
|
||||
*/
|
||||
void main()
|
||||
{
|
||||
int n;
|
||||
int B[10];
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
// start test
|
||||
// reg_mprj_datal = 0xAAAA0000;
|
||||
|
||||
// n =factorial(12);
|
||||
// if(n != 479001600)
|
||||
// reg_mprj_datal = 0xFFFF0000; //fail
|
||||
|
||||
// reg_mprj_datal = 0x11110000; //phase 1 pass
|
||||
|
||||
n = fibbonacci(10);
|
||||
if(n != 55)
|
||||
reg_debug_1 = 0x1E; // fail pahse 1
|
||||
else
|
||||
reg_debug_1 = 0x1B; // pass pahse 1
|
||||
|
||||
int sumA = 0;
|
||||
for(int i=0; i<10; i++){
|
||||
B[i] = A[i];
|
||||
sumA += A[i];
|
||||
}
|
||||
|
||||
if(sumA != 401)
|
||||
reg_debug_1 = 0x2E; // fail pahse 2
|
||||
else
|
||||
reg_debug_1 = 0x2B; // pass pahse 2
|
||||
|
||||
recursiveInsertionSort(B, 10);
|
||||
|
||||
int sumB = 0;
|
||||
for(int i=0; i<10; i++){
|
||||
sumB += B[i];
|
||||
}
|
||||
|
||||
if(sumA != sumB)
|
||||
reg_debug_1 = 0x3E;// fail pahse 3
|
||||
else
|
||||
reg_debug_1 = 0x3B; // pass pahse 3
|
||||
|
||||
for(int i=0; i<10; i++){
|
||||
B[i] = A[i];
|
||||
sumA += A[i];
|
||||
}
|
||||
quick_sort(B, 0, 9);
|
||||
|
||||
for(int i=0; i<10; i++){
|
||||
sumB += B[i];
|
||||
}
|
||||
|
||||
if(sumA != sumB)
|
||||
reg_debug_1 = 0x4E;// fail pahse 4
|
||||
else
|
||||
reg_debug_1 = 0x4B; // pass pahse 4
|
||||
|
||||
int sum = f8(10, 20, 30, 40, 50, 60, 70, 80);
|
||||
|
||||
if(sum != (10+20+30+40+50+60+70+80))
|
||||
reg_debug_1 = 0x5E; // fail pahse 5
|
||||
else
|
||||
reg_debug_1 = 0x5B; // pass pahse 5
|
||||
|
||||
// test finish
|
||||
reg_debug_2 = 0xFF;
|
||||
}
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from interfaces.caravel import GPIO_MODE
|
||||
|
||||
reg = Regs()
|
||||
"""stress the cpu with heavy processing"""
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def cpu_stress(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=1492541)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info(f"[TEST] Start CPU stress test")
|
||||
pass_list = (0x1B,0x2B,0x3B,0x4B,0x5B)
|
||||
fail_list = (0x1E,0x2E,0x3E,0x4E,0x5E)
|
||||
phases_fails = 5
|
||||
phases_passes = 0
|
||||
reg1 =0 # buffer
|
||||
while True:
|
||||
if cpu.read_debug_reg2() == 0xFF: # test finish
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
if reg1 in pass_list: # pass phase
|
||||
phases_passes +=1
|
||||
phases_fails -=1
|
||||
cocotb.log.info(f"[TEST] pass phase {hex(reg1)[2]}")
|
||||
elif reg1 in fail_list: # pass phase
|
||||
cocotb.log.error(f"[TEST] failed phase {hex(reg1)[2]}")
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
|
||||
if phases_fails > 0:
|
||||
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
|
||||
|
|
@ -0,0 +1,421 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from interfaces.caravel import GPIO_MODE
|
||||
from cocotb.binary import BinaryValue
|
||||
|
||||
reg = Regs()
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def gpio_all_o(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=376123)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xAA)
|
||||
cocotb.log.info("[TEST] finish configuring ")
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await wait_reg2(cpu,caravelEnv,37-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,0)).integer != i<<32:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,0)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await wait_reg2(cpu,caravelEnv,32-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
|
||||
if caravelEnv.monitor_gpio((31,0)).integer != i :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,0)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0XBB)
|
||||
data_in = 0x8F66FD7B
|
||||
cocotb.log.info(f"[TEST] try send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
reg2 =0
|
||||
await wait_reg1(cpu,caravelEnv,0XFF)
|
||||
try:
|
||||
reg2 =cpu.read_debug_reg2()
|
||||
if reg2 == data_in:
|
||||
cocotb.log.error(f"[TEST] Error: data {hex(data_in)} driven on gpio[31:0] is seen by firmware while gpios are configured as output")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output it can see {reg2}")
|
||||
except Exception as e:
|
||||
cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output")
|
||||
return
|
||||
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def gpio_all_i(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=44980)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0xAA)
|
||||
cocotb.log.info(f"[TEST] configuration finished")
|
||||
data_in = 0x8F66FD7B
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xBB)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
data_in = 0xFFA88C5A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xCC)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
data_in = 0xC9536346
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD1)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
data_in = 0x3F
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD2)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
|
||||
data_in = 0x0
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD3)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
|
||||
data_in = 0x15
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD4)
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
|
||||
data_in = 0x2A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg2(cpu,caravelEnv,0xFF)
|
||||
cocotb.log.info(f"[TEST] finish")
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def gpio_all_i_pu(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
|
||||
await caravelEnv.release_csb()
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xAA)
|
||||
# monitor the output of padframe module it suppose to be all ones when no input is applied
|
||||
await ClockCycles(caravelEnv.clk,100)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i] != "1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and float")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive gpios with zero
|
||||
data_in = 0x0
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i] != "0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with 0")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive gpios with ones
|
||||
data_in = 0x3FFFFFFFFF
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i] != "1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with 1")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive odd half gpios with zeros and float other half
|
||||
data_in = 0x0
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
for i in range(0,38,2):
|
||||
caravelEnv.release_gpio(i) # release even gpios
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if i%2 ==1: #odd
|
||||
if gpio[i]!="1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 0")
|
||||
else:
|
||||
if gpio[i] != "0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with odd half with 0")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive even half gpios with zeros and float other half
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
for i in range(1,38,2):
|
||||
caravelEnv.release_gpio(i) # release odd gpios
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if i%2 ==1: #odd
|
||||
if gpio[i] != "0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with even half with 0")
|
||||
else:
|
||||
if gpio[i]!="1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with even half with 0")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive odd half gpios with ones and float other half
|
||||
data_in = 0x3FFFFFFFFF
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
for i in range(0,38,2):
|
||||
caravelEnv.release_gpio(i) # release even gpios
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i]!="1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 1")
|
||||
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive even half gpios with zeros and float other half
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
for i in range(1,38,2):
|
||||
caravelEnv.release_gpio(i) # release odd gpios
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i] != "1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with even half with 1")
|
||||
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
|
||||
# drive with zeros then release all gpio
|
||||
data_in = 0x0
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
caravelEnv.release_gpio((37,0))
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i] != "1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and all released")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def gpio_all_i_pd(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
|
||||
await caravelEnv.release_csb()
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xAA)
|
||||
# monitor the output of padframe module it suppose to be all ones when no input is applied
|
||||
await ClockCycles(caravelEnv.clk,100)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i] != "0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and float")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive gpios with zero
|
||||
data_in = 0x0
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i] != "0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with 0")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive gpios with ones
|
||||
data_in = 0x3FFFFFFFFF
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i] != "1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with 1")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive odd half gpios with zeros and float other half
|
||||
data_in = 0x0
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
for i in range(0,38,2):
|
||||
caravelEnv.release_gpio(i) # release even gpios
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i]!="0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 0")
|
||||
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive even half gpios with zeros and float other half
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
for i in range(1,38,2):
|
||||
caravelEnv.release_gpio(i) # release odd gpios
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i]!="0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with even half with 0")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive odd half gpios with ones and float other half
|
||||
data_in = 0x3FFFFFFFFF
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
for i in range(0,38,2):
|
||||
caravelEnv.release_gpio(i) # release even gpios
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if i%2 ==0: #even
|
||||
if gpio[i]!="1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with odd half with 1")
|
||||
else:
|
||||
if gpio[i] != "0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 1")
|
||||
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
# drive even half gpios with zeros and float other half
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
for i in range(1,38,2):
|
||||
caravelEnv.release_gpio(i) # release odd gpios
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if i%2 ==1: #odd
|
||||
if gpio[i]!="1":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with odd half with 1")
|
||||
else:
|
||||
if gpio[i] != "0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 1")
|
||||
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
|
||||
# drive with ones then release all gpio
|
||||
data_in = 0x3FFFFFFFFF
|
||||
caravelEnv.drive_gpio_in((37,0),data_in)
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
caravelEnv.release_gpio((37,0))
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
gpio = dut.uut.padframe.mprj_io_in.value.binstr
|
||||
for i in range(38):
|
||||
if gpio[i] != "0":
|
||||
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and all released")
|
||||
await ClockCycles(caravelEnv.clk,1000)
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def gpio_all_bidir(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=1144980)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
uut = dut.uut
|
||||
await wait_reg1(cpu,caravelEnv,0x1A)
|
||||
cocotb.log.info("[TEST] finish configuring ")
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await wait_reg2(cpu,caravelEnv,37-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,0)).integer != i << 32:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i << 32)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,0)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await wait_reg2(cpu,caravelEnv,32-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
|
||||
if caravelEnv.monitor_gpio((31,0)).integer != i :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,0)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0x2A)
|
||||
cocotb.log.info(f"[TEST] configuration finished")
|
||||
data_in = 0x8F66FD7B
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xBB)
|
||||
if cpu.read_debug_reg2() == data_in:
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
|
||||
data_in = 0xFFA88C5A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xCC)
|
||||
if cpu.read_debug_reg2() == data_in:
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
|
||||
data_in = 0xC9536346
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD1)
|
||||
if cpu.read_debug_reg2() == data_in:
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
|
||||
data_in = 0xC9536346
|
||||
data_in = 0x3F
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD2)
|
||||
if cpu.read_debug_reg2() == data_in:
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
|
||||
data_in = 0xC9536346
|
||||
data_in = 0x0
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD3)
|
||||
if cpu.read_debug_reg2() == data_in:
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
|
||||
data_in = 0xC9536346
|
||||
data_in = 0x15
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg1(cpu,caravelEnv,0xD4)
|
||||
if cpu.read_debug_reg2() == data_in:
|
||||
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
|
||||
data_in = 0xC9536346
|
||||
data_in = 0x2A
|
||||
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
|
||||
caravelEnv.drive_gpio_in((37,32),data_in)
|
||||
await wait_reg2(cpu,caravelEnv,0xFF)
|
||||
cocotb.log.info(f"[TEST] finish")
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
|
@ -0,0 +1,98 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
reg_hkspi_disable = 1;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
|
||||
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
reg_debug_1 = 0x1A; // try the gpios as output
|
||||
reg_mprj_datal = 0x0;
|
||||
reg_mprj_datah = 0x0;
|
||||
i = 0x20;
|
||||
for (j = 0; j < 5; j++) {
|
||||
reg_mprj_datah = i;
|
||||
reg_debug_2 = 37-j;
|
||||
reg_mprj_datah = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x20;
|
||||
}
|
||||
i = 0x80000000;
|
||||
for (j = 0; j < 32; j++) {
|
||||
reg_mprj_datah = 0x3f;
|
||||
reg_mprj_datal = i;
|
||||
reg_debug_2 = 32-j;
|
||||
reg_mprj_datah = 0x00;
|
||||
reg_mprj_datal = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x80000000;
|
||||
}
|
||||
// test input
|
||||
reg_debug_1 = 0X2A; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0x8F66FD7B);
|
||||
reg_debug_2 = reg_mprj_datal;
|
||||
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xFFA88C5A);
|
||||
reg_debug_2 = reg_mprj_datal;
|
||||
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xC9536346);
|
||||
reg_debug_2 = reg_mprj_datal;
|
||||
reg_debug_1 = 0XD1;
|
||||
while (reg_mprj_datah != 0x3F);
|
||||
reg_debug_2 = reg_mprj_datal;
|
||||
reg_debug_1 = 0XD2;
|
||||
while (reg_mprj_datah != 0x0);
|
||||
reg_debug_2 = reg_mprj_datal;
|
||||
reg_debug_1 = 0XD3;
|
||||
while (reg_mprj_datah != 0x15);
|
||||
reg_debug_2 = reg_mprj_datal;
|
||||
reg_debug_1 = 0XD4;
|
||||
while (reg_mprj_datah != 0x2A);
|
||||
|
||||
reg_debug_2=0xFF;
|
||||
}
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "../bitbang/bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0x8F66FD7B);
|
||||
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xFFA88C5A);
|
||||
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
|
||||
while (reg_mprj_datal != 0xC9536346);
|
||||
reg_debug_1 = 0XD1;
|
||||
while (reg_mprj_datah != 0x3F);
|
||||
reg_debug_1 = 0XD2;
|
||||
while (reg_mprj_datah != 0x0);
|
||||
reg_debug_1 = 0XD3;
|
||||
while (reg_mprj_datah != 0x15);
|
||||
reg_debug_1 = 0XD4;
|
||||
while (reg_mprj_datah != 0x2A);
|
||||
|
||||
reg_debug_2 = 0xFF;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "../bitbang/bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
reg_hkspi_disable = 1;
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
|
||||
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
reg_debug_1 = 0XAA; // configuration done
|
||||
|
||||
while (true);
|
||||
}
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "../bitbang/bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
reg_hkspi_disable = 1;
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
|
||||
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
reg_debug_1 = 0XAA; // configuration done
|
||||
|
||||
while (true);
|
||||
}
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "../bitbang/bitbang_functions.c"
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
reg_hkspi_disable = 1;
|
||||
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
reg_debug_1 = 0xAA; // finish configuration
|
||||
reg_mprj_datal = 0x0;
|
||||
reg_mprj_datah = 0x0;
|
||||
i = 0x20;
|
||||
for (j = 0; j < 5; j++) {
|
||||
reg_mprj_datah = i;
|
||||
reg_debug_2 = 37-j;
|
||||
reg_mprj_datah = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x20;
|
||||
}
|
||||
i = 0x80000000;
|
||||
for (j = 0; j < 32; j++) {
|
||||
reg_mprj_datah = 0x3f;
|
||||
reg_mprj_datal = i;
|
||||
reg_debug_2 = 32-j;
|
||||
reg_mprj_datah = 0x00;
|
||||
reg_mprj_datal = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x80000000;
|
||||
}
|
||||
|
||||
// try to give input
|
||||
reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
|
||||
int timeout = 1000;
|
||||
while (reg_mprj_datal != 0x8F66FD7B){
|
||||
timeout--;
|
||||
if (timeout==0){
|
||||
break;
|
||||
}
|
||||
}
|
||||
reg_debug_2 = reg_mprj_datal;
|
||||
reg_debug_1 = 0XFF; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
#include "../bitbang/bitbang_functions.c"
|
||||
// Debug reg DEBUG_ON
|
||||
#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0)
|
||||
#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4)
|
||||
|
||||
void main(){
|
||||
unsigned int i, j, k;
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
reg_hkspi_disable = 1;
|
||||
reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
|
||||
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
reg_debug_1 = 0xAA; // finish configuration
|
||||
reg_mprj_userl = 0x0;
|
||||
reg_mprj_userh = 0x0;
|
||||
i = 0x20;
|
||||
for (j = 0; j < 5; j++) {
|
||||
reg_mprj_userh = i;
|
||||
reg_debug_2 = 37-j;
|
||||
reg_mprj_userh = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x20;
|
||||
}
|
||||
i = 0x80000000;
|
||||
for (j = 0; j < 32; j++) {
|
||||
reg_mprj_userh = 0x3f;
|
||||
reg_mprj_userl = i;
|
||||
reg_debug_2 = 32-j;
|
||||
reg_mprj_userh = 0x00;
|
||||
reg_mprj_userl = 0x00000000;
|
||||
reg_debug_2 = 0;
|
||||
i >>=1;
|
||||
i |= 0x80000000;
|
||||
}
|
||||
|
||||
// try to give input
|
||||
reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_userl
|
||||
int timeout = 1000;
|
||||
while (reg_mprj_userl != 0x8F66FD7B){
|
||||
timeout--;
|
||||
if (timeout==0){
|
||||
break;
|
||||
}
|
||||
}
|
||||
reg_debug_2 = reg_mprj_userl;
|
||||
reg_debug_1 = 0XFF; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_userl
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from interfaces.caravel import GPIO_MODE
|
||||
from cocotb.binary import BinaryValue
|
||||
|
||||
reg = Regs()
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def gpio_all_o_user(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=376123)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xAA)
|
||||
cocotb.log.info("[TEST] finish configuring as user output")
|
||||
i= 0x20
|
||||
for j in range(5):
|
||||
await wait_reg2(cpu,caravelEnv,37-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,0)).integer != i<<32:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,0)).integer != 0:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
|
||||
i = i >> 1
|
||||
i |= 0x20
|
||||
|
||||
i= 0x80000000
|
||||
for j in range(32):
|
||||
await wait_reg2(cpu,caravelEnv,32-j)
|
||||
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
|
||||
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
|
||||
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
|
||||
if caravelEnv.monitor_gpio((31,0)).integer != i :
|
||||
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
|
||||
await wait_reg2(cpu,caravelEnv,0)
|
||||
if caravelEnv.monitor_gpio((37,0)).integer != 0:
|
||||
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
|
||||
|
||||
i = i >> 1
|
||||
i |= 0x80000000
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0XBB)
|
||||
data_in = 0x8F66FD7B
|
||||
cocotb.log.info(f"[TEST] try send {hex(data_in)} to gpio[31:0]")
|
||||
caravelEnv.drive_gpio_in((31,0),data_in)
|
||||
reg2 =0
|
||||
await wait_reg1(cpu,caravelEnv,0XFF)
|
||||
try:
|
||||
reg2 =cpu.read_debug_reg2()
|
||||
if reg2 == data_in:
|
||||
cocotb.log.error(f"[TEST] Error: data {hex(data_in)} driven on gpio[31:0] is seen by firmware while gpios are configured as output")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output it can see {reg2}")
|
||||
except Exception as e:
|
||||
cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output")
|
||||
return
|
||||
|
||||
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
int main(){
|
||||
// do nothing
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
import cocotb
|
||||
from tests.common_functions.test_functions import *
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
|
||||
async def helloWorld(dut):
|
||||
caravelEnv,clock = await test_configure(dut)
|
||||
cocotb.log.info("[Test] Hello world")
|
||||
caravelEnv.print_gpios_ctrl_val()
|
||||
caravelEnv.print_gpios_HW_val()
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
// --------------------------------------------------------
|
||||
|
||||
void main(){
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
/* Monitor pins must be set to output */
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
/* Apply configuration */
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
reg_debug_1 =0xAA;
|
||||
return;
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
// --------------------------------------------------------
|
||||
|
||||
void main(){
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0xBB;
|
||||
|
||||
while (reg_debug_1 != 0xAA);
|
||||
reg_hkspi_disable = 0;
|
||||
// reg_hkspi_pll_ena =0;
|
||||
reg_debug_1 =0xBB;
|
||||
}
|
||||
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
// --------------------------------------------------------
|
||||
|
||||
/*
|
||||
* PLL Test (self-switching)
|
||||
* - Switches PLL bypass in housekeeping
|
||||
* - Changes PLL divider in housekeeping
|
||||
*
|
||||
*/
|
||||
void main()
|
||||
{
|
||||
int i;
|
||||
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
/* Monitor pins must be set to output */
|
||||
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
|
||||
/* Apply configuration */
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
// Start test
|
||||
|
||||
/*
|
||||
*-------------------------------------------------------------
|
||||
* Register 2610_000c reg_hkspi_pll_ena
|
||||
* SPI address 0x08 = PLL enables
|
||||
* bit 0 = PLL enable, bit 1 = DCO enable
|
||||
*
|
||||
* Register 2610_0010 reg_hkspi_pll_bypass
|
||||
* SPI address 0x09 = PLL bypass
|
||||
* bit 0 = PLL bypass
|
||||
*
|
||||
* Register 2610_0020 reg_hkspi_pll_source
|
||||
* SPI address 0x11 = PLL source
|
||||
* bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
|
||||
*
|
||||
* Register 2610_0024 reg_hkspi_pll_divider
|
||||
* SPI address 0x12 = PLL divider
|
||||
* bits 0-4 = feedback divider
|
||||
*
|
||||
* Register 2620_0004 reg_clk_out_dest
|
||||
* SPI address 0x1b = Output redirect
|
||||
* bit 0 = trap to mprj_io[13]
|
||||
* bit 1 = clk to mprj_io[14]
|
||||
* bit 2 = clk2 to mprj_io[15]
|
||||
*-------------------------------------------------------------
|
||||
*/
|
||||
|
||||
// Monitor the core clock and user clock on mprj_io[14] and mprj_io[15]
|
||||
// reg_clk_out_dest = 0x6 to turn on, 0x0 to turn off
|
||||
|
||||
// Write checkpoint for clock counting (PLL bypassed)
|
||||
reg_debug_1 = 0xA1;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x0;
|
||||
reg_debug_1 = 0xA2;
|
||||
|
||||
// Set PLL enable, no DCO mode
|
||||
reg_hkspi_pll_ena = 0x1;
|
||||
|
||||
// Set PLL output divider to 0x03
|
||||
reg_hkspi_pll_source = 0x3;
|
||||
|
||||
// Write checkpoint for clock counting (PLL bypassed)
|
||||
reg_debug_1 = 0xA3;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x0;
|
||||
reg_debug_1 = 0xA4;
|
||||
|
||||
// Disable PLL bypass
|
||||
reg_hkspi_pll_bypass = 0x0;
|
||||
|
||||
// Write checkpoint for clock counting
|
||||
reg_debug_1 = 0xA5;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x0;
|
||||
reg_debug_1 = 0xA6;
|
||||
|
||||
// Write 0x03 to feedback divider (was 0x04)
|
||||
reg_hkspi_pll_divider = 0x3;
|
||||
|
||||
// Write checkpoint
|
||||
reg_debug_1 = 0xA7;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x0;
|
||||
reg_debug_1 = 0xA8;
|
||||
|
||||
// Write 0x04 to PLL output divider
|
||||
reg_hkspi_pll_source = 0x4;
|
||||
|
||||
// Write checkpoint
|
||||
reg_debug_1 = 0xA9;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x6;
|
||||
reg_clk_out_dest = 0x0;
|
||||
reg_debug_1 = 0xAa;
|
||||
|
||||
// End test
|
||||
reg_mprj_datal = 0xA0900000;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from interfaces.caravel import GPIO_MODE
|
||||
from cocotb.binary import BinaryValue
|
||||
|
||||
reg = Regs()
|
||||
caravel_clock = 0
|
||||
user_clock = 0
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def pll(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
error_margin = 0.1
|
||||
|
||||
await wait_reg1(cpu,caravelEnv,0xA1)
|
||||
|
||||
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
|
||||
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock"))
|
||||
await wait_reg1(cpu,caravelEnv,0xA3)
|
||||
if abs(caravel_clock - user_clock) > error_margin*caravel_clock:
|
||||
cocotb.log.error(f"[TEST] Error: clocks should be equal in phase 1 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] pass phase 1 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
|
||||
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock"))
|
||||
await wait_reg1(cpu,caravelEnv,0xA5)
|
||||
if abs(caravel_clock - user_clock) > error_margin*caravel_clock:
|
||||
cocotb.log.error(f"[TEST] Error: clocks should be equal in phase 2 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] pass phase 2 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
|
||||
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock"))
|
||||
await wait_reg1(cpu,caravelEnv,0xA7)
|
||||
if abs(caravel_clock - user_clock*3) > error_margin*caravel_clock:
|
||||
cocotb.log.error(f"[TEST] Error: user clock shoud be 3 times caravel clock in phase 3 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] pass phase 3 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
|
||||
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock "))
|
||||
await wait_reg1(cpu,caravelEnv,0xA9)
|
||||
if abs(caravel_clock - user_clock*3) > error_margin*caravel_clock:
|
||||
cocotb.log.error(f"[TEST] Error: user clock shoud be 3 times caravel clock in phase 4 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] pass phase 4 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
|
||||
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock"))
|
||||
await wait_reg1(cpu,caravelEnv,0xAa)
|
||||
if abs(caravel_clock - user_clock*4) > error_margin*caravel_clock:
|
||||
cocotb.log.error(f"[TEST] Error: user clock shoud be 4 times caravel clock in phase 5 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] pass phase 5 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
|
||||
await ClockCycles(caravelEnv.clk,10000)
|
||||
|
||||
# for i in range(1000):
|
||||
# await ClockCycles(caravelEnv.clk,10000)
|
||||
# cocotb.log.info(f"time = {cocotb.simulator.get_sim_time()}")
|
||||
|
||||
async def calculate_clk_period(clk,name):
|
||||
await RisingEdge(clk)
|
||||
initial_time = cocotb.simulator.get_sim_time()
|
||||
initial_time = (initial_time[0] <<32) | (initial_time[1])
|
||||
for i in range(100):
|
||||
await RisingEdge(clk)
|
||||
end_time = cocotb.simulator.get_sim_time()
|
||||
end_time = (end_time[0] <<32) | (end_time[1])
|
||||
val = (end_time - initial_time) / 100
|
||||
cocotb.log.debug(f"[TEST] clock of {name} is {val}")
|
||||
if name == "caravel clock":
|
||||
global caravel_clock
|
||||
caravel_clock = val
|
||||
elif name == "user clock":
|
||||
global user_clock
|
||||
user_clock = val
|
||||
|
||||
val = str(val)
|
||||
return val
|
||||
|
|
@ -0,0 +1,147 @@
|
|||
from faulthandler import disable
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from interfaces.caravel import GPIO_MODE
|
||||
from cocotb.binary import BinaryValue
|
||||
from tests.housekeeping.housekeeping_spi.spi_access_functions import *
|
||||
|
||||
reg = Regs()
|
||||
caravel_clock = 0
|
||||
user_clock = 0
|
||||
core_clock = 0
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def clock_redirect(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=13060)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
# calculate core clock
|
||||
await cocotb.start(calculate_clk_period(dut.uut.clock,"core clock"))
|
||||
await ClockCycles(caravelEnv.clk,110)
|
||||
cocotb.log.info(f"[TEST] core clock requency = {round(1000000/core_clock,2)} MHz period = {core_clock}ps")
|
||||
await wait_reg1(cpu,caravelEnv,0xAa)
|
||||
# check clk redirect working
|
||||
#user clock
|
||||
clock_name = "user clock"
|
||||
await write_reg_spi(caravelEnv,0x1b,0x0) # disable user clock output redirect
|
||||
await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
|
||||
await ClockCycles(caravelEnv.clk,110)
|
||||
if user_clock != 0:
|
||||
cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled")
|
||||
|
||||
await write_reg_spi(caravelEnv,0x1b,0x4) # enable user clock output redirect
|
||||
await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
|
||||
await ClockCycles(caravelEnv.clk,110)
|
||||
if user_clock != core_clock:
|
||||
cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {user_clock} and core clock = {core_clock}")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
|
||||
|
||||
#caravel clock
|
||||
clock_name = "caravel clock"
|
||||
await write_reg_spi(caravelEnv,0x1b,0x0) # disable caravel clock output redirect
|
||||
await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
|
||||
await ClockCycles(caravelEnv.clk,110)
|
||||
if caravel_clock != 0:
|
||||
cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled")
|
||||
|
||||
await write_reg_spi(caravelEnv,0x1b,0x4) # enable caravel clock output redirect
|
||||
await cocotb.start(calculate_clk_period(dut.bin15_monitor,clock_name))
|
||||
await ClockCycles(caravelEnv.clk,110)
|
||||
if caravel_clock != core_clock:
|
||||
cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {caravel_clock} and core clock = {core_clock}")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
|
||||
|
||||
|
||||
async def calculate_clk_period(clk,name):
|
||||
await RisingEdge(clk)
|
||||
initial_time = cocotb.simulator.get_sim_time()
|
||||
initial_time = (initial_time[0] <<32) | (initial_time[1])
|
||||
for i in range(100):
|
||||
await RisingEdge(clk)
|
||||
end_time = cocotb.simulator.get_sim_time()
|
||||
end_time = (end_time[0] <<32) | (end_time[1])
|
||||
val = (end_time - initial_time) / 100
|
||||
cocotb.log.debug(f"[TEST] clock of {name} is {val}")
|
||||
if name == "caravel clock":
|
||||
global caravel_clock
|
||||
caravel_clock = val
|
||||
elif name == "user clock":
|
||||
global user_clock
|
||||
user_clock = val
|
||||
elif name == "core clock":
|
||||
global core_clock
|
||||
core_clock = val
|
||||
return val
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def hk_disable(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=11243)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
|
||||
# check spi working by writing to PLL enables
|
||||
old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
|
||||
cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
|
||||
await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
|
||||
pll_enable = dut.uut.housekeeping.pll_ena.value.integer
|
||||
cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
|
||||
if pll_enable == 1-old_pll_enable:
|
||||
cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}")
|
||||
old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
|
||||
cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
|
||||
await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
|
||||
pll_enable = dut.uut.housekeeping.pll_ena.value.integer
|
||||
cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
|
||||
if pll_enable == 1-old_pll_enable:
|
||||
cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}")
|
||||
|
||||
# disable Housekeeping SPIca
|
||||
await write_reg_spi(caravelEnv,0x6f,0x1)
|
||||
|
||||
# try to change pll_en
|
||||
old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
|
||||
cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
|
||||
await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
|
||||
pll_enable = dut.uut.housekeeping.pll_ena.value.integer
|
||||
cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
|
||||
if pll_enable == 1-old_pll_enable:
|
||||
cocotb.log.error(f"[TEST] Error: SPI swap pll_enable value from {old_pll_enable} to {pll_enable} while housekeeping spi is disabled")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] pass: SPI isn't working when SPI housekeeping is disabled")
|
||||
|
||||
# enable SPI housekeeping through firmware
|
||||
await wait_reg2(cpu,caravelEnv,0xBB) # start waiting on reg1 AA
|
||||
cpu.write_debug_reg1_backdoor(0xAA)
|
||||
await wait_reg1(cpu,caravelEnv,0xBB) # enabled the housekeeping
|
||||
|
||||
old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
|
||||
cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
|
||||
await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
|
||||
pll_enable = dut.uut.housekeeping.pll_ena.value.integer
|
||||
cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
|
||||
if pll_enable == 1-old_pll_enable:
|
||||
cocotb.log.info(f"[TEST] Pass: Housekeeping SPI has been enabled correctly through firmware")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] Error: Housekeeping SPI failed to be enabled through firmware")
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
// Empty C code
|
||||
|
||||
void main()
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,333 @@
|
|||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
|
||||
// access all housekeeping registers that can be access through firmware and change it's value
|
||||
void main(){
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
// store RO value regs
|
||||
int old_reg_hkspi_status = reg_hkspi_status;
|
||||
int old_reg_hkspi_chip_id = reg_hkspi_chip_id;
|
||||
int old_reg_hkspi_user_id = reg_hkspi_user_id;
|
||||
int old_reg_hkspi_trap = reg_hkspi_trap;
|
||||
int old_reg_hkspi_irq = reg_hkspi_irq;
|
||||
// write 1 ones to all registers
|
||||
reg_mprj_io_0 = 0xFFFFFFFF;
|
||||
reg_mprj_io_1 = 0xFFFFFFFF;
|
||||
reg_mprj_io_2 = 0xFFFFFFFF;
|
||||
reg_mprj_io_3 = 0xFFFFFFFF;
|
||||
reg_mprj_io_4 = 0xFFFFFFFF;
|
||||
reg_mprj_io_5 = 0xFFFFFFFF;
|
||||
reg_mprj_io_6 = 0xFFFFFFFF;
|
||||
reg_mprj_io_7 = 0xFFFFFFFF;
|
||||
reg_mprj_io_8 = 0xFFFFFFFF;
|
||||
reg_mprj_io_9 = 0xFFFFFFFF;
|
||||
reg_mprj_io_10 = 0xFFFFFFFF;
|
||||
reg_mprj_io_11 = 0xFFFFFFFF;
|
||||
reg_mprj_io_12 = 0xFFFFFFFF;
|
||||
reg_mprj_io_13 = 0xFFFFFFFF;
|
||||
reg_mprj_io_14 = 0xFFFFFFFF;
|
||||
reg_mprj_io_15 = 0xFFFFFFFF;
|
||||
reg_mprj_io_16 = 0xFFFFFFFF;
|
||||
reg_mprj_io_17 = 0xFFFFFFFF;
|
||||
reg_mprj_io_18 = 0xFFFFFFFF;
|
||||
reg_mprj_io_19 = 0xFFFFFFFF;
|
||||
reg_mprj_io_20 = 0xFFFFFFFF;
|
||||
reg_mprj_io_21 = 0xFFFFFFFF;
|
||||
reg_mprj_io_22 = 0xFFFFFFFF;
|
||||
reg_mprj_io_23 = 0xFFFFFFFF;
|
||||
reg_mprj_io_24 = 0xFFFFFFFF;
|
||||
reg_mprj_io_25 = 0xFFFFFFFF;
|
||||
reg_mprj_io_26 = 0xFFFFFFFF;
|
||||
reg_mprj_io_27 = 0xFFFFFFFF;
|
||||
reg_mprj_io_28 = 0xFFFFFFFF;
|
||||
reg_mprj_io_29 = 0xFFFFFFFF;
|
||||
reg_mprj_io_30 = 0xFFFFFFFF;
|
||||
reg_mprj_io_31 = 0xFFFFFFFF;
|
||||
reg_mprj_io_32 = 0xFFFFFFFF;
|
||||
reg_mprj_io_33 = 0xFFFFFFFF;
|
||||
reg_mprj_io_34 = 0xFFFFFFFF;
|
||||
reg_mprj_io_35 = 0xFFFFFFFF;
|
||||
reg_mprj_io_36 = 0xFFFFFFFF;
|
||||
reg_mprj_io_37 = 0xFFFFFFFF;
|
||||
// house keeping
|
||||
reg_hkspi_status = 0xFFFFFFFF;
|
||||
reg_hkspi_chip_id = 0xFFFFFFFF;
|
||||
reg_hkspi_user_id = 0xFFFFFFFF;
|
||||
reg_hkspi_pll_ena = 0xFFFFFFFF;
|
||||
reg_hkspi_pll_bypass = 0xFFFFFFFF;
|
||||
reg_hkspi_irq = 0xFFFFFFFF;
|
||||
// reg_hkspi_reset = 0xFFFFFFFF; can't write 1 to it cpu would be reset
|
||||
reg_hkspi_trap = 0xFFFFFFFF;
|
||||
reg_hkspi_pll_trim = 0xFFFFFFFF;
|
||||
reg_hkspi_pll_source = 0xFFFFFFFF;
|
||||
reg_hkspi_pll_divider = 0xFFFFFFFF;
|
||||
// sys
|
||||
reg_clk_out_dest = 0xFFFFFFFF;
|
||||
reg_hkspi_disable = 0xFFFFFFFF;
|
||||
|
||||
// read ones that has been written
|
||||
if (reg_mprj_io_0 != 0x1FFF)
|
||||
reg_debug_1 =0x1;
|
||||
if (reg_mprj_io_1 != 0x1FFF)
|
||||
reg_debug_1 =0x2;
|
||||
if (reg_mprj_io_2 != 0x1FFF)
|
||||
reg_debug_1 =0x3;
|
||||
if (reg_mprj_io_3 != 0x1FFF)
|
||||
reg_debug_1 =0x4;
|
||||
if (reg_mprj_io_4 != 0x1FFF)
|
||||
reg_debug_1 =0x5;
|
||||
if (reg_mprj_io_5 != 0x1FFF)
|
||||
reg_debug_1 =0x6;
|
||||
if (reg_mprj_io_6 != 0x1FFF)
|
||||
reg_debug_1 =0x7;
|
||||
if (reg_mprj_io_7 != 0x1FFF)
|
||||
reg_debug_1 =0x8;
|
||||
if (reg_mprj_io_8 != 0x1FFF)
|
||||
reg_debug_1 =0x9;
|
||||
if (reg_mprj_io_9 != 0x1FFF)
|
||||
reg_debug_1 =0xa;
|
||||
if (reg_mprj_io_10 != 0x1FFF)
|
||||
reg_debug_1 =0xb;
|
||||
if (reg_mprj_io_11 != 0x1FFF)
|
||||
reg_debug_1 =0xc;
|
||||
if (reg_mprj_io_12 != 0x1FFF)
|
||||
reg_debug_1 =0xd;
|
||||
if (reg_mprj_io_13 != 0x1FFF)
|
||||
reg_debug_1 =0xe;
|
||||
if (reg_mprj_io_14 != 0x1FFF)
|
||||
reg_debug_1 =0xf;
|
||||
if (reg_mprj_io_15 != 0x1FFF)
|
||||
reg_debug_1 =0x10;
|
||||
if (reg_mprj_io_16 != 0x1FFF)
|
||||
reg_debug_1 =0x11;
|
||||
if (reg_mprj_io_17 != 0x1FFF)
|
||||
reg_debug_1 =0x12;
|
||||
if (reg_mprj_io_18 != 0x1FFF)
|
||||
reg_debug_1 =0x13;
|
||||
if (reg_mprj_io_19 != 0x1FFF)
|
||||
reg_debug_1 =0x14;
|
||||
if (reg_mprj_io_20 != 0x1FFF)
|
||||
reg_debug_1 =0x15;
|
||||
if (reg_mprj_io_21 != 0x1FFF)
|
||||
reg_debug_1 =0x16;
|
||||
if (reg_mprj_io_22 != 0x1FFF)
|
||||
reg_debug_1 =0x17;
|
||||
if (reg_mprj_io_23 != 0x1FFF)
|
||||
reg_debug_1 =0x18;
|
||||
if (reg_mprj_io_24 != 0x1FFF)
|
||||
reg_debug_1 =0x19;
|
||||
if (reg_mprj_io_25 != 0x1FFF)
|
||||
reg_debug_1 =0x1a;
|
||||
if (reg_mprj_io_26 != 0x1FFF)
|
||||
reg_debug_1 =0x1b;
|
||||
if (reg_mprj_io_27 != 0x1FFF)
|
||||
reg_debug_1 =0x1c;
|
||||
if (reg_mprj_io_28 != 0x1FFF)
|
||||
reg_debug_1 =0x1d;
|
||||
if (reg_mprj_io_29 != 0x1FFF)
|
||||
reg_debug_1 =0x1e;
|
||||
if (reg_mprj_io_30 != 0x1FFF)
|
||||
reg_debug_1 =0x1f;
|
||||
if (reg_mprj_io_31 != 0x1FFF)
|
||||
reg_debug_1 =0x20;
|
||||
if (reg_mprj_io_32 != 0x1FFF)
|
||||
reg_debug_1 =0x21;
|
||||
if (reg_mprj_io_33 != 0x1FFF)
|
||||
reg_debug_1 =0x22;
|
||||
if (reg_mprj_io_34 != 0x1FFF)
|
||||
reg_debug_1 =0x23;
|
||||
if (reg_mprj_io_35 != 0x1FFF)
|
||||
reg_debug_1 =0x24;
|
||||
if (reg_mprj_io_36 != 0x1FFF)
|
||||
reg_debug_1 =0x25;
|
||||
if (reg_mprj_io_37 != 0x1FFF)
|
||||
reg_debug_1 =0x26;
|
||||
// housekeeping
|
||||
if (reg_hkspi_status != old_reg_hkspi_status) // RO
|
||||
reg_debug_1 =0x27;
|
||||
if (reg_hkspi_chip_id != old_reg_hkspi_chip_id) // RO
|
||||
reg_debug_1 =0x28;
|
||||
if (reg_hkspi_user_id != old_reg_hkspi_user_id) // RO
|
||||
reg_debug_1 =0x29;
|
||||
if (reg_hkspi_pll_ena != 0x3) // size =2
|
||||
reg_debug_1 =0x2a;
|
||||
if (reg_hkspi_pll_bypass != 0x1) // size = 1
|
||||
reg_debug_1 = 0x2b;
|
||||
if (reg_hkspi_irq != old_reg_hkspi_irq) // RO
|
||||
reg_debug_1 = 0x2c;
|
||||
if (reg_hkspi_trap != old_reg_hkspi_trap) // RO
|
||||
reg_debug_1 =0x2d;
|
||||
if (reg_hkspi_pll_trim != 0x3FFFFFF) // size 26
|
||||
reg_debug_1 = 0x2f;
|
||||
if (reg_hkspi_pll_source != 0x3F) // size 6 bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
|
||||
reg_debug_1 =0x2f;
|
||||
if (reg_hkspi_pll_divider != 0x1F) // size 7 -> PLL output divider, PLL output divider2 , PLL feedback divider
|
||||
reg_debug_1 =0x30;
|
||||
if (reg_hkspi_disable != 0x1) // size 1
|
||||
reg_debug_1 =0x31;
|
||||
if (reg_clk_out_dest != 0x7) // trap and clocks redirect
|
||||
reg_debug_1 =0x32;
|
||||
// // write zeros to all registers
|
||||
reg_mprj_io_0 = 0x0;
|
||||
reg_mprj_io_1 = 0x0;
|
||||
reg_mprj_io_2 = 0x0;
|
||||
reg_mprj_io_3 = 0x0;
|
||||
reg_mprj_io_4 = 0x0;
|
||||
reg_mprj_io_5 = 0x0;
|
||||
reg_mprj_io_6 = 0x0;
|
||||
reg_mprj_io_7 = 0x0;
|
||||
reg_mprj_io_8 = 0x0;
|
||||
reg_mprj_io_9 = 0x0;
|
||||
reg_mprj_io_10 = 0x0;
|
||||
reg_mprj_io_11 = 0x0;
|
||||
reg_mprj_io_12 = 0x0;
|
||||
reg_mprj_io_13 = 0x0;
|
||||
reg_mprj_io_14 = 0x0;
|
||||
reg_mprj_io_15 = 0x0;
|
||||
reg_mprj_io_16 = 0x0;
|
||||
reg_mprj_io_17 = 0x0;
|
||||
reg_mprj_io_18 = 0x0;
|
||||
reg_mprj_io_19 = 0x0;
|
||||
reg_mprj_io_20 = 0x0;
|
||||
reg_mprj_io_21 = 0x0;
|
||||
reg_mprj_io_22 = 0x0;
|
||||
reg_mprj_io_23 = 0x0;
|
||||
reg_mprj_io_24 = 0x0;
|
||||
reg_mprj_io_25 = 0x0;
|
||||
reg_mprj_io_26 = 0x0;
|
||||
reg_mprj_io_27 = 0x0;
|
||||
reg_mprj_io_28 = 0x0;
|
||||
reg_mprj_io_29 = 0x0;
|
||||
reg_mprj_io_30 = 0x0;
|
||||
reg_mprj_io_31 = 0x0;
|
||||
reg_mprj_io_32 = 0x0;
|
||||
reg_mprj_io_33 = 0x0;
|
||||
reg_mprj_io_34 = 0x0;
|
||||
reg_mprj_io_35 = 0x0;
|
||||
reg_mprj_io_36 = 0x0;
|
||||
reg_mprj_io_37 = 0x0;
|
||||
// house keeping
|
||||
reg_hkspi_status = 0x0;
|
||||
reg_hkspi_chip_id = 0x0;
|
||||
reg_hkspi_user_id = 0x0;
|
||||
reg_hkspi_pll_ena = 0x0;
|
||||
reg_hkspi_pll_bypass = 0x0;
|
||||
reg_hkspi_irq = 0x0;
|
||||
reg_hkspi_reset = 0x0;
|
||||
reg_hkspi_trap = 0x0;
|
||||
reg_hkspi_pll_trim = 0x0;
|
||||
reg_hkspi_pll_source = 0x0;
|
||||
reg_hkspi_pll_divider = 0x0;
|
||||
// sys
|
||||
reg_clk_out_dest = 0x0;
|
||||
reg_hkspi_disable = 0x0;
|
||||
|
||||
// // read zeros that has been written
|
||||
if (reg_mprj_io_0 != 0x0)
|
||||
reg_debug_2 =0x1;
|
||||
if (reg_mprj_io_1 != 0x0)
|
||||
reg_debug_2 =0x2;
|
||||
if (reg_mprj_io_2 != 0x0)
|
||||
reg_debug_2 =0x3;
|
||||
if (reg_mprj_io_3 != 0x0)
|
||||
reg_debug_2 =0x4;
|
||||
if (reg_mprj_io_4 != 0x0)
|
||||
reg_debug_2 =0x5;
|
||||
if (reg_mprj_io_5 != 0x0)
|
||||
reg_debug_2 =0x6;
|
||||
if (reg_mprj_io_6 != 0x0)
|
||||
reg_debug_2 =0x7;
|
||||
if (reg_mprj_io_7 != 0x0)
|
||||
reg_debug_2 =0x8;
|
||||
if (reg_mprj_io_8 != 0x0)
|
||||
reg_debug_2 =0x9;
|
||||
if (reg_mprj_io_9 != 0x0)
|
||||
reg_debug_2 =0xa;
|
||||
if (reg_mprj_io_10 != 0x0)
|
||||
reg_debug_2 =0xb;
|
||||
if (reg_mprj_io_11 != 0x0)
|
||||
reg_debug_2 =0xc;
|
||||
if (reg_mprj_io_12 != 0x0)
|
||||
reg_debug_2 =0xd;
|
||||
if (reg_mprj_io_13 != 0x0)
|
||||
reg_debug_2 =0xe;
|
||||
if (reg_mprj_io_14 != 0x0)
|
||||
reg_debug_2 =0xf;
|
||||
if (reg_mprj_io_15 != 0x0)
|
||||
reg_debug_2 =0x10;
|
||||
if (reg_mprj_io_16 != 0x0)
|
||||
reg_debug_2 =0x11;
|
||||
if (reg_mprj_io_17 != 0x0)
|
||||
reg_debug_2 =0x12;
|
||||
if (reg_mprj_io_18 != 0x0)
|
||||
reg_debug_2 =0x13;
|
||||
if (reg_mprj_io_19 != 0x0)
|
||||
reg_debug_2 =0x14;
|
||||
if (reg_mprj_io_20 != 0x0)
|
||||
reg_debug_2 =0x15;
|
||||
if (reg_mprj_io_21 != 0x0)
|
||||
reg_debug_2 =0x16;
|
||||
if (reg_mprj_io_22 != 0x0)
|
||||
reg_debug_2 =0x17;
|
||||
if (reg_mprj_io_23 != 0x0)
|
||||
reg_debug_2 =0x18;
|
||||
if (reg_mprj_io_24 != 0x0)
|
||||
reg_debug_2 =0x19;
|
||||
if (reg_mprj_io_25 != 0x0)
|
||||
reg_debug_2 =0x1a;
|
||||
if (reg_mprj_io_26 != 0x0)
|
||||
reg_debug_2 =0x1b;
|
||||
if (reg_mprj_io_27 != 0x0)
|
||||
reg_debug_2 =0x1c;
|
||||
if (reg_mprj_io_28 != 0x0)
|
||||
reg_debug_2 =0x1d;
|
||||
if (reg_mprj_io_29 != 0x0)
|
||||
reg_debug_2 =0x1e;
|
||||
if (reg_mprj_io_30 != 0x0)
|
||||
reg_debug_2 =0x1f;
|
||||
if (reg_mprj_io_31 != 0x0)
|
||||
reg_debug_2 =0x20;
|
||||
if (reg_mprj_io_32 != 0x0)
|
||||
reg_debug_2 =0x21;
|
||||
if (reg_mprj_io_33 != 0x0)
|
||||
reg_debug_2 =0x22;
|
||||
if (reg_mprj_io_34 != 0x0)
|
||||
reg_debug_2 =0x23;
|
||||
if (reg_mprj_io_35 != 0x0)
|
||||
reg_debug_2 =0x24;
|
||||
if (reg_mprj_io_36 != 0x0)
|
||||
reg_debug_2 =0x25;
|
||||
if (reg_mprj_io_37 != 0x0)
|
||||
reg_debug_2 =0x26;
|
||||
// housekeeping
|
||||
if (reg_hkspi_status != old_reg_hkspi_status) // RO
|
||||
reg_debug_2 =0x27;
|
||||
if (reg_hkspi_chip_id != old_reg_hkspi_chip_id) // RO
|
||||
reg_debug_2 =0x28;
|
||||
if (reg_hkspi_user_id != old_reg_hkspi_user_id) // RO
|
||||
reg_debug_2 =0x29;
|
||||
if (reg_hkspi_pll_ena != 0x0) // size =2
|
||||
reg_debug_2 =0x2a;
|
||||
if (reg_hkspi_pll_bypass != 0x0) // size = 1
|
||||
reg_debug_2 = 0x2b;
|
||||
if (reg_hkspi_irq != old_reg_hkspi_irq) // RO
|
||||
reg_debug_2 = 0x2c;
|
||||
if (reg_hkspi_trap != old_reg_hkspi_trap) // RO
|
||||
reg_debug_2 =0x2d;
|
||||
if (reg_hkspi_pll_trim != 0x0) // size 26
|
||||
reg_debug_2 = 0x2f;
|
||||
if (reg_hkspi_pll_source != 0x0) // size 6 bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
|
||||
reg_debug_2 =0x2f;
|
||||
if (reg_hkspi_pll_divider != 0x0) // size 7 -> PLL output divider, PLL output divider2 , PLL feedback divider
|
||||
reg_debug_2 =0x30;
|
||||
if (reg_hkspi_disable != 0x0) // size 1
|
||||
reg_debug_2 =0x31;
|
||||
if (reg_clk_out_dest != 0x0) // trap and clocks redirect
|
||||
reg_debug_2 =0x32;
|
||||
|
||||
reg_debug_2 = 0xFF;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
from json.encoder import INFINITY
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.bitbang.bitbang_functions import *
|
||||
from interfaces.caravel import GPIO_MODE
|
||||
from tests.housekeeping.housekeeping_spi.spi_access_functions import *
|
||||
import json
|
||||
reg = Regs()
|
||||
|
||||
|
||||
'''randomly write then read housekeeping regs through wishbone'''
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def hk_regs_wr_wb(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=700,num_error=INFINITY)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
with open('wb_models/housekeepingWB/HK_regs.json') as f:
|
||||
regs = json.load(f)
|
||||
await ClockCycles(caravelEnv.clk, 10)
|
||||
# write then read
|
||||
for i in range(random.randint(7, 20)):
|
||||
bits_num = 32
|
||||
mem = random.choice(['GPIO']) # can't access 'SPI' and 'sys' register from interfaces.cpu / read or write
|
||||
key = random.choice(list(regs[mem].keys()))
|
||||
if key == 'base_addr':
|
||||
continue
|
||||
key_num = int(key,16) & 0xFC
|
||||
key = generate_key_from_num(key_num)
|
||||
address = (int(key,16) + regs[mem]['base_addr'][1])
|
||||
if address in [0x26000010,0x2600000c]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
|
||||
continue
|
||||
data_in = random.getrandbits(bits_num)
|
||||
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to {regs[mem][key][0][0]} address {hex(address)} through wishbone")
|
||||
await cpu.drive_data2address(address,data_in)
|
||||
#calculate the expected value for each bit
|
||||
data_exp = ''
|
||||
keys = [generate_key_from_num(key_num+3),generate_key_from_num(key_num+2),generate_key_from_num(key_num+1),generate_key_from_num(key_num)]
|
||||
for count , k in enumerate(keys):
|
||||
for i in range(int(bits_num/len(keys)) * (count),int(bits_num/len(keys)) * (count+1)):
|
||||
bit_exist = False
|
||||
if k in regs[mem].keys():
|
||||
for field in regs[mem][k]:
|
||||
field_shift = field[2]
|
||||
field_size = field[3]
|
||||
field_access = field[4]
|
||||
i_temp = (bits_num -1 -i) % (bits_num/4)
|
||||
if field_shift <= i_temp and i_temp <= (field_shift + field_size-1):
|
||||
if field_access == "RW":
|
||||
data_exp += bin(data_in)[2:].zfill(bits_num)[i]
|
||||
bit_exist = True
|
||||
break
|
||||
if not bit_exist:
|
||||
data_exp += '0'
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
|
||||
cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")
|
||||
data_out = await cpu.read_address(address)
|
||||
cocotb.log.info(f"[TEST] Read {bin(data_out)} from {regs[mem][key][0][0]} address {hex(address)} through wishbone")
|
||||
if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from {regs[mem][key][0][0]} address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
|
||||
else: cocotb.log.info(f"[TEST] read the right value {hex(data_out)} from {regs[mem][key][0][0]} address {hex(address)} ")
|
||||
|
||||
'''randomly write then read housekeeping regs through wishbone'''
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def hk_regs_wr_wb_cpu(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=198243,num_error=INFINITY)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
reg1 =0 # buffer
|
||||
reg2 =0
|
||||
regs_list = ("reg_hkspi_status","reg_hkspi_chip_id","reg_hkspi_user_id", "reg_hkspi_pll_ena","reg_hkspi_pll_bypass","reg_hkspi_irq","reg_hkspi_trap","reg_hkspi_pll_trim","reg_hkspi_pll_source","reg_hkspi_pll_divide","reg_clk_out_des","reg_hkspi_disable")
|
||||
while True:
|
||||
if cpu.read_debug_reg2() == 0xFF: # test finish
|
||||
break
|
||||
if reg1 != cpu.read_debug_reg1():
|
||||
reg1 = cpu.read_debug_reg1()
|
||||
if reg1 < 38:
|
||||
cocotb.log.error(f"[TEST] error while writing 0xFFFFFFFF to reg_mprj_io_{reg1-1}")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] error while writing 0xFFFFFFFF to {regs_list[reg1-39]}")
|
||||
if reg2 != cpu.read_debug_reg2():
|
||||
reg2 = cpu.read_debug_reg2()
|
||||
if reg1 < 38:
|
||||
cocotb.log.error(f"[TEST] error while writing 0x0 to reg_mprj_io_{reg2-1}")
|
||||
else:
|
||||
cocotb.log.error(f"[TEST] error while writing 0x0 to {regs_list[reg1-39]}")
|
||||
await ClockCycles(caravelEnv.clk,1)
|
||||
|
||||
'''randomly write then read housekeeping regs through SPI'''
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def hk_regs_wr_spi(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
|
||||
|
||||
with open('wb_models/housekeepingWB/HK_regs.json') as f:
|
||||
regs = json.load(f)
|
||||
# write then read single byte
|
||||
for i in range(random.randint(10, 40)):
|
||||
bits_num = 8 # byte testing
|
||||
mem = random.choice(['GPIO','SPI','sys'])
|
||||
key = random.choice(list(regs[mem].keys()))
|
||||
if key == 'base_addr':
|
||||
continue
|
||||
address = regs[mem][key][0][7]
|
||||
if address in [111,36]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled
|
||||
continue
|
||||
# address = int(key,16)
|
||||
if address in [0x69,0x6A,0x6B,0x6C]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
|
||||
continue
|
||||
data_in = random.getrandbits(bits_num)
|
||||
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
|
||||
await write_reg_spi(caravelEnv,address=address,data=data_in)
|
||||
#calculate the expected value for each bit
|
||||
is_unknown = False
|
||||
data_exp = ''
|
||||
for i in range(bits_num):
|
||||
bit_exist = False
|
||||
for field in regs[mem][key]:
|
||||
field_shift = field[2]
|
||||
field_size = field[3]
|
||||
field_access = field[4]
|
||||
reset_val = field[5]
|
||||
i_temp = bits_num -1 -i
|
||||
if field_shift <= i_temp and i_temp <= (field_shift + field_size-1):
|
||||
if field_access == "RW":
|
||||
data_exp += bin(data_in)[2:].zfill(bits_num)[i]
|
||||
bit_exist = True
|
||||
break
|
||||
else : # read only get the value from reset
|
||||
data_exp += bin(reset_val)[2:].zfill(bits_num)[i]
|
||||
bit_exist = True
|
||||
break
|
||||
if field_access == "NA": # that mean the value is unknown as the register value can change by hardware mostly the reg value is input to the housekeeping from other blocks
|
||||
is_unknown = True
|
||||
break
|
||||
if not bit_exist:
|
||||
data_exp += '0'
|
||||
if is_unknown:# that mean the value is unknown as the register value can change by hardware mostly the reg value is input to the housekeeping from other blocks
|
||||
continue
|
||||
|
||||
await ClockCycles(caravelEnv.clk,10)
|
||||
cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")
|
||||
data_out = await read_reg_spi(caravelEnv,address=address)
|
||||
cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
|
||||
if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from [{regs[mem][key][0][0]}] address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
|
||||
else: cocotb.log.info(f"[TEST] read the right value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ")
|
||||
|
||||
'''check reset value of house keeping register'''
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def hk_regs_rst_spi(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
|
||||
|
||||
with open('wb_models/housekeepingWB/HK_regs.json') as f:
|
||||
regs = json.load(f)
|
||||
# read
|
||||
bits_num = 8 # byte testing
|
||||
mems = ['GPIO','SPI','sys']
|
||||
|
||||
for mem in mems:
|
||||
keys = [k for k in regs[mem].keys()]
|
||||
for key in keys:
|
||||
if key == 'base_addr':
|
||||
continue
|
||||
address = regs[mem][key][0][7]
|
||||
if address in [0x69,0x6A,0x6B,0x6C,0x6D,0x1A]: # skip testing reg_mprj_datal, reg_mprj_datah and usr2_vdd_pwrgood because when reading them it's getting the gpio input value
|
||||
continue
|
||||
#calculate the expected value for each bit for reset value
|
||||
data_exp = ''
|
||||
# for i in range(bits_num):
|
||||
bit_exist = False
|
||||
for field in regs[mem][key]:
|
||||
field_shift = field[2]
|
||||
field_size = field[3]
|
||||
field_access = field[4]
|
||||
reset_val = field[5]
|
||||
i_temp = bits_num -1 #-i
|
||||
# if field_shift <= i_temp and i_temp <= (field_shift + field_size-1):
|
||||
data_exp = bin(reset_val)[2:].zfill(field_size) + data_exp
|
||||
print (f'reset = {bin(reset_val)[2:].zfill(bits_num)} data exp = {data_exp} i temp = {i_temp} shift {field_shift} size {field_size}')
|
||||
# bit_exist = True
|
||||
# break
|
||||
# if not bit_exist:
|
||||
# data_exp += '0'
|
||||
|
||||
cocotb.log.info(f"[TEST] expected reset value for [{regs[mem][key][0][0]}] is {data_exp}")
|
||||
data_out = await read_reg_spi(caravelEnv,address=address)
|
||||
cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through wishbone")
|
||||
if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong reset value read from [{regs[mem][key][0][0]}] address {address} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
|
||||
else: cocotb.log.info(f"[TEST] read the right reset value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ")
|
||||
|
||||
|
||||
|
||||
|
||||
def generate_key_from_num(num):
|
||||
hex_string = hex(num)
|
||||
hex_list = [i for i in hex_string]
|
||||
if len(hex_list)==3:
|
||||
hex_list.insert(2,'0')
|
||||
hex_string = "".join(hex_list)
|
||||
return hex_string
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
|
||||
|
||||
async def write_reg_spi(caravelEnv,address,data):
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x80) # Write stream command
|
||||
await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
|
||||
await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
|
||||
async def read_reg_spi(caravelEnv,address):
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0x40) # read stream command
|
||||
await caravelEnv.hk_write_byte(address) # Address
|
||||
data = await caravelEnv.hk_read_byte() # Data = 0x01 (enable bit-bang mode)
|
||||
await caravelEnv.disable_csb()
|
||||
return data
|
||||
|
||||
|
||||
async def reg_spi_user_pass_thru(caravelEnv,command,address):
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(0xc2) # Apply user pass-thru command to housekeeping SPI
|
||||
await caravelEnv.hk_write_byte(command) # read command
|
||||
address = address.to_bytes(3,'big')
|
||||
await caravelEnv.hk_write_byte(address[0]) # high byte
|
||||
await caravelEnv.hk_write_byte(address[1]) # middle byte
|
||||
await caravelEnv.hk_write_byte(address[2]) # low byte
|
||||
|
||||
async def reg_spi_user_pass_thru_read(caravelEnv):
|
||||
data = await caravelEnv.hk_read_byte()
|
||||
return data
|
||||
|
||||
# use for configure in mgmt pass thru or user pass thru
|
||||
async def reg_spi_op(caravelEnv,command,address):
|
||||
await caravelEnv.enable_csb()
|
||||
await caravelEnv.hk_write_byte(command) # command
|
||||
await caravelEnv.hk_write_byte(address) # Address
|
||||
await caravelEnv.disable_csb()
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
@00000000
|
||||
6F 00 00 0B 93 01 00 00 13 02 63 57 b5 00 23 20
|
||||
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00
|
||||
|
|
@ -0,0 +1,51 @@
|
|||
from email.headerregistry import Address
|
||||
import random
|
||||
import cocotb
|
||||
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
|
||||
import cocotb.log
|
||||
from interfaces.cpu import RiskV
|
||||
from interfaces.defsParser import Regs
|
||||
from cocotb.result import TestSuccess
|
||||
from tests.common_functions.test_functions import *
|
||||
from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP
|
||||
from tests.housekeeping.housekeeping_spi.spi_access_functions import *
|
||||
|
||||
|
||||
bit_time_ns = 0
|
||||
reg = Regs()
|
||||
|
||||
|
||||
@cocotb.test()
|
||||
@repot_test
|
||||
async def user_pass_thru_rd(dut):
|
||||
caravelEnv,clock = await test_configure(dut,timeout_cycles=14833)
|
||||
cpu = RiskV(dut)
|
||||
cpu.cpu_force_reset()
|
||||
cpu.cpu_release_reset()
|
||||
cocotb.log.info (f"[TEST] start spi_master_rd test")
|
||||
file_name = f"{os.getenv('CARAVEL_VERILOG_PATH')}/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data"
|
||||
mem = read_mem(file_name)
|
||||
await cocotb.start(SPI_VIP(dut.bin8_monitor,dut.bin9_monitor,dut.bin10_monitor,(dut.bin11_en,dut.bin11),mem)) # fork for SPI
|
||||
await wait_reg1(cpu,caravelEnv,0XAA)
|
||||
cocotb.log.info (f"[TEST] Configuration finished")
|
||||
#The SPI flash may need to be reset
|
||||
# 0xff and 0xAB commands are suppose to have functionality in the future but for now they would do nothing
|
||||
await write_reg_spi(caravelEnv,0xc2,0xff) # 0xc2 is for appling user pass-thru command to housekeeping SPI
|
||||
await write_reg_spi(caravelEnv,0xc2,0xab) # 0xc2 is for appling user pass-thru command to housekeeping SPI
|
||||
|
||||
# start reading from memory
|
||||
address = 0x0
|
||||
await reg_spi_user_pass_thru(caravelEnv,command = 0x3,address=address) # read command
|
||||
for i in range(8):
|
||||
val = await reg_spi_user_pass_thru_read(caravelEnv)
|
||||
if val != mem[address]:
|
||||
cocotb.log.error(f"[TEST] reading incorrect value from address {hex(address)} expected = {hex(mem[address])} returened = {val}")
|
||||
else:
|
||||
cocotb.log.info(f"[TEST] reading correct value {hex(val)} from address {hex(address)} ")
|
||||
address +=1
|
||||
|
||||
await caravelEnv.disable_csb()
|
||||
|
||||
# Wait for processor to restart
|
||||
await wait_reg1(cpu,caravelEnv,0xBB)
|
||||
cocotb.log.info(f"[TEST] processor has restarted successfully")
|
||||
|
|
@ -0,0 +1,62 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <defs.h>
|
||||
#include <stub.c>
|
||||
|
||||
|
||||
|
||||
void main()
|
||||
{
|
||||
// This program is just to keep the processor busy while the
|
||||
// housekeeping SPI is being accessed. to show that the
|
||||
// processor is halted while the SPI is accessing the
|
||||
// flash SPI in pass-through mode.
|
||||
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
// Management needs to apply output on these pads to access the user area SPI flash
|
||||
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI
|
||||
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; // SDO
|
||||
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; // clk
|
||||
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; // csb
|
||||
|
||||
|
||||
// Apply configuration
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
|
||||
// Start test
|
||||
reg_debug_1 = 0xAA;
|
||||
reg_debug_1 = 0xBB;
|
||||
reg_uart_enable = 1;
|
||||
|
||||
// Test in progress
|
||||
reg_mprj_datal = 0xa5000000;
|
||||
|
||||
// Test message
|
||||
// print("Test message\n");
|
||||
print("ABC\n");
|
||||
|
||||
for (int i=0; i<1200; i++);
|
||||
|
||||
// End test
|
||||
reg_debug_1 = 0xFF;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <csr.h>
|
||||
#include <soc.h>
|
||||
#include <irq_vex.h>
|
||||
#include <uart.h>
|
||||
|
||||
#include <defs.h>
|
||||
|
||||
/*
|
||||
Testing timer interrupts
|
||||
Enable interrupt for IRQ external pin mprj_io[7] -> should be drived to 1 by the environment
|
||||
**NOTE** housekeeping SPI should used to update register irq_1_inputsrc to 1 see verilog code
|
||||
|
||||
@wait for environment to make mprj[7] high
|
||||
send packet size = 1
|
||||
|
||||
@received interrupt correctly test pass
|
||||
send packet size = 5
|
||||
|
||||
@ timeout test fail
|
||||
send packet size = 9
|
||||
|
||||
@ end test
|
||||
send packet size = 3
|
||||
send packet size = 3
|
||||
send packet size = 3
|
||||
|
||||
*/
|
||||
|
||||
extern uint16_t flag;
|
||||
|
||||
void main(){
|
||||
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
|
||||
reg_debug_1 = 0x0;
|
||||
reg_debug_2 = 0x0;
|
||||
|
||||
// setting bit 7 as input
|
||||
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
|
||||
|
||||
// automatic bitbang approach
|
||||
if(1){
|
||||
reg_mprj_xfer = 1;
|
||||
while (reg_mprj_xfer == 1);
|
||||
}
|
||||
irq_setmask(0);
|
||||
irq_setie(1);
|
||||
irq_setmask(irq_getmask() | (1 << USER_IRQ_4_INTERRUPT));
|
||||
reg_user4_irq_en =1;
|
||||
|
||||
// test interrrupt happen when mprj[7] is asserted
|
||||
reg_debug_2 = 0xAA; //wait for environment to make mprj[7] high
|
||||
flag = 0;
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
bool is_pass = false;
|
||||
int timeout = 40;
|
||||
|
||||
for (int i = 0; i < timeout; i++){
|
||||
if (flag == 1){
|
||||
reg_debug_1 = 0x1B; //test pass irq sent at mprj 7
|
||||
is_pass = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!is_pass){
|
||||
reg_debug_1 = 0x1E; // timeout
|
||||
}
|
||||
|
||||
// test interrupt doesn't happened when mprj[7] is deasserted
|
||||
reg_debug_2 = 0xBB;
|
||||
flag = 0;
|
||||
// Loop, waiting for the interrupt to change reg_mprj_datah
|
||||
is_pass = false;
|
||||
|
||||
for (int i = 0; i < timeout; i++){
|
||||
if (flag == 1){
|
||||
reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened
|
||||
is_pass = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (!is_pass){
|
||||
reg_debug_1 = 0x2B; // test pass
|
||||
}
|
||||
|
||||
// test finish
|
||||
reg_debug_2 = 0xFF;
|
||||
}
|
||||
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Reference in New Issue