riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #139 from efabless/cocotb 

new environment for simulation automation with cocotb and vcs
This commit is contained in:
Mohamed Shalan 2022-10-11 10:41:22 +02:00 committed by GitHub
parent 4f1ee965a9 11ce4a30eb
commit fe3d2b927f
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
101 changed files with 10989 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
manifest
View File

@ -1,7 +1,9 @@
535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
1315c3df4decc1a015ec78dfb7df174eb3a74e9a verilog/rtl/__user_project_gpio_example.v
5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v
ef356bbc8938fef0c1866a709a3bf846d8c7e1e4 verilog/rtl/__user_project_wrapper.v
f93c57988b0044d2bff4470a84b5eddc158f2094 verilog/rtl/caravan.v
1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
@ -13,12 +15,13 @@ d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
97c958944dd74a87f75d9fe2309837e567468722 verilog/rtl/chip_io_alt.v
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
653b230c7cbf092a6210ba7820bc942f312e53f3 verilog/rtl/debug_regs.v
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
00d2c61e4f424dfce3635f96a1c1bfdeaf7d0cf8 verilog/rtl/gpio_control_block.v
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
9b602cb0e7f0e6b7e21d87d3a2bd30cb631302c4 verilog/rtl/housekeeping.v
4290fcaf6bbcff701c2c47c7a23ce4fd4698e888 verilog/rtl/housekeeping.v
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v

11
verilog/dv/cocotb/.gitignore vendored Normal file
View File

@ -0,0 +1,11 @@
*.log
sim_build
sim
__pycache__
*.
./wb_models/housekeepingWB/__pycache__
*.xml
*.yml
*.hex*
*.elf
AN.DB

79
verilog/dv/cocotb/Makefile Normal file
View File

@ -0,0 +1,79 @@
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
PWDD := $(shell pwd)
BLOCKS := $(shell basename $(PWDD))
# ---- Include Partitioned Makefiles ----
CONFIG = caravel_user_project
# TestName = temp_partial
# export COCOTB_ANSI_OUTPUT=0 # disable color in termianl
export GUI=1
export COCOTB_REDUCED_LOG_FMT=1
# Change this line if you want to use existing cocotb test modules:
# export PYTHONPATH := $(DESIGNS)/verilog/rtl/<your design python tests>
# export LIBPYTHON_LOC=$(cocotb-config --libpython)
#export VERILOG_PATH = ../../../
#export CARAVEL_PATH = ../../../../../caravel/verilog/
# include $(MCW_ROOT)/verilog/dv/make/env.makefile
# #export VERILOG_PATH = ../../../
# include $(MCW_ROOT)/verilog/dv/make/var.makefile
# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
# include $(MCW_ROOT)/verilog/dv/make/sim.makefile
TESTCASE=$(TestName)
MODULE=caravel_tests
$(info $$MODULE is [$(MODULE)])
cocotb:
rm -rf sim_build/
mkdir sim_build/
# change project_tb.v to match your testbench
#RTL
iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
-DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
-o sim_build/sim.vvp $(CARAVEL_PATH)/rtl/__user_project_wrapper.v $(CARAVEL_PATH)/rtl/debug_regs.v caravel_top.sv
#GL
# iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
# -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
# -f$(VERILOG_PATH)/includes/includes.gl.caravel \
# -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv
#CVC
# TESTCASE=$(TestName) MODULE=caravel_tests cvc64 +interp +acc+2 \
# +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap\
# +change_port_type +maxerrors 1\
# +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY=#0 \
# +define+TESTNAME=\"$(TestName)\" +define+RUNTAG=\"$(RUNTAG)\" +define+COCOTB_SIM=1\
# -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
# -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) -o sim_build/sim.vvp
# verilator --vpi --public-flat-rw --prefix Vtop \
# -LDFLAGS "-Wl,-rpath,$(cocotb-config --prefix)/cocotb/libs \
# -L$(cocotb-config --prefix)/cocotb/libs \
# -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils" \
# $(cocotb-config --share)/lib/verilator/verilator.cpp\
# -y $(VERILOG_PATH)/includes/includes.rtl.caravel \
# -y $(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) --cc -o sim_build/sim.vvp caravel_top.sv
# change this line to choose the comma separated test cases and the name of your python test module
TESTCASE=$(TestName) MODULE=caravel_tests vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
! grep failure results.xml

92
verilog/dv/cocotb/README.md Normal file
View File

@ -0,0 +1,92 @@
Overview
========
Cocotb environment (CTN) is a dynamic simulation testing environment. It's purpose is to speed testing simulation time and get coverage data. The environment is developed using cocotb, an open source coroutine-based co simulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. CTN has 2 main layers: tests and whitebox models. Tests layer contain multiple tests and sequences that can communicate with the caravel (dut) through drivers shown in read at fig 1. Whitebox models layer contain multiple models that should mimic the behavior of each main block inside caravel see fig1. Model is supposed to check if the model is working as expected, if its registers contain the expected values all the time and report coverage of features provided by this block if it’s tested or not.
<img src="doc/CTN.png" alt="Alt text" title="fig1. caravel testbench environment (read lines are drivers )">
fig1. caravel testbench environment (read lines are drivers )
Prerequisites
=============================
- Docker: [Linux](https://hub.docker.com/search?q=&type=edition&offering=community&operating_system=linux&utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Windows](https://desktop.docker.com/win/main/amd64/Docker%20Desktop%20Installer.exe?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with Intel Chip](https://desktop.docker.com/mac/main/amd64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with M1 Chip](https://desktop.docker.com/mac/main/arm64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header)
- Python 3.6+ with PIP
- cocotb
```
apt update && apt install python3 python3-pip
pip3 install cocotb
pip3 install cocotb_coverage
pip3 install coverage
pip3 install cocotb-bus
```
- iverilog or vcs
run a test
=============================
Use script verify_cocotb.py
```
-h, --help show this help message and exit
-regression REGRESSION, -r REGRESSION
name of regression can found in tests.json
-test TEST [TEST ...], -t TEST [TEST ...]
name of test if no --sim provided RTL will be run
<takes list as input>
-sim SIM [SIM ...] Simulation type to be run RTL,GL&GL_SDF provided only
when run -test <takes list as input>
-testlist TESTLIST, -tl TESTLIST
path of testlist to be run
-tag TAG provide tag of the run default would be regression
name and if no regression is provided would be
run_<random float>_<timestamp>_
-maxerr MAXERR max number of errors for every test before simulation
breaks default = 3
-vcs, -v use vcs as compiler if not used iverilog would be used
-cov, -c enable code coverage
```
Tests
===============
Refer to [tests.json](tests.json) for tests list
Directories names fixed for now
===============
>repo
>>caravel_mgmt_soc_litex/
>>caravel
>>>verilog
>>>>dv
>>>>cocotb
cocotb directory tree
===============
```
├── caravel.py -> contains driving and mentoring functions for caravel interface
├── caravel_top.sv -> testbench top level
├── cpu.py -> contains driving and mentoring functions for wishbone when disable the cpu
├── hex_files -> folder that contains hex files
├── verify_cocotb.py -> script that run tests and regressions
├── sim -> directory get generate when run a test
│   └── <tag> -> tag of the run
│   ├── <sim type>-<test name> -> test result directory contain all logs and wave related to the test
│   ├── command.log -> command use for this run
│   └── runs.log -> contains status of the run fails and passes tests
├── tests -> directory contains all the tests
├── tests.json -> test list have all the tests, regressions and contain small description about every test
└── wb_models -> contains checkers and models for some caravel blocks
```

432
verilog/dv/cocotb/caravel.py Normal file
View File

@ -0,0 +1,432 @@
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
import cocotb.simulator
from cocotb.handle import SimHandleBase
from cocotb.handle import Force
from cocotb_coverage.coverage import *
from cocotb.binary import BinaryValue
import enum
from cocotb.handle import (
ConstantObject,
HierarchyArrayObject,
HierarchyObject,
ModifiableObject,
NonHierarchyIndexableObject,
SimHandle,
)
from itertools import groupby, product
import interfaces.common as common
from common import GPIO_MODE
from common import MASK_GPIO_CTRL
from common import Macros
def gpio_mode(gpios_values:list):
gpios=[]
for array in gpios_values:
gpio_value = GPIO_MODE(array[1]).name
for gpio in array[0]:
gpios.append((gpio,gpio_value))
cocotb.log.info(f'[caravel][gpio_mode] gpios {gpios}')
return gpios
Carvel_Coverage = coverage_section (
CoverPoint("top.caravel.gpio", vname="gpios mode", xf = lambda gpio ,gpio_mode: (gpio,gpio_mode) ,
bins = list(product(range(38),[e.name for e in GPIO_MODE])))
)
class Caravel_env:
def __init__(self,dut:SimHandleBase):
self.dut = dut
self.clk = dut.clock_tb
self.caravel_hdl = dut.uut
self.hk_hdl = dut.uut.housekeeping
"""start carvel by insert power then reset"""
async def start_up(self):
await self.power_up()
# await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup
await self.reset()
await self.disable_bins()
common.fill_macros(self.dut.macros) # get macros value
async def disable_bins(self):
for i in range(38):
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
"""setup the vdd and vcc power bins"""
async def power_up(self):
cocotb.log.info(f' [caravel] start powering up')
self.set_vdd(0)
self.set_vcc(0)
await ClockCycles(self.clk, 10)
cocotb.log.info(f' [caravel] power up -> connect vdd' )
self.set_vdd(1)
# await ClockCycles(self.clk, 10)
cocotb.log.info(f' [caravel] power up -> connect vcc' )
self.set_vcc(1)
await ClockCycles(self.clk, 10)
""""reset caravel"""
async def reset(self):
cocotb.log.info(f' [caravel] start resetting')
self.dut.resetb_tb.value = 0
await ClockCycles(self.clk, 20)
self.dut.resetb_tb.value = 1
await ClockCycles(self.clk, 1)
cocotb.log.info(f' [caravel] finish resetting')
def set_vdd(self,value:bool):
self.dut.vddio_tb.value = value
self.dut.vssio_tb.value = 0
self.dut.vddio_2_tb.value = value
self.dut.vssio_2_tb.value = 0
self.dut.vdda_tb.value = value
self.dut.vssa_tb.value = 0
self.dut.vdda1_tb.value = value
self.dut.vssa1_tb.value = 0
self.dut.vdda1_2_tb.value = value
self.dut.vssa1_2_tb.value = 0
self.dut.vdda2_tb.value = value
self.dut.vssa2_tb.value = 0
def set_vcc(self , value:bool):
self.dut.vccd_tb.value = value
self.dut.vssd_tb.value = 0
self.dut.vccd1_tb.value = value
self.dut.vssd1_tb.value = 0
self.dut.vccd2_tb.value = value
self.dut.vssd2_tb.value = 0
"""drive csb signal bin E8 mprj[3]"""
async def drive_csb(self,bit):
self.drive_gpio_in((3,3),bit)
self.drive_gpio_in((2,2),0)
await ClockCycles(self.clk, 1)
"""set the spi vsb signal high to disable housekeeping spi transmission bin E8 mprj[3]"""
async def disable_csb(self ):
cocotb.log.info(f' [caravel] disable housekeeping spi transmission')
await self.drive_csb(1)
"""set the spi vsb signal high impedance """
async def release_csb(self ):
cocotb.log.info(f' [caravel] release housekeeping spi transmission')
self.release_gpio(3)
self.release_gpio(2)
await ClockCycles(self.clk, 1)
"""set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]"""
async def enable_csb(self ):
cocotb.log.info(f' [caravel] enable housekeeping spi transmission')
await self.drive_csb(0)
"""return the value of mprj in bits used tp monitor the output gpios value"""
def monitor_gpio(self,bits:tuple):
mprj = self.dut.mprj_io_tb.value
size =mprj.n_bits -1 #size of bins array
mprj_out= self.dut.mprj_io_tb.value[size - bits[0]:size - bits[1]]
if(mprj_out.is_resolvable):
cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {hex(mprj_out)}')
else:
cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {mprj_out}')
return mprj_out
"""return the value of management gpio"""
def monitor_mgmt_gpio(self):
data = self.dut.gpio_tb.value
cocotb.log.debug(f' [caravel] Monitor mgmt gpio = {data}')
return data
"""change the configration of the gpios by overwrite their defaults value then reset
need to take at least 1 cycle for reset """
### dont use back door accessing
async def configure_gpio_defaults(self,gpios_values: list):
gpio_defaults = self.caravel_hdl.gpio_defaults.value
cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
for array in gpios_values:
gpio_value = array[1]
for gpio in array[0]:
self.cov_configure_gpios(gpio,gpio_value.name)
gpio_defaults[size - (gpio*13 + 12): size -gpio*13] = gpio_value.value
#cocotb.log.info(f' [caravel] gpio_defaults[{size - (gpio*13 + 12)}:{size -gpio*13}] = {gpio_value.value} ')
self.caravel_hdl.gpio_defaults.value = gpio_defaults
#reset
self.caravel_hdl.gpio_resetn_1_shifted.value = 0
self.caravel_hdl.gpio_resetn_2_shifted.value = 0
await ClockCycles(self.clk, 1)
self.caravel_hdl.gpio_resetn_1_shifted.value = 1
self.caravel_hdl.gpio_resetn_2_shifted.value = 1
cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
self.print_gpios_ctrl_val()
"""change the configration of the gpios by overwrite the register value
in control registers and housekeeping regs, don't consume simulation cycles"""
### dont use back door accessing
def configure_gpios_regs(self,gpios_values: list):
cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
control_modules = self.control_blocks_paths()
# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
for array in gpios_values:
gpio_value = array[1]
for gpio in array[0]:
self.cov_configure_gpios(gpio,gpio_value.name)
self.gpio_control_reg_write(control_modules[gpio],gpio_value.value) # for control blocks regs
self.caravel_hdl.housekeeping.gpio_configure[gpio].value = gpio_value.value # for house keeping regs
cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
self.print_gpios_ctrl_val()
self.print_gpios_HW_val()
"""dummy function for coverage sampling"""
@Carvel_Coverage
def cov_configure_gpios(self,gpio,gpio_mode):
cocotb.log.debug(f' [caravel] gpio [{gpio}] = {gpio_mode} ')
pass
def print_gpios_default_val(self,print=1):
gpio_defaults = self.caravel_hdl.gpio_defaults.value
size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
gpios = []
for gpio in range(Macros['MPRJ_IO_PADS']):
gpio_value = gpio_defaults[size - (gpio*13 + 12): size -gpio*13]
gpio_enum = GPIO_MODE(gpio_value.integer)
gpios.append((gpio,gpio_enum))
group_bins = groupby(gpios,key=lambda x: x[1])
for key,value in group_bins:
gpios=[]
for gpio in list(value):
gpios.append(gpio[0])
if (print):
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
return gpios
"""print the values return in the gpio of control block mode in GPIO Mode format"""
def print_gpios_ctrl_val(self, print=1):
control_modules = self.control_blocks_paths()
gpios = []
for i , gpio in enumerate(control_modules):
gpios.append((i,self.gpio_control_reg_read(gpio)))
group_bins = groupby(gpios,key=lambda x: x[1])
for key,value in group_bins:
gpios=[]
for gpio in list(value):
gpios.append(gpio[0])
if (print):
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
return gpios
def _check_gpio_ctrl_eq_HW(self):
assert self.print_gpios_ctrl_val(1) == self.print_gpios_HW_val(1), f'there is an issue while configuration the control block register value isn\'t the same as the house keeping gpio register'
"""print the values return in the gpio of housekeeping block mode in GPIO Mode format"""
def print_gpios_HW_val(self,print=1):
gpios = []
for pin in range(Macros['MPRJ_IO_PADS']):
gpios.append((pin,GPIO_MODE(self.caravel_hdl.housekeeping.gpio_configure[pin].value)))
group_bins = groupby(gpios,key=lambda x: x[1])
for key,value in group_bins:
gpios=[]
for gpio in list(value):
gpios.append(gpio[0])
if (print):
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
return gpios
"""return the paths of the control blocks"""
def control_blocks_paths(self)-> list:
car = self.caravel_hdl
control_modules =[car._id("gpio_control_bidir_1[0]",False),car._id("gpio_control_bidir_1[1]",False)]
#add gpio_control_in_1a (GPIO 2 to 7)
for i in range(6):
control_modules.append(car._id(f'gpio_control_in_1a[{i}]',False))
#add gpio_control_in_1 (GPIO 8 to 18)
for i in range(Macros['MPRJ_IO_PADS_1']-9+1):
control_modules.append(car._id(f'gpio_control_in_1[{i}]',False))
#add gpio_control_in_2 (GPIO 19 to 34)
for i in range(Macros['MPRJ_IO_PADS_2']-4+1):
control_modules.append(car._id(f'gpio_control_in_2[{i}]',False))
# Last three GPIOs (spi_sdo, flash_io2, and flash_io3) gpio_control_bidir_2
for i in range(3):
control_modules.append(car._id(f'gpio_control_bidir_2[{i}]',False))
return control_modules
"""read the control register and return a GPIO Mode it takes the path to the control reg"""
def gpio_control_reg_read(self,path:SimHandleBase) -> GPIO_MODE:
gpio_mgmt_en = path.mgmt_ena.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value
gpio_out_dis = path.gpio_outenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value
gpio_holdover = path.gpio_holdover.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value
gpio_in_dis = path.gpio_inenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value
gpio_mode_sel = path.gpio_ib_mode_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value
gpio_anlg_en = path.gpio_ana_en.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value
gpio_anlg_sel = path.gpio_ana_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value
gpio_anlg_pol = path.gpio_ana_pol.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value
gpio_slow_sel = path.gpio_slow_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value
gpio_vtrip_sel = path.gpio_vtrip_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value
gpio_dgtl_mode = path.gpio_dm.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value
control_reg = (gpio_mgmt_en | gpio_out_dis | gpio_holdover| gpio_in_dis | gpio_mode_sel | gpio_anlg_en
|gpio_anlg_sel|gpio_anlg_pol|gpio_slow_sel|gpio_vtrip_sel|gpio_dgtl_mode)
return(GPIO_MODE(control_reg))
"""read the control register and return a GPIO Mode it takes the path to the control reg"""
def gpio_control_reg_write(self,path:SimHandleBase,data) :
bits =common.int_to_bin_list(data,14)
path.mgmt_ena.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value]
path.gpio_outenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value]
path.gpio_holdover.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value]
path.gpio_inenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value]
path.gpio_ib_mode_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value]
path.gpio_ana_en.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value]
path.gpio_ana_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value]
path.gpio_ana_pol.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value]
path.gpio_slow_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value]
path.gpio_vtrip_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value]
gpio_dm =bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value:MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value+3]
gpio_dm =sum(d * 2**i for i, d in enumerate(gpio_dm)) # convert list to binary int
path.gpio_dm.value = gpio_dm
# """drive the value of mprj bits with spicific data from input pad at the top"""
# def release_gpio(self):
# io = self.caravel_hdl.padframe.mprj_pads.io
# mprj , n_bits = common.signal_valueZ_size(io)
# io.value = mprj
# cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
"""drive the value of mprj bits with spicific data from input pad at the top"""
def drive_gpio_in(self,bits,data):
# io = self.caravel_hdl.padframe.mprj_pads.io
# mprj , n_bits = common.signal_value_size(io)
# cocotb.log.debug(f' [caravel] before mprj with {mprj} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
# mprj[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
# io.value = mprj
# cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
data_bits = []
is_list = isinstance(bits, (list,tuple))
if is_list :
cocotb.log.debug(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0]<bits[1]))
for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
self.dut._id(f"bin{bits2}",False).value = data_bits[i]
self.dut._id(f"bin{bits2}_en",False).value = 1
cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits2} with {data_bits[i]} and bin{bits2}_en with 1')
else:
self.dut._id(f'bin{bits}',False).value = data
self.dut._id(f'bin{bits}_en',False).value = 1
cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1')
""" release driving the value of mprj bits """
def release_gpio(self,bits):
data_bits = []
is_list = isinstance(bits, (list,tuple))
if is_list :
cocotb.log.debug(f'[caravel] [drive_gpio_disable] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
self.dut._id(f"bin{bits2}_en",False).value = 0
cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits2}')
else:
self.dut._id(f'bin{bits}_en',False).value = 0
cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits}')
"""drive the value of gpio management"""
def drive_mgmt_gpio(self,data):
mgmt_io = self.dut.gpio_tb
mgmt_io.value = data
cocotb.log.info(f' [caravel] drive_mgmt_gpio through management area mprj with {data}')
"""update the value of mprj bits with spicific data then after certain number of cycle drive z to free the signal"""
async def drive_gpio_in_with_cycles(self,bits,data,num_cycles):
self.drive_gpio_in(bits,data)
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
"""drive the value of mprj bits with spicific data from management area then after certain number of cycle drive z to free the signal"""
async def drive_mgmt_gpio_with_cycles(self,bits,data,num_cycles):
self.drive_mgmt_gpio(bits,data)
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
async def wait_then_undrive(self,bits,num_cycles):
await ClockCycles(self.clk, num_cycles)
n_bits = bits[0]-bits[1]+1
self.drive_gpio_in(bits, (n_bits)* 'z')
cocotb.log.info(f' [caravel] finish wait_then_drive ')
async def hk_write_byte(self, data):
self.path = self.dut.mprj_io_tb
data_bit = BinaryValue(value = data , n_bits = 8,bigEndian=False)
for i in range(7,-1,-1):
await FallingEdge(self.clk)
#common.drive_hdl(self.path,[(4,4),(2,2)],[0,int(data_bit[i])]) # 2 = SDI 4 = SCK
self.drive_gpio_in((2,2),int(data_bit[i]))
self.drive_gpio_in((4,4),0)
await RisingEdge(self.clk)
self.drive_gpio_in((4,4),1)
await FallingEdge(self.clk)
""" read byte using housekeeping spi
when writing to SCK we can't use mprj[4] as there is a limitation in cocotb for accessing pack array #2587
so use back door access to write the clock then read the output from the SDO mprj[1] value"""
async def hk_read_byte(self,last_read= False):
read_data =''
for i in range(8,0,-1):
self.drive_gpio_in((4,4),1)# SCK
await FallingEdge(self.clk)
self.drive_gpio_in((4,4),0)# SCK
await RisingEdge(self.clk)
read_data= f'{read_data}{self.dut.mprj_io_tb.value[37-1]}'
await FallingEdge(self.clk)
self.drive_gpio_in((4,4),0) # SCK
# if (last_read):
# common.drive_hdl(self.dut.bin4_en,(0,0),'z') #4 = SCK
# common.drive_hdl(self.path,[(1,1)],'z')
return int(read_data,2)
"""write to the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
async def hk_write_backdoor(self,addr, data):
await RisingEdge(self.dut.wb_clk_i)
self.hk_hdl.wb_stb_i.value = 1
self.hk_hdl.wb_cyc_i.value = 1
self.hk_hdl.wb_sel_i.value = 0xF
self.hk_hdl.wb_we_i.value = 1
self.hk_hdl.wb_adr_i.value = addr
self.hk_hdl.wb_dat_i.value = data
cocotb.log.info(f'Monitor: Start Writing to {hex(addr)} -> {data}')
await FallingEdge(self.dut.wb_ack_o) # wait for acknowledge
self.hk_hdl.wb_stb_i.value = 0
self.hk_hdl.wb_cyc_i.value = 0
cocotb.log.info(f'Monitor: End writing {hex(addr)} -> {data}')
"""read from the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
async def hk_read_backdoor(self,addr):
await RisingEdge(self.clk)
self.hk_hdl.wb_stb_i.value = 1
self.hk_hdl.wb_cyc_i.value = 1
self.hk_hdl.wb_sel_i.value = 0
self.hk_hdl.wb_we_i.value = 0
self.hk_hdl.wb_adr_i.value = addr
cocotb.log.info(f' [housekeeping] Monitor: Start reading from {hex(addr)}')
await FallingEdge(self.hk_hdl.wb_ack_o)
self.hk_hdl.wb_stb_i.value = 0
self.hk_hdl.wb_cyc_i.value = 0
cocotb.log.info(f' [housekeeping] Monitor: read from {hex(addr)} value {(self.hk_hdl.wb_dat_o.value)}')
return self.hk_hdl.wb_dat_o.value

205
verilog/dv/cocotb/caravel_tests.py Normal file
View File

@ -0,0 +1,205 @@
from cgitb import handler
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
import cocotb.simulator
from cocotb_coverage.coverage import *
from cocotb.binary import BinaryValue
import interfaces.caravel
from interfaces.logic_analyzer import LA
from interfaces.caravel import GPIO_MODE, Caravel_env
from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox
import interfaces.common as common
import logging
from interfaces.cpu import RiskV
from cocotb.log import SimTimeContextFilter
from cocotb.log import SimLogFormatter
from interfaces.defsParser import Regs
from tests.common_functions.Timeout import Timeout
from cocotb.result import TestSuccess
import inspect
import os
# tests
from tests.bitbang.bitbang_tests import *
from tests.bitbang.bitbang_tests_cpu import *
from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import *
from tests.housekeeping.housekeeping_spi.user_pass_thru import *
from tests.housekeeping.general.pll import *
from tests.housekeeping.general.sys_ctrl import *
from tests.temp_partial_test.partial import *
from tests.hello_world.helloWorld import *
from tests.cpu.cpu_stress import *
from tests.mem.mem_stress import *
from tests.irq.IRQ_external import *
from tests.irq.IRQ_timer import *
from tests.irq.IRQ_uart import *
from tests.gpio.gpio import *
from tests.gpio.gpio_user import *
from tests.mgmt_gpio.mgmt_gpio import *
from tests.timer.timer import *
from tests.uart.uart import *
from tests.spi_master.spi_master import *
from tests.logicAnalyzer.la import *
# archive tests
@cocotb.test()
async def cpu_drive(dut):
TestName = inspect.stack()[0][3]
if not os.path.exists(f'sim/{TestName}'):
os.mkdir(f'sim/{TestName}') # create test folder
cocotb.log.setLevel(logging.INFO)
handler = logging.FileHandler(f"sim/{TestName}/{TestName}.log",mode='w')
handler.addFilter(SimTimeContextFilter())
handler.setFormatter(SimLogFormatter())
cocotb.log.addHandler(handler)
caravelEnv = caravel.Caravel_env(dut)
Timeout(caravelEnv.clk,1000000,0.1)
la = LA(dut)
clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk
cpu = RiskV(dut)
cpu.cpu_force_reset()
cocotb.start_soon(clock.start()) # Start the clock
await caravelEnv.start_up()
hk = HK_whiteBox(dut)
reg = Regs()
time_out_count =0
await ClockCycles(caravelEnv.clk, 100)
address = reg.get_addr('reg_wb_enable')
await cpu.drive_data2address(address,1)
address = reg.get_addr('reg_debug_2')
await cpu.drive_data2address(address,0xdFF0)
await ClockCycles(caravelEnv.clk, 10)
cpu.cpu_release_reset()
await ClockCycles(caravelEnv.clk, 10)
raise TestSuccess(f" TEST {TestName} passed")
while True:
await ClockCycles(caravelEnv.clk, 1)
if (cpu.read_debug_reg1() == 0xFFF0):
break
cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xFFF0")
await ClockCycles(caravelEnv.clk, 10)
address = reg.get_addr('reg_debug_2')
await cpu.drive_data2address(address,0xdFF0)
await ClockCycles(caravelEnv.clk, 50)
# address = reg.get_addr('reg_mprj_io_0')
# await cpu.drive_data2address(address,0x0c03)
cocotb.log.info(f"[TEST][cpu_drive] wait debug reg1 = 0xddd0")
while True:
await ClockCycles(caravelEnv.clk, 1)
if (cpu.read_debug_reg1() == 0xddd0):
break
cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xddd0")
await ClockCycles(caravelEnv.clk, 10)
caravelEnv.print_gpios_HW_val()
coverage_db.export_to_yaml(filename="coverage.yalm")
@cocotb.test()
async def spi_drive(dut):
cocotb.log.setLevel(logging.INFO)
handler = logging.FileHandler(f"test.log",mode='w')
handler.addFilter(SimTimeContextFilter())
handler.setFormatter(SimLogFormatter())
cocotb.log.addHandler(handler)
caravelEnv = caravel.Caravel_env(dut)
la = LA(dut)
clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk
cocotb.start_soon(clock.start()) # Start the clock
await caravelEnv.start_up()
hk = HK_whiteBox(dut,True)
caravelEnv.enable_csb()
await ClockCycles(caravelEnv.clk,1)
# caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]])
await ClockCycles(caravelEnv.clk,1)
await caravelEnv.hk_write_byte(0x40) # read command
# await caravelEnv.hk_write_byte(0x80) # command write
await caravelEnv.hk_write_byte(0x0) # address
# await caravelEnv.hk_write_byte(0x03) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
read_data = await caravelEnv.hk_read_byte() # read value
print(read_data)
read_data = await caravelEnv.hk_read_byte() # read value
print(read_data)
read_data = await caravelEnv.hk_read_byte() # read value
print(read_data)
read_data = await caravelEnv.hk_read_byte() # read value
print(read_data)
read_data = await caravelEnv.hk_read_byte() # read value
print(read_data)
read_data = await caravelEnv.hk_read_byte() # read value
print(read_data)
read_data = await caravelEnv.hk_read_byte() # read value
print(read_data)
read_data = await caravelEnv.hk_read_byte(True) # read value
caravelEnv.disable_csb()
await ClockCycles(caravelEnv.clk,1)
caravelEnv.enable_csb()
await ClockCycles(caravelEnv.clk,1)
# caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]])
await ClockCycles(caravelEnv.clk,1)
await caravelEnv.hk_write_byte(0x40) # read command
# await caravelEnv.hk_write_byte(0x80) # command write
await caravelEnv.hk_write_byte(0x8) # address
# await caravelEnv.hk_write_byte(0x03) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
# await caravelEnv.hk_write_byte(0xaa) # data
read_data = await caravelEnv.hk_read_byte() # read value
read_data = await caravelEnv.hk_read_byte() # read value
read_data = await caravelEnv.hk_read_byte() # read value
read_data = await caravelEnv.hk_read_byte() # read value
read_data = await caravelEnv.hk_read_byte() # read value
read_data = await caravelEnv.hk_read_byte() # read value
read_data = await caravelEnv.hk_read_byte() # read value
read_data = await caravelEnv.hk_read_byte() # read value
# caravelEnv.drive_gpio_in([5,5],1)
await ClockCycles(caravelEnv.clk,40)
coverage_db.export_to_yaml(filename="coverage.yml")
coverage_db.export_to_xml(filename="coverage.xml")
return

358
verilog/dv/cocotb/caravel_top.sv Normal file
View File

@ -0,0 +1,358 @@
`ifdef VCS
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
`endif
`timescale 1 ns / 1 ps
module caravel_top ;
// parameter FILENAME = {"hex_files/",`TESTNAME,".hex"};
parameter FILENAME={"hex_files/",`TESTNAME,".hex"};
initial begin
`ifdef VCS
`ifdef ENABLE_SDF
$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME , `SDF_POSTFIX, ".vpd"});
`else
$vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME ,".vpd"});
`endif
$vcdpluson();
`else
$dumpfile ({"sim/",`TAG,"/",`SIM,"-",`TESTNAME,"/",`SIM,"-",`TESTNAME,".vcd"});
$dumpvars (0, caravel_top);
`endif
end
wire vddio_tb; // Common 3.3V padframe/ESD power
wire vddio_2_tb; // Common 3.3V padframe/ESD power
wire vssio_tb; // Common padframe/ESD ground
wire vssio_2_tb; // Common padframe/ESD ground
wire vdda_tb; // Management 3.3V power
wire vssa_tb; // Common analog ground
wire vccd_tb; // Management/Common 1.8V power
wire vssd_tb; // Common digital ground
wire vdda1_tb; // User area 1 3.3V power
wire vdda1_2_tb; // User area 1 3.3V power
wire vdda2_tb; // User area 2 3.3V power
wire vssa1_tb; // User area 1 analog ground
wire vssa1_2_tb; // User area 1 analog ground
wire vssa2_tb; // User area 2 analog ground
wire vccd1_tb; // User area 1 1.8V power
wire vccd2_tb; // User area 2 1.8V power
wire vssd1_tb; // User area 1 digital ground
wire vssd2_tb; // User area 2 digital ground
wire gpio_tb; // Used for external LDO control
wire [38-1:0] mprj_io_tb;
reg clock_tb; // CMOS core clock input; not a crystal
wire resetb_tb; // Reset input (sense inverted)
// Note that only two flash data pins are dedicated to the
// management SoC wrapper. The management SoC exports the
// quad SPI mode status to make use of the top two mprj_io
// pins for io2 and io3.
wire flash_csb_tb;
wire flash_clk_tb;
wire flash_io0_tb;
wire flash_io1_tb;
caravel uut (
.vddio (vddio_tb),
.vddio_2 (vddio_2_tb),
.vssio (vssio_tb),
.vssio_2 (vssio_2_tb),
.vdda (vdda_tb),
.vssa (vssa_tb),
.vccd (vccd_tb),
.vssd (vssd_tb),
.vdda1 (vdda1_tb),
.vdda1_2 (vdda1_2_tb),
.vdda2 (vdda2_tb),
.vssa1 (vssa1_tb),
.vssa1_2 (vssa1_2_tb),
.vssa2 (vssa2_tb),
.vccd1 (vccd1_tb),
.vccd2 (vccd2_tb),
.vssd1 (vssd1_tb),
.vssd2 (vssd2_tb),
.clock (clock_tb),
.gpio (gpio_tb),
.mprj_io (mprj_io_tb),
.flash_csb(flash_csb_tb),
.flash_clk(flash_clk_tb),
.flash_io0(flash_io0_tb),
.flash_io1(flash_io1_tb),
.resetb (resetb_tb)
);
spiflash #(
FILENAME
) spiflash (
.csb(flash_csb_tb),
.clk(flash_clk_tb),
.io0(flash_io0_tb),
.io1(flash_io1_tb),
.io2(), // not used
.io3() // not used
);
mac macros();
// make speical variables for the mprj input to assign the input without writing to the output gpios
// cocotb limitation #2587: iverilog deal with array as 1 object not multiple of objects so can't write to only 1 element
wire bin0;
wire bin0_en;
wire bin1;
wire bin1_en;
wire bin2;
wire bin2_en;
wire bin3;
wire bin3_en;
wire bin4;
wire bin4_en;
wire bin5;
wire bin5_en;
wire bin6;
wire bin6_en;
wire bin7;
wire bin7_en;
wire bin8;
wire bin8_en;
wire bin9;
wire bin9_en;
wire bin10;
wire bin10_en;
wire bin11;
wire bin11_en;
wire bin12;
wire bin12_en;
wire bin13;
wire bin13_en;
wire bin14;
wire bin14_en;
wire bin15;
wire bin15_en;
wire bin16;
wire bin16_en;
wire bin17;
wire bin17_en;
wire bin18;
wire bin18_en;
wire bin19;
wire bin19_en;
wire bin20;
wire bin20_en;
wire bin21;
wire bin21_en;
wire bin22;
wire bin22_en;
wire bin23;
wire bin23_en;
wire bin24;
wire bin24_en;
wire bin25;
wire bin25_en;
wire bin26;
wire bin26_en;
wire bin27;
wire bin27_en;
wire bin28;
wire bin28_en;
wire bin29;
wire bin29_en;
wire bin30;
wire bin30_en;
wire bin31;
wire bin31_en;
wire bin32;
wire bin32_en;
wire bin33;
wire bin33_en;
wire bin34;
wire bin34_en;
wire bin35;
wire bin35_en;
wire bin36;
wire bin36_en;
wire bin37;
wire bin37_en;
assign mprj_io_tb[0] = (bin0_en) ? bin0 : 1'bz;
assign mprj_io_tb[1] = (bin1_en) ? bin1 : 1'bz;
assign mprj_io_tb[2] = (bin2_en) ? bin2 : 1'bz;
assign mprj_io_tb[3] = (bin3_en) ? bin3 : 1'bz;
assign mprj_io_tb[4] = (bin4_en) ? bin4 : 1'bz;
assign mprj_io_tb[5] = (bin5_en) ? bin5 : 1'bz;
assign mprj_io_tb[6] = (bin6_en) ? bin6 : 1'bz;
assign mprj_io_tb[7] = (bin7_en) ? bin7 : 1'bz;
assign mprj_io_tb[8] = (bin8_en) ? bin8 : 1'bz;
assign mprj_io_tb[9] = (bin9_en) ? bin9 : 1'bz;
assign mprj_io_tb[10] = (bin10_en) ? bin10 : 1'bz;
assign mprj_io_tb[11] = (bin11_en) ? bin11 : 1'bz;
assign mprj_io_tb[12] = (bin12_en) ? bin12 : 1'bz;
assign mprj_io_tb[13] = (bin13_en) ? bin13 : 1'bz;
assign mprj_io_tb[14] = (bin14_en) ? bin14 : 1'bz;
assign mprj_io_tb[15] = (bin15_en) ? bin15 : 1'bz;
assign mprj_io_tb[16] = (bin16_en) ? bin16 : 1'bz;
assign mprj_io_tb[17] = (bin17_en) ? bin17 : 1'bz;
assign mprj_io_tb[18] = (bin18_en) ? bin18 : 1'bz;
assign mprj_io_tb[19] = (bin19_en) ? bin19 : 1'bz;
assign mprj_io_tb[20] = (bin20_en) ? bin20 : 1'bz;
assign mprj_io_tb[21] = (bin21_en) ? bin21 : 1'bz;
assign mprj_io_tb[22] = (bin22_en) ? bin22 : 1'bz;
assign mprj_io_tb[23] = (bin23_en) ? bin23 : 1'bz;
assign mprj_io_tb[24] = (bin24_en) ? bin24 : 1'bz;
assign mprj_io_tb[25] = (bin25_en) ? bin25 : 1'bz;
assign mprj_io_tb[26] = (bin26_en) ? bin26 : 1'bz;
assign mprj_io_tb[27] = (bin27_en) ? bin27 : 1'bz;
assign mprj_io_tb[28] = (bin28_en) ? bin28 : 1'bz;
assign mprj_io_tb[29] = (bin29_en) ? bin29 : 1'bz;
assign mprj_io_tb[30] = (bin30_en) ? bin30 : 1'bz;
assign mprj_io_tb[31] = (bin31_en) ? bin31 : 1'bz;
assign mprj_io_tb[32] = (bin32_en) ? bin32 : 1'bz;
assign mprj_io_tb[33] = (bin33_en) ? bin33 : 1'bz;
assign mprj_io_tb[34] = (bin34_en) ? bin34 : 1'bz;
assign mprj_io_tb[35] = (bin35_en) ? bin35 : 1'bz;
assign mprj_io_tb[36] = (bin36_en) ? bin36 : 1'bz;
assign mprj_io_tb[37] = (bin37_en) ? bin37 : 1'bz;
// to read from mprj array with iverilog
wire bin0_monitor;
wire bin1_monitor;
wire bin2_monitor;
wire bin3_monitor;
wire bin4_monitor;
wire bin5_monitor;
wire bin6_monitor;
wire bin7_monitor;
wire bin8_monitor;
wire bin9_monitor;
wire bin10_monitor;
wire bin11_monitor;
wire bin12_monitor;
wire bin13_monitor;
wire bin14_monitor;
wire bin15_monitor;
wire bin16_monitor;
wire bin17_monitor;
wire bin18_monitor;
wire bin19_monitor;
wire bin20_monitor;
wire bin21_monitor;
wire bin22_monitor;
wire bin23_monitor;
wire bin24_monitor;
wire bin25_monitor;
wire bin26_monitor;
wire bin27_monitor;
wire bin28_monitor;
wire bin29_monitor;
wire bin30_monitor;
wire bin31_monitor;
wire bin32_monitor;
wire bin33_monitor;
wire bin34_monitor;
wire bin35_monitor;
wire bin36_monitor;
wire bin37_monitor;
assign bin0_monitor = mprj_io_tb[0];
assign bin1_monitor = mprj_io_tb[1];
assign bin2_monitor = mprj_io_tb[2];
assign bin3_monitor = mprj_io_tb[3];
assign bin4_monitor = mprj_io_tb[4];
assign bin5_monitor = mprj_io_tb[5];
assign bin6_monitor = mprj_io_tb[6];
assign bin7_monitor = mprj_io_tb[7];
assign bin8_monitor = mprj_io_tb[8];
assign bin9_monitor = mprj_io_tb[9];
assign bin10_monitor = mprj_io_tb[10];
assign bin11_monitor = mprj_io_tb[11];
assign bin12_monitor = mprj_io_tb[12];
assign bin13_monitor = mprj_io_tb[13];
assign bin14_monitor = mprj_io_tb[14];
assign bin15_monitor = mprj_io_tb[15];
assign bin16_monitor = mprj_io_tb[16];
assign bin17_monitor = mprj_io_tb[17];
assign bin18_monitor = mprj_io_tb[18];
assign bin19_monitor = mprj_io_tb[19];
assign bin20_monitor = mprj_io_tb[20];
assign bin21_monitor = mprj_io_tb[21];
assign bin22_monitor = mprj_io_tb[22];
assign bin23_monitor = mprj_io_tb[23];
assign bin24_monitor = mprj_io_tb[24];
assign bin25_monitor = mprj_io_tb[25];
assign bin26_monitor = mprj_io_tb[26];
assign bin27_monitor = mprj_io_tb[27];
assign bin28_monitor = mprj_io_tb[28];
assign bin29_monitor = mprj_io_tb[29];
assign bin30_monitor = mprj_io_tb[30];
assign bin31_monitor = mprj_io_tb[31];
assign bin32_monitor = mprj_io_tb[32];
assign bin33_monitor = mprj_io_tb[33];
assign bin34_monitor = mprj_io_tb[34];
assign bin35_monitor = mprj_io_tb[35];
assign bin36_monitor = mprj_io_tb[36];
assign bin37_monitor = mprj_io_tb[37];
endmodule
// module that has all needed macros by cocotb
module mac;
reg [7:0] MPRJ_IO_PADS_1 = `ifdef MPRJ_IO_PADS_1 `MPRJ_IO_PADS_1 `else 0 `endif; /* number of user GPIO pads on user1 side */
reg [7:0] MPRJ_IO_PADS_2 = `ifdef MPRJ_IO_PADS_2 `MPRJ_IO_PADS_2 `else 0 `endif; /* number of user GPIO pads on user2 side */
reg [7:0] MPRJ_IO_PADS = `ifdef MPRJ_IO_PADS `MPRJ_IO_PADS `else 0 `endif;
reg [7:0] MPRJ_PWR_PADS_1 =`ifdef MPRJ_PWR_PADS_1 `MPRJ_PWR_PADS_1 `else 0 `endif; /* vdda1, vccd1 enable/disable control */
reg [7:0] MPRJ_PWR_PADS_2 = `ifdef MPRJ_PWR_PADS_2 `MPRJ_PWR_PADS_2 `else 0 `endif; /* vdda2, vccd2 enable/disable control */
reg [7:0] MPRJ_PWR_PADS =`ifdef MPRJ_PWR_PADS `MPRJ_PWR_PADS `else 0 `endif;
// Analog pads are only used by the "caravan" module and associated
// modules such as user_analog_project_wrapper and chip_io_alt.
reg [7:0] ANALOG_PADS_1 = `ifdef ANALOG_PADS_1 `ANALOG_PADS_1 `else 0 `endif;
reg [7:0] ANALOG_PADS_2 = `ifdef ANALOG_PADS_2 `ANALOG_PADS_2 `else 0 `endif;
reg [7:0] ANALOG_PADS = `ifdef ANALOG_PADS `ANALOG_PADS `else 0 `endif;
// Type and size of soc_mem
reg USE_CUSTOM_DFFRAM = `ifdef USE_CUSTOM_DFFRAM 1 `else 0 `endif;
// don't change the following without double checking addr widths
reg [7:0] MEM_WORDS = `ifdef MEM_WORDS `MEM_WORDS `else 0 `endif;
// Number of columns in the custom memory; takes one of three values:
// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
reg [7:0] DFFRAM_WSIZE = `ifdef DFFRAM_WSIZE `DFFRAM_WSIZE `else 0 `endif;
reg [7:0] DFFRAM_USE_LATCH = `ifdef DFFRAM_USE_LATCH `DFFRAM_USE_LATCH `else 0 `endif;
// not really parameterized but just to easily keep track of the number
// of ram_block across different modules
reg [7:0] RAM_BLOCKS = `ifdef RAM_BLOCKS `RAM_BLOCKS `else 0 `endif;
// Clock divisor default value
reg [7:0] CLK_DIV = `ifdef CLK_DIV `CLK_DIV `else 0 `endif;
// GPIO control default mode and enable for most I/Os
// Most I/Os set to be user bidirectional pins on power-up.
reg [7:0] MGMT_INIT = `ifdef MGMT_INIT `MGMT_INIT `else 0 `endif;
reg [7:0] OENB_INIT = `ifdef OENB_INIT `OENB_INIT `else 0 `endif;
reg [7:0] DM_INIT = `ifdef DM_INIT `DM_INIT `else 0 `endif;
// GL
reg GL = `ifdef GL 1 `else 0 `endif;
endmodule

232
verilog/dv/cocotb/cpu.py Normal file
View File

@ -0,0 +1,232 @@
from operator import add
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
import cocotb.simulator
from cocotb.handle import SimHandleBase
from cocotb.handle import Force
from cocotb_coverage.coverage import *
from cocotb.binary import BinaryValue
import enum
from cocotb.handle import (
ConstantObject,
HierarchyArrayObject,
HierarchyObject,
ModifiableObject,
NonHierarchyIndexableObject,
SimHandle,
)
from itertools import groupby, product
import interfaces.common as common
from common import GPIO_MODE
from common import MASK_GPIO_CTRL
from common import Macros
class RiskV:
def __init__(self,dut:SimHandleBase):
self.dut = dut
self.clk = dut.clock_tb
if not Macros['GL']:
self.cpu_hdl = dut.uut.soc.core.VexRiscv
else:
self.cpu_hdl = dut.uut.soc.core
self.debug_hdl = dut.uut.mprj.debug
self.force_reset = 0
cocotb.scheduler.add(self.force_reset_fun())
""" """
async def drive_data_with_address(self,address,data,SEL=0xF):
self.cpu_hdl.dBusWishbone_CYC.value = 1
self.cpu_hdl.iBusWishbone_CYC.value = 0
self.cpu_hdl.dBusWishbone_STB.value = 1
self.cpu_hdl.dBusWishbone_WE.value = 1
self.cpu_hdl.dBusWishbone_SEL.value = SEL
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
await ClockCycles(self.clk, 1)
self.cpu_hdl.dBusWishbone_CYC.value = BinaryValue(value = 'z')
self.cpu_hdl.iBusWishbone_CYC.value = BinaryValue(value = 'z')
self.cpu_hdl.dBusWishbone_STB.value = BinaryValue(value = 'z')
self.cpu_hdl.dBusWishbone_WE.value = BinaryValue(value = 'z')
self.cpu_hdl.dBusWishbone_SEL.value = BinaryValue(value = 'zzzz')
self.cpu_hdl.dBusWishbone_ADR.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_ADR)[0]
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_DAT_MOSI)[0]
""" """
async def drive_data2address(self,address,data,SEL=0xF):
cocotb.log.info(f"[RiskV][drive_data2address] start driving address {hex(address)} with {hex(data)}")
# print(dir(self.cpu_hdl))
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
if not Macros['GL']:
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
if not Macros['GL']:
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
else:
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
if not Macros['GL']:
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
self.cpu_hdl.dBusWishbone_CYC.value = 1
if not Macros['GL']:
self.cpu_hdl.iBusWishbone_CYC.value = 0
self.cpu_hdl.dBusWishbone_STB.value = 1
self.cpu_hdl.dBusWishbone_WE.value = 1
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_SEL.value = SEL
else:
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
self.cpu_hdl.net848.value = (SEL >>2 ) &1
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
else:
address_temp = address >> 2
for i in range(30):
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
else:
for i in range(32):
self.cpu_hdl._id(f'dBusWishbone_DAT_MOSI[{i}]',False).value = (data >> i) & 1
if not Macros['GL']:
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
else:
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
await ClockCycles(self.clk, 1)
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
await ClockCycles(self.clk, 1)
cocotb.log.info(f"[RiskV][drive_data2address] finish driving address {hex(address)} with {hex(data)}")
""" """
async def read_address(self,address,SEL=0xF):
cocotb.log.info(f"[RiskV][read_address] start reading address {hex(address)}")
# print(dir(self.cpu_hdl))
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
if not Macros['GL']:
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
if not Macros['GL']:
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
else:
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
if not Macros['GL']:
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
self.cpu_hdl.dBusWishbone_CYC.value = 1
if not Macros['GL']:
self.cpu_hdl.iBusWishbone_CYC.value = 0
self.cpu_hdl.dBusWishbone_STB.value = 1
self.cpu_hdl.dBusWishbone_WE.value = 0
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_SEL.value = SEL
else:
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
self.cpu_hdl.net848.value = (SEL >>2 ) &1
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
else:
address_temp = address >> 2
for i in range(30):
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
if not Macros['GL']:
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
else:
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
await ClockCycles(self.clk, 1)
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
data = self.cpu_hdl.dBusWishbone_DAT_MISO.value
await ClockCycles(self.clk, 1)
cocotb.log.info(f"[RiskV][read_address] finish reading address {hex(address)} data = {data}")
# return data
return int(str(bin(data.integer)[2:]).zfill(32),2)
# return int(str(bin(data.integer)[2:]).zfill(32)[::-1],2)
def read_debug_reg1(self):
return self.debug_hdl.debug_reg_1.value.integer
def read_debug_reg2(self):
return self.debug_hdl.debug_reg_2.value.integer
# writing debug registers using backdoor because in GL cpu can't be disabled for now because of different netlist names
def write_debug_reg1_backdoor(self,data):
self.debug_hdl.debug_reg_1.value = data
def write_debug_reg2_backdoor(self,data):
self.debug_hdl.debug_reg_2.value = data
async def force_reset_fun(self):
first_time_force = True
first_time_release = True
while True:
if self.force_reset:
if first_time_force:
cocotb.log.info(f"[RiskV][force_reset_fun] Force CPU reset")
first_time_force = False
first_time_release = True
self.cpu_hdl.reset.value =1
if not Macros['GL']:
common.drive_hdl(self.cpu_hdl.reset,(0,0),1)
else:
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),1)
else:
if first_time_release:
first_time_force = True
first_time_release = False
if not Macros['GL']:
common.drive_hdl(self.cpu_hdl.reset,(0,0),0)
else:
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),0)
cocotb.log.info(f"[RiskV][force_reset_fun] release CPU reset")
await ClockCycles(self.clk, 1)
def cpu_force_reset(self):
self.force_reset = True
def cpu_release_reset(self):
self.force_reset = False

BIN
verilog/dv/cocotb/doc/CTN.png Normal file
View File

Binary file not shown.
Side by Side

After

Width:  |  Height:  |  Size: 45 KiB

1
verilog/dv/cocotb/doc/README.md Normal file
View File

@ -0,0 +1 @@

432
verilog/dv/cocotb/interfaces/caravel.py Normal file
View File

@ -0,0 +1,432 @@
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
import cocotb.simulator
from cocotb.handle import SimHandleBase
from cocotb.handle import Force
from cocotb_coverage.coverage import *
from cocotb.binary import BinaryValue
import enum
from cocotb.handle import (
ConstantObject,
HierarchyArrayObject,
HierarchyObject,
ModifiableObject,
NonHierarchyIndexableObject,
SimHandle,
)
from itertools import groupby, product
import interfaces.common as common
from interfaces.common import GPIO_MODE
from interfaces.common import MASK_GPIO_CTRL
from interfaces.common import Macros
def gpio_mode(gpios_values:list):
gpios=[]
for array in gpios_values:
gpio_value = GPIO_MODE(array[1]).name
for gpio in array[0]:
gpios.append((gpio,gpio_value))
cocotb.log.info(f'[caravel][gpio_mode] gpios {gpios}')
return gpios
Carvel_Coverage = coverage_section (
CoverPoint("top.caravel.gpio", vname="gpios mode", xf = lambda gpio ,gpio_mode: (gpio,gpio_mode) ,
bins = list(product(range(38),[e.name for e in GPIO_MODE])))
)
class Caravel_env:
def __init__(self,dut:SimHandleBase):
self.dut = dut
self.clk = dut.clock_tb
self.caravel_hdl = dut.uut
self.hk_hdl = dut.uut.housekeeping
"""start carvel by insert power then reset"""
async def start_up(self):
await self.power_up()
# await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup
await self.reset()
await self.disable_bins()
common.fill_macros(self.dut.macros) # get macros value
async def disable_bins(self):
for i in range(38):
common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0)
"""setup the vdd and vcc power bins"""
async def power_up(self):
cocotb.log.info(f' [caravel] start powering up')
self.set_vdd(0)
self.set_vcc(0)
await ClockCycles(self.clk, 10)
cocotb.log.info(f' [caravel] power up -> connect vdd' )
self.set_vdd(1)
# await ClockCycles(self.clk, 10)
cocotb.log.info(f' [caravel] power up -> connect vcc' )
self.set_vcc(1)
await ClockCycles(self.clk, 10)
""""reset caravel"""
async def reset(self):
cocotb.log.info(f' [caravel] start resetting')
self.dut.resetb_tb.value = 0
await ClockCycles(self.clk, 20)
self.dut.resetb_tb.value = 1
await ClockCycles(self.clk, 1)
cocotb.log.info(f' [caravel] finish resetting')
def set_vdd(self,value:bool):
self.dut.vddio_tb.value = value
self.dut.vssio_tb.value = 0
self.dut.vddio_2_tb.value = value
self.dut.vssio_2_tb.value = 0
self.dut.vdda_tb.value = value
self.dut.vssa_tb.value = 0
self.dut.vdda1_tb.value = value
self.dut.vssa1_tb.value = 0
self.dut.vdda1_2_tb.value = value
self.dut.vssa1_2_tb.value = 0
self.dut.vdda2_tb.value = value
self.dut.vssa2_tb.value = 0
def set_vcc(self , value:bool):
self.dut.vccd_tb.value = value
self.dut.vssd_tb.value = 0
self.dut.vccd1_tb.value = value
self.dut.vssd1_tb.value = 0
self.dut.vccd2_tb.value = value
self.dut.vssd2_tb.value = 0
"""drive csb signal bin E8 mprj[3]"""
async def drive_csb(self,bit):
self.drive_gpio_in((3,3),bit)
self.drive_gpio_in((2,2),0)
await ClockCycles(self.clk, 1)
"""set the spi vsb signal high to disable housekeeping spi transmission bin E8 mprj[3]"""
async def disable_csb(self ):
cocotb.log.info(f' [caravel] disable housekeeping spi transmission')
await self.drive_csb(1)
"""set the spi vsb signal high impedance """
async def release_csb(self ):
cocotb.log.info(f' [caravel] release housekeeping spi transmission')
self.release_gpio(3)
self.release_gpio(2)
await ClockCycles(self.clk, 1)
"""set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]"""
async def enable_csb(self ):
cocotb.log.info(f' [caravel] enable housekeeping spi transmission')
await self.drive_csb(0)
"""return the value of mprj in bits used tp monitor the output gpios value"""
def monitor_gpio(self,bits:tuple):
mprj = self.dut.mprj_io_tb.value
size =mprj.n_bits -1 #size of bins array
mprj_out= self.dut.mprj_io_tb.value[size - bits[0]:size - bits[1]]
if(mprj_out.is_resolvable):
cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {hex(mprj_out)}')
else:
cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {mprj_out}')
return mprj_out
"""return the value of management gpio"""
def monitor_mgmt_gpio(self):
data = self.dut.gpio_tb.value
cocotb.log.debug(f' [caravel] Monitor mgmt gpio = {data}')
return data
"""change the configration of the gpios by overwrite their defaults value then reset
need to take at least 1 cycle for reset """
### dont use back door accessing
async def configure_gpio_defaults(self,gpios_values: list):
gpio_defaults = self.caravel_hdl.gpio_defaults.value
cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
for array in gpios_values:
gpio_value = array[1]
for gpio in array[0]:
self.cov_configure_gpios(gpio,gpio_value.name)
gpio_defaults[size - (gpio*13 + 12): size -gpio*13] = gpio_value.value
#cocotb.log.info(f' [caravel] gpio_defaults[{size - (gpio*13 + 12)}:{size -gpio*13}] = {gpio_value.value} ')
self.caravel_hdl.gpio_defaults.value = gpio_defaults
#reset
self.caravel_hdl.gpio_resetn_1_shifted.value = 0
self.caravel_hdl.gpio_resetn_2_shifted.value = 0
await ClockCycles(self.clk, 1)
self.caravel_hdl.gpio_resetn_1_shifted.value = 1
self.caravel_hdl.gpio_resetn_2_shifted.value = 1
cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
self.print_gpios_ctrl_val()
"""change the configration of the gpios by overwrite the register value
in control registers and housekeeping regs, don't consume simulation cycles"""
### dont use back door accessing
def configure_gpios_regs(self,gpios_values: list):
cocotb.log.info(f' [caravel] start cofigure gpio gpios ')
control_modules = self.control_blocks_paths()
# list example [[(gpios),value],[(gpios),value],[(gpios),value]]
for array in gpios_values:
gpio_value = array[1]
for gpio in array[0]:
self.cov_configure_gpios(gpio,gpio_value.name)
self.gpio_control_reg_write(control_modules[gpio],gpio_value.value) # for control blocks regs
self.caravel_hdl.housekeeping.gpio_configure[gpio].value = gpio_value.value # for house keeping regs
cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ')
self.print_gpios_ctrl_val()
self.print_gpios_HW_val()
"""dummy function for coverage sampling"""
@Carvel_Coverage
def cov_configure_gpios(self,gpio,gpio_mode):
cocotb.log.debug(f' [caravel] gpio [{gpio}] = {gpio_mode} ')
pass
def print_gpios_default_val(self,print=1):
gpio_defaults = self.caravel_hdl.gpio_defaults.value
size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults
gpios = []
for gpio in range(Macros['MPRJ_IO_PADS']):
gpio_value = gpio_defaults[size - (gpio*13 + 12): size -gpio*13]
gpio_enum = GPIO_MODE(gpio_value.integer)
gpios.append((gpio,gpio_enum))
group_bins = groupby(gpios,key=lambda x: x[1])
for key,value in group_bins:
gpios=[]
for gpio in list(value):
gpios.append(gpio[0])
if (print):
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
return gpios
"""print the values return in the gpio of control block mode in GPIO Mode format"""
def print_gpios_ctrl_val(self, print=1):
control_modules = self.control_blocks_paths()
gpios = []
for i , gpio in enumerate(control_modules):
gpios.append((i,self.gpio_control_reg_read(gpio)))
group_bins = groupby(gpios,key=lambda x: x[1])
for key,value in group_bins:
gpios=[]
for gpio in list(value):
gpios.append(gpio[0])
if (print):
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
return gpios
def _check_gpio_ctrl_eq_HW(self):
assert self.print_gpios_ctrl_val(1) == self.print_gpios_HW_val(1), f'there is an issue while configuration the control block register value isn\'t the same as the house keeping gpio register'
"""print the values return in the gpio of housekeeping block mode in GPIO Mode format"""
def print_gpios_HW_val(self,print=1):
gpios = []
for pin in range(Macros['MPRJ_IO_PADS']):
gpios.append((pin,GPIO_MODE(self.caravel_hdl.housekeeping.gpio_configure[pin].value)))
group_bins = groupby(gpios,key=lambda x: x[1])
for key,value in group_bins:
gpios=[]
for gpio in list(value):
gpios.append(gpio[0])
if (print):
cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ')
return gpios
"""return the paths of the control blocks"""
def control_blocks_paths(self)-> list:
car = self.caravel_hdl
control_modules =[car._id("gpio_control_bidir_1[0]",False),car._id("gpio_control_bidir_1[1]",False)]
#add gpio_control_in_1a (GPIO 2 to 7)
for i in range(6):
control_modules.append(car._id(f'gpio_control_in_1a[{i}]',False))
#add gpio_control_in_1 (GPIO 8 to 18)
for i in range(Macros['MPRJ_IO_PADS_1']-9+1):
control_modules.append(car._id(f'gpio_control_in_1[{i}]',False))
#add gpio_control_in_2 (GPIO 19 to 34)
for i in range(Macros['MPRJ_IO_PADS_2']-4+1):
control_modules.append(car._id(f'gpio_control_in_2[{i}]',False))
# Last three GPIOs (spi_sdo, flash_io2, and flash_io3) gpio_control_bidir_2
for i in range(3):
control_modules.append(car._id(f'gpio_control_bidir_2[{i}]',False))
return control_modules
"""read the control register and return a GPIO Mode it takes the path to the control reg"""
def gpio_control_reg_read(self,path:SimHandleBase) -> GPIO_MODE:
gpio_mgmt_en = path.mgmt_ena.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value
gpio_out_dis = path.gpio_outenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value
gpio_holdover = path.gpio_holdover.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value
gpio_in_dis = path.gpio_inenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value
gpio_mode_sel = path.gpio_ib_mode_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value
gpio_anlg_en = path.gpio_ana_en.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value
gpio_anlg_sel = path.gpio_ana_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value
gpio_anlg_pol = path.gpio_ana_pol.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value
gpio_slow_sel = path.gpio_slow_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value
gpio_vtrip_sel = path.gpio_vtrip_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value
gpio_dgtl_mode = path.gpio_dm.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value
control_reg = (gpio_mgmt_en | gpio_out_dis | gpio_holdover| gpio_in_dis | gpio_mode_sel | gpio_anlg_en
|gpio_anlg_sel|gpio_anlg_pol|gpio_slow_sel|gpio_vtrip_sel|gpio_dgtl_mode)
return(GPIO_MODE(control_reg))
"""read the control register and return a GPIO Mode it takes the path to the control reg"""
def gpio_control_reg_write(self,path:SimHandleBase,data) :
bits =common.int_to_bin_list(data,14)
path.mgmt_ena.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value]
path.gpio_outenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value]
path.gpio_holdover.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value]
path.gpio_inenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value]
path.gpio_ib_mode_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value]
path.gpio_ana_en.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value]
path.gpio_ana_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value]
path.gpio_ana_pol.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value]
path.gpio_slow_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value]
path.gpio_vtrip_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value]
gpio_dm =bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value:MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value+3]
gpio_dm =sum(d * 2**i for i, d in enumerate(gpio_dm)) # convert list to binary int
path.gpio_dm.value = gpio_dm
# """drive the value of mprj bits with spicific data from input pad at the top"""
# def release_gpio(self):
# io = self.caravel_hdl.padframe.mprj_pads.io
# mprj , n_bits = common.signal_valueZ_size(io)
# io.value = mprj
# cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
"""drive the value of mprj bits with spicific data from input pad at the top"""
def drive_gpio_in(self,bits,data):
# io = self.caravel_hdl.padframe.mprj_pads.io
# mprj , n_bits = common.signal_value_size(io)
# cocotb.log.debug(f' [caravel] before mprj with {mprj} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
# mprj[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
# io.value = mprj
# cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}')
data_bits = []
is_list = isinstance(bits, (list,tuple))
if is_list :
cocotb.log.debug(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0]<bits[1]))
for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
self.dut._id(f"bin{bits2}",False).value = data_bits[i]
self.dut._id(f"bin{bits2}_en",False).value = 1
cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits2} with {data_bits[i]} and bin{bits2}_en with 1')
else:
self.dut._id(f'bin{bits}',False).value = data
self.dut._id(f'bin{bits}_en',False).value = 1
cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1')
""" release driving the value of mprj bits """
def release_gpio(self,bits):
data_bits = []
is_list = isinstance(bits, (list,tuple))
if is_list :
cocotb.log.debug(f'[caravel] [drive_gpio_disable] start bits[1] = {bits[1]} bits[0]= {bits[0]}')
for i,bits2 in enumerate(range(bits[1],bits[0]+1)):
self.dut._id(f"bin{bits2}_en",False).value = 0
cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits2}')
else:
self.dut._id(f'bin{bits}_en',False).value = 0
cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits}')
"""drive the value of gpio management"""
def drive_mgmt_gpio(self,data):
mgmt_io = self.dut.gpio_tb
mgmt_io.value = data
cocotb.log.info(f' [caravel] drive_mgmt_gpio through management area mprj with {data}')
"""update the value of mprj bits with spicific data then after certain number of cycle drive z to free the signal"""
async def drive_gpio_in_with_cycles(self,bits,data,num_cycles):
self.drive_gpio_in(bits,data)
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
"""drive the value of mprj bits with spicific data from management area then after certain number of cycle drive z to free the signal"""
async def drive_mgmt_gpio_with_cycles(self,bits,data,num_cycles):
self.drive_mgmt_gpio(bits,data)
cocotb.log.info(f' [caravel] wait {num_cycles} cycles')
await cocotb.start(self.wait_then_undrive(bits,num_cycles))
cocotb.log.info(f' [caravel] finish drive_gpio_with_in_cycles ')
async def wait_then_undrive(self,bits,num_cycles):
await ClockCycles(self.clk, num_cycles)
n_bits = bits[0]-bits[1]+1
self.drive_gpio_in(bits, (n_bits)* 'z')
cocotb.log.info(f' [caravel] finish wait_then_drive ')
async def hk_write_byte(self, data):
self.path = self.dut.mprj_io_tb
data_bit = BinaryValue(value = data , n_bits = 8,bigEndian=False)
for i in range(7,-1,-1):
await FallingEdge(self.clk)
#common.drive_hdl(self.path,[(4,4),(2,2)],[0,int(data_bit[i])]) # 2 = SDI 4 = SCK
self.drive_gpio_in((2,2),int(data_bit[i]))
self.drive_gpio_in((4,4),0)
await RisingEdge(self.clk)
self.drive_gpio_in((4,4),1)
await FallingEdge(self.clk)
""" read byte using housekeeping spi
when writing to SCK we can't use mprj[4] as there is a limitation in cocotb for accessing pack array #2587
so use back door access to write the clock then read the output from the SDO mprj[1] value"""
async def hk_read_byte(self,last_read= False):
read_data =''
for i in range(8,0,-1):
self.drive_gpio_in((4,4),1)# SCK
await FallingEdge(self.clk)
self.drive_gpio_in((4,4),0)# SCK
await RisingEdge(self.clk)
read_data= f'{read_data}{self.dut.mprj_io_tb.value[37-1]}'
await FallingEdge(self.clk)
self.drive_gpio_in((4,4),0) # SCK
# if (last_read):
# common.drive_hdl(self.dut.bin4_en,(0,0),'z') #4 = SCK
# common.drive_hdl(self.path,[(1,1)],'z')
return int(read_data,2)
"""write to the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
async def hk_write_backdoor(self,addr, data):
await RisingEdge(self.dut.wb_clk_i)
self.hk_hdl.wb_stb_i.value = 1
self.hk_hdl.wb_cyc_i.value = 1
self.hk_hdl.wb_sel_i.value = 0xF
self.hk_hdl.wb_we_i.value = 1
self.hk_hdl.wb_adr_i.value = addr
self.hk_hdl.wb_dat_i.value = data
cocotb.log.info(f'Monitor: Start Writing to {hex(addr)} -> {data}')
await FallingEdge(self.dut.wb_ack_o) # wait for acknowledge
self.hk_hdl.wb_stb_i.value = 0
self.hk_hdl.wb_cyc_i.value = 0
cocotb.log.info(f'Monitor: End writing {hex(addr)} -> {data}')
"""read from the house keeping registers by back door no need for commands and waiting for the data to show on mprj"""
async def hk_read_backdoor(self,addr):
await RisingEdge(self.clk)
self.hk_hdl.wb_stb_i.value = 1
self.hk_hdl.wb_cyc_i.value = 1
self.hk_hdl.wb_sel_i.value = 0
self.hk_hdl.wb_we_i.value = 0
self.hk_hdl.wb_adr_i.value = addr
cocotb.log.info(f' [housekeeping] Monitor: Start reading from {hex(addr)}')
await FallingEdge(self.hk_hdl.wb_ack_o)
self.hk_hdl.wb_stb_i.value = 0
self.hk_hdl.wb_cyc_i.value = 0
cocotb.log.info(f' [housekeeping] Monitor: read from {hex(addr)} value {(self.hk_hdl.wb_dat_o.value)}')
return self.hk_hdl.wb_dat_o.value

79
verilog/dv/cocotb/interfaces/common.py Normal file
View File

@ -0,0 +1,79 @@
from cocotb.handle import SimHandleBase
from cocotb.binary import BinaryValue
from enum import Enum
import cocotb
"""return the value and the size of the signal"""
def signal_value_size(path:SimHandleBase):
value = path.value
size = value.n_bits
return value, size
"""
Create a binaryValue object with all Z that helps when drive to drive only the bits needed
return value with all z and the size
"""
def signal_valueZ_size(path:SimHandleBase):
value = path.value
size = value.n_bits
value = BinaryValue(value = int(size) * 'z',n_bits=size)
return value, size
def int_to_bin_list(number:bin,number_of_bits)-> list:
data = bin(number)
data = data[2:].zfill(number_of_bits)[::-1]
bits = [int(bit) for bit in data]
return bits
def drive_hdl(path,bits,data):
hdl , n_bits = signal_value_size(path)
is_list_of_lists = all(isinstance(x, list) for x in bits)
is_list_of_tuples = all(isinstance(x, tuple) for x in bits)
if is_list_of_lists | is_list_of_tuples:
for i,bits2 in enumerate(bits):
hdl[n_bits-1-bits2[0]:n_bits-1-bits2[1]] = data[i]
else:
hdl[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
path.value = hdl
cocotb.log.debug(f' [common] drive { path._path } with {hdl}')
"""Enum for GPIO modes valus used to configured the pins"""
class GPIO_MODE(Enum):
GPIO_MODE_MGMT_STD_INPUT_NOPULL = 0x0403
GPIO_MODE_MGMT_STD_INPUT_PULLDOWN = 0x0803
GPIO_MODE_MGMT_STD_INPUT_PULLUP = 0x0c03
GPIO_MODE_MGMT_STD_OUTPUT = 0x1809
GPIO_MODE_MGMT_STD_INPUT = 0x1803 # TODO: ask if this legal the default value for first 2 bin is like that
GPIO_MODE_MGMT_STD_BIDIRECTIONAL = 0x1801
GPIO_MODE_MGMT_STD_ANALOG = 0x000b
GPIO_MODE_USER_STD_INPUT_NOPULL = 0x0402
GPIO_MODE_USER_STD_INPUT_PULLDOWN = 0x0802
GPIO_MODE_USER_STD_INPUT_PULLUP = 0x0c02
GPIO_MODE_USER_STD_OUTPUT = 0x1808
GPIO_MODE_USER_STD_BIDIRECTIONAL = 0x1800
GPIO_MODE_USER_STD_OUT_MONITORED = 0x1802
GPIO_MODE_USER_STD_ANALOG = 0x000a
class MASK_GPIO_CTRL(Enum):
MASK_GPIO_CTRL_MGMT_EN = 0
MASK_GPIO_CTRL_OUT_DIS = 1
MASK_GPIO_CTRL_OVERRIDE = 2
MASK_GPIO_CTRL_INP_DIS = 3
MASK_GPIO_CTRL_MOD_SEL = 4
MASK_GPIO_CTRL_ANLG_EN = 5
MASK_GPIO_CTRL_ANLG_SEL = 6
MASK_GPIO_CTRL_ANLG_POL = 7
MASK_GPIO_CTRL_SLOW = 8
MASK_GPIO_CTRL_TRIP = 9
MASK_GPIO_CTRL_DGTL_MODE = 10
Macros= {}
def fill_macros(macros_hdl):
Macros['MPRJ_IO_PADS_1'] = macros_hdl.MPRJ_IO_PADS_1.value.integer
Macros['MPRJ_IO_PADS_2'] = macros_hdl.MPRJ_IO_PADS_2.value.integer
Macros['MPRJ_IO_PADS'] = macros_hdl.MPRJ_IO_PADS.value.integer
Macros['GL'] = macros_hdl.GL.value.integer

232
verilog/dv/cocotb/interfaces/cpu.py Normal file
View File

@ -0,0 +1,232 @@
from operator import add
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
import cocotb.simulator
from cocotb.handle import SimHandleBase
from cocotb.handle import Force
from cocotb_coverage.coverage import *
from cocotb.binary import BinaryValue
import enum
from cocotb.handle import (
ConstantObject,
HierarchyArrayObject,
HierarchyObject,
ModifiableObject,
NonHierarchyIndexableObject,
SimHandle,
)
from itertools import groupby, product
import interfaces.common as common
from interfaces.common import GPIO_MODE
from interfaces.common import MASK_GPIO_CTRL
from interfaces.common import Macros
class RiskV:
def __init__(self,dut:SimHandleBase):
self.dut = dut
self.clk = dut.clock_tb
if not Macros['GL']:
self.cpu_hdl = dut.uut.soc.core.VexRiscv
else:
self.cpu_hdl = dut.uut.soc.core
self.debug_hdl = dut.uut.mprj.debug
self.force_reset = 0
cocotb.scheduler.add(self.force_reset_fun())
""" """
async def drive_data_with_address(self,address,data,SEL=0xF):
self.cpu_hdl.dBusWishbone_CYC.value = 1
self.cpu_hdl.iBusWishbone_CYC.value = 0
self.cpu_hdl.dBusWishbone_STB.value = 1
self.cpu_hdl.dBusWishbone_WE.value = 1
self.cpu_hdl.dBusWishbone_SEL.value = SEL
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
await ClockCycles(self.clk, 1)
self.cpu_hdl.dBusWishbone_CYC.value = BinaryValue(value = 'z')
self.cpu_hdl.iBusWishbone_CYC.value = BinaryValue(value = 'z')
self.cpu_hdl.dBusWishbone_STB.value = BinaryValue(value = 'z')
self.cpu_hdl.dBusWishbone_WE.value = BinaryValue(value = 'z')
self.cpu_hdl.dBusWishbone_SEL.value = BinaryValue(value = 'zzzz')
self.cpu_hdl.dBusWishbone_ADR.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_ADR)[0]
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_DAT_MOSI)[0]
""" """
async def drive_data2address(self,address,data,SEL=0xF):
cocotb.log.info(f"[RiskV][drive_data2address] start driving address {hex(address)} with {hex(data)}")
# print(dir(self.cpu_hdl))
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
if not Macros['GL']:
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
if not Macros['GL']:
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
else:
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
if not Macros['GL']:
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
self.cpu_hdl.dBusWishbone_CYC.value = 1
if not Macros['GL']:
self.cpu_hdl.iBusWishbone_CYC.value = 0
self.cpu_hdl.dBusWishbone_STB.value = 1
self.cpu_hdl.dBusWishbone_WE.value = 1
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_SEL.value = SEL
else:
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
self.cpu_hdl.net848.value = (SEL >>2 ) &1
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
else:
address_temp = address >> 2
for i in range(30):
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data
else:
for i in range(32):
self.cpu_hdl._id(f'dBusWishbone_DAT_MOSI[{i}]',False).value = (data >> i) & 1
if not Macros['GL']:
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
else:
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
await ClockCycles(self.clk, 1)
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
await ClockCycles(self.clk, 1)
cocotb.log.info(f"[RiskV][drive_data2address] finish driving address {hex(address)} with {hex(data)}")
""" """
async def read_address(self,address,SEL=0xF):
cocotb.log.info(f"[RiskV][read_address] start reading address {hex(address)}")
# print(dir(self.cpu_hdl))
dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value
if not Macros['GL']:
iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value
dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value
dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value
if not Macros['GL']:
dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value
else:
dBusWishbone_SEL0 = self.cpu_hdl.net2121.value
dBusWishbone_SEL1 = self.cpu_hdl.net1979.value
dBusWishbone_SEL2 = self.cpu_hdl.net848.value
dBusWishbone_SEL3 = self.cpu_hdl.net1956.value
if not Macros['GL']:
dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value
dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value
self.cpu_hdl.dBusWishbone_CYC.value = 1
if not Macros['GL']:
self.cpu_hdl.iBusWishbone_CYC.value = 0
self.cpu_hdl.dBusWishbone_STB.value = 1
self.cpu_hdl.dBusWishbone_WE.value = 0
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_SEL.value = SEL
else:
self.cpu_hdl.net2121.value = (SEL >>0 ) &1
self.cpu_hdl.net1979.value = (SEL >>1 ) &1
self.cpu_hdl.net848.value = (SEL >>2 ) &1
self.cpu_hdl.net1956.value = (SEL >>3 ) &1
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_ADR.value = address >> 2
else:
address_temp = address >> 2
for i in range(30):
self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1
if not Macros['GL']:
await RisingEdge(self.cpu_hdl.dBusWishbone_ACK)
else:
# await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False)))
await RisingEdge(self.cpu_hdl._id("_07019_",False) )
await ClockCycles(self.clk, 1)
self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC
if not Macros['GL']:
self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR
self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI
self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC
self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB
self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE
self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL
data = self.cpu_hdl.dBusWishbone_DAT_MISO.value
await ClockCycles(self.clk, 1)
cocotb.log.info(f"[RiskV][read_address] finish reading address {hex(address)} data = {data}")
# return data
return int(str(bin(data.integer)[2:]).zfill(32),2)
# return int(str(bin(data.integer)[2:]).zfill(32)[::-1],2)
def read_debug_reg1(self):
return self.debug_hdl.debug_reg_1.value.integer
def read_debug_reg2(self):
return self.debug_hdl.debug_reg_2.value.integer
# writing debug registers using backdoor because in GL cpu can't be disabled for now because of different netlist names
def write_debug_reg1_backdoor(self,data):
self.debug_hdl.debug_reg_1.value = data
def write_debug_reg2_backdoor(self,data):
self.debug_hdl.debug_reg_2.value = data
async def force_reset_fun(self):
first_time_force = True
first_time_release = True
while True:
if self.force_reset:
if first_time_force:
cocotb.log.info(f"[RiskV][force_reset_fun] Force CPU reset")
first_time_force = False
first_time_release = True
self.cpu_hdl.reset.value =1
if not Macros['GL']:
common.drive_hdl(self.cpu_hdl.reset,(0,0),1)
else:
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),1)
else:
if first_time_release:
first_time_force = True
first_time_release = False
if not Macros['GL']:
common.drive_hdl(self.cpu_hdl.reset,(0,0),0)
else:
common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),0)
cocotb.log.info(f"[RiskV][force_reset_fun] release CPU reset")
await ClockCycles(self.clk, 1)
def cpu_force_reset(self):
self.force_reset = True
def cpu_release_reset(self):
self.force_reset = False

87
verilog/dv/cocotb/interfaces/defsParser.py Normal file
View File

@ -0,0 +1,87 @@
import re
import sys
from tokenize import group
from unittest.util import _MIN_COMMON_LEN
import string
import cocotb
import os
class Regs:
def __init__(self):
pass
def get_addr(self,reg):
search1 = self.get_add_defs(reg)
# if all(c in string.hexdigits for c in search1[2:]):
return int(search1,16)
# return hex(self.get_hexa(search1))
"""get address from defs.h"""
def get_add_defs(self,reg):
pattern = re.compile(rf'#define {reg}\s*\(\*\(volatile uint32_t\*\)\s*(.*)\s*\)')
with open(f'{os.getenv("FIRMWARE_PATH")}/defs.h') as f:
for line in f:
m= re.search(pattern,line)
if m:
break
if m:
if not all(c in string.hexdigits for c in m.group(1)):
return hex(self.get_hexa(m.group(1)))
else:
return m.group(1)
else:
cocotb.log.info(f" [defsParser] can't find {reg} inside defs")
sys.exit()
"""get address from defs.h"""
def get_add_csr(self,reg):
pattern1 = re.compile(rf'#define {reg}\s*\(\*\(volatile uint32_t\*\)\s*(.*)\s*\)')
pattern2 = re.compile(rf'#define {reg}\s*(.*)')
m = False
with open(f'{os.getenv("FIRMWARE_PATH")}/../generated/csr.h') as f:
for line in f:
m1= re.search(pattern1,line)
m2= re.search(pattern2,line)
if m1:
m = m1
break
if m2:
m=m2
break
if m:
matched_str= m.group(1)
if matched_str[-1] == "L" and matched_str[-2].isnumeric:
matched_str = matched_str[:-1]
if not all(c in string.hexdigits for c in matched_str[2:]):
matched_str= hex(self.get_hexa(matched_str))
return matched_str
else:
cocotb.log.info(f" [defsParser] can't find {reg} inside csr")
sys.exit()
def get_hexa(self,s:string):
pattern2 = re.compile(r'\((.*)\s*\+\s*(.*)\)')
search_match = re.search(pattern2,s)
if search_match :
matches = [search_match.group(1),search_match.group(2)]
else:
matches = [s]
nothex = 1
while nothex:
nothex = 0
for i,match in enumerate(matches):
if not all(c in string.hexdigits for c in match[2:-1]):
matches[i]=self.get_add_csr(match)
nothex = 0
else:
if match[-1] == "L" and match[-2].isnumeric:
matches[i]=matches[i][:-1]
if len(matches) ==2:
return int(matches[0],16) + int(matches[1],16)
else:
return int(matches[0],16)

84
verilog/dv/cocotb/interfaces/logic_analyzer.py Normal file
View File

@ -0,0 +1,84 @@
import random
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
import cocotb.simulator
from cocotb.handle import SimHandleBase
from cocotb.handle import Force
from cocotb_coverage.coverage import *
from cocotb.binary import BinaryValue
import enum
from cocotb.handle import (
ConstantObject,
HierarchyArrayObject,
HierarchyObject,
ModifiableObject,
NonHierarchyIndexableObject,
SimHandle,
)
from itertools import groupby, product
import interfaces.common as common
from interfaces.common import GPIO_MODE
from interfaces.common import MASK_GPIO_CTRL
from interfaces.common import Macros
class LA:
def __init__(self,dut:SimHandleBase):
self.dut = dut
self.clk = dut.clock_tb
self.core_hdl = dut.uut.soc.core
""" Configure the value of LA probes [0:127]
writing 1 to any bit means bit acts as outputs from the cpu
writing 0 to any bit means bit acts as inputs to the cpu """
async def configure_la_en(self, bits,data):
self.__drive_la_iena(bits,data)
self.__drive_la_oenb(bits,data)
await ClockCycles(self.clk, 1)
def __drive_la_iena(self, bits,data):
iena , n_bits = common.signal_value_size(self.core_hdl.la_ien_storage)
cocotb.log.debug(f' [LA] before change iena with {iena} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
iena[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
self.core_hdl.la_ien_storage.value = iena
cocotb.log.info(f' [LA] drive reg_la_iena with {hex(iena)}')
def __drive_la_oenb(self, bits,data):
oenb , n_bits = common.signal_value_size(self.core_hdl.la_oe_storage)
cocotb.log.debug(f' [LA] before change oenb with {oenb} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
oenb[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
self.core_hdl.la_oe_storage.value = oenb
cocotb.log.info(f' [LA] drive reg_la_oenb with {hex(oenb)}')
""" update the value of LA data input from cpu to user project """
def drive_la_data_to_user(self,bits,data):
la , n_bits = common.signal_value_size(self.core_hdl.la_out_storage)
cocotb.log.debug(f' [LA] before la data update with LA ={la} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]')
la[n_bits-1-bits[0]:n_bits-1-bits[1]] = data
self.core_hdl.la_out_storage.value = la
cocotb.log.info(f' [LA] drive_la_data_to_user: drive data {hex(la)} to user project')
"""return the value of LA data output from user project tp cpu"""
def check_la_user_out(self):
LA_out = self.core_hdl.la_input.value
if(LA_out.is_resolvable):
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}')
else:
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}')
return LA_out
"""return the value of LA data output from user project tp cpu"""
def check_la_ctrl_reg(self):
LA_out = self.dut.uut.la_oenb_mprj.value
if(LA_out.is_resolvable):
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}')
else:
cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}')
return LA_out

1
verilog/dv/cocotb/pli.tab Normal file
View File

@ -0,0 +1 @@
acc+=rw,wn:*

263
verilog/dv/cocotb/tests.json Normal file
View File

@ -0,0 +1,263 @@
{
"Tests": {
"_comment0" :"level is priorty of the test low is better, SW spcify if the test uses SW, RTL regressions run this test in RTL ",
"_comment1" :"GL regressions run this test in gatelevel, GL_SDF regression run this test with SDF included"
,"bitbang_no_cpu_all_o" :{"level":0,
"SW":false,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":[],
"GL_SDF":[],
"description":"test disable CPU and control the wishbone to configure gpio[4:37] as mgmt output using bitbang and check them"}
,"bitbang_cpu_all_o" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt output using bitbang and check them"}
,"gpio_all_o" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt output using automatic approach firmware and check them"}
,"gpio_all_o_user" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as user output using automatic approach firmware and check them"}
,"gpio_all_i" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt input using automatic approach firmware and check them"}
,"gpio_all_i_pu" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them"}
,"gpio_all_i_pd" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them"}
,"gpio_all_bidir" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"configure all gpios as mgmt bidir using automatic approach firmware and check them"}
,"bitbang_cpu_all_10" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"shift all the register with 10"}
,"bitbang_cpu_all_01" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"shift all the register with 01"}
,"bitbang_cpu_all_1100" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"shift all the register with 1100"}
,"bitbang_cpu_all_0011" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"shift all the register with 0011"}
,"bitbang_no_cpu_all_i" :{"level":0,
"SW":false,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":[],
"GL_SDF":[],
"description":"test disable CPU and control the wishbone to configure gpio[0:31] as mgmt input using bitbang and check them"}
,"bitbang_cpu_all_i" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":" configure gpio[0:37] as mgmt input using bitbang and check them"}
,"bitbang_spi_o" :{"level":0,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"SW":true,
"description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"}
,"bitbang_spi_i" :{"level":0,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"SW":true,
"description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"}
,"hk_regs_wr_wb_cpu" :{"level":0,
"SW":false,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"bit bash test for housekeeping registers"}
,"hk_regs_wr_wb" :{"level":0,
"SW":false,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"write then read (the written value) from random housekeeping registers through the firmware but without using CPU, the SPI and system regs can't be read using firmware so the test only GPIO regs inside housekeeping "}
,"hk_regs_wr_spi" :{"level":0,
"SW":false,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"write then read(the written value) from random housekeeping registers through the SPI housekeeping"}
,"hk_regs_rst_spi" :{"level":0,
"SW":false,
"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"check reset value of house keeping registers by reading them trough the spi housekeeping"}
,"helloWorld" :{"level":3,
"SW":false,
"RTL":[],
"GL":[],
"GL_SDF":[],
"description":"hello world test"}
,"cpu_stress" :{"level":2,
"SW":true,
"RTL":["r_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"stress the cpu with heavy processing"}
,"mem_stress" :{"level":2,
"SW":true,
"RTL":["r_rtl","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"Memory stress tests write and read from 800 bytes 200 words and 400 half words"}
,"IRQ_external" :{"level":2,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"test external interrupt by mprj 7"}
,"IRQ_timer" :{"level":2,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"test timer0 interrupt"}
,"IRQ_uart" :{"level":2,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"test timer0 interrupt"}
,"mgmt_gpio_out" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"tests blinking of mgmt gpio bit as an output"}
,"mgmt_gpio_in" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"tests blinking of mgmt gpio bit as an output"}
,"mgmt_gpio_bidir" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"send random number of blinks through mgmt_gpio and expect to recieve the same number back "}
,"timer0_oneshot" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"check timer0 oneshot mode"}
,"timer0_periodic" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"check timer0 periodic mode"}
,"uart_tx" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"test uart transmit"}
,"uart_rx" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"test uart reception"}
,"uart_loopback" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"test uart in loopback mode input and output is shorted"}
,"spi_master_rd" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"using SPI master for reading from external memory"}
,"spi_master_temp" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"To be deleted"}
,"user_pass_thru_rd" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"use the housekeeping spi in user pass thru mode to read from external mem"}
,"pll" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"Check pll diffrent configuration"}
,"clock_redirect" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"check clock redirect is working as expected"}
,"hk_disable" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"check Housekeeping SPI disable register is working"}
,"la" :{"level":0,
"SW":true,
"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
"GL":["r_gl","nightly","weekly","tape_out"],
"GL_SDF":["r_sdf","weekly","tape_out"],
"description":"check logic analyzer input and output enable"}
}
}

62
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_0011.c Normal file
View File

@ -0,0 +1,62 @@
#include <defs.h>
#include <stub.c>
#include "bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = 0x1803 ;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
for(int i =0;i<19*13;i++){
clock00();
clock00();
clock11();
clock11();
}
reg_debug_1 = 0xFF; // finish configuration
}

60
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_01.c Normal file
View File

@ -0,0 +1,60 @@
#include <defs.h>
#include <stub.c>
#include "bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = 0x1803 ;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
for(int i =0;i<19*13;i++){
clock00();
clock11();
}
reg_debug_1 = 0xFF; // finish configuration
}

60
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_10.c Normal file
View File

@ -0,0 +1,60 @@
#include <defs.h>
#include <stub.c>
#include "bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = 0x1803 ;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
for(int i =0;i<19*13;i++){
clock11();
clock00();
}
reg_debug_1 = 0xFF; // finish configuration
}

62
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_1100.c Normal file
View File

@ -0,0 +1,62 @@
#include <defs.h>
#include <stub.c>
#include "bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = 0x1803 ;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
for(int i =0;i<19*13;i++){
clock11();
clock11();
clock00();
clock00();
}
reg_debug_1 = 0xFF; // finish configuration
}

91
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_i.c Normal file
View File

@ -0,0 +1,91 @@
#include <defs.h>
#include <stub.c>
#include "bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = 0x1803;
reg_mprj_io_36 = 0x1803;
reg_mprj_io_35 = 0x1803;
reg_mprj_io_34 = 0x1803;
reg_mprj_io_33 = 0x1803;
reg_mprj_io_32 = 0x1803;
reg_mprj_io_31 = 0x1803;
reg_mprj_io_30 = 0x1803;
reg_mprj_io_29 = 0x1803;
reg_mprj_io_28 = 0x1803;
reg_mprj_io_27 = 0x1803;
reg_mprj_io_26 = 0x1803;
reg_mprj_io_25 = 0x1803;
reg_mprj_io_24 = 0x1803;
reg_mprj_io_23 = 0x1803;
reg_mprj_io_22 = 0x1803;
reg_mprj_io_21 = 0x1803;
reg_mprj_io_20 = 0x1803;
reg_mprj_io_19 = 0x1803;
reg_mprj_io_18 = 0x1803;
reg_mprj_io_17 = 0x1803;
reg_mprj_io_16 = 0x1803;
reg_mprj_io_15 = 0x1803;
reg_mprj_io_14 = 0x1803;
reg_mprj_io_13 = 0x1803;
reg_mprj_io_12 = 0x1803;
reg_mprj_io_11 = 0x1803;
reg_mprj_io_10 = 0x1803;
reg_mprj_io_9 = 0x1803;
reg_mprj_io_8 = 0x1803;
reg_mprj_io_7 = 0x1803;
reg_mprj_io_6 = 0x1803;
reg_mprj_io_5 = 0x1803;
reg_mprj_io_4 = 0x1803;
reg_mprj_io_3 = 0x1803;
reg_mprj_io_2 = 0x1803;
reg_mprj_io_1 = 0x1803;
reg_mprj_io_0 = 0x1803;
reg_mprj_io_0 = 0x1803;
// bitbang
//Configure all as input except reg_mprj_io_3
clock_in_right_i_left_i_standard(0); // 18 and 19
clock_in_right_i_left_i_standard(0); // 17 and 20
clock_in_right_i_left_i_standard(0); // 16 and 21
clock_in_right_i_left_i_standard(0); // 15 and 22
clock_in_right_i_left_i_standard(0); // 14 and 23
clock_in_right_i_left_i_standard(0); // 13 and 24
clock_in_right_i_left_i_standard(0); // 12 and 25
clock_in_right_i_left_i_standard(0); // 11 and 26
clock_in_right_i_left_i_standard(0); // 10 and 27
clock_in_right_i_left_i_standard(0); // 9 and 28
clock_in_right_i_left_i_standard(0); // 8 and 29
clock_in_right_i_left_i_standard(0); // 7 and 30
clock_in_right_i_left_i_standard(0); // 6 and 31
clock_in_right_i_left_i_standard(0); // 5 and 32
clock_in_right_i_left_i_standard(0); // 4 and 33
clock_in_right_i_left_i_standard(0); // 3 and 34
clock_in_right_i_left_i_standard(0); // 2 and 35
clock_in_right_i_left_i_standard(0); // 1 and 36
clock_in_right_i_left_i_standard(0); // 0 and 37
load(); // load
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
while (reg_mprj_datal != 0x8F66FD7B);
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
while (reg_mprj_datal != 0xFFA88C5A);
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
while (reg_mprj_datal != 0xC9536346);
reg_debug_1 = 0XD1;
while (reg_mprj_datah != 0x3F);
reg_debug_1 = 0XD2;
while (reg_mprj_datah != 0x0);
reg_debug_1 = 0XD3;
while (reg_mprj_datah != 0x15);
reg_debug_1 = 0XD4;
while (reg_mprj_datah != 0x2A);
reg_debug_2 = 0xFF;
}

99
verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c Normal file
View File

@ -0,0 +1,99 @@
#include <defs.h>
#include <stub.c>
#include "bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = 0x1803 ;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
// bitbang
// Configure all as output except reg_mprj_io_3
clock_in_right_o_left_o_standard(0); // 18 and 19
clock_in_right_o_left_o_standard(0); // 17 and 20
clock_in_right_o_left_o_standard(0); // 16 and 21
clock_in_right_o_left_o_standard(0); // 15 and 22
clock_in_right_o_left_o_standard(0); // 14 and 23
clock_in_right_o_left_o_standard(0); // 13 and 24
clock_in_right_o_left_o_standard(0); // 12 and 25
clock_in_right_o_left_o_standard(0); // 11 and 26
clock_in_right_o_left_o_standard(0); // 10 and 27
clock_in_right_o_left_o_standard(0); // 9 and 28
clock_in_right_o_left_o_standard(0); // 8 and 29
clock_in_right_o_left_o_standard(0); // 7 and 30
clock_in_right_o_left_o_standard(0); // 6 and 31
clock_in_right_o_left_o_standard(0); // 5 and 32
clock_in_right_o_left_o_standard(0); // 4 and 33
clock_in_right_o_left_i_standard(0); // 3 and 34
clock_in_right_o_left_o_standard(0); // 2 and 35
clock_in_right_o_left_o_standard(0); // 1 and 36
clock_in_right_o_left_o_standard(0); // 0 and 37
load();
reg_debug_1 = 0xFF; // finish configuration
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_datah = i;
reg_debug_2 = 37-j;
reg_mprj_datah = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_datah = 0x3f;
reg_mprj_datal = i;
reg_debug_2 = 32-j;
reg_mprj_datah = 0x00;
reg_mprj_datal = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
}

325
verilog/dv/cocotb/tests/bitbang/bitbang_functions.c Normal file
View File

@ -0,0 +1,325 @@
void clock11()
{
reg_mprj_xfer = 0x66; reg_mprj_xfer = 0x76;
}
void clock00()
{
reg_mprj_xfer = 0x06; reg_mprj_xfer = 0x16;
}
// --------------------------------------------------------
void clock10()
{
reg_mprj_xfer = 0x46; reg_mprj_xfer = 0x56;
}
void clock01()
{
reg_mprj_xfer = 0x26; reg_mprj_xfer = 0x36;
}
// --------------------------------------------------------
// Load registers
// --------------------------------------------------------
void load()
{
reg_mprj_xfer = 0x06;
reg_mprj_xfer = 0x0e; reg_mprj_xfer = 0x06; // Apply load
}
// --------------------------------------------------------
// Enable bit-bang mode and clear registers
// --------------------------------------------------------
void clear_registers()
{
reg_mprj_xfer = 0x06; // Enable bit-bang mode
reg_mprj_xfer = 0x04; reg_mprj_xfer = 0x06; // Pulse reset
}
// --------------------------------------------------------
// Clock in an input + output configuration. The value
// passed in "ddhold" is the number of data-dependent hold
// violations up to this point.
// --------------------------------------------------------
/* Clock in data on the left side. Assume standard hold
* violation, so clock in12 times and assume that the
* next data to be clocked will start with "1", enforced
* by the code.
*
* Left side = GPIOs 37 to19
*/
void clock_in_left_short(uint32_t ddhold)
{
uint32_t count;
uint32_t holds = ddhold;
clock10();
clock10();
for (count = 0; count < 9; count++) {
if (holds != 0) {
clock10();
holds--;
}
else
clock00();
}
clock00();
}
/* Clock in data on the right side. Assume standard hold
* violation, so clock in12 times and assume that the
* next data to be clocked will start with "1", enforced
* by the code.
*
* Right side = GPIOs 0 to18
*/
void clock_in_right_short(uint32_t ddhold)
{
uint32_t count;
uint32_t holds = ddhold;
clock01();
clock01();
for (count = 0; count < 9; count++) {
if (holds != 0) {
clock01();
holds--;
}
else
clock00();
}
clock00();
}
/* Clock in data on the left side. Clock the normal13 times,
* which is correct for no hold violation or for a data-
* dependent hold violation (for the latter, ddhold must be
* incremented before calling the subroutine).
*
* Left side = GPIOs 37 to19
*/
void clock_in_left_standard(uint32_t ddhold){
uint32_t count;
uint32_t holds = ddhold;
clock10();
clock10();
for (count = 0; count < 7; count++) {
if (holds != 0) {
clock10();
holds--;
}
else
clock00();
}
clock10();
clock00();
clock00();
clock10();
}
void clock_in_right_o_left_o_standard(uint32_t ddhold){
uint32_t count;
uint32_t holds = ddhold;
clock11();
clock11();
for (count = 0; count < 7; count++) {
if (holds != 0) {
clock11();
holds--;
}
else
clock00();
}
clock11();
clock00();
clock00();
clock11();
}
void clock_in_right_o_left_i_standard(uint32_t ddhold){
uint32_t count;
uint32_t holds = ddhold;
clock11();
clock11();
for (count = 0; count < 7; count++) {
if (holds != 0) {
clock11();
holds--;
}
else
clock00();
}
clock10();
clock00();
clock01();
clock11();
}
void clock_in_right_i_left_o_standard(uint32_t ddhold){
uint32_t count;
uint32_t holds = ddhold;
clock11();
clock11();
for (count = 0; count < 7; count++) {
if (holds != 0) {
clock11();
holds--;
}
else
clock00();
}
clock01();
clock00();
clock10();
clock11();
}
void clock_in_right_i_left_i_standard(uint32_t ddhold){
uint32_t count;
uint32_t holds = ddhold;
clock11();
clock11();
for (count = 0; count < 7; count++) {
if (holds != 0) {
clock11();
holds--;
}
else
clock00();
}
clock00();
clock00();
clock11();
clock11();
}
/* Clock in data on the right side. Clock the normal13 times,
* which is correct for no hold violation or for a data-
* dependent hold violation (for the latter, ddhold must be
* incremented before calling the subroutine).
*
* Right side = GPIOs 0 to18
*/
void clock_in_right_standard(uint32_t ddhold){
uint32_t count;
uint32_t holds = ddhold;
clock11();
clock11();
for (count = 0; count < 7; count++) {
if (holds != 0) {
clock01();
holds--;
}
else
clock00();
}
clock10();
clock00();
clock01();
clock11();
}
void clock_in_right_i_left_io_standard(uint32_t ddhold){
uint32_t count;
uint32_t holds = ddhold;
clock11();
clock11();
for (count = 0; count < 7; count++) {
if (holds != 0) {
clock11();
holds--;
}
else
clock00();
}
clock01();
clock00();
clock11();
clock11();
}
// --------------------------------------------------------
// Clock in data for GPIO 0 and 37 (fixed) and apply load.
// --------------------------------------------------------
void clock_in_end(){
// Right side: GPIO 0 configured disabled
// Left side: GPIO 37 configured as input
clock11();
clock10();
clock00();
clock00();
clock00();
clock00();
clock00();
clock00();
clock00();
clock01();
clock00();
clock11();
clock11();
load();
}
// --------------------------------------------------------
// Same as above, except that GPIO is configured as an
// output for a quick sanity check.
// --------------------------------------------------------
void clock_in_end_output()
{
// Right side: GPIO 0 configured disabled
// Left side: GPIO 37 configured as output
clock11();
clock10();
clock00();
clock00();
clock00();
clock00();
clock00();
clock00();
clock00();
clock01();
clock00();
clock01();
clock11();
load();
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
}

355
verilog/dv/cocotb/tests/bitbang/bitbang_functions.py Normal file
View File

@ -0,0 +1,355 @@
from interfaces.defsParser import Regs
reg = Regs()
"""
reg_mprj_xfer contain
bit 0 : busy
bit 1 : bitbang enable
bit 2 : bitbang reset active low
bit 3 : bitbang load registers
bit 4 : bitbang clock
bit 5 : serial data 1
bit 6 : serial data 2
"""
"""shift the 2 registers with 2 ones"""
async def clock11(cpu):
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
await cpu.drive_data2address(reg_mprj_xfer_addr,0x66) # 0110_0110
await cpu.drive_data2address(reg_mprj_xfer_addr,0x76) # 0111_0110
"""shift the 2 registers with 2 zeros"""
async def clock00(cpu):
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # 0000_0110
await cpu.drive_data2address(reg_mprj_xfer_addr,0x16) # 0001_0110
"""shift the 2 registers with 1 in the left side and zero in right side"""
async def clock01(cpu):
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
await cpu.drive_data2address(reg_mprj_xfer_addr,0x26) # 0010_0110
await cpu.drive_data2address(reg_mprj_xfer_addr,0x36) # 0011_0110
"""shift the 2 registers with 1 in the left side and zero in right side"""
async def clock10(cpu):
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
await cpu.drive_data2address(reg_mprj_xfer_addr,0x46) # 0100_0110
await cpu.drive_data2address(reg_mprj_xfer_addr,0x56) # 0101_0110
"""enable the serial loader bit to load registers"""
async def load(cpu):
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
await cpu.drive_data2address(reg_mprj_xfer_addr,0x0e) # enable loader
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
"""Enable bit-bang mode and clear registers"""
async def clear_registers(cpu):
reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer')
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
await cpu.drive_data2address(reg_mprj_xfer_addr,0x04) # reset
await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang
"""
--------------------------------------------------------
Clock in an input + output configuration. The value
passed in "ddhold" is the number of data-dependent hold
violations up to this point.
--------------------------------------------------------
* Clock in data on the left side. Assume standard hold
* violation, so clock in 12 times and assume that the
* next data to be clocked will start with "1", enforced
* by the code.
*
* Left side = GPIOs 37 to 19
"""
async def clock_in_left_short(cpu,ddhold):
await clock10(cpu)
await clock10(cpu)
for i in range(9):
if ddhold != 0:
await clock10(cpu)
ddhold -=1
else:
await clock00(cpu)
await clock00(cpu)
async def clock_in_right_short(cpu,ddhold):
await clock01(cpu)
await clock01(cpu)
for i in range(9):
if ddhold != 0:
await clock01(cpu)
ddhold -=1
else:
await clock00(cpu)
await clock00(cpu)
async def clock_in_left_standard(cpu,ddhold):
await clock10(cpu)
await clock10(cpu)
for i in range(7):
if ddhold != 0:
await clock10(cpu)
ddhold -=1
else:
await clock00(cpu)
await clock10(cpu)
await clock00(cpu)
await clock00(cpu)
await clock10(cpu)
"""right output left input"""
async def clock_in_right_o_left_i_standard(cpu,ddhold):
await clock11(cpu)
await clock11(cpu)
for i in range(7):
if ddhold != 0:
await clock01(cpu)
ddhold -=1
else:
await clock00(cpu)
await clock10(cpu)
await clock00(cpu)
await clock01(cpu)
await clock11(cpu)
"""right input left output"""
async def clock_in_right_i_left_o_standard(cpu,ddhold):
await clock11(cpu)
await clock11(cpu)
for i in range(7):
if ddhold != 0:
await clock10(cpu)
ddhold -=1
else:
await clock00(cpu)
await clock01(cpu)
await clock00(cpu)
await clock10(cpu)
await clock11(cpu)
"""right input left output"""
async def clock_in_right_i_left_i_standard(cpu,ddhold):
await clock11(cpu)
await clock11(cpu)
for i in range(7):
if ddhold != 0:
await clock01(cpu)
ddhold -=1
else:
await clock00(cpu)
await clock00(cpu)
await clock00(cpu)
await clock11(cpu)
await clock11(cpu)
"""right output left output"""
async def clock_in_right_o_left_o_standard(cpu,ddhold):
await clock11(cpu)
await clock11(cpu)
for i in range(7):
if ddhold != 0:
await clock01(cpu)
ddhold -=1
else:
await clock00(cpu)
await clock11(cpu)
await clock00(cpu)
await clock00(cpu)
await clock11(cpu)
async def clock_in_end_output(cpu):
# Right side: GPIO 0 configured disabled
# /Left side: GPIO 37 configured as output
await clock11(cpu)
await clock11(cpu)
await clock00(cpu)
await clock00(cpu)
await clock00(cpu)
await clock00(cpu)
await clock00(cpu)
await clock00(cpu)
await clock00(cpu)
await clock00(cpu)
await clock00(cpu)
await clock01(cpu)
await clock11(cpu)
await load(cpu)
reg_mprj_io_37_addr = reg.get_addr('reg_mprj_io_37')
await cpu.drive_data2address(reg_mprj_io_37_addr,0x1809)
async def clock11_spi(caravelEnv):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x66) # Data = 0x01 (enable bit-bang mode)
await caravelEnv.disable_csb()
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x76) # 11
await caravelEnv.disable_csb()
async def clock00_spi(caravelEnv):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x06) # Data = 0x01 (enable bit-bang mode)
await caravelEnv.disable_csb()
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x16) # 00
await caravelEnv.disable_csb()
async def clock01_spi(caravelEnv):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x26) # Data = 0x01 (enable bit-bang mode)
await caravelEnv.disable_csb()
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x36) # 01
await caravelEnv.disable_csb()
async def clock10_spi(caravelEnv):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x46) # Data = 0x01 (enable bit-bang mode)
await caravelEnv.disable_csb()
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x56) # 10
await caravelEnv.disable_csb()
async def load_spi(caravelEnv):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x0e) # load enable
await caravelEnv.disable_csb()
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(0x16) # 00
await caravelEnv.disable_csb()
"""right output left input"""
async def clock_in_right_o_left_i_standard_spi(caravelEnv,ddhold):
await clock11_spi(caravelEnv)
await clock11_spi(caravelEnv)
for i in range(7):
if ddhold != 0:
await clock01_spi(caravelEnv)
ddhold -=1
else:
await clock00_spi(caravelEnv)
await clock10_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock01_spi(caravelEnv)
await clock11_spi(caravelEnv)
"""right input left output"""
async def clock_in_right_i_left_o_standard_spi(caravelEnv,ddhold):
await clock11_spi(caravelEnv)
await clock11_spi(caravelEnv)
for i in range(7):
if ddhold != 0:
await clock10_spi(caravelEnv)
ddhold -=1
else:
await clock00_spi(caravelEnv)
await clock01_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock10_spi(caravelEnv)
await clock11_spi(caravelEnv)
"""right input left output"""
async def clock_in_right_i_left_i_standard_spi(caravelEnv,ddhold):
await clock11_spi(caravelEnv)
await clock11_spi(caravelEnv)
for i in range(7):
if ddhold != 0:
await clock01_spi(caravelEnv)
ddhold -=1
else:
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock11_spi(caravelEnv)
await clock11_spi(caravelEnv)
"""right output left output"""
async def clock_in_right_o_left_o_standard_spi(caravelEnv,ddhold):
await clock11_spi(caravelEnv)
await clock11_spi(caravelEnv)
for i in range(7):
if ddhold != 0:
await clock01_spi(caravelEnv)
ddhold -=1
else:
await clock00_spi(caravelEnv)
await clock11_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock11_spi(caravelEnv)
async def clock_in_end_output_spi(caravelEnv):
# Right side: GPIO 0 configured disabled
# /Left side: GPIO 37 configured as output
await clock11_spi(caravelEnv)
await clock11_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock00_spi(caravelEnv)
await clock01_spi(caravelEnv)
await clock11_spi(caravelEnv)
await load_spi(caravelEnv)

10
verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu.c Normal file
View File

@ -0,0 +1,10 @@
#include <defs.h>
#include <stub.c>
// Empty C code
void main()
{
return;
}

10
verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_i.c Normal file
View File

@ -0,0 +1,10 @@
#include <defs.h>
#include <stub.c>
// Empty C code
void main()
{
return;
}

9
verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_o.c Normal file
View File

@ -0,0 +1,9 @@
#include <defs.h>
#include <stub.c>
// Empty C code
void main()
{
return;
}

72
verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c Normal file
View File

@ -0,0 +1,72 @@
#include <defs.h>
#include <stub.c>
// Empty C code
void main()
{
int i,j;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_debug_1 = 0xFF; // finish configuration
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
while (reg_mprj_datal != 0x8F66FD7B);
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
while (reg_mprj_datal != 0xFFA88C5A);
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
while (reg_mprj_datal != 0xC9536346);
reg_debug_1 = 0XD1;
while (reg_mprj_datah != 0x3F);
reg_debug_1 = 0XD2;
while (reg_mprj_datah != 0x0);
reg_debug_1 = 0XD3;
while (reg_mprj_datah != 0x15);
reg_debug_1 = 0XD4;
while (reg_mprj_datah != 0x2A);
reg_debug_2 = 0xFF;
}

78
verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c Normal file
View File

@ -0,0 +1,78 @@
#include <defs.h>
#include <stub.c>
// Empty C code
void main()
{
int i,j;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = 0x1803;
reg_mprj_io_3 = 0x1803;
reg_mprj_io_2 = 0x1803;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_debug_1 = 0xFF; // finish configuration
while (reg_debug_2 != 0xFF); // finish bit bang
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_datah = i;
reg_debug_2 = 37-j;
reg_mprj_datah = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_datah = 0x3f;
reg_mprj_datal = i;
reg_debug_2 = 32-j;
reg_mprj_datah = 0x00;
reg_mprj_datal = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
}

258
verilog/dv/cocotb/tests/bitbang/bitbang_tests.py Normal file
View File

@ -0,0 +1,258 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
reg = Regs()
@cocotb.test()
@repot_test
async def bitbang_no_cpu_all_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=10206)
cpu = RiskV(dut)
cpu.cpu_force_reset()
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
#Configure all as output except reg_mprj_io_3
await clear_registers(cpu)
await clock_in_right_o_left_o_standard(cpu,0) # 18 and 19
await clock_in_right_o_left_o_standard(cpu,0) # 17 and 20
await clock_in_right_o_left_o_standard(cpu,0) # 16 and 21
await clock_in_right_o_left_o_standard(cpu,0) # 15 and 22
await clock_in_right_o_left_o_standard(cpu,0) # 14 and 23
await clock_in_right_o_left_o_standard(cpu,0) # 13 and 24
await clock_in_right_o_left_o_standard(cpu,0) # 12 and 25
await clock_in_right_o_left_o_standard(cpu,0) # 11 and 26
await clock_in_right_o_left_o_standard(cpu,0) # 10 and 27
await clock_in_right_o_left_o_standard(cpu,0) # 9 and 28
await clock_in_right_o_left_o_standard(cpu,0) # 8 and 29
await clock_in_right_o_left_o_standard(cpu,0) # 7 and 30
await clock_in_right_o_left_o_standard(cpu,0) # 6 and 31
await clock_in_right_o_left_o_standard(cpu,0) # 5 and 32
await clock_in_right_o_left_o_standard(cpu,0) # 4 and 33
await clock_in_right_o_left_i_standard(cpu,0) # 3 and 34
await clock_in_right_o_left_i_standard(cpu,0) # 2 and 35
await clock_in_right_o_left_i_standard(cpu,0) # 1 and 36
await clock_in_end_output(cpu) # 0 and 37 and load
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
i= 0x20
for j in range(5):
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),i)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} int {caravelEnv.monitor_gpio((37,4)).integer} i = {i}')
if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
# for k in range(250):
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0)
if caravelEnv.monitor_gpio((37,4)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
await ClockCycles(caravelEnv.clk, 1)
i= 0x80000000
for j in range(32):
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3f)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),i)
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)}')
if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {i>>4}')
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} type {int(caravelEnv.monitor_gpio((37,4)))} i = {i}')
await ClockCycles(caravelEnv.clk, 1)
# await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
await ClockCycles(caravelEnv.clk, 1)
if caravelEnv.monitor_gpio((37,4)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000
await ClockCycles(caravelEnv.clk, 1000)
@cocotb.test()
@repot_test
async def bitbang_no_cpu_all_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=8005)
cpu = RiskV(dut)
cpu.cpu_force_reset()
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value)
#Configure all as input except reg_mprj_io_3
await clear_registers(cpu)
await clock_in_right_i_left_i_standard(cpu,0) # 18 and 19
await clock_in_right_i_left_i_standard(cpu,0) # 17 and 20
await clock_in_right_i_left_i_standard(cpu,0) # 16 and 21
await clock_in_right_i_left_i_standard(cpu,0) # 15 and 22
await clock_in_right_i_left_i_standard(cpu,0) # 14 and 23
await clock_in_right_i_left_i_standard(cpu,0) # 13 and 24
await clock_in_right_i_left_i_standard(cpu,0) # 12 and 25
await clock_in_right_i_left_i_standard(cpu,0) # 11 and 26
await clock_in_right_i_left_i_standard(cpu,0) # 10 and 27
await clock_in_right_i_left_i_standard(cpu,0) # 9 and 28
await clock_in_right_i_left_i_standard(cpu,0) # 8 and 29
await clock_in_right_i_left_i_standard(cpu,0) # 7 and 30
await clock_in_right_i_left_i_standard(cpu,0) # 6 and 31
await clock_in_right_i_left_i_standard(cpu,0) # 5 and 32
await clock_in_right_i_left_i_standard(cpu,0) # 4 and 33
await clock_in_right_i_left_i_standard(cpu,0) # 3 and 34
await clock_in_right_i_left_i_standard(cpu,0) # 2 and 35
await clock_in_right_i_left_i_standard(cpu,0) # 1 and 36
await clock_in_right_i_left_i_standard(cpu,0) # 0 and 37
await load(cpu) # load
caravelEnv.drive_gpio_in((31,0),0x8F66FD7B)
await ClockCycles(caravelEnv.clk, 100)
reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
# value_masked = reg_mprj_datal & mask_input
if reg_mprj_datal == 0x8F66FD7B:
cocotb.log.info(f'[TEST] Passed with value 0x8F66FD7B')
else:
cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0x8F66FD7B)}')
await ClockCycles(caravelEnv.clk, 100)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x1B)
x = caravelEnv.monitor_gpio((37,32))
print(f"xxxxxxxx {x}")
await ClockCycles(caravelEnv.clk, 100)
caravelEnv.drive_gpio_in((31,0),0xFFA88C5A)
await ClockCycles(caravelEnv.clk, 100)
reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
# value_masked = reg_mprj_datal & mask_input
if reg_mprj_datal == 0xFFA88C5A:
cocotb.log.info(f'[TEST] Passed with value 0xFFA88C5A')
else:
cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xFFA88C5A)}')
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x2B)
await ClockCycles(caravelEnv.clk, 100)
caravelEnv.drive_gpio_in((31,0),0xC9536346)
await ClockCycles(caravelEnv.clk, 100)
reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal'))
# value_masked = reg_mprj_datal & mask_input
if reg_mprj_datal == 0xC9536346:
cocotb.log.info(f'[TEST] Passed with value 0xC9536346')
else:
cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xC9536346)}')
await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3B)
await ClockCycles(caravelEnv.clk, 100)
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@cocotb.test()
@repot_test
async def io_ports(dut):
caravelEnv,clock = await test_configure(dut)
cpu = RiskV(dut)
cpu.cpu_force_reset()
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value)
# Apply configuration
await cpu.drive_data2address(reg.get_addr('reg_mprj_xfer'),1)
while True:
if await cpu.read_address(reg.get_addr('reg_mprj_xfer')) != 1 :
break

356
verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py Normal file
View File

@ -0,0 +1,356 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from interfaces.common import Macros
reg = Regs()
@cocotb.test()
@repot_test
async def bitbang_cpu_all_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=2075459)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
await wait_reg1(cpu,caravelEnv,0xFF)
cocotb.log.info("[TEST] finish configuring using bitbang")
i= 0x20
for j in range(5):
await wait_reg2(cpu,caravelEnv,37-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
if caravelEnv.monitor_gpio((37,4)).integer != i << 28:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,4)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
i= 0x80000000
for j in range(32):
await wait_reg2(cpu,caravelEnv,32-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}')
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
if caravelEnv.monitor_gpio((31,4)).integer != i>>4 :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,4)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000
await ClockCycles(caravelEnv.clk, 10)
@cocotb.test()
@repot_test
async def bitbang_cpu_all_10(dut):
caravelEnv = await test_configure(dut,timeout_cycles=2863378)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xFF)
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
type = True # type of shifting 01 or 10
for gpio in gpios_l:
shift(uut._id(gpio,False),type)
type = not type
type = True # type of shifting 01 or 10
for gpio in reversed(gpios_h):
shift(uut._id(gpio,False),type)
type = not type
def shift(gpio,shift_type):
if shift_type:
bits = "0101010101010"
else:
bits = "1010101010101"
fail = False
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
for i in range(13):
if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
fail = True
cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
if not fail:
cocotb.log.info(f"[TEST] gpio {gpio} passed")
@cocotb.test()
@repot_test
async def bitbang_cpu_all_01(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=2863378)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xFF)
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
type = False # type of shifting 01 or 10
for gpio in gpios_l:
shift(uut._id(gpio,False),type)
type = not type
type = False # type of shifting 01 or 10
for gpio in reversed(gpios_h):
shift(uut._id(gpio,False),type)
type = not type
@cocotb.test()
@repot_test
async def bitbang_cpu_all_0011(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xFF)
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
type = 0 # type of shifting 01 or 10
for gpio in gpios_l:
shift_2(uut._id(gpio,False),type)
type = (type + 1) %4
type = 0 # type of shifting 01 or 10
for gpio in reversed(gpios_h):
shift_2(uut._id(gpio,False),type)
type = (type + 1) %4
@cocotb.test()
@repot_test
async def bitbang_cpu_all_1100(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=10000000000)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xFF)
gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]")
gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]")
type = 2 # type of shifting 01 or 10
for gpio in gpios_l:
shift_2(uut._id(gpio,False),type)
type = (type + 1) %4
type = 2 # type of shifting 01 or 10
for gpio in reversed(gpios_h):
shift_2(uut._id(gpio,False),type)
type = (type + 1) %4
def shift_2(gpio,shift_type):
if shift_type == 0:
bits = "1001100110011"
elif shift_type == 1:
bits = "1100110011001"
elif shift_type == 2:
bits = "0110011001100"
elif shift_type == 3:
bits = "0011001100110"
fail = False
cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}")
for i in range(13):
if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]:
fail = True
cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}")
if not fail:
cocotb.log.info(f"[TEST] gpio {gpio} passed")
@cocotb.test()
@repot_test
async def bitbang_cpu_all_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=1691295)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0x8F66FD7B
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xBB)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0xFFA88C5A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xCC)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0xC9536346
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xD1)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0x3F
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD2)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
data_in = 0x0
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD3)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
data_in = 0x15
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD4)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
data_in = 0x2A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg2(cpu,caravelEnv,0xFF)
cocotb.log.info(f"[TEST] finish")
"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as output."""
@cocotb.test()
@repot_test
async def bitbang_spi_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=639757)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured
#Configure all as output except reg_mprj_io_3
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 18 and 19
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 17 and 20
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 16 and 21
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 15 and 22
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 14 and 23
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 13 and 24
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 12 and 25
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 11 and 26
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 10 and 27
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 9 and 28
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 8 and 29
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 7 and 30
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 6 and 31
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 5 and 32
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 4 and 33
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 3 and 34
await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 2 and 35
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 1 and 36
await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 0 and 37
await load_spi(caravelEnv) # load
cpu.write_debug_reg2_backdoor(0xFF)
cocotb.log.info("[TEST] finish configuring using bitbang")
i= 0x20
for j in range(5):
await wait_reg2(cpu,caravelEnv,37-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}')
if caravelEnv.monitor_gpio((37,5)).integer != i << 27:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,5))} instead of {bin(i << 28)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,5)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
i= 0x80000000
for j in range(32):
await wait_reg2(cpu,caravelEnv,32-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}')
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
if caravelEnv.monitor_gpio((31,5)).integer != i>>5 :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,5)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000
await ClockCycles(caravelEnv.clk, 10)
"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as input."""
@cocotb.test()
@repot_test
async def bitbang_spi_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=56703)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured
#Configure all as output except reg_mprj_io_3
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 18 and 19
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 17 and 20
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 16 and 21
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 15 and 22
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 14 and 23
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 13 and 24
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 12 and 25
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 11 and 26
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 10 and 27
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 9 and 28
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 8 and 29
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 7 and 30
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 6 and 31
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 5 and 32
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 4 and 33
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 3 and 34
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 2 and 35
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 1 and 36
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 0 and 37
await load_spi(caravelEnv) # load
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0x8F66FD7B
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xBB)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0xFFA88C5A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xCC)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0xC9536346
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xD1)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0x3F
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD2)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
data_in = 0x0
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD3)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
data_in = 0x15
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD4)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
data_in = 0x2A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg2(cpu,caravelEnv,0xFF)
cocotb.log.info(f"[TEST] finish")

32
verilog/dv/cocotb/tests/common_functions/Timeout.py Normal file
View File

@ -0,0 +1,32 @@
# from turtle import st
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from cocotb.result import SimTimeoutError
import cocotb
import time
"""class to handle timeout inside the tests. after the provided number of cycles (cycle_num) are exceeded test would fail
precision would determine when to log timeout warning for example if cycle_num=1000 and percision = 10% so after each 1000*10% = 100 cycle log would be printed
"""
class Timeout:
def __init__(self,clk,cycle_num,precision=0.20):
self.clk = clk
self.cycle_num = cycle_num
self.cycle_precision = precision * cycle_num
cocotb.scheduler.add(self._timeout_check())
async def _timeout_check(self):
number_of_cycles = 0
for i in range(0,self.cycle_num):
await ClockCycles(self.clk,1)
number_of_cycles +=1
if number_of_cycles %self.cycle_precision ==0:
cocotb.log.warning(f"simulation are only {self.cycle_num-number_of_cycles} cycles away from TIMEOUT ")
raise SimTimeoutError(f"simulation exceeds the max number of cycles {self.cycle_num}")
pass

95
verilog/dv/cocotb/tests/common_functions/test_functions.py Normal file
View File

@ -0,0 +1,95 @@
import random
import cocotb
from cocotb.clock import Clock
import cocotb.log
import interfaces.caravel as caravel
from interfaces.logic_analyzer import LA
from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox
import interfaces.common as common
import logging
from interfaces.cpu import RiskV
from cocotb.log import SimTimeContextFilter
from cocotb.log import SimLogFormatter
from tests.common_functions.Timeout import Timeout
import os
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
"""configure the test log file location and log verbosity
configure the test clock
configure the test timeout
configure whitbox models
start up the test connecting power vdd to the design then reset and disable the CSB bit
return the caravel environmnet with clock and start up
"""
async def test_configure(dut,timeout_cycles=1000000,clk=25,timeout_precision=0.2,num_error=3):
caravelEnv = caravel.Caravel_env(dut)
Timeout(caravelEnv.clk,timeout_cycles,timeout_precision)
if os.getenv('ERRORMAX') != 'None':
num_error = int(os.getenv('ERRORMAX'))
cocotb.scheduler.add(max_num_error(num_error,caravelEnv.clk))
clock = Clock(caravelEnv.clk, clk, units="ns") # Create a 10ns period clock on port clk
cocotb.start_soon(clock.start()) # Start the clock
await caravelEnv.start_up()
await ClockCycles(caravelEnv.clk, 10)
# HK_whiteBox(dut)
return caravelEnv,clock
class CallCounted:
"""Decorator to determine number of calls for a method"""
def __init__(self,method):
self.method=method
self.counter=0
def __call__(self,*args,**kwargs):
self.counter+=1
return self.method(*args,**kwargs)
def repot_test(func):
async def wrapper_func(*args, **kwargs):
## configure logging
COCOTB_ANSI_OUTPUT=0
TestName = func.__name__
cocotb.log.setLevel(logging.INFO)
cocotb.log.error = CallCounted(cocotb.log.error)
cocotb.log.critical = CallCounted(cocotb.log.critical)
cocotb.log.warning = CallCounted(cocotb.log.warning)
handler = logging.FileHandler(f"sim/{os.getenv('RUNTAG')}/{os.getenv('SIM')}-{TestName}/{TestName}.log",mode='w')
handler.addFilter(SimTimeContextFilter())
handler.setFormatter(SimLogFormatter())
cocotb.log.addHandler(handler)
## call test
await func(*args, **kwargs)
## report after finish simulation
msg = f'with ({cocotb.log.critical.counter})criticals ({cocotb.log.error.counter})errors ({cocotb.log.warning.counter})warnings '
if cocotb.log.error.counter > 0 or cocotb.log.critical.counter >0:
raise cocotb.result.TestComplete(f'Test failed {msg}')
else:
raise cocotb.result.TestComplete(f'Test passed {msg}')
return retval
return wrapper_func
async def max_num_error(num_error,clk):
while True:
await ClockCycles(clk,1)
if cocotb.log.error.counter + cocotb.log.critical.counter > num_error:
msg = f'Test failed with max number of errors {num_error} ({cocotb.log.critical.counter})criticals ({cocotb.log.error.counter})errors ({cocotb.log.warning.counter})warnings '
raise cocotb.result.TestFailure(msg)
async def wait_reg1(cpu,caravelEnv,data):
while (True):
if cpu.read_debug_reg1() == data:
return
await ClockCycles(caravelEnv.clk,10)
async def wait_reg2(cpu,caravelEnv,data):
while (True):
if cpu.read_debug_reg2() == data:
return
await ClockCycles(caravelEnv.clk,10)

156
verilog/dv/cocotb/tests/cpu/cpu_stress.c Normal file
View File

@ -0,0 +1,156 @@
#include <defs.h>
int A[]={1, 40, 2, 5, 22, 11, 90, 200, 10, 20, 25};
// int factorial(int n) {
// int fac=1;
// for(int i=1; i<=n;++i){
// fac = fac * i;
// }
// return fac;
// }
int fibbonacci(int n) {
if(n == 0){
return 0;
} else if(n == 1) {
return 1;
} else {
return (fibbonacci(n-1) + fibbonacci(n-2));
}
}
void recursiveInsertionSort(int arr[], int n){
if (n <= 1)
return;
recursiveInsertionSort( arr, n-1 );
int nth = arr[n-1];
int j = n-2;
while (j >= 0 && arr[j] > nth){
arr[j+1] = arr[j];
j--;
}
arr[j+1] = nth;
}
void quick_sort(int number[],int first,int last){
int i, j, pivot, temp;
if(first<last){
pivot=first;
i=first;
j=last;
while(i<j){
while(number[i]<=number[pivot]&&i<last)
i++;
while(number[j]>number[pivot])
j--;
if(i<j){
temp=number[i];
number[i]=number[j];
number[j]=temp;
}
}
temp=number[pivot];
number[pivot]=number[j];
number[j]=temp;
quick_sort(number,first,j-1);
quick_sort(number,j+1,last);
}
}
int f4(int a, int b, int c, int d){
return a + b + c + d;
}
int f5(int a, int b, int c, int d, int e){
return e + f4(a, b, c, d);
}
int f6(int a, int b, int c, int d, int e, int f){
return f + f5(a, b, c, d, e);
}
int f7(int a, int b, int c, int d, int e, int f, int g){
return g + f6(a, b, c, d, e, f);
}
int f8(int a, int b, int c, int d, int e, int f, int g, int h){
return h + f7(a, b, c, d, e, f, g);
}
/*
Stress the cpu with heavy processing
*/
void main()
{
int n;
int B[10];
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
// start test
// reg_mprj_datal = 0xAAAA0000;
// n =factorial(12);
// if(n != 479001600)
// reg_mprj_datal = 0xFFFF0000; //fail
// reg_mprj_datal = 0x11110000; //phase 1 pass
n = fibbonacci(10);
if(n != 55)
reg_debug_1 = 0x1E; // fail pahse 1
else
reg_debug_1 = 0x1B; // pass pahse 1
int sumA = 0;
for(int i=0; i<10; i++){
B[i] = A[i];
sumA += A[i];
}
if(sumA != 401)
reg_debug_1 = 0x2E; // fail pahse 2
else
reg_debug_1 = 0x2B; // pass pahse 2
recursiveInsertionSort(B, 10);
int sumB = 0;
for(int i=0; i<10; i++){
sumB += B[i];
}
if(sumA != sumB)
reg_debug_1 = 0x3E;// fail pahse 3
else
reg_debug_1 = 0x3B; // pass pahse 3
for(int i=0; i<10; i++){
B[i] = A[i];
sumA += A[i];
}
quick_sort(B, 0, 9);
for(int i=0; i<10; i++){
sumB += B[i];
}
if(sumA != sumB)
reg_debug_1 = 0x4E;// fail pahse 4
else
reg_debug_1 = 0x4B; // pass pahse 4
int sum = f8(10, 20, 30, 40, 50, 60, 70, 80);
if(sum != (10+20+30+40+50+60+70+80))
reg_debug_1 = 0x5E; // fail pahse 5
else
reg_debug_1 = 0x5B; // pass pahse 5
// test finish
reg_debug_2 = 0xFF;
}

43
verilog/dv/cocotb/tests/cpu/cpu_stress.py Normal file
View File

@ -0,0 +1,43 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
reg = Regs()
"""stress the cpu with heavy processing"""
@cocotb.test()
@repot_test
async def cpu_stress(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=1492541)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start CPU stress test")
pass_list = (0x1B,0x2B,0x3B,0x4B,0x5B)
fail_list = (0x1E,0x2E,0x3E,0x4E,0x5E)
phases_fails = 5
phases_passes = 0
reg1 =0 # buffer
while True:
if cpu.read_debug_reg2() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
cocotb.log.info(f"[TEST] pass phase {hex(reg1)[2]}")
elif reg1 in fail_list: # pass phase
cocotb.log.error(f"[TEST] failed phase {hex(reg1)[2]}")
await ClockCycles(caravelEnv.clk,1)
if phases_fails > 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")

421
verilog/dv/cocotb/tests/gpio/gpio.py Normal file
View File

@ -0,0 +1,421 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from cocotb.binary import BinaryValue
reg = Regs()
@cocotb.test()
@repot_test
async def gpio_all_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=376123)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info("[TEST] finish configuring ")
i= 0x20
for j in range(5):
await wait_reg2(cpu,caravelEnv,37-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,0)).integer != i<<32:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
i= 0x80000000
for j in range(32):
await wait_reg2(cpu,caravelEnv,32-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
if caravelEnv.monitor_gpio((31,0)).integer != i :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000
await wait_reg1(cpu,caravelEnv,0XBB)
data_in = 0x8F66FD7B
cocotb.log.info(f"[TEST] try send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
reg2 =0
await wait_reg1(cpu,caravelEnv,0XFF)
try:
reg2 =cpu.read_debug_reg2()
if reg2 == data_in:
cocotb.log.error(f"[TEST] Error: data {hex(data_in)} driven on gpio[31:0] is seen by firmware while gpios are configured as output")
else:
cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output it can see {reg2}")
except Exception as e:
cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output")
return
await ClockCycles(caravelEnv.clk, 10)
@cocotb.test()
@repot_test
async def gpio_all_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=44980)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0x8F66FD7B
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xBB)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0xFFA88C5A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xCC)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0xC9536346
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xD1)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
data_in = 0x3F
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD2)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
data_in = 0x0
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD3)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
data_in = 0x15
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD4)
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]")
data_in = 0x2A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg2(cpu,caravelEnv,0xFF)
cocotb.log.info(f"[TEST] finish")
@cocotb.test()
@repot_test
async def gpio_all_i_pu(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
await caravelEnv.release_csb()
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xAA)
# monitor the output of padframe module it suppose to be all ones when no input is applied
await ClockCycles(caravelEnv.clk,100)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and float")
await ClockCycles(caravelEnv.clk,1000)
# drive gpios with zero
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive gpios with ones
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive odd half gpios with zeros and float other half
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(0,38,2):
caravelEnv.release_gpio(i) # release even gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if i%2 ==1: #odd
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 0")
else:
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with odd half with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive even half gpios with zeros and float other half
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(1,38,2):
caravelEnv.release_gpio(i) # release odd gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if i%2 ==1: #odd
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with even half with 0")
else:
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with even half with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive odd half gpios with ones and float other half
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(0,38,2):
caravelEnv.release_gpio(i) # release even gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive even half gpios with zeros and float other half
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(1,38,2):
caravelEnv.release_gpio(i) # release odd gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with even half with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive with zeros then release all gpio
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
caravelEnv.release_gpio((37,0))
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and all released")
await ClockCycles(caravelEnv.clk,1000)
@cocotb.test()
@repot_test
async def gpio_all_i_pd(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
await caravelEnv.release_csb()
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0xAA)
# monitor the output of padframe module it suppose to be all ones when no input is applied
await ClockCycles(caravelEnv.clk,100)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and float")
await ClockCycles(caravelEnv.clk,1000)
# drive gpios with zero
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive gpios with ones
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive odd half gpios with zeros and float other half
data_in = 0x0
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(0,38,2):
caravelEnv.release_gpio(i) # release even gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i]!="0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive even half gpios with zeros and float other half
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(1,38,2):
caravelEnv.release_gpio(i) # release odd gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i]!="0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with even half with 0")
await ClockCycles(caravelEnv.clk,1000)
# drive odd half gpios with ones and float other half
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(0,38,2):
caravelEnv.release_gpio(i) # release even gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if i%2 ==0: #even
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with odd half with 1")
else:
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive even half gpios with zeros and float other half
caravelEnv.drive_gpio_in((37,0),data_in)
for i in range(1,38,2):
caravelEnv.release_gpio(i) # release odd gpios
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if i%2 ==1: #odd
if gpio[i]!="1":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with odd half with 1")
else:
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 1")
await ClockCycles(caravelEnv.clk,1000)
# drive with ones then release all gpio
data_in = 0x3FFFFFFFFF
caravelEnv.drive_gpio_in((37,0),data_in)
await ClockCycles(caravelEnv.clk,1000)
caravelEnv.release_gpio((37,0))
await ClockCycles(caravelEnv.clk,1000)
gpio = dut.uut.padframe.mprj_io_in.value.binstr
for i in range(38):
if gpio[i] != "0":
cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and all released")
await ClockCycles(caravelEnv.clk,1000)
@cocotb.test()
@repot_test
async def gpio_all_bidir(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=1144980)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
uut = dut.uut
await wait_reg1(cpu,caravelEnv,0x1A)
cocotb.log.info("[TEST] finish configuring ")
i= 0x20
for j in range(5):
await wait_reg2(cpu,caravelEnv,37-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,0)).integer != i << 32:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i << 32)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
i= 0x80000000
for j in range(32):
await wait_reg2(cpu,caravelEnv,32-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
if caravelEnv.monitor_gpio((31,0)).integer != i :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000
await wait_reg1(cpu,caravelEnv,0x2A)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0x8F66FD7B
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xBB)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xFFA88C5A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xCC)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
await wait_reg1(cpu,caravelEnv,0xD1)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
data_in = 0x3F
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD2)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
data_in = 0x0
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD3)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
data_in = 0x15
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg1(cpu,caravelEnv,0xD4)
if cpu.read_debug_reg2() == data_in:
cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]")
else:
cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
data_in = 0xC9536346
data_in = 0x2A
cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]")
caravelEnv.drive_gpio_in((37,32),data_in)
await wait_reg2(cpu,caravelEnv,0xFF)
cocotb.log.info(f"[TEST] finish")
await ClockCycles(caravelEnv.clk, 10)

98
verilog/dv/cocotb/tests/gpio/gpio_all_bidir.c Normal file
View File

@ -0,0 +1,98 @@
#include <defs.h>
#include <stub.c>
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0x1A; // try the gpios as output
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_datah = i;
reg_debug_2 = 37-j;
reg_mprj_datah = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_datah = 0x3f;
reg_mprj_datal = i;
reg_debug_2 = 32-j;
reg_mprj_datah = 0x00;
reg_mprj_datal = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
// test input
reg_debug_1 = 0X2A; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
while (reg_mprj_datal != 0x8F66FD7B);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
while (reg_mprj_datal != 0xFFA88C5A);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
while (reg_mprj_datal != 0xC9536346);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XD1;
while (reg_mprj_datah != 0x3F);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XD2;
while (reg_mprj_datah != 0x0);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XD3;
while (reg_mprj_datah != 0x15);
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XD4;
while (reg_mprj_datah != 0x2A);
reg_debug_2=0xFF;
}

71
verilog/dv/cocotb/tests/gpio/gpio_all_i.c Normal file
View File

@ -0,0 +1,71 @@
#include <defs.h>
#include <stub.c>
#include "../bitbang/bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
while (reg_mprj_datal != 0x8F66FD7B);
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
while (reg_mprj_datal != 0xFFA88C5A);
reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal
while (reg_mprj_datal != 0xC9536346);
reg_debug_1 = 0XD1;
while (reg_mprj_datah != 0x3F);
reg_debug_1 = 0XD2;
while (reg_mprj_datah != 0x0);
reg_debug_1 = 0XD3;
while (reg_mprj_datah != 0x15);
reg_debug_1 = 0XD4;
while (reg_mprj_datah != 0x2A);
reg_debug_2 = 0xFF;
}

57
verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c Normal file
View File

@ -0,0 +1,57 @@
#include <defs.h>
#include <stub.c>
#include "../bitbang/bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done
while (true);
}

57
verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c Normal file
View File

@ -0,0 +1,57 @@
#include <defs.h>
#include <stub.c>
#include "../bitbang/bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLUP;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0XAA; // configuration done
while (true);
}

90
verilog/dv/cocotb/tests/gpio/gpio_all_o.c Normal file
View File

@ -0,0 +1,90 @@
#include <defs.h>
#include <stub.c>
#include "../bitbang/bitbang_functions.c"
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0xAA; // finish configuration
reg_mprj_datal = 0x0;
reg_mprj_datah = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_datah = i;
reg_debug_2 = 37-j;
reg_mprj_datah = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_datah = 0x3f;
reg_mprj_datal = i;
reg_debug_2 = 32-j;
reg_mprj_datah = 0x00;
reg_mprj_datal = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
// try to give input
reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
int timeout = 1000;
while (reg_mprj_datal != 0x8F66FD7B){
timeout--;
if (timeout==0){
break;
}
}
reg_debug_2 = reg_mprj_datal;
reg_debug_1 = 0XFF; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
}

93
verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c Normal file
View File

@ -0,0 +1,93 @@
#include <defs.h>
#include <stub.c>
#include "../bitbang/bitbang_functions.c"
// Debug reg DEBUG_ON
#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0)
#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4)
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 = 0xAA; // finish configuration
reg_mprj_userl = 0x0;
reg_mprj_userh = 0x0;
i = 0x20;
for (j = 0; j < 5; j++) {
reg_mprj_userh = i;
reg_debug_2 = 37-j;
reg_mprj_userh = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x20;
}
i = 0x80000000;
for (j = 0; j < 32; j++) {
reg_mprj_userh = 0x3f;
reg_mprj_userl = i;
reg_debug_2 = 32-j;
reg_mprj_userh = 0x00;
reg_mprj_userl = 0x00000000;
reg_debug_2 = 0;
i >>=1;
i |= 0x80000000;
}
// try to give input
reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_userl
int timeout = 1000;
while (reg_mprj_userl != 0x8F66FD7B){
timeout--;
if (timeout==0){
break;
}
}
reg_debug_2 = reg_mprj_userl;
reg_debug_1 = 0XFF; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_userl
}

69
verilog/dv/cocotb/tests/gpio/gpio_user.py Normal file
View File

@ -0,0 +1,69 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from cocotb.binary import BinaryValue
reg = Regs()
@cocotb.test()
@repot_test
async def gpio_all_o_user(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=376123)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info("[TEST] finish configuring as user output")
i= 0x20
for j in range(5):
await wait_reg2(cpu,caravelEnv,37-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,0)).integer != i<<32:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x20
i= 0x80000000
for j in range(32):
await wait_reg2(cpu,caravelEnv,32-j)
cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
if caravelEnv.monitor_gpio((31,0)).integer != i :
cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
await wait_reg2(cpu,caravelEnv,0)
if caravelEnv.monitor_gpio((37,0)).integer != 0:
cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
i = i >> 1
i |= 0x80000000
await wait_reg1(cpu,caravelEnv,0XBB)
data_in = 0x8F66FD7B
cocotb.log.info(f"[TEST] try send {hex(data_in)} to gpio[31:0]")
caravelEnv.drive_gpio_in((31,0),data_in)
reg2 =0
await wait_reg1(cpu,caravelEnv,0XFF)
try:
reg2 =cpu.read_debug_reg2()
if reg2 == data_in:
cocotb.log.error(f"[TEST] Error: data {hex(data_in)} driven on gpio[31:0] is seen by firmware while gpios are configured as output")
else:
cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output it can see {reg2}")
except Exception as e:
cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output")
return
await ClockCycles(caravelEnv.clk, 10)

5
verilog/dv/cocotb/tests/hello_world/helloWorld.c Normal file
View File

@ -0,0 +1,5 @@
int main(){
// do nothing
return 0;
}

11
verilog/dv/cocotb/tests/hello_world/helloWorld.py Normal file
View File

@ -0,0 +1,11 @@
import cocotb
from tests.common_functions.test_functions import *
@cocotb.test()
@repot_test
async def helloWorld(dut):
caravelEnv,clock = await test_configure(dut)
cocotb.log.info("[Test] Hello world")
caravelEnv.print_gpios_ctrl_val()
caravelEnv.print_gpios_HW_val()

18
verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c Normal file
View File

@ -0,0 +1,18 @@
#include <defs.h>
#include <stub.c>
// --------------------------------------------------------
void main(){
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
/* Monitor pins must be set to output */
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_1 =0xAA;
return;
}

14
verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c Normal file
View File

@ -0,0 +1,14 @@
#include <defs.h>
#include <stub.c>
// --------------------------------------------------------
void main(){
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0xBB;
while (reg_debug_1 != 0xAA);
reg_hkspi_disable = 0;
// reg_hkspi_pll_ena =0;
reg_debug_1 =0xBB;
}

152
verilog/dv/cocotb/tests/housekeeping/general/pll.c Normal file
View File

@ -0,0 +1,152 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
#include <stub.c>
// --------------------------------------------------------
/*
* PLL Test (self-switching)
* - Switches PLL bypass in housekeeping
* - Changes PLL divider in housekeeping
*
*/
void main()
{
int i;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
/* Monitor pins must be set to output */
reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT;
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
// Start test
/*
*-------------------------------------------------------------
* Register 2610_000c reg_hkspi_pll_ena
* SPI address 0x08 = PLL enables
* bit 0 = PLL enable, bit 1 = DCO enable
*
* Register 2610_0010 reg_hkspi_pll_bypass
* SPI address 0x09 = PLL bypass
* bit 0 = PLL bypass
*
* Register 2610_0020 reg_hkspi_pll_source
* SPI address 0x11 = PLL source
* bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
*
* Register 2610_0024 reg_hkspi_pll_divider
* SPI address 0x12 = PLL divider
* bits 0-4 = feedback divider
*
* Register 2620_0004 reg_clk_out_dest
* SPI address 0x1b = Output redirect
* bit 0 = trap to mprj_io[13]
* bit 1 = clk to mprj_io[14]
* bit 2 = clk2 to mprj_io[15]
*-------------------------------------------------------------
*/
// Monitor the core clock and user clock on mprj_io[14] and mprj_io[15]
// reg_clk_out_dest = 0x6 to turn on, 0x0 to turn off
// Write checkpoint for clock counting (PLL bypassed)
reg_debug_1 = 0xA1;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_debug_1 = 0xA2;
// Set PLL enable, no DCO mode
reg_hkspi_pll_ena = 0x1;
// Set PLL output divider to 0x03
reg_hkspi_pll_source = 0x3;
// Write checkpoint for clock counting (PLL bypassed)
reg_debug_1 = 0xA3;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_debug_1 = 0xA4;
// Disable PLL bypass
reg_hkspi_pll_bypass = 0x0;
// Write checkpoint for clock counting
reg_debug_1 = 0xA5;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_debug_1 = 0xA6;
// Write 0x03 to feedback divider (was 0x04)
reg_hkspi_pll_divider = 0x3;
// Write checkpoint
reg_debug_1 = 0xA7;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_debug_1 = 0xA8;
// Write 0x04 to PLL output divider
reg_hkspi_pll_source = 0x4;
// Write checkpoint
reg_debug_1 = 0xA9;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x6;
reg_clk_out_dest = 0x0;
reg_debug_1 = 0xAa;
// End test
reg_mprj_datal = 0xA0900000;
}

86
verilog/dv/cocotb/tests/housekeeping/general/pll.py Normal file
View File

@ -0,0 +1,86 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from cocotb.binary import BinaryValue
reg = Regs()
caravel_clock = 0
user_clock = 0
@cocotb.test()
@repot_test
async def pll(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
error_margin = 0.1
await wait_reg1(cpu,caravelEnv,0xA1)
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock"))
await wait_reg1(cpu,caravelEnv,0xA3)
if abs(caravel_clock - user_clock) > error_margin*caravel_clock:
cocotb.log.error(f"[TEST] Error: clocks should be equal in phase 1 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
else:
cocotb.log.info(f"[TEST] pass phase 1 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock"))
await wait_reg1(cpu,caravelEnv,0xA5)
if abs(caravel_clock - user_clock) > error_margin*caravel_clock:
cocotb.log.error(f"[TEST] Error: clocks should be equal in phase 2 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
else:
cocotb.log.info(f"[TEST] pass phase 2 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock"))
await wait_reg1(cpu,caravelEnv,0xA7)
if abs(caravel_clock - user_clock*3) > error_margin*caravel_clock:
cocotb.log.error(f"[TEST] Error: user clock shoud be 3 times caravel clock in phase 3 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
else:
cocotb.log.info(f"[TEST] pass phase 3 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock "))
await wait_reg1(cpu,caravelEnv,0xA9)
if abs(caravel_clock - user_clock*3) > error_margin*caravel_clock:
cocotb.log.error(f"[TEST] Error: user clock shoud be 3 times caravel clock in phase 4 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
else:
cocotb.log.info(f"[TEST] pass phase 4 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock"))
await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock"))
await wait_reg1(cpu,caravelEnv,0xAa)
if abs(caravel_clock - user_clock*4) > error_margin*caravel_clock:
cocotb.log.error(f"[TEST] Error: user clock shoud be 4 times caravel clock in phase 5 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
else:
cocotb.log.info(f"[TEST] pass phase 5 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz")
await ClockCycles(caravelEnv.clk,10000)
# for i in range(1000):
# await ClockCycles(caravelEnv.clk,10000)
# cocotb.log.info(f"time = {cocotb.simulator.get_sim_time()}")
async def calculate_clk_period(clk,name):
await RisingEdge(clk)
initial_time = cocotb.simulator.get_sim_time()
initial_time = (initial_time[0] <<32) | (initial_time[1])
for i in range(100):
await RisingEdge(clk)
end_time = cocotb.simulator.get_sim_time()
end_time = (end_time[0] <<32) | (end_time[1])
val = (end_time - initial_time) / 100
cocotb.log.debug(f"[TEST] clock of {name} is {val}")
if name == "caravel clock":
global caravel_clock
caravel_clock = val
elif name == "user clock":
global user_clock
user_clock = val
val = str(val)
return val

147
verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py Normal file
View File

@ -0,0 +1,147 @@
from faulthandler import disable
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from cocotb.binary import BinaryValue
from tests.housekeeping.housekeeping_spi.spi_access_functions import *
reg = Regs()
caravel_clock = 0
user_clock = 0
core_clock = 0
@cocotb.test()
@repot_test
async def clock_redirect(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=13060)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
# calculate core clock
await cocotb.start(calculate_clk_period(dut.uut.clock,"core clock"))
await ClockCycles(caravelEnv.clk,110)
cocotb.log.info(f"[TEST] core clock requency = {round(1000000/core_clock,2)} MHz period = {core_clock}ps")
await wait_reg1(cpu,caravelEnv,0xAa)
# check clk redirect working
#user clock
clock_name = "user clock"
await write_reg_spi(caravelEnv,0x1b,0x0) # disable user clock output redirect
await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
await ClockCycles(caravelEnv.clk,110)
if user_clock != 0:
cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled")
else:
cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled")
await write_reg_spi(caravelEnv,0x1b,0x4) # enable user clock output redirect
await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
await ClockCycles(caravelEnv.clk,110)
if user_clock != core_clock:
cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {user_clock} and core clock = {core_clock}")
else:
cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
#caravel clock
clock_name = "caravel clock"
await write_reg_spi(caravelEnv,0x1b,0x0) # disable caravel clock output redirect
await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name))
await ClockCycles(caravelEnv.clk,110)
if caravel_clock != 0:
cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled")
else:
cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled")
await write_reg_spi(caravelEnv,0x1b,0x4) # enable caravel clock output redirect
await cocotb.start(calculate_clk_period(dut.bin15_monitor,clock_name))
await ClockCycles(caravelEnv.clk,110)
if caravel_clock != core_clock:
cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {caravel_clock} and core clock = {core_clock}")
else:
cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully")
async def calculate_clk_period(clk,name):
await RisingEdge(clk)
initial_time = cocotb.simulator.get_sim_time()
initial_time = (initial_time[0] <<32) | (initial_time[1])
for i in range(100):
await RisingEdge(clk)
end_time = cocotb.simulator.get_sim_time()
end_time = (end_time[0] <<32) | (end_time[1])
val = (end_time - initial_time) / 100
cocotb.log.debug(f"[TEST] clock of {name} is {val}")
if name == "caravel clock":
global caravel_clock
caravel_clock = val
elif name == "user clock":
global user_clock
user_clock = val
elif name == "core clock":
global core_clock
core_clock = val
return val
@cocotb.test()
@repot_test
async def hk_disable(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=11243)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
# check spi working by writing to PLL enables
old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
pll_enable = dut.uut.housekeeping.pll_ena.value.integer
cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
if pll_enable == 1-old_pll_enable:
cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}")
else:
cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}")
old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
pll_enable = dut.uut.housekeeping.pll_ena.value.integer
cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
if pll_enable == 1-old_pll_enable:
cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}")
else:
cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}")
# disable Housekeeping SPIca
await write_reg_spi(caravelEnv,0x6f,0x1)
# try to change pll_en
old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
pll_enable = dut.uut.housekeeping.pll_ena.value.integer
cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
if pll_enable == 1-old_pll_enable:
cocotb.log.error(f"[TEST] Error: SPI swap pll_enable value from {old_pll_enable} to {pll_enable} while housekeeping spi is disabled")
else:
cocotb.log.info(f"[TEST] pass: SPI isn't working when SPI housekeeping is disabled")
# enable SPI housekeeping through firmware
await wait_reg2(cpu,caravelEnv,0xBB) # start waiting on reg1 AA
cpu.write_debug_reg1_backdoor(0xAA)
await wait_reg1(cpu,caravelEnv,0xBB) # enabled the housekeeping
old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
pll_enable = dut.uut.housekeeping.pll_ena.value.integer
cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
if pll_enable == 1-old_pll_enable:
cocotb.log.info(f"[TEST] Pass: Housekeeping SPI has been enabled correctly through firmware")
else:
cocotb.log.error(f"[TEST] Error: Housekeeping SPI failed to be enabled through firmware")

10
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c Normal file
View File

@ -0,0 +1,10 @@
#include <defs.h>
#include <stub.c>
// Empty C code
void main()
{
return;
}

10
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c Normal file
View File

@ -0,0 +1,10 @@
#include <defs.h>
#include <stub.c>
// Empty C code
void main()
{
return;
}

10
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c Normal file
View File

@ -0,0 +1,10 @@
#include <defs.h>
#include <stub.c>
// Empty C code
void main()
{
return;
}

333
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c Normal file
View File

@ -0,0 +1,333 @@
#include <defs.h>
#include <stub.c>
// access all housekeeping registers that can be access through firmware and change it's value
void main(){
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
// store RO value regs
int old_reg_hkspi_status = reg_hkspi_status;
int old_reg_hkspi_chip_id = reg_hkspi_chip_id;
int old_reg_hkspi_user_id = reg_hkspi_user_id;
int old_reg_hkspi_trap = reg_hkspi_trap;
int old_reg_hkspi_irq = reg_hkspi_irq;
// write 1 ones to all registers
reg_mprj_io_0 = 0xFFFFFFFF;
reg_mprj_io_1 = 0xFFFFFFFF;
reg_mprj_io_2 = 0xFFFFFFFF;
reg_mprj_io_3 = 0xFFFFFFFF;
reg_mprj_io_4 = 0xFFFFFFFF;
reg_mprj_io_5 = 0xFFFFFFFF;
reg_mprj_io_6 = 0xFFFFFFFF;
reg_mprj_io_7 = 0xFFFFFFFF;
reg_mprj_io_8 = 0xFFFFFFFF;
reg_mprj_io_9 = 0xFFFFFFFF;
reg_mprj_io_10 = 0xFFFFFFFF;
reg_mprj_io_11 = 0xFFFFFFFF;
reg_mprj_io_12 = 0xFFFFFFFF;
reg_mprj_io_13 = 0xFFFFFFFF;
reg_mprj_io_14 = 0xFFFFFFFF;
reg_mprj_io_15 = 0xFFFFFFFF;
reg_mprj_io_16 = 0xFFFFFFFF;
reg_mprj_io_17 = 0xFFFFFFFF;
reg_mprj_io_18 = 0xFFFFFFFF;
reg_mprj_io_19 = 0xFFFFFFFF;
reg_mprj_io_20 = 0xFFFFFFFF;
reg_mprj_io_21 = 0xFFFFFFFF;
reg_mprj_io_22 = 0xFFFFFFFF;
reg_mprj_io_23 = 0xFFFFFFFF;
reg_mprj_io_24 = 0xFFFFFFFF;
reg_mprj_io_25 = 0xFFFFFFFF;
reg_mprj_io_26 = 0xFFFFFFFF;
reg_mprj_io_27 = 0xFFFFFFFF;
reg_mprj_io_28 = 0xFFFFFFFF;
reg_mprj_io_29 = 0xFFFFFFFF;
reg_mprj_io_30 = 0xFFFFFFFF;
reg_mprj_io_31 = 0xFFFFFFFF;
reg_mprj_io_32 = 0xFFFFFFFF;
reg_mprj_io_33 = 0xFFFFFFFF;
reg_mprj_io_34 = 0xFFFFFFFF;
reg_mprj_io_35 = 0xFFFFFFFF;
reg_mprj_io_36 = 0xFFFFFFFF;
reg_mprj_io_37 = 0xFFFFFFFF;
// house keeping
reg_hkspi_status = 0xFFFFFFFF;
reg_hkspi_chip_id = 0xFFFFFFFF;
reg_hkspi_user_id = 0xFFFFFFFF;
reg_hkspi_pll_ena = 0xFFFFFFFF;
reg_hkspi_pll_bypass = 0xFFFFFFFF;
reg_hkspi_irq = 0xFFFFFFFF;
// reg_hkspi_reset = 0xFFFFFFFF; can't write 1 to it cpu would be reset
reg_hkspi_trap = 0xFFFFFFFF;
reg_hkspi_pll_trim = 0xFFFFFFFF;
reg_hkspi_pll_source = 0xFFFFFFFF;
reg_hkspi_pll_divider = 0xFFFFFFFF;
// sys
reg_clk_out_dest = 0xFFFFFFFF;
reg_hkspi_disable = 0xFFFFFFFF;
// read ones that has been written
if (reg_mprj_io_0 != 0x1FFF)
reg_debug_1 =0x1;
if (reg_mprj_io_1 != 0x1FFF)
reg_debug_1 =0x2;
if (reg_mprj_io_2 != 0x1FFF)
reg_debug_1 =0x3;
if (reg_mprj_io_3 != 0x1FFF)
reg_debug_1 =0x4;
if (reg_mprj_io_4 != 0x1FFF)
reg_debug_1 =0x5;
if (reg_mprj_io_5 != 0x1FFF)
reg_debug_1 =0x6;
if (reg_mprj_io_6 != 0x1FFF)
reg_debug_1 =0x7;
if (reg_mprj_io_7 != 0x1FFF)
reg_debug_1 =0x8;
if (reg_mprj_io_8 != 0x1FFF)
reg_debug_1 =0x9;
if (reg_mprj_io_9 != 0x1FFF)
reg_debug_1 =0xa;
if (reg_mprj_io_10 != 0x1FFF)
reg_debug_1 =0xb;
if (reg_mprj_io_11 != 0x1FFF)
reg_debug_1 =0xc;
if (reg_mprj_io_12 != 0x1FFF)
reg_debug_1 =0xd;
if (reg_mprj_io_13 != 0x1FFF)
reg_debug_1 =0xe;
if (reg_mprj_io_14 != 0x1FFF)
reg_debug_1 =0xf;
if (reg_mprj_io_15 != 0x1FFF)
reg_debug_1 =0x10;
if (reg_mprj_io_16 != 0x1FFF)
reg_debug_1 =0x11;
if (reg_mprj_io_17 != 0x1FFF)
reg_debug_1 =0x12;
if (reg_mprj_io_18 != 0x1FFF)
reg_debug_1 =0x13;
if (reg_mprj_io_19 != 0x1FFF)
reg_debug_1 =0x14;
if (reg_mprj_io_20 != 0x1FFF)
reg_debug_1 =0x15;
if (reg_mprj_io_21 != 0x1FFF)
reg_debug_1 =0x16;
if (reg_mprj_io_22 != 0x1FFF)
reg_debug_1 =0x17;
if (reg_mprj_io_23 != 0x1FFF)
reg_debug_1 =0x18;
if (reg_mprj_io_24 != 0x1FFF)
reg_debug_1 =0x19;
if (reg_mprj_io_25 != 0x1FFF)
reg_debug_1 =0x1a;
if (reg_mprj_io_26 != 0x1FFF)
reg_debug_1 =0x1b;
if (reg_mprj_io_27 != 0x1FFF)
reg_debug_1 =0x1c;
if (reg_mprj_io_28 != 0x1FFF)
reg_debug_1 =0x1d;
if (reg_mprj_io_29 != 0x1FFF)
reg_debug_1 =0x1e;
if (reg_mprj_io_30 != 0x1FFF)
reg_debug_1 =0x1f;
if (reg_mprj_io_31 != 0x1FFF)
reg_debug_1 =0x20;
if (reg_mprj_io_32 != 0x1FFF)
reg_debug_1 =0x21;
if (reg_mprj_io_33 != 0x1FFF)
reg_debug_1 =0x22;
if (reg_mprj_io_34 != 0x1FFF)
reg_debug_1 =0x23;
if (reg_mprj_io_35 != 0x1FFF)
reg_debug_1 =0x24;
if (reg_mprj_io_36 != 0x1FFF)
reg_debug_1 =0x25;
if (reg_mprj_io_37 != 0x1FFF)
reg_debug_1 =0x26;
// housekeeping
if (reg_hkspi_status != old_reg_hkspi_status) // RO
reg_debug_1 =0x27;
if (reg_hkspi_chip_id != old_reg_hkspi_chip_id) // RO
reg_debug_1 =0x28;
if (reg_hkspi_user_id != old_reg_hkspi_user_id) // RO
reg_debug_1 =0x29;
if (reg_hkspi_pll_ena != 0x3) // size =2
reg_debug_1 =0x2a;
if (reg_hkspi_pll_bypass != 0x1) // size = 1
reg_debug_1 = 0x2b;
if (reg_hkspi_irq != old_reg_hkspi_irq) // RO
reg_debug_1 = 0x2c;
if (reg_hkspi_trap != old_reg_hkspi_trap) // RO
reg_debug_1 =0x2d;
if (reg_hkspi_pll_trim != 0x3FFFFFF) // size 26
reg_debug_1 = 0x2f;
if (reg_hkspi_pll_source != 0x3F) // size 6 bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
reg_debug_1 =0x2f;
if (reg_hkspi_pll_divider != 0x1F) // size 7 -> PLL output divider, PLL output divider2 , PLL feedback divider
reg_debug_1 =0x30;
if (reg_hkspi_disable != 0x1) // size 1
reg_debug_1 =0x31;
if (reg_clk_out_dest != 0x7) // trap and clocks redirect
reg_debug_1 =0x32;
// // write zeros to all registers
reg_mprj_io_0 = 0x0;
reg_mprj_io_1 = 0x0;
reg_mprj_io_2 = 0x0;
reg_mprj_io_3 = 0x0;
reg_mprj_io_4 = 0x0;
reg_mprj_io_5 = 0x0;
reg_mprj_io_6 = 0x0;
reg_mprj_io_7 = 0x0;
reg_mprj_io_8 = 0x0;
reg_mprj_io_9 = 0x0;
reg_mprj_io_10 = 0x0;
reg_mprj_io_11 = 0x0;
reg_mprj_io_12 = 0x0;
reg_mprj_io_13 = 0x0;
reg_mprj_io_14 = 0x0;
reg_mprj_io_15 = 0x0;
reg_mprj_io_16 = 0x0;
reg_mprj_io_17 = 0x0;
reg_mprj_io_18 = 0x0;
reg_mprj_io_19 = 0x0;
reg_mprj_io_20 = 0x0;
reg_mprj_io_21 = 0x0;
reg_mprj_io_22 = 0x0;
reg_mprj_io_23 = 0x0;
reg_mprj_io_24 = 0x0;
reg_mprj_io_25 = 0x0;
reg_mprj_io_26 = 0x0;
reg_mprj_io_27 = 0x0;
reg_mprj_io_28 = 0x0;
reg_mprj_io_29 = 0x0;
reg_mprj_io_30 = 0x0;
reg_mprj_io_31 = 0x0;
reg_mprj_io_32 = 0x0;
reg_mprj_io_33 = 0x0;
reg_mprj_io_34 = 0x0;
reg_mprj_io_35 = 0x0;
reg_mprj_io_36 = 0x0;
reg_mprj_io_37 = 0x0;
// house keeping
reg_hkspi_status = 0x0;
reg_hkspi_chip_id = 0x0;
reg_hkspi_user_id = 0x0;
reg_hkspi_pll_ena = 0x0;
reg_hkspi_pll_bypass = 0x0;
reg_hkspi_irq = 0x0;
reg_hkspi_reset = 0x0;
reg_hkspi_trap = 0x0;
reg_hkspi_pll_trim = 0x0;
reg_hkspi_pll_source = 0x0;
reg_hkspi_pll_divider = 0x0;
// sys
reg_clk_out_dest = 0x0;
reg_hkspi_disable = 0x0;
// // read zeros that has been written
if (reg_mprj_io_0 != 0x0)
reg_debug_2 =0x1;
if (reg_mprj_io_1 != 0x0)
reg_debug_2 =0x2;
if (reg_mprj_io_2 != 0x0)
reg_debug_2 =0x3;
if (reg_mprj_io_3 != 0x0)
reg_debug_2 =0x4;
if (reg_mprj_io_4 != 0x0)
reg_debug_2 =0x5;
if (reg_mprj_io_5 != 0x0)
reg_debug_2 =0x6;
if (reg_mprj_io_6 != 0x0)
reg_debug_2 =0x7;
if (reg_mprj_io_7 != 0x0)
reg_debug_2 =0x8;
if (reg_mprj_io_8 != 0x0)
reg_debug_2 =0x9;
if (reg_mprj_io_9 != 0x0)
reg_debug_2 =0xa;
if (reg_mprj_io_10 != 0x0)
reg_debug_2 =0xb;
if (reg_mprj_io_11 != 0x0)
reg_debug_2 =0xc;
if (reg_mprj_io_12 != 0x0)
reg_debug_2 =0xd;
if (reg_mprj_io_13 != 0x0)
reg_debug_2 =0xe;
if (reg_mprj_io_14 != 0x0)
reg_debug_2 =0xf;
if (reg_mprj_io_15 != 0x0)
reg_debug_2 =0x10;
if (reg_mprj_io_16 != 0x0)
reg_debug_2 =0x11;
if (reg_mprj_io_17 != 0x0)
reg_debug_2 =0x12;
if (reg_mprj_io_18 != 0x0)
reg_debug_2 =0x13;
if (reg_mprj_io_19 != 0x0)
reg_debug_2 =0x14;
if (reg_mprj_io_20 != 0x0)
reg_debug_2 =0x15;
if (reg_mprj_io_21 != 0x0)
reg_debug_2 =0x16;
if (reg_mprj_io_22 != 0x0)
reg_debug_2 =0x17;
if (reg_mprj_io_23 != 0x0)
reg_debug_2 =0x18;
if (reg_mprj_io_24 != 0x0)
reg_debug_2 =0x19;
if (reg_mprj_io_25 != 0x0)
reg_debug_2 =0x1a;
if (reg_mprj_io_26 != 0x0)
reg_debug_2 =0x1b;
if (reg_mprj_io_27 != 0x0)
reg_debug_2 =0x1c;
if (reg_mprj_io_28 != 0x0)
reg_debug_2 =0x1d;
if (reg_mprj_io_29 != 0x0)
reg_debug_2 =0x1e;
if (reg_mprj_io_30 != 0x0)
reg_debug_2 =0x1f;
if (reg_mprj_io_31 != 0x0)
reg_debug_2 =0x20;
if (reg_mprj_io_32 != 0x0)
reg_debug_2 =0x21;
if (reg_mprj_io_33 != 0x0)
reg_debug_2 =0x22;
if (reg_mprj_io_34 != 0x0)
reg_debug_2 =0x23;
if (reg_mprj_io_35 != 0x0)
reg_debug_2 =0x24;
if (reg_mprj_io_36 != 0x0)
reg_debug_2 =0x25;
if (reg_mprj_io_37 != 0x0)
reg_debug_2 =0x26;
// housekeeping
if (reg_hkspi_status != old_reg_hkspi_status) // RO
reg_debug_2 =0x27;
if (reg_hkspi_chip_id != old_reg_hkspi_chip_id) // RO
reg_debug_2 =0x28;
if (reg_hkspi_user_id != old_reg_hkspi_user_id) // RO
reg_debug_2 =0x29;
if (reg_hkspi_pll_ena != 0x0) // size =2
reg_debug_2 =0x2a;
if (reg_hkspi_pll_bypass != 0x0) // size = 1
reg_debug_2 = 0x2b;
if (reg_hkspi_irq != old_reg_hkspi_irq) // RO
reg_debug_2 = 0x2c;
if (reg_hkspi_trap != old_reg_hkspi_trap) // RO
reg_debug_2 =0x2d;
if (reg_hkspi_pll_trim != 0x0) // size 26
reg_debug_2 = 0x2f;
if (reg_hkspi_pll_source != 0x0) // size 6 bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider
reg_debug_2 =0x2f;
if (reg_hkspi_pll_divider != 0x0) // size 7 -> PLL output divider, PLL output divider2 , PLL feedback divider
reg_debug_2 =0x30;
if (reg_hkspi_disable != 0x0) // size 1
reg_debug_2 =0x31;
if (reg_clk_out_dest != 0x0) // trap and clocks redirect
reg_debug_2 =0x32;
reg_debug_2 = 0xFF;
}

213
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py Normal file
View File

@ -0,0 +1,213 @@
from json.encoder import INFINITY
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from tests.housekeeping.housekeeping_spi.spi_access_functions import *
import json
reg = Regs()
'''randomly write then read housekeeping regs through wishbone'''
@cocotb.test()
@repot_test
async def hk_regs_wr_wb(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=700,num_error=INFINITY)
cpu = RiskV(dut)
cpu.cpu_force_reset()
with open('wb_models/housekeepingWB/HK_regs.json') as f:
regs = json.load(f)
await ClockCycles(caravelEnv.clk, 10)
# write then read
for i in range(random.randint(7, 20)):
bits_num = 32
mem = random.choice(['GPIO']) # can't access 'SPI' and 'sys' register from interfaces.cpu / read or write
key = random.choice(list(regs[mem].keys()))
if key == 'base_addr':
continue
key_num = int(key,16) & 0xFC
key = generate_key_from_num(key_num)
address = (int(key,16) + regs[mem]['base_addr'][1])
if address in [0x26000010,0x2600000c]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
continue
data_in = random.getrandbits(bits_num)
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to {regs[mem][key][0][0]} address {hex(address)} through wishbone")
await cpu.drive_data2address(address,data_in)
#calculate the expected value for each bit
data_exp = ''
keys = [generate_key_from_num(key_num+3),generate_key_from_num(key_num+2),generate_key_from_num(key_num+1),generate_key_from_num(key_num)]
for count , k in enumerate(keys):
for i in range(int(bits_num/len(keys)) * (count),int(bits_num/len(keys)) * (count+1)):
bit_exist = False
if k in regs[mem].keys():
for field in regs[mem][k]:
field_shift = field[2]
field_size = field[3]
field_access = field[4]
i_temp = (bits_num -1 -i) % (bits_num/4)
if field_shift <= i_temp and i_temp <= (field_shift + field_size-1):
if field_access == "RW":
data_exp += bin(data_in)[2:].zfill(bits_num)[i]
bit_exist = True
break
if not bit_exist:
data_exp += '0'
await ClockCycles(caravelEnv.clk,10)
cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")
data_out = await cpu.read_address(address)
cocotb.log.info(f"[TEST] Read {bin(data_out)} from {regs[mem][key][0][0]} address {hex(address)} through wishbone")
if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from {regs[mem][key][0][0]} address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
else: cocotb.log.info(f"[TEST] read the right value {hex(data_out)} from {regs[mem][key][0][0]} address {hex(address)} ")
'''randomly write then read housekeeping regs through wishbone'''
@cocotb.test()
@repot_test
async def hk_regs_wr_wb_cpu(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=198243,num_error=INFINITY)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
reg1 =0 # buffer
reg2 =0
regs_list = ("reg_hkspi_status","reg_hkspi_chip_id","reg_hkspi_user_id", "reg_hkspi_pll_ena","reg_hkspi_pll_bypass","reg_hkspi_irq","reg_hkspi_trap","reg_hkspi_pll_trim","reg_hkspi_pll_source","reg_hkspi_pll_divide","reg_clk_out_des","reg_hkspi_disable")
while True:
if cpu.read_debug_reg2() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 < 38:
cocotb.log.error(f"[TEST] error while writing 0xFFFFFFFF to reg_mprj_io_{reg1-1}")
else:
cocotb.log.error(f"[TEST] error while writing 0xFFFFFFFF to {regs_list[reg1-39]}")
if reg2 != cpu.read_debug_reg2():
reg2 = cpu.read_debug_reg2()
if reg1 < 38:
cocotb.log.error(f"[TEST] error while writing 0x0 to reg_mprj_io_{reg2-1}")
else:
cocotb.log.error(f"[TEST] error while writing 0x0 to {regs_list[reg1-39]}")
await ClockCycles(caravelEnv.clk,1)
'''randomly write then read housekeeping regs through SPI'''
@cocotb.test()
@repot_test
async def hk_regs_wr_spi(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
with open('wb_models/housekeepingWB/HK_regs.json') as f:
regs = json.load(f)
# write then read single byte
for i in range(random.randint(10, 40)):
bits_num = 8 # byte testing
mem = random.choice(['GPIO','SPI','sys'])
key = random.choice(list(regs[mem].keys()))
if key == 'base_addr':
continue
address = regs[mem][key][0][7]
if address in [111,36]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled
continue
# address = int(key,16)
if address in [0x69,0x6A,0x6B,0x6C]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
continue
data_in = random.getrandbits(bits_num)
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
await write_reg_spi(caravelEnv,address=address,data=data_in)
#calculate the expected value for each bit
is_unknown = False
data_exp = ''
for i in range(bits_num):
bit_exist = False
for field in regs[mem][key]:
field_shift = field[2]
field_size = field[3]
field_access = field[4]
reset_val = field[5]
i_temp = bits_num -1 -i
if field_shift <= i_temp and i_temp <= (field_shift + field_size-1):
if field_access == "RW":
data_exp += bin(data_in)[2:].zfill(bits_num)[i]
bit_exist = True
break
else : # read only get the value from reset
data_exp += bin(reset_val)[2:].zfill(bits_num)[i]
bit_exist = True
break
if field_access == "NA": # that mean the value is unknown as the register value can change by hardware mostly the reg value is input to the housekeeping from other blocks
is_unknown = True
break
if not bit_exist:
data_exp += '0'
if is_unknown:# that mean the value is unknown as the register value can change by hardware mostly the reg value is input to the housekeeping from other blocks
continue
await ClockCycles(caravelEnv.clk,10)
cocotb.log.info(f"[TEST] expected data calculated = {data_exp}")
data_out = await read_reg_spi(caravelEnv,address=address)
cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through SPI")
if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from [{regs[mem][key][0][0]}] address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
else: cocotb.log.info(f"[TEST] read the right value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ")
'''check reset value of house keeping register'''
@cocotb.test()
@repot_test
async def hk_regs_rst_spi(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
with open('wb_models/housekeepingWB/HK_regs.json') as f:
regs = json.load(f)
# read
bits_num = 8 # byte testing
mems = ['GPIO','SPI','sys']
for mem in mems:
keys = [k for k in regs[mem].keys()]
for key in keys:
if key == 'base_addr':
continue
address = regs[mem][key][0][7]
if address in [0x69,0x6A,0x6B,0x6C,0x6D,0x1A]: # skip testing reg_mprj_datal, reg_mprj_datah and usr2_vdd_pwrgood because when reading them it's getting the gpio input value
continue
#calculate the expected value for each bit for reset value
data_exp = ''
# for i in range(bits_num):
bit_exist = False
for field in regs[mem][key]:
field_shift = field[2]
field_size = field[3]
field_access = field[4]
reset_val = field[5]
i_temp = bits_num -1 #-i
# if field_shift <= i_temp and i_temp <= (field_shift + field_size-1):
data_exp = bin(reset_val)[2:].zfill(field_size) + data_exp
print (f'reset = {bin(reset_val)[2:].zfill(bits_num)} data exp = {data_exp} i temp = {i_temp} shift {field_shift} size {field_size}')
# bit_exist = True
# break
# if not bit_exist:
# data_exp += '0'
cocotb.log.info(f"[TEST] expected reset value for [{regs[mem][key][0][0]}] is {data_exp}")
data_out = await read_reg_spi(caravelEnv,address=address)
cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through wishbone")
if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong reset value read from [{regs[mem][key][0][0]}] address {address} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}")
else: cocotb.log.info(f"[TEST] read the right reset value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ")
def generate_key_from_num(num):
hex_string = hex(num)
hex_list = [i for i in hex_string]
if len(hex_list)==3:
hex_list.insert(2,'0')
hex_string = "".join(hex_list)
return hex_string

38
verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py Normal file
View File

@ -0,0 +1,38 @@
async def write_reg_spi(caravelEnv,address,data):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode)
await caravelEnv.disable_csb()
async def read_reg_spi(caravelEnv,address):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x40) # read stream command
await caravelEnv.hk_write_byte(address) # Address
data = await caravelEnv.hk_read_byte() # Data = 0x01 (enable bit-bang mode)
await caravelEnv.disable_csb()
return data
async def reg_spi_user_pass_thru(caravelEnv,command,address):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0xc2) # Apply user pass-thru command to housekeeping SPI
await caravelEnv.hk_write_byte(command) # read command
address = address.to_bytes(3,'big')
await caravelEnv.hk_write_byte(address[0]) # high byte
await caravelEnv.hk_write_byte(address[1]) # middle byte
await caravelEnv.hk_write_byte(address[2]) # low byte
async def reg_spi_user_pass_thru_read(caravelEnv):
data = await caravelEnv.hk_read_byte()
return data
# use for configure in mgmt pass thru or user pass thru
async def reg_spi_op(caravelEnv,command,address):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(command) # command
await caravelEnv.hk_write_byte(address) # Address
await caravelEnv.disable_csb()

3
verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data Normal file
View File

@ -0,0 +1,3 @@
@00000000
6F 00 00 0B 93 01 00 00 13 02 63 57 b5 00 23 20
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00

51
verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py Normal file
View File

@ -0,0 +1,51 @@
from email.headerregistry import Address
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP
from tests.housekeeping.housekeeping_spi.spi_access_functions import *
bit_time_ns = 0
reg = Regs()
@cocotb.test()
@repot_test
async def user_pass_thru_rd(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=14833)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info (f"[TEST] start spi_master_rd test")
file_name = f"{os.getenv('CARAVEL_VERILOG_PATH')}/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data"
mem = read_mem(file_name)
await cocotb.start(SPI_VIP(dut.bin8_monitor,dut.bin9_monitor,dut.bin10_monitor,(dut.bin11_en,dut.bin11),mem)) # fork for SPI
await wait_reg1(cpu,caravelEnv,0XAA)
cocotb.log.info (f"[TEST] Configuration finished")
#The SPI flash may need to be reset
# 0xff and 0xAB commands are suppose to have functionality in the future but for now they would do nothing
await write_reg_spi(caravelEnv,0xc2,0xff) # 0xc2 is for appling user pass-thru command to housekeeping SPI
await write_reg_spi(caravelEnv,0xc2,0xab) # 0xc2 is for appling user pass-thru command to housekeeping SPI
# start reading from memory
address = 0x0
await reg_spi_user_pass_thru(caravelEnv,command = 0x3,address=address) # read command
for i in range(8):
val = await reg_spi_user_pass_thru_read(caravelEnv)
if val != mem[address]:
cocotb.log.error(f"[TEST] reading incorrect value from address {hex(address)} expected = {hex(mem[address])} returened = {val}")
else:
cocotb.log.info(f"[TEST] reading correct value {hex(val)} from address {hex(address)} ")
address +=1
await caravelEnv.disable_csb()
# Wait for processor to restart
await wait_reg1(cpu,caravelEnv,0xBB)
cocotb.log.info(f"[TEST] processor has restarted successfully")

62
verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru_rd.c Normal file
View File

@ -0,0 +1,62 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
#include <stub.c>
void main()
{
// This program is just to keep the processor busy while the
// housekeeping SPI is being accessed. to show that the
// processor is halted while the SPI is accessing the
// flash SPI in pass-through mode.
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
// Management needs to apply output on these pads to access the user area SPI flash
reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI
reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; // SDO
reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; // clk
reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; // csb
// Apply configuration
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
// Start test
reg_debug_1 = 0xAA;
reg_debug_1 = 0xBB;
reg_uart_enable = 1;
// Test in progress
reg_mprj_datal = 0xa5000000;
// Test message
// print("Test message\n");
print("ABC\n");
for (int i=0; i<1200; i++);
// End test
reg_debug_1 = 0xFF;
}

103
verilog/dv/cocotb/tests/irq/IRQ_external.c Normal file
View File

@ -0,0 +1,103 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <csr.h>
#include <soc.h>
#include <irq_vex.h>
#include <uart.h>
#include <defs.h>
/*
Testing timer interrupts
Enable interrupt for IRQ external pin mprj_io[7] -> should be drived to 1 by the environment
**NOTE** housekeeping SPI should used to update register irq_1_inputsrc to 1 see verilog code
@wait for environment to make mprj[7] high
send packet size = 1
@received interrupt correctly test pass
send packet size = 5
@ timeout test fail
send packet size = 9
@ end test
send packet size = 3
send packet size = 3
send packet size = 3
*/
extern uint16_t flag;
void main(){
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
// setting bit 7 as input
reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
// automatic bitbang approach
if(1){
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
}
irq_setmask(0);
irq_setie(1);
irq_setmask(irq_getmask() | (1 << USER_IRQ_4_INTERRUPT));
reg_user4_irq_en =1;
// test interrrupt happen when mprj[7] is asserted
reg_debug_2 = 0xAA; //wait for environment to make mprj[7] high
flag = 0;
// Loop, waiting for the interrupt to change reg_mprj_datah
bool is_pass = false;
int timeout = 40;
for (int i = 0; i < timeout; i++){
if (flag == 1){
reg_debug_1 = 0x1B; //test pass irq sent at mprj 7
is_pass = true;
break;
}
}
if (!is_pass){
reg_debug_1 = 0x1E; // timeout
}
// test interrupt doesn't happened when mprj[7] is deasserted
reg_debug_2 = 0xBB;
flag = 0;
// Loop, waiting for the interrupt to change reg_mprj_datah
is_pass = false;
for (int i = 0; i < timeout; i++){
if (flag == 1){
reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened
is_pass = true;
break;
}
}
if (!is_pass){
reg_debug_1 = 0x2B; // test pass
}
// test finish
reg_debug_2 = 0xFF;
}

71
verilog/dv/cocotb/tests/irq/IRQ_external.py Normal file
View File

@ -0,0 +1,71 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from tests.housekeeping.housekeeping_spi.spi_access_functions import *
reg = Regs()
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@cocotb.test()
@repot_test
async def IRQ_external(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=164360)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start IRQ_external test")
pass_list = (0x1B,0x2B)
fail_list = (0x1E,0x2E)
phases_fails = 2
phases_passes = 0
reg1 =0 # buffer
reg2 = 0 #buffer
await ClockCycles(caravelEnv.clk,10)
await write_reg_spi(caravelEnv,0x1c,1)
await ClockCycles(caravelEnv.clk,10)
cocotb.log.info(f"irq 1 = {dut.uut.housekeeping.irq_1_inputsrc.value}")
while True:
if reg2 != cpu.read_debug_reg2():
reg2 = cpu.read_debug_reg2()
if reg2 == 0xFF: # test finish
break
if reg2 == 0xAA: # assert mprj 7
caravelEnv.drive_gpio_in((7,7),0)
await ClockCycles(caravelEnv.clk,10)
caravelEnv.drive_gpio_in((7,7),1)
if reg2 == 0xBB: # deassert mprj 7
caravelEnv.drive_gpio_in((7,7),0)
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
if reg1 == 0x1B:
cocotb.log.info(f"[TEST] Pass interrupt is detected when mprj 7 asserted")
elif reg1 == 0x2B:
cocotb.log.info(f"[TEST] Pass interrupt isn't detected when mprj 7 deasserted")
elif reg1 in fail_list: # pass phase
if reg1 == 0x1E:
cocotb.log.error(f"[TEST] Failed interrupt isn't detected when mprj 7 asserted")
elif reg1 == 0x2E:
cocotb.log.error(f"[TEST] Failed interrupt is detected when mprj 7 deasserted")
else:
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
await ClockCycles(caravelEnv.clk,10)
if phases_fails != 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")

88
verilog/dv/cocotb/tests/irq/IRQ_timer.c Normal file
View File

@ -0,0 +1,88 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <csr.h>
#include <soc.h>
#include <irq_vex.h>
#include <uart.h>
#include <defs.h>
extern uint16_t flag;
void main(){
uint16_t data;
int i;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
irq_setmask(0);
irq_setie(1);
irq_setmask(irq_getmask() | (1 << TIMER0_INTERRUPT));
reg_debug_2 = 0xAA; //wait for timer to send irq
flag = 0;
/* Configure timer for a single-shot countdown */
reg_timer0_config = 0;
reg_timer0_data = 30;
reg_timer0_irq_en = 1;
reg_timer0_config = 1;
// Loop, waiting for the interrupt to change reg_mprj_datah
bool is_pass = false;
int timeout = 40;
for (int i = 0; i < timeout; i++){
if (flag == 1){
reg_debug_1 = 0x1B; //test pass irq sent at timer0
is_pass = true;
break;
}
}
if (!is_pass){
reg_debug_1 = 0x1E; // timeout
}
flag = 0;
// test interrupt doesn't happened when timer isnt used
reg_debug_2 = 0xBB;
reg_timer0_config = 0; // disable counter
flag = 0;
// Loop, waiting for the interrupt to change reg_mprj_datah
is_pass = false;
for (int i = 0; i < timeout; i++){
if (flag == 1){
reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened
is_pass = true;
break;
}
}
if (!is_pass){
reg_debug_1 = 0x2B; // test pass
}
// test finish
reg_debug_2 = 0xFF;
}

51
verilog/dv/cocotb/tests/irq/IRQ_timer.py Normal file
View File

@ -0,0 +1,51 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
reg = Regs()
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@cocotb.test()
@repot_test
async def IRQ_timer(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=166519)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start IRQ_timer test")
pass_list = (0x1B,0x2B)
fail_list = (0x1E,0x2E)
phases_fails = 2
phases_passes = 0
reg1 =0 # buffer
while True:
if cpu.read_debug_reg2() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
if reg1 == 0x1B:
cocotb.log.info(f"[TEST] Pass interrupt is detected when timer is used")
elif reg1 == 0x2B:
cocotb.log.info(f"[TEST] Pass interrupt isn't detected when timer isnt used")
elif reg1 in fail_list: # pass phase
if reg1 == 0x1E:
cocotb.log.info(f"[TEST] Failed interrupt isn't detected when timer is used")
elif reg1 == 0x2E:
cocotb.log.error(f"[TEST] Failed interrupt is detected when timer isnt used")
else:
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
await ClockCycles(caravelEnv.clk,10)
if phases_fails != 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")

88
verilog/dv/cocotb/tests/irq/IRQ_uart.c Normal file
View File

@ -0,0 +1,88 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
#include <csr.h>
#include <soc.h>
#include <irq_vex.h>
#include <uart.h>
#include <stub.c>
extern uint16_t flag;
void main(){
flag = 0;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = 0x1803;
if(1){
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
}
reg_uart_enable = 1;
reg_uart_irq_en =1;
irq_setmask(0);
irq_setie(1);
irq_setmask(irq_getmask() | (1 << UART_INTERRUPT));
reg_debug_2 = 0xAA; //start sending data through the uart
print("M");
// Loop, waiting for the interrupt to change reg_mprj_datah
bool is_pass = false;
int timeout = 100;
for (int i = 0; i < timeout; i++){
if (flag == 1){
reg_debug_1 = 0x1B; //test pass irq sent
is_pass = true;
break;
}
}
if (!is_pass){
reg_debug_1 = 0x1E; // timeout
}
// test interrupt doesn't happened nothing sent at uart
reg_debug_2 = 0xBB;
flag = 0;
// Loop, waiting for the interrupt to change reg_mprj_datah
is_pass = false;
for (int i = 0; i < timeout; i++){
if (flag == 1){
reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened
is_pass = true;
break;
}
}
if (!is_pass){
reg_debug_1 = 0x2B; // test pass
}
// test finish
reg_debug_2 = 0xFF;
}

64
verilog/dv/cocotb/tests/irq/IRQ_uart.py Normal file
View File

@ -0,0 +1,64 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
async def write_reg_spi(caravelEnv,address,data):
await caravelEnv.enable_csb()
await caravelEnv.hk_write_byte(0x80) # Write stream command
await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control)
await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode)
await caravelEnv.disable_csb()
reg = Regs()
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@cocotb.test()
@repot_test
async def IRQ_uart(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=18613481)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start IRQ_uart test")
pass_list = (0x1B,0x2B)
fail_list = (0x1E,0x2E)
phases_fails = 2
phases_passes = 0
reg1 =0 # buffer
reg2 = 0 #buffer
while True:
if reg2 != cpu.read_debug_reg2():
reg2 = cpu.read_debug_reg2()
if reg2 == 0xFF: # test finish
break
if reg2 == 0xAA:
cocotb.log.info(f"[TEST] start sending through uart")
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
if reg1 == 0x1B:
cocotb.log.info(f"[TEST] Pass interrupt is detected when uart is sending data")
elif reg1 == 0x2B:
cocotb.log.info(f"[TEST] Pass interrupt isn't detected when uart isnt sending data")
elif reg1 in fail_list: # pass phase
if reg1 == 0x1E:
cocotb.log.info(f"[TEST] Failed interrupt isn't detected uart is sending data")
elif reg1 == 0x2E:
cocotb.log.error(f"[TEST] Failed interrupt is detected uart isnt sending data")
else:
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
await ClockCycles(caravelEnv.clk,10)
if phases_fails != 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")

16
verilog/dv/cocotb/tests/logicAnalyzer/.vscode/c_cpp_properties.json vendored Normal file
View File

@ -0,0 +1,16 @@
{
"configurations": [
{
"name": "Linux",
"includePath": [
"${workspaceFolder}/**"
],
"defines": [],
"compilerPath": "/usr/bin/gcc",
"cStandard": "gnu17",
"cppStandard": "gnu++14",
"intelliSenseMode": "linux-gcc-x64"
}
],
"version": 4
}

111
verilog/dv/cocotb/tests/logicAnalyzer/la.c Normal file
View File

@ -0,0 +1,111 @@
#include <defs.h>
#include <stub.c>
void main(){
unsigned int i, j, k;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_hkspi_disable = 1;
// Configure LA probes [63:32] and [127:96] as inputs to the cpu
// Configure LA probes [31:0] and [63:32] as outputs from the cpu
reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0]
reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64]
reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
reg_la0_data = 0xAAAAAAAA;
reg_la2_data = 0xAAAAAAAA;
reg_debug_2 = reg_la1_data_in;
if (reg_la1_data_in != 0xAAAAAAAA)
reg_debug_1 = 0x1E;
else
reg_debug_1 = 0x1B;
reg_debug_2 = reg_la3_data_in;
if (reg_la3_data_in != 0xAAAAAAAA)
reg_debug_1 = 0x2E;
else
reg_debug_1 = 0x2B;
reg_la0_data = 0x55555555;
reg_la2_data = 0x55555555;
reg_debug_2 = reg_la1_data_in;
if (reg_la1_data_in != 0x55555555)
reg_debug_1 = 0x3E;
else
reg_debug_1 = 0x3B;
reg_debug_2 = reg_la3_data_in;
if (reg_la3_data_in != 0x55555555)
reg_debug_1 = 0x4E;
else
reg_debug_1 = 0x4B;
// Configure LA probes [31:0] and [63:32] as inputs to the cpu
// Configure LA probes [63:32] and [127:96] as outputs from the cpu
reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
reg_la1_data = 0xAAAAAAAA;
reg_la3_data = 0xAAAAAAAA;
reg_debug_2 = reg_la0_data_in;
if (reg_la0_data_in != 0xAAAAAAAA)
reg_debug_1 = 0x5E;
else
reg_debug_1 = 0x5B;
reg_debug_2 = reg_la2_data_in;
if (reg_la2_data_in != 0xAAAAAAAA)
reg_debug_1 = 0x6E;
else
reg_debug_1 = 0x6B;
reg_la1_data = 0x55555555;
reg_la3_data = 0x55555555;
reg_debug_2 = reg_la0_data_in;
if (reg_la0_data_in != 0x55555555)
reg_debug_1 = 0x7E;
else
reg_debug_1 = 0x7B;
reg_debug_2 = reg_la2_data_in;
if (reg_la2_data_in != 0x55555555)
reg_debug_1 = 0x8E;
else
reg_debug_1 = 0x8B;
// Configure LA probes [31:0] and [63:32] as inputs to the cpu
// Configure LA probes [63:32] and [127:96] as disabled input and output
reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96]
reg_la1_iena = reg_la3_iena = 0x00000000; // disable input for la1 and la3
reg_la1_data = 0xAAAAAAAA;
reg_la3_data = 0xAAAAAAAA;
reg_debug_2 = reg_la0_data_in;
if (reg_la0_data == 0xAAAAAAAA)
reg_debug_1 = 0x9E;
else
reg_debug_1 = 0x9B;
reg_debug_2 = reg_la2_data_in;
if (reg_la2_data == 0xAAAAAAAA)
reg_debug_1 = 0xaE;
else
reg_debug_1 = 0xaB;
reg_debug_2 = 0xFF;
}

48
verilog/dv/cocotb/tests/logicAnalyzer/la.py Normal file
View File

@ -0,0 +1,48 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
from cocotb.binary import BinaryValue
reg = Regs()
@cocotb.test()
@repot_test
async def la(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
pass_list = (0x1B,0x2B,0x3B,0x4B,0x5B,0x6B,0x7B,0x8B,0x9B,0xaB)
fail_list = (0x1E,0x2E,0x3E,0x4E,0x5E,0x6E,0x7E,0x8E,0x9E,0xaE)
phases_fails = 10
phases_passes = 0
reg1 =0 # buffer
while True:
if cpu.read_debug_reg2() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
cocotb.log.info(f"[TEST] test passes phase {hex(reg1)[2]}")
elif reg1 in fail_list: # fail phase
cocotb.log.error(f"[TEST] test fails phase {hex(reg1)[2]} incorrect value recieved {hex(cpu.read_debug_reg2())}")
await ClockCycles(caravelEnv.clk,1)
if phases_fails != 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
await ClockCycles(caravelEnv.clk, 10000)

102
verilog/dv/cocotb/tests/mem/mem_stress.c Normal file
View File

@ -0,0 +1,102 @@
#include <defs.h>
/*
@ start of test
send packet with size = 1
@ pass bytes
send packet with size = 2
@ pass int
send packet with size = 3
@ pass short
send packet with size = 4
@ error reading
send packet with size = 9
@ test finish
send packet with size = 7
send packet with size = 7
send packet with size = 7
*/
#define BYTE_SIZE 800
#define SHORT_SIZE BYTE_SIZE/2
#define INT_SIZE BYTE_SIZE/4
void main()
{
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
unsigned char dff_bytes[BYTE_SIZE];
unsigned short *dff_shorts=(unsigned short *) dff_bytes;
unsigned int *dff_ints=(unsigned int *) dff_bytes;
unsigned char magic = 0x79;
unsigned int magic_int = 0x79797979;
unsigned short magic_short = 0x7979;
unsigned char magic1;
unsigned int magic1_int;
unsigned short magic1_short;
int i;
magic1 = magic;
for ( i=0; i<BYTE_SIZE; i++){
dff_bytes[i] = (magic1*3+5)|magic;
magic1 += 11;
}
magic1 = magic;
bool is_fail = false;
for ( i=0; i<BYTE_SIZE; i++){
unsigned char t = (magic1*3+5)|magic;
if (t != dff_bytes[i]){
reg_debug_1 = 0x1E; // fail reading bytes expected value
is_fail = true;
break;
}
magic1 += 11;
}
if (!is_fail)
reg_debug_1 = 0x1B; // pass reading bytes expected value
is_fail = false;
// int
magic1_int = magic_int;
for ( i=0; i<INT_SIZE; i++){
dff_ints[i] = (magic1_int*3+5)|magic_int;
magic1_int += 11;
}
magic1_int = magic_int;
for ( i=0; i<INT_SIZE; i++){
unsigned int t = (magic1_int*3+5)|magic_int;
if (t != dff_ints[i]){
reg_debug_1 = 0x2E; // fail reading ints expected value
is_fail = true;
break;
}
magic1_int += 11;
}
if (!is_fail)
reg_debug_1 = 0x2B; // pass reading ints expected value
is_fail = false;
// short
magic1_short = magic_short;
for ( i=0; i<SHORT_SIZE; i++){
dff_shorts[i] = (magic1_short*3+5)|magic_short;
magic1_short += 11;
}
magic1_short = magic_short;
for ( i=0; i<SHORT_SIZE; i++){
unsigned short t = (magic1_short*3+5)|magic_short;
if (t != dff_shorts[i]){
reg_debug_1 = 0x3E; // fail reading shorts expected value
is_fail = true;
break;
}
magic1_short += 11;
}
if (!is_fail)
reg_debug_1 = 0x3B; // pass reading ints expected value
// test finish
reg_debug_2 = 0xFF;
}

51
verilog/dv/cocotb/tests/mem/mem_stress.py Normal file
View File

@ -0,0 +1,51 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
reg = Regs()
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@cocotb.test()
@repot_test
async def mem_stress(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start mem stress test")
pass_list = (0x1B,0x2B,0x3B)
fail_list = (0x1E,0x2E,0x3E)
phases_fails = 3
phases_passes = 0
reg1 =0 # buffer
while True:
if cpu.read_debug_reg2() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
cocotb.log.info(f"[TEST] pass writing and reading from {phase_to_type(hex(reg1)[2])}")
elif reg1 in fail_list: # pass phase
cocotb.log.error(f"[TEST] failed phase {phase_to_type(hex(reg1)[2])}")
await ClockCycles(caravelEnv.clk,1)
if phases_fails > 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
def phase_to_type(phase):
if phase == "1":
return "800 Bytes"
elif phase == "2":
return "200 Words"
elif phase == "3":
return "400 Halfwords"

166
verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py Normal file
View File

@ -0,0 +1,166 @@
import random
import re
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
reg = Regs()
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@cocotb.test()
@repot_test
async def mgmt_gpio_out(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=99562)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start mgmt_gpio_out test")
phases_fails = 3
phases_passes = 0
reg1 =0 # buffer
reg2 = 0 #buffer
while True:
if reg2 != cpu.read_debug_reg2():
reg2 = cpu.read_debug_reg2()
if reg2 == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
cocotb.log.info(f"[TEST] waiting for {reg1} blinks")
for i in range(reg1):
while (True):
if caravelEnv.monitor_mgmt_gpio() == 0:
break
if reg1 != cpu.read_debug_reg1():
cocotb.log.error("[TEST] error failing to catch all blinking ")
return
await ClockCycles(caravelEnv.clk,10)
while (True):
if caravelEnv.monitor_mgmt_gpio() == 1:
break
if reg1 != cpu.read_debug_reg1():
cocotb.log.error("[TEST] error failing to catch all blinking ")
return
await ClockCycles(caravelEnv.clk,10)
cocotb.log.info("[TEST] passing sending {reg1} blinks ")
phases_fails -=1
phases_passes +=1
await ClockCycles(caravelEnv.clk,10)
if phases_fails != 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
@cocotb.test()
@repot_test
async def mgmt_gpio_in(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=326525)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start mgmt_gpio_in test")
phases_fails = 3
phases_passes = 0
pass_list = (0x1B,0x2B,0xFF)
fail_list = tuple([0xEE])
reg1 =0 # buffer
reg2 = 0 #buffer
while True:
if reg2 != cpu.read_debug_reg2():
reg2 = cpu.read_debug_reg2()
if reg2 in pass_list:
cocotb.log.info (f"[TEST] reg2 = {reg2}")
phases_passes +=1
phases_fails -=1
if reg2 == 0xFF: # test finish
break
elif reg2 == 0x1B:
cocotb.log.info(f"[TEST] pass sending 10 blink ")
elif reg2 == 0x2B:
cocotb.log.info(f"[TEST] pass sending 20 blink ")
if reg2 in fail_list:
cocotb.log.error(f"[TEST] gpio change without sending anything")
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
cocotb.log.info(f"[TEST] start sending {reg1} blinks")
for i in range(reg1):
caravelEnv.drive_mgmt_gpio(1)
await wait_reg2(cpu,caravelEnv,0XAA)
caravelEnv.drive_mgmt_gpio(0)
await wait_reg2(cpu,caravelEnv,0XBB)
cocotb.log.info(f"[TEST] finish sending {reg1} blinks ")
await ClockCycles(caravelEnv.clk,10)
if phases_fails != 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
@cocotb.test()
@repot_test
async def mgmt_gpio_bidir(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=243058)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start mgmt_gpio_in test")
phases_fails = 3
phases_passes = 0
pass_list = (0x1B,0x2B,0xFF)
fail_list = tuple([0xEE])
reg2 = 0 #buffer
await wait_reg1(cpu,caravelEnv,0XAA)
num_blinks = random.randint(1, 20)
cocotb.log.info (f"[TEST] start send {num_blinks} blinks")
for i in range(num_blinks):
if i == num_blinks-1: #last iteration
# await cpu.drive_data2address(reg.get_addr('reg_debug_1'),0xFF)
cpu.write_debug_reg1_backdoor(0xFF)
caravelEnv.drive_mgmt_gpio(1)
await ClockCycles(caravelEnv.clk,4000)
caravelEnv.drive_mgmt_gpio(0)
await ClockCycles(caravelEnv.clk,4000)
cocotb.log.info(f"[TEST] finish sending {num_blinks} blinks ")
cocotb.log.info(f"[TEST] waiting for {num_blinks} blinks ")
recieved_blinks = 0
while True:
cocotb.log.info(f"[TEST] here 0 ")
if cpu.read_debug_reg2() == 0xFF: #test finish
break
while (True):
if caravelEnv.monitor_mgmt_gpio() == 0:
break
if cpu.read_debug_reg2() == 0xFF: #test finish
break
cocotb.log.info(f"[TEST] here 1 ")
await ClockCycles(caravelEnv.clk,10)
while (True):
if caravelEnv.monitor_mgmt_gpio() == 1:
recieved_blinks +=1
break
if cpu.read_debug_reg2() == 0xFF: #test finish
break
cocotb.log.info(f"[TEST] here 2 ")
await ClockCycles(caravelEnv.clk,10)
await ClockCycles(caravelEnv.clk,1)
if recieved_blinks == num_blinks:
cocotb.log.info(f"[TEST] recieved the correct number of blinks {num_blinks}")
else:
cocotb.log.error(f"[TEST] recieved the incorrect number of blinks recieved = {recieved_blinks} expected = {num_blinks}")

61
verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c Normal file
View File

@ -0,0 +1,61 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
// --------------------------------------------------------
/*
* Management SoC GPIO Pin Test
* Tests writing to the GPIO pin.
*/
void main()
{
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_gpio_mode1 = 1;
reg_gpio_mode0 = 0; // for full swing
reg_gpio_ien = 1;
reg_gpio_oe = 0;
int num_blinks = 0;
reg_debug_1 = 0xAA; // start of the test
int z = reg_debug_1;
while (true) {
// reg_debug_2 = z;
// z= reg_debug_1;
while(reg_gpio_in == 0);
while(reg_gpio_in == 1);
num_blinks++;
if (reg_debug_1 == 0xFF)
break;
}
reg_gpio_ien = 0;
reg_gpio_oe = 1;
for (int i = 0; i < num_blinks; i++) {
/* Fast blink for simulation */
reg_gpio_out = 1;
reg_gpio_out = 0;
}
reg_debug_2 = 0xFF; //finish test
}

67
verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_in.c Normal file
View File

@ -0,0 +1,67 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
// --------------------------------------------------------
/*
* Management SoC GPIO Pin Test
* Tests writing to the GPIO pin.
*/
void main()
{
int temp_in;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_gpio_mode1 = 1;
reg_gpio_mode0 = 0; // for full swing
reg_gpio_ien = 1;
reg_gpio_oe = 1;
reg_debug_1 = 10; // wait for 10 blinks
for (int i = 0; i < 10; i++) {
while(reg_gpio_in == 0);
reg_debug_2 = 0XAA; // 1 is recieved
while(reg_gpio_in == 1);
reg_debug_2 = 0XBB; // 0 is recieved
}
reg_debug_2 = 0x1B;
reg_debug_1 = 20;
for (int i = 0; i < 20; i++) {
while(reg_gpio_in == 0);
reg_debug_2 = 0XAA; // 1 is recieved
while(reg_gpio_in == 1);
reg_debug_2 = 0XBB; // 0 is recieved
}
reg_debug_2 = 0x2B;
temp_in = reg_gpio_in;
reg_debug_1 = 0;
for (int i =0; i<50;i++){ // timeout
if (temp_in != reg_gpio_in)
reg_debug_2 = 0xEE; //finish test
}
reg_debug_2 = 0xFF; //finish test
}

59
verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_out.c Normal file
View File

@ -0,0 +1,59 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
// --------------------------------------------------------
/*
* Management SoC GPIO Pin Test
* Tests writing to the GPIO pin.
*/
void main()
{
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_gpio_mode1 = 1;
reg_gpio_mode0 = 0; // for full swing
reg_gpio_ien = 1;
reg_gpio_oe = 1;
reg_debug_1 = 10;
for (int i = 0; i < 10; i++) {
/* Fast blink for simulation */
reg_gpio_out = 1;
reg_gpio_out = 0;
}
reg_debug_1 = 20;
for (int i = 0; i < 20; i++) {
/* Fast blink for simulation */
reg_gpio_out = 1;
reg_gpio_out = 0;
}
reg_debug_1 = 0;
reg_debug_1 = 0; // for more delay
reg_debug_1 = 0;
reg_debug_2 = 0xFF; //finish test
}

86
verilog/dv/cocotb/tests/spi_master/SPI_VIP.py Normal file
View File

@ -0,0 +1,86 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
import cocotb.log
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
#VIP for SPI
"""
support commands
00000000 -> No operation
00000011 -> Read in streaming mode
"""
async def SPI_VIP(csb,clk,SDI,SDO,mem):
while True:
await FallingEdge(csb)
cocotb.log.info (f"[SPI_VIP] CSB is asserted operation has begin ")
op = await cocotb.start(SPI_op(clk,SDI,SDO,mem))
await csb_watcher(csb,op)
cocotb.log.info (f"[SPI_VIP] CSB is deasserted operation has been killed")
# watch the csb and when it's diable kill the SPI_op thread
async def csb_watcher(csb,thread):
cocotb.log.info (f"[csb_watcher] start CSB watching")
await RisingEdge(csb)
thread.kill()
# detect command and address and apply the command
async def SPI_op(clk,SDI,SDO,mem):
address =''
command =''
await RisingEdge(clk)
# command
for i in range(8):
command = command + SDI.value.binstr
await RisingEdge(clk)
cocotb.log.info (f"[SPI_VIP] [SPI_op] command = {command}")
# address
address =''
for i in range(8*3): # address is 3 parts each part are 8 bits
address = address + SDI.value.binstr
if i != 23: # skip last cycle wait
await RisingEdge(clk)
cocotb.log.info (f"[SPI_VIP] [SPI_op] address = {address}")
address = int(address,2)
#data
if command == "10000000" and False: # not sure about the read command
for i in range(8):
data_in += SDI
await RisingEdge(clk)
elif command == "00000011":
await FallingEdge(clk)
while True:
data = bin(mem[address])[2:].zfill(8)
for i in range(8):
SDO[0].value = 1 # enable
SDO[1].value = int(data[i],2) # bin
cocotb.log.debug (f"[SPI_VIP] [SPI_op] SDO = {data[i]} ")
await FallingEdge(clk)
SDO[0].value = 0 # enable
cocotb.log.info (f"[SPI_VIP] [SPI_op] finish reading address {hex(address) } data = {hex(int(data,2))} ")
address +=1
def read_mem (file_name):
with open(file_name, 'r') as file:
lines = file.readlines()
mem = dict()
for line in lines:
if line[0] == "@":
address = int(line[1:],16)
cocotb.log.debug (f" found line = {line} address = {hex(address)} ")
else:
line_no_space = line.strip().replace(' ','')
for i in range (0,len(line_no_space),2):
cocotb.log.debug (f" i = {i} ine_no_space[{i}:{i+2}] = {line_no_space[i:i+2]} address = {hex(address)}")
mem[address] = int(line_no_space[i:i+2],16)
address +=1
cocotb.log.debug (f" found line = {line} line_no_space = {line_no_space} size = {len(line_no_space)}")
cocotb.log.info (f"[read_mem] SPI mem = {mem}")
return mem

104
verilog/dv/cocotb/tests/spi_master/spi_master.py Normal file
View File

@ -0,0 +1,104 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP
from interfaces.caravel import GPIO_MODE
bit_time_ns = 0
reg = Regs()
@cocotb.test()
@repot_test
async def spi_master_rd(dut):
""" the firmware is configured to always send clk to spi so I can't insert alot of logics reading values
the method of testing used can't work if 2 addresses Consecutive have the same address
"""
caravelEnv,clock = await test_configure(dut,timeout_cycles=214842)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info (f"[TEST] start spi_master_rd test")
file_name = f"{os.getenv('CARAVEL_VERILOG_PATH')}/dv/cocotb/tests/spi_master/test_data"
mem = read_mem(file_name)
await cocotb.start(SPI_VIP(dut.bin33_monitor,dut.bin32_monitor,dut.bin35_monitor,(dut.bin34_en,dut.bin34),mem)) # fork for SPI
addresses_to_read = (0x04,0x05,0x06,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf) # the addresses that the firmware read from mem file
await wait_reg2(cpu,caravelEnv,0XAA)
cocotb.log.info (f"[TEST] GPIO configuration finished ans start reading from mememory")
val =0
for address in addresses_to_read:
# await wait_reg2(cpu,caravelEnv,0x55) # value is ready to be read
#wait until value change
while True:
if val != cpu.read_debug_reg1():
break
await ClockCycles(caravelEnv.clk,100)
expected_val = mem[address]
val = cpu.read_debug_reg1()
if val == expected_val:
cocotb.log.info(f"[TEST] correct read of value {hex(val)} from address {hex(address)} ")
else:
cocotb.log.error(f"[TEST] wrong read from address {hex(address)} expected value = {hex(expected_val)} value {hex(val)} ")
# cpu.write_debug_reg2_backdoor(0xCC)
await ClockCycles(caravelEnv.clk,1000)
@cocotb.test()
@repot_test
async def spi_master_temp(dut):
""" the firmware is configured to always send clk to spi so I can't insert alot of logics reading values
the method of testing used can't work if 2 addresses Consecutive have the same address
"""
caravelEnv,clock = await test_configure(dut,timeout_cycles=214842)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info (f"[TEST] start spi_master_temp test")
await FallingEdge(dut.bin33_monitor)
await RisingEdge(dut.bin32_monitor)
a = ''
b = ''
# first value
for i in range(8):
a = a + dut.bin35_monitor.value.binstr
await RisingEdge(dut.bin32_monitor)
cocotb.log.info (f" [TEST] a = {a} = {int(a,2)}")
# second val
for i in range(8):
b = b + dut.bin35_monitor.value.binstr
await RisingEdge(dut.bin32_monitor)
cocotb.log.info (f" [TEST] b = {b} = {int(b,2)}")
s = int(a,2) + int(b,2)
s_bin = bin(s)[2:].zfill(8)
cocotb.log.info (f" [TEST] sending sum of {int(a,2)} + {int(b,2)} = {s} = {s_bin}")
for i in range(8):
dut.bin34_en.value = 1
dut.bin34.value = int(s_bin[i],2) # bin
cocotb.log.debug (f"[SPI_VIP] [SPI_op] SDO = {s_bin[i]} ")
await FallingEdge(dut.bin32_monitor)
dut.bin34_en.value = 0 # enable
while True:
if cpu.read_debug_reg1() == 0xBB:
cocotb.log.info(f" [TEST] firmware recieve the right value {s}")
break
elif cpu.read_debug_reg1() == 0xBB:
cocotb.log.error(f" [TEST] firmware recieve the incorrect value {cpu.read_debug_reg2()} instead of {s}")
break
await ClockCycles(caravelEnv.clk,10)

180
verilog/dv/cocotb/tests/spi_master/spi_master_rd.c Normal file
View File

@ -0,0 +1,180 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
#include <csr.h>
// --------------------------------------------------------
/*
* SPI master Test
* - Enables SPI master
* - Uses SPI master to talk to external SPI module
*/
void spi_write(char c)
{
reg_spimaster_wdata = (unsigned long) c;
// reg_spimaster_wdata = c;
// spi_master_control_length_write(8);
// spi_master_control_start_write(1);
// reg_spimaster_control = 0x0800;
reg_spimaster_control = 0x0801;
}
char spi_read()
{
// reg_spimaster_wdata = c;
// spi_master_control_length_write(8);
// spi_master_control_start_write(1);
// reg_spimaster_control = 0x0800;
// spi_write(0x00);
// reg_spimaster_rdata = 0x00;
// reg_spimaster_control = 0x0801;
spi_write(0x00);
while (reg_spimaster_status != 1);
return reg_spimaster_rdata;
}
void main()
{
int i;
uint32_t value;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
// For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4
// should be outputs.
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; // SDO
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; // CSB
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; // SCK
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_2 =0xAA;
reg_spi_enable = 1;
// For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4
// should be outputs.
// Start test
// Enable SPI master
// SPI master configuration bits:
// bits 7-0: Clock prescaler value (default 2)
// bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
// bit 9: CSB sense (0 = inverted, 1 = noninverted)
// bit 10: SCK sense (0 = noninverted, 1 = inverted)
// bit 11: mode (0 = read/write opposite edges, 1 = same edges)
// bit 12: stream (1 = CSB ends transmission)
// bit 13: enable (1 = enabled)
// bit 14: IRQ enable (1 = enabled)
// bit 15: (unused)
reg_spimaster_cs = 0x10001; // sel=0, manual CS
spi_write(0x03); // Write 0x03 (read mode)
spi_write(0x00); // Write 0x00 (start address high byte)
spi_write(0x00); // Write 0x00 (start address middle byte)
spi_write(0x04); // Write 0x04 (start address low byte)
value = spi_read(); // 0x93
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
value = spi_read(); // 0x01
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
value = spi_read(); // 0x00
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
reg_spimaster_cs = 0x0000; // release CS
reg_spimaster_cs = 0x10001; // sel=0, manual CS
spi_write(0x03); // Write 0x03 (read mode)
spi_write(0x00); // Write 0x00 (start address high byte)
spi_write(0x00); // Write 0x00 (start address middle byte)
spi_write(0x08); // Write 0x08 (start address low byte)
value = spi_read(); // 0x13
if (value == 0x13)
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
value = spi_read(); // 0x02
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
reg_spimaster_cs = 0x0000; // release CS
reg_spimaster_cs = 0x10001; // sel=0, manual CS
spi_write(0x03); // Write 0x03 (read mode)
spi_write(0x00); // Write 0x00 (start address high byte)
spi_write(0x00); // Write 0x00 (start address middle byte)
spi_write(0x0a); // Write 0x0a (start address low byte)
value = spi_read(); // 0x63
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
value = spi_read(); // 0x57
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
value = spi_read(); // 0xb5
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
value = spi_read(); // 0x00
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
value = spi_read();// 0x23
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
value = spi_read(); // 0x20
reg_debug_1 = value;
// reg_debug_2 =0x55; // value is ready to be read
// while (reg_debug_2 != 0xCC) // testbench has read the value
reg_spimaster_cs = 0x0000; // release CS
reg_spimaster_cs = 0x10001; // sel=0, manual CS
}

111
verilog/dv/cocotb/tests/spi_master/spi_master_temp.c Normal file
View File

@ -0,0 +1,111 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
#include <csr.h>
// --------------------------------------------------------
/*
* SPI master Test
* - Enables SPI master
* - Uses SPI master to talk to external SPI module
*/
void spi_write(char c)
{
reg_spimaster_wdata = (unsigned long) c;
// reg_spimaster_wdata = c;
// spi_master_control_length_write(8);
// spi_master_control_start_write(1);
// reg_spimaster_control = 0x0800;
reg_spimaster_control = 0x0801;
}
char spi_read()
{
// reg_spimaster_wdata = c;
// spi_master_control_length_write(8);
// spi_master_control_start_write(1);
// reg_spimaster_control = 0x0800;
// spi_write(0x00);
// reg_spimaster_rdata = 0x00;
// reg_spimaster_control = 0x0801;
spi_write(0x00);
while (reg_spimaster_status != 1);
return reg_spimaster_rdata;
}
void main()
{
int i;
uint32_t value;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
// For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4
// should be outputs.
reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI
reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; // SDO
reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; // CSB
reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; // SCK
/* Apply configuration */
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_debug_2 =0xAA;
reg_spi_enable = 1;
// For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4
// should be outputs.
// Start test
// Enable SPI master
// SPI master configuration bits:
// bits 7-0: Clock prescaler value (default 2)
// bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first)
// bit 9: CSB sense (0 = inverted, 1 = noninverted)
// bit 10: SCK sense (0 = noninverted, 1 = inverted)
// bit 11: mode (0 = read/write opposite edges, 1 = same edges)
// bit 12: stream (1 = CSB ends transmission)
// bit 13: enable (1 = enabled)
// bit 14: IRQ enable (1 = enabled)
// bit 15: (unused)
reg_spimaster_cs = 0x10001; // sel=0, manual CS
spi_write(0x08); // Write 0x03 (read mode)
spi_write(0x05); // Write 0x00 (start address high byte)
value = spi_read(); // 0x93
if (value == 0xD)
reg_debug_1 = 0xBB; // get correct value
else {
reg_debug_2 = value;
reg_debug_1 = 0xEE; // get wrong value
}
reg_spimaster_cs = 0x0000; // release CS
reg_spimaster_cs = 0x10001; // sel=0, manual CS
}

3
verilog/dv/cocotb/tests/spi_master/test_data Normal file
View File

@ -0,0 +1,3 @@
@00000000
6F 00 00 0B 93 01 00 00 13 02 63 57 b5 00 23 20
13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00

47
verilog/dv/cocotb/tests/temp_partial_test/partial.py Normal file
View File

@ -0,0 +1,47 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
reg = Regs()
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@cocotb.test()
@repot_test
async def temp_partial(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=70000)
# Apply data 0x1809 (management standard output) to first block of
# user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
while True:
if cpu.read_debug_reg2() == 0xAA:
break
await ClockCycles(caravelEnv.clk,1)
cpu.cpu_force_reset()
await ClockCycles(caravelEnv.clk,100)
await cpu.drive_data2address(reg.get_addr('reg_wb_enable'),1)
await cpu.drive_data2address(reg.get_addr('reg_debug_1'),0xAA)
# await cpu.drive_data2address(reg.get_addr('reg_debug_2'),0xBB)
await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0)
# await ClockCycles(caravelEnv.clk,100)
cpu.cpu_release_reset()
while True:
if cpu.read_debug_reg2() == 0xBB:
break
await ClockCycles(caravelEnv.clk,1)
await ClockCycles(caravelEnv.clk,100)

103
verilog/dv/cocotb/tests/timer/timer.py Normal file
View File

@ -0,0 +1,103 @@
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
reg = Regs()
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
@cocotb.test()
@repot_test
async def timer0_oneshot(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=1114136)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start timer0_oneshot test")
cocotb.log.info(f"[TEST] Configure timer as oneshot")
pass_list = (0x1B,0x2B,0x3B)
fail_list = (0x1E,0x2E)
phases_fails = 3
phases_passes = 0
reg1 =0 # buffer
while True:
if cpu.read_debug_reg2() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
if reg1 == 0x1B:
cocotb.log.info(f"[TEST] Pass timer0 value is decreasing")
elif reg1 == 0x2B:
cocotb.log.info(f"[TEST] Pass timer0 value reach 0")
elif reg1 == 0x3B:
cocotb.log.info(f"[TEST] Pass timer0 isn't changing after it reachs 0")
elif reg1 in fail_list: # pass phase
if reg1 == 0x1E:
cocotb.log.info(f"[TEST] Failed timer0 value increasing not decresing in oneshot mode")
elif reg1 == 0x2E:
cocotb.log.error(f"[TEST] Failed timer0 is changing before it reachs 0 in oneshot mode")
else:
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
await ClockCycles(caravelEnv.clk,10)
if phases_fails != 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
@cocotb.test()
@repot_test
async def timer0_periodic(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=58257)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start timer0_periodic test")
cocotb.log.info(f"[TEST] Configure timer as periodic")
pass_list = (0x1B,0x2B,0x3B,0x4B)
fail_list = (0xEE)
phases_fails = 4
phases_passes = 0
reg1 =0 # buffer
fourB_happened = False
while True:
if cpu.read_debug_reg2() == 0xFF: # test finish
break
if reg1 != cpu.read_debug_reg1():
reg1 = cpu.read_debug_reg1()
if reg1 in pass_list: # pass phase
phases_passes +=1
phases_fails -=1
if reg1 == 0x1B:
cocotb.log.info(f"[TEST] Pass timer0 first rollover")
elif reg1 == 0x2B:
cocotb.log.info(f"[TEST] Pass timer0 second rollover")
elif reg1 == 0x3B:
cocotb.log.info(f"[TEST] Pass timer0 third rollover")
elif reg1 == 0x4B:
if fourB_happened: # this phase happened one time before
phases_passes -=1
phases_fails +=1
else:
cocotb.log.info(f"[TEST] Pass timer0 counter value decreases")
fourB_happened = True
elif reg1 in fail_list: # pass phase
if reg1 == 0xEE:
cocotb.log.info(f"[TEST] Failed timer0 value hasn't rollovered in periodic mode")
else:
cocotb.log.error(f"[TEST] debug register 1 has illegal value")
await ClockCycles(caravelEnv.clk,10)
if phases_fails != 0:
cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")
else:
cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")

70
verilog/dv/cocotb/tests/timer/timer0_oneshot.c Normal file
View File

@ -0,0 +1,70 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
/*
Testing timer interrupts
Enable interrupt for timer0 and configure it as countdown 1 shot wait for interrupt
*/
void main(){
uint32_t value;
uint32_t old_value;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
/* Configure timer for a single-shot countdown */
reg_timer0_config = 0; // disable
reg_timer0_data = 0xF3000;
reg_timer0_config = 1; // enable
// Loop, waiting for the interrupt to change reg_mprj_datah
// test path if counter value stop updated after reach 0 and also the value is always decrementing
reg_timer0_update = 1; // update reg_timer0_value with new counter value
old_value = reg_timer0_value;
// value us decrementing until it reachs zero
while (1) {
reg_timer0_update = 1; // update reg_timer0_value with new counter value
value = reg_timer0_value;
if (value < old_value && value != 0){
reg_debug_1 = 0x1B; // value decrease
}
else if (value == 0){
reg_debug_1 = 0x2B; // value reach 0
break;
}else{
reg_debug_1 = 0x1F; // value updated incorrectly
}
old_value = value;
}
// check 10 times that value don't change from 0
for (int i = 0; i < 10; i++);
reg_timer0_update = 1; // update reg_timer0_value with new counter value
if (reg_timer0_value == 0){
reg_debug_1 = 0x3B; //timer updated correctly
}else{
reg_debug_1 = 0x2F; //timer updated incorrectly
}
reg_debug_2 = 0xFF; // finish test
}

73
verilog/dv/cocotb/tests/timer/timer0_periodic.c Normal file
View File

@ -0,0 +1,73 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
/*
Testing timer interrupts
Enable interrupt for timer0 and configure it as countdown 1 shot
wait for interrupt
*/
void main(){
uint32_t value;
uint32_t old_value;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
/* Configure timer for a single-shot countdown */
reg_timer0_config = 0; // disable
reg_timer0_data = 0;
reg_timer0_data_periodic = 0x300;
reg_timer0_config = 1; // enable
// Loop, waiting for the interrupt to change reg_mprj_datah
// test path if counter value stop updated after reach 0 and also the value is always decrementing
reg_timer0_update = 1; // update reg_timer0_value with new counter value
old_value = reg_timer0_value;
// value us decrementing until it reachs zero
int rollover = 0;
int timeout = 400;
for (int i = 0; i < timeout; i++){
reg_timer0_update = 1; // update reg_timer0_value with new counter value
value = reg_timer0_value;
if (value > old_value){
rollover++;
if (rollover==1)
reg_debug_1 = 0x1B; // timer rollover
else if (rollover==2)
reg_debug_1 = 0x2B; //timer rollover second time
else if (rollover==3){
reg_debug_1 = 0x3B; //timer rollover second time
break;
}
}
if (value < old_value){
reg_debug_1 = 0x4B; // value decreases
}
old_value = value;
}
if (rollover ==0){
reg_debug_1 = 0xEE; // counter didn't rollover
}
reg_debug_2 = 0xFF; // finish test
}

164
verilog/dv/cocotb/tests/uart/uart.py Normal file
View File

@ -0,0 +1,164 @@
from curses import baudrate
import random
import cocotb
from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer,Edge
import cocotb.log
from interfaces.cpu import RiskV
from interfaces.defsParser import Regs
from cocotb.result import TestSuccess
from tests.common_functions.test_functions import *
from tests.bitbang.bitbang_functions import *
from interfaces.caravel import GPIO_MODE
bit_time_ns = 0
reg = Regs()
@cocotb.test()
@repot_test
async def uart_tx(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=375862)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start uart test")
expected_msg = "Monitor: Test UART (RTL) passed"
# calculate bit time
clk = clock.period/1000
global bit_time_ns
bit_time_ns = round(10**5 * clk / (96))
# wait for start of sending
await wait_reg1(cpu,caravelEnv,0XAA)
cocotb.log.info (f"[TEST] start receiving from uart")
counter =0
data_out =''
while True:
if counter %8 == 0:
if counter != 0:
data_out = data_out+chr(int(char,2))
cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_msg}'")
if data_out == expected_msg:
cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{data_out}'")
break
await start_of_tx(caravelEnv)
char = ''
# if temp != caravelEnv.monitor_gpio((6,6))
char = caravelEnv.monitor_gpio((6,6)).binstr + char
cocotb.log.debug (f"[TEST] bit[{counter}] = {caravelEnv.monitor_gpio((6,6))} data out = {char} ")
await Timer(bit_time_ns, units='ns')
counter +=1
async def start_of_tx(caravelEnv):
while (True): # wait for the start of the transimission it 1 then 0
if (caravelEnv.monitor_gpio((6,6)).integer == 0):
break
await Timer(bit_time_ns, units='ns')
await Timer(bit_time_ns, units='ns')
@cocotb.test()
@repot_test
async def uart_rx(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=104029)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start uart test")
caravelEnv.drive_gpio_in((0,0),0) # IO[0] affects the uart selecting btw system and debug
caravelEnv.drive_gpio_in((5,5),1)
# calculate bit time
clk = clock.period/1000
global bit_time_ns
bit_time_ns = round(10**5 * clk / (96))
# send first char
await wait_reg1(cpu,caravelEnv,0XAA)
await uart_send_char(caravelEnv,"B")
await uart_check_char_recieved(caravelEnv,cpu)
# send second char
await wait_reg1(cpu,caravelEnv,0XBB)
await uart_send_char(caravelEnv,"M")
await uart_check_char_recieved(caravelEnv,cpu)
# send third char
await wait_reg1(cpu,caravelEnv,0XCC)
await uart_send_char(caravelEnv,"A")
await uart_check_char_recieved(caravelEnv,cpu)
async def uart_send_char(caravelEnv,char):
char_bits = [int(x) for x in '{:08b}'.format(ord(char))]
cocotb.log.info (f"[TEST] start sending on uart {char}")
#send start bit
caravelEnv.drive_gpio_in((5,5),0)
await Timer(bit_time_ns, units='ns')
#send bits
for i in reversed(range(8)):
caravelEnv.drive_gpio_in((5,5),char_bits[i])
await Timer(bit_time_ns, units='ns')
# stop of frame
caravelEnv.drive_gpio_in((5,5),1)
await Timer(bit_time_ns, units='ns')
await Timer(bit_time_ns, units='ns')
# insert 4 bit delay just for debugging
await Timer(bit_time_ns, units='ns')
await Timer(bit_time_ns, units='ns')
await Timer(bit_time_ns, units='ns')
await Timer(bit_time_ns, units='ns')
async def uart_check_char_recieved(caravelEnv,cpu):
# check cpu recieved the correct character
while True:
reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
reg1 = cpu.read_debug_reg1()
cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}")
if reg1 == 0x1B:
cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}")
return
if reg1 == 0x1E:
cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character {chr(int(reg_uart_data,2))}")
return
await ClockCycles(caravelEnv.clk,1)
@cocotb.test()
@repot_test
async def uart_loopback(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=216756)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
cocotb.log.info(f"[TEST] Start uart test")
await cocotb.start( connect_5_6(dut,caravelEnv)) # short gpio 6 and 5
caravelEnv.drive_gpio_in((0,0),0) # IO[0] affects the uart selecting btw system and debug
# setup watcher loopback results
await cocotb.start(uart_check_char_recieved_loopback(caravelEnv,cpu))
await ClockCycles(caravelEnv.clk,197000)
async def connect_5_6(dut,caravelEnv):
while True:
caravelEnv.drive_gpio_in(5,dut.bin6_monitor.value)
await Edge(dut.bin6_monitor)
async def uart_check_char_recieved_loopback(caravelEnv,cpu):
# check cpu recieved the correct character
while True:
reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr
reg1 = cpu.read_debug_reg1()
cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}")
if reg1 == 0x1B:
cocotb.log.info(f"[TEST] Pass cpu has sent and recieved the correct character {chr(int(reg_uart_data,2))}")
await wait_reg1(cpu,caravelEnv,0)
if reg1 == 0x1E:
cocotb.log.error(f"[TEST] Failed cpu has sent and recieved the wrong character {chr(int(reg_uart_data,2))}")
await wait_reg1(cpu,caravelEnv,0)
await ClockCycles(caravelEnv.clk,1)

64
verilog/dv/cocotb/tests/uart/uart_loopback.c Normal file
View File

@ -0,0 +1,64 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
#include <stub.c>
#include <uart.h>
// --------------------------------------------------------
void wait_for_char(char *c){
while (uart_rxempty_read() == 1);
if (reg_uart_data == *c){
reg_debug_1 = 0x1B; // recieved the correct character
}else{
reg_debug_1 = 0x1E; // timeout didn't recieve the character
}
reg_debug_1 =0;
uart_ev_pending_write(UART_EV_RX);
}
void main(){
int j;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
// Now, apply the configuration
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_uart_enable = 1;
print("M");
wait_for_char("M");
print("B");
wait_for_char("B");
print("A");
wait_for_char("A");
print("5");
wait_for_char("5");
print("o");
wait_for_char("o");
}

58
verilog/dv/cocotb/tests/uart/uart_rx.c Normal file
View File

@ -0,0 +1,58 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
#include <stub.c>
#include <uart.h>
// --------------------------------------------------------
void wait_for_char(char *c){
while (uart_rxempty_read() == 1);
if (reg_uart_data == *c){
reg_debug_1 = 0x1B; // recieved the correct character
}else{
reg_debug_1 = 0x1E; // timeout didn't recieve the character
}
uart_ev_pending_write(UART_EV_RX);
}
void main(){
int j;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
// Now, apply the configuration
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
reg_uart_enable = 1;
reg_debug_1 = 0xAA; // start sending B
wait_for_char("B");
reg_debug_1 = 0xBB; // start sending M
wait_for_char("M");
reg_debug_1 = 0xCC; // start sending A
wait_for_char("A");
}

53
verilog/dv/cocotb/tests/uart/uart_tx.c Normal file
View File

@ -0,0 +1,53 @@
/*
* SPDX-FileCopyrightText: 2020 Efabless Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
* SPDX-License-Identifier: Apache-2.0
*/
#include <defs.h>
#include <stub.c>
// --------------------------------------------------------
void main()
{
int j;
reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
reg_debug_1 = 0x0;
reg_debug_2 = 0x0;
reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
// Set clock to 64 kbaud and enable the UART. It is important to do this
// before applying the configuration, or else the Tx line initializes as
// zero, which indicates the start of a byte to the receiver.
// Now, apply the configuration
reg_mprj_xfer = 1;
while (reg_mprj_xfer == 1);
// reg_uart_clkdiv = 625;
reg_uart_enable = 1;
reg_debug_1 = 0xAA;
// This should appear at the output, received by the testbench UART.
// (Makes simulation time long.)
// print("test msg\n");
print("Monitor: Test UART (RTL) passed");
// Allow transmission to complete before signalling that the program
// has ended.
for (j = 0; j < 160; j++);
}

356
verilog/dv/cocotb/verify_cocotb.py Executable file
View File

@ -0,0 +1,356 @@
#!/usr/bin/python3
# -*- coding: utf-8 -*-
import collections
import json
import sys
import os
from pathlib import Path
import json
from fnmatch import fnmatch
from datetime import datetime
import random
from pathlib import Path
iverilog = True
vcs = False
coverage = False
def go_up(path, n):
for i in range(n):
path = os.path.dirname(path)
return path
# search pattern in file
def search_str(file_path, word):
with open(file_path, 'r') as file:
# read all content of a file
content = file.read()
# check if string present in a file
if word in content:
return "passed"
else:
return "failed"
class RunTest:
def __init__(self,test_name,sim) -> None:
self.cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb"
self.test_name = test_name
self.sim_type = sim
self.create_log_file()
self.hex_generate()
self.runTest()
# create and open full terminal log to be able to use it before run the test
def create_log_file(self):
self.cd_cocotb()
os.chdir(f"sim/{os.getenv('RUNTAG')}")
test_dir = f"{self.sim_type}-{self.test_name}"
os.makedirs(f"{test_dir}",exist_ok=True)
self.cd_cocotb()
self.sim_path = f"sim/{os.getenv('RUNTAG')}/{test_dir}/"
terminal_log=f"{self.sim_path}/fullTerminal.log"
test_log=f"{self.sim_path}/{self.test_name}.log"
self.full_terminal = open(test_log, "w")
def runTest(self):
if (iverilog):return self.runTest_iverilog()
elif(vcs): return self.runTest_vcs()
# iverilog function
def runTest_iverilog(self):
CARAVEL_ROOT = os.getenv('CARAVEL_ROOT')
CARAVEL_VERILOG_PATH = os.getenv('CARAVEL_VERILOG_PATH')
MCW_ROOT = os.getenv('MCW_ROOT')
VERILOG_PATH = os.getenv('VERILOG_PATH')
CARAVEL_PATH = os.getenv('CARAVEL_PATH')
USER_PROJECT_VERILOG = os.getenv('USER_PROJECT_VERILOG')
FIRMWARE_PATH = os.getenv('FIRMWARE_PATH')
RUNTAG = os.getenv('RUNTAG')
ERRORMAX = os.getenv('ERRORMAX')
PDK_ROOT = os.getenv('PDK_ROOT')
PDK = os.getenv('PDK')
env_vars = f"-e {CARAVEL_ROOT} -e CARAVEL_VERILOG_PATH={CARAVEL_VERILOG_PATH} -e MCW_ROOT={MCW_ROOT} -e VERILOG_PATH={VERILOG_PATH} -e CARAVEL_PATH={CARAVEL_PATH} -e USER_PROJECT_VERILOG={USER_PROJECT_VERILOG} -e FIRMWARE_PATH={FIRMWARE_PATH} -e RUNTAG={RUNTAG} -e ERRORMAX={ERRORMAX} -e PDK_ROOT={PDK_ROOT} -e PDK={PDK}"
print(f"Start running test: {self.sim_type}-{self.test_name}")
command = f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} "
os.system(f"docker run -it {env_vars} -v {os.getenv('CARAVEL_ROOT')}:{os.getenv('CARAVEL_ROOT')} -v {os.getenv('MCW_ROOT')}:{os.getenv('MCW_ROOT')} -v {os.getenv('PDK_ROOT')}:{os.getenv('PDK_ROOT')} efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {command}'")
self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
Path(f'{self.sim_path}/{self.passed}').touch()
# vcs function
def runTest_vcs(self):
print(f"Start running test: {self.sim_type}-{self.test_name}")
PDK_ROOT = os.getenv('PDK_ROOT')
PDK = os.getenv('PDK')
VERILOG_PATH = os.getenv('VERILOG_PATH')
dirs = f'+incdir+\\\"{PDK_ROOT}/{PDK}\\\" '
if self.sim_type == "RTL":
dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/rtl_caravel_vcs.list\\\" '
else:
dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/gl_caravel_vcs.list\\\" '
macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS '
if self.test_name == "la":
macros = f'{macros} +define+LA_TESTING'
if self.test_name == "gpio_all_o_user":
macros = f'{macros} +define+GPIO_TESTING'
# shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex')
# if os.path.exists(f'{self.test_full_dir}/test_data'):
# shutil.copyfile(f'{self.test_full_dir}/test_data',f'{self.sim_path}/test_data')
if (self.sim_type=="GL_SDF"):
macros = f'{macros} +define+ENABLE_SDF +define+SIM=GL_SDF +define+GL +define+SDF_POSTFIX=\\\"-{self.corner}\\\"'
os.makedirs(f"annotation_logs",exist_ok=True)
elif(self.sim_type=="GL"):
macros = f'{macros} +define+GL +define+SIM=GL'
elif (self.sim_type=="RTL"):
macros = f'{macros} +define+SIM=\\\"RTL\\\"'
else:
print(f"Fatal: incorrect simulation type {self.sim_type}")
coverage_command = ""
if coverage:
coverage_command = "-cm line+tgl+cond+fsm+branch+assert"
os.environ["TESTCASE"] = f"{self.test_name}"
os.environ["MODULE"] = f"caravel_tests"
os.environ["SIM"] = self.sim_type
os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
os.system(f"vcs {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
Path(f'{self.sim_path}/{self.passed}').touch()
os.system("rm AN.DB/ cm.log results.xml ucli.key -rf")
def find(self,name, path):
for root, dirs, files in os.walk(path):
if name in files:
return os.path.join(root, name)
print(f"Test {name} doesn't exist or don't have a C file ")
def test_path(self):
test_name = self.test_name
test_name += ".c"
tests_path = os.path.abspath(f"{self.cocotb_path}/tests")
test_file = self.find(test_name,tests_path)
test_path = os.path.dirname(test_file)
return (test_path)
def hex_generate(self):
#open docker
test_path =self.test_path()
self.cd_make()
if not os.path.exists(f"{self.cocotb_path}/hex_files"):
os.makedirs(f"{self.cocotb_path}/hex_files") # Create a new hex_files directory because it does not exist
elf_out = f"{self.cocotb_path}/hex_files/{self.test_name}.elf"
c_file = f"{test_path}/{self.test_name}.c"
hex_file = f"{self.cocotb_path}/hex_files/{self.test_name}.hex"
GCC_PATH = "/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937/bin/"
GCC_PREFIX = "riscv32-unknown-linux-gnu"
SOURCE_FILES = f"{os.getenv('FIRMWARE_PATH')}/crt0_vex.S {os.getenv('FIRMWARE_PATH')}/isr.c"
LINKER_SCRIPT = f"{os.getenv('FIRMWARE_PATH')}/sections.lds"
CPUFLAGS = f"-march=rv32i -mabi=ilp32 -D__vexriscv__ "
verilog_path = f"{os.getenv('VERILOG_PATH')}"
test_dir = f"{os.getenv('VERILOG_PATH')}/dv/tests-caravel/mem" # linker script include // TODO: to fix this in the future from the mgmt repo
print(test_dir)
elf_command = (f"{GCC_PATH}/{GCC_PREFIX}-gcc -g -I{verilog_path}/dv/firmware -I{verilog_path}/dv/generated -I{verilog_path}/dv/ "
f"-I{verilog_path}/common {CPUFLAGS} -Wl,-Bstatic,-T,{LINKER_SCRIPT},"
f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}")
hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} "
sed_command = f"sed -ie 's/@10/@00/g' {hex_file}"
hex_gen_state = os.system(f"docker run -it -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)} efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '")
self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n")
self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n")
self.full_terminal.write(os.path.expandvars(sed_command)+"\n"+"\n")
self.cd_cocotb()
self.full_terminal.close()
if hex_gen_state != 0 :
print(f"fatal: Error when generating hex")
sys.exit()
def cd_make(self):
os.chdir(f"{os.getenv('VERILOG_PATH')}/dv/make")
def cd_cocotb(self):
os.chdir(self.cocotb_path)
class RunRegression:
def __init__(self,regression,test,type_arg,testlist) -> None:
self.cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb"
self.regression_arg = regression
self.test_arg = test
self.testlist_arg = testlist
if type_arg is None:
type_arg = "RTL"
self.type_arg = type_arg
self.write_command_log()
with open('tests.json') as f:
self.tests_json = json.load(f)
self.tests_json = self.tests_json["Tests"]
self.get_tests()
self.run_regression()
def get_tests(self):
self.tests = collections.defaultdict(lambda : collections.defaultdict(dict)) #key is testname and value is list of sim types
self.unknown_tests = 0
self.passed_tests = 0
self.failed_tests = 0
# regression
if self.regression_arg is not None:
sim_types = ("RTL","GL","GL_SDF")
for test,test_elements in self.tests_json.items():
if fnmatch(test,"_*"):
continue
for sim_type in sim_types:
if self.regression_arg in test_elements[sim_type]:
self.add_new_test(test_name=test,sim_type = sim_type)
if (len(self.tests)==0):
print(f"fatal:{self.regression_arg} is not a valid regression name please input a valid regression \ncheck tests.json for more info")
sys.exit()
#test
if self.test_arg is not None:
if isinstance(self.test_arg,list):
for test in self.test_arg:
if test in self.tests_json:
if isinstance(self.type_arg,list):
for sim_type in self.type_arg:
self.add_new_test(test_name=test,sim_type = sim_type)
else:
self.add_new_test(test_name=test,sim_type = self.type_arg)
else:
if self.test_arg in self.tests_json:
if isinstance(self.type_arg,list):
for sim_type in self.type_arg:
self.add_new_test(test_name=self.test_arg,sim_type = sim_type)
else:
self.add_new_test(test_name=self.test_arg,sim_type = self.type_arg)
# testlist TODO: add logic for test list
if self.testlist_arg is not None:
print(f'fatal: code for test list isnt added yet')
sys.exit()
self.update_reg_log()
def add_new_test(self,test_name,sim_type):
self.tests[test_name][sim_type]["status"]= "pending"
self.tests[test_name][sim_type]["starttime"]= "-"
self.tests[test_name][sim_type]["endtime"]= "-"
self.tests[test_name][sim_type]["duration"] = "-"
self.tests[test_name][sim_type]["pass"]= "-"
self.unknown_tests +=1
def run_regression(self):
for test,sim_types in self.tests.items():
for sim_type,status in sim_types.items(): # TODO: add multithreading or multiprocessing here
start_time = datetime.now()
self.tests[test][sim_type]["starttime"] = datetime.now().strftime("%H:%M:%S(%a)")
self.tests[test][sim_type]["duration"] = "-"
self.tests[test][sim_type]["status"] = "running"
self.update_reg_log()
test_run = RunTest(test,sim_type)
self.tests[test][sim_type]["status"] = "done"
self.tests[test][sim_type]["endtime"] = datetime.now().strftime("%H:%M:%S(%a)")
self.tests[test][sim_type]["duration"] = ("%.10s" % (datetime.now() - start_time))
self.tests[test][sim_type]["pass"]= test_run.passed
if test_run.passed == "passed":
self.passed_tests +=1
elif test_run.passed == "failed":
self.failed_tests +=1
self.unknown_tests -=1
self.update_reg_log()
if coverage:
self.generate_cov()
#TODO: add send mail here
def generate_cov(self):
os.chdir(f"{self.cocotb_path}/sim/{os.getenv('RUNTAG')}")
os.system(f"urg -dir RTL*/*.vdb -format both -show tests -report coverageRTL/")
os.system(f"urg -dir GL*/*.vdb -format both -show tests -report coverageGL/")
os.system(f"urg -dir SDF*/*.vdb -format both -show tests -report coverageSDF/")
os.chdir(self.cocotb_path)
def update_reg_log(self):
file_name=f"sim/{os.getenv('RUNTAG')}/runs.log"
f = open(file_name, "w")
f.write(f"{'Test':<25} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n")
for test,sim_types in self.tests.items():
for sim_type,status in sim_types.items():
new_test_name= f"{sim_type}-{test}"
f.write(f"{new_test_name:<25} {status['status']:<10} {status['starttime']:<15} {status['endtime']:<15} {status['duration']:<13} {status['pass']:<5}\n")
f.write(f"\n\nTotal: ({self.passed_tests})passed ({self.failed_tests})failed ({self.unknown_tests})unknown ")
f.close()
def write_command_log(self):
file_name=f"sim/{os.getenv('RUNTAG')}/command.log"
f = open(file_name, "w")
f.write(f"{' '.join(sys.argv)}")
f.close()
class main():
def __init__(self,args) -> None:
self.regression = args.regression
self.test = args.test
self.testlist = args.testlist
self.type = args.sim
self.tag = args.tag
self.maxerr = args.maxerr
self.check_valid_args()
self.set_tag()
self.def_env_vars()
RunRegression(self.regression,self.test,self.type,self.testlist)
def check_valid_args(self):
if all(v is None for v in [self.regression, self.test, self.testlist]):
print ("Fatal: Should provide at least one of the following options regression, test or testlist for more info use --help")
sys.exit()
if not set(self.type).issubset(["RTL","GL","GL_SDF"]):
print (f"Fatal: {self.type} isnt a correct type for -sim it should be one or combination of the following RTL, GL or GL_SDF")
sys.exit()
def set_tag(self):
self.TAG = None # tag will be set in the main phase and other functions will use it
if self.tag is not None:
self.TAG = self.tag
elif self.regression is not None:
self.TAG = f'{self.regression}_{datetime.now().strftime("%H_%M_%S_%d_%m")}'
else:
self.TAG = f'run{random.randint(0,1000)}_{datetime.now().strftime("%H_%M_%S_%d_%m")}'
Path(f"sim/{self.TAG}").mkdir(parents=True, exist_ok=True)
print(f"Run tag: {self.TAG}")
def def_env_vars(self):
if os.getenv('CARAVEL_ROOT') is None or os.getenv('MCW_ROOT') is None:
print(f"Fatal: CARAVEL_ROOT or MCW_ROOT are not defined")
sys.exit()
cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb"
os.environ["CARAVEL_VERILOG_PATH"] = f"{os.getenv('CARAVEL_ROOT')}/verilog"
os.environ["VERILOG_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog"
os.environ["CARAVEL_PATH"] = f"{os.getenv('CARAVEL_VERILOG_PATH')}"
os.environ["FIRMWARE_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog/dv/firmware"
os.environ["RUNTAG"] = f"{self.TAG}"
os.environ["ERRORMAX"] = f"{self.maxerr}"
import argparse
parser = argparse.ArgumentParser(description='Run cocotb tests')
parser.add_argument('-regression','-r', help='name of regression can found in tests.json')
parser.add_argument('-test','-t', nargs='+' ,help='name of test if no --sim provided RTL will be run <takes list as input>')
parser.add_argument('-sim', nargs='+' ,help='Simulation type to be run RTL,GL&GL_SDF provided only when run -test <takes list as input>')
parser.add_argument('-testlist','-tl', help='path of testlist to be run ')
parser.add_argument('-tag', help='provide tag of the run default would be regression name and if no regression is provided would be run_<random float>_<timestamp>_')
parser.add_argument('-maxerr', help='max number of errors for every test before simulation breaks default = 3')
parser.add_argument('-vcs','-v',action='store_true', help='use vcs as compiler if not used iverilog would be used')
parser.add_argument('-cov','-c',action='store_true', help='enable code coverage')
args = parser.parse_args()
if (args.vcs) :
iverilog = False
vcs = True
if args.cov:
coverage = True
if args.sim == None:
args.sim= ["RTL"]
print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}")
main(args)

157
verilog/dv/cocotb/wb_models/housekeepingWB/HKSPImonitor.py Normal file
View File

@ -0,0 +1,157 @@
from fnmatch import fnmatch
import cocotb
from cocotb.triggers import Timer, FallingEdge,RisingEdge, ReadOnly
from cocotb_bus.monitors import Monitor
from cocotb.log import SimLogFormatter, SimTimeContextFilter
from cocotb.binary import BinaryValue
from cocotb.result import TestFailure
from math import ceil
import copy
import logging
from wb_models.housekeepingWB.HKmonitor import HKmonitor
from interfaces.common import Macros
class HKSPImonitor(Monitor):
"""Observes single input """
def __init__(self, name, block_path,interfaces, clock,reset,is_logger = False, input=True, callback=None, event=None):
self.name = name
self.interfaces = interfaces
self.clock = clock
self.reset = reset
self.block_path = block_path
self.is_logger = is_logger
self.input = input
self.setup_logger()
Monitor.__init__(self, callback, event)
async def _monitor_recv(self):
old_trans_hold = None
old_trans_no_valid = None
while True:
if Macros['GL']:
await RisingEdge(self.block_path.clknet_0_mgmt_gpio_in) # the main reason for doing all this can't use mgmt_gpio_in[4] as signal
else :
await RisingEdge(self.block_path.hkspi.SCK) # the main reason for doing all this can't use mgmt_gpio_in[4] as signal
cocotb.log.debug(f'reset {self.reset.value.binstr }')
if self.reset.value.binstr == '0':
continue
mgmt_gpio_in = self.block_path.mgmt_gpio_in.value
gpio_size = mgmt_gpio_in.n_bits-1
CSB = mgmt_gpio_in[gpio_size-3]
if CSB.binstr == '1':
continue
SCK = mgmt_gpio_in[gpio_size-4]
SDI = mgmt_gpio_in[gpio_size-2]
SDO = self.block_path.mgmt_gpio_out.value[gpio_size-1]
if not self.input:
if self.block_path.hkspi.SCK.value.binstr != '0':
continue
# update signal
self.interfaces['CSB']['val'] = CSB
self.interfaces['SCK']['val'] = SCK
if self.input:
self.interfaces['SDI']['val'] = SDI
else :
self.interfaces['SDO']['val'] = SDO
# logger
self.logger.debug(f' ')
self.handler.terminator = ""
self.handler.setFormatter(SimLogFormatter())
self.logger.debug(f'')
self.handler.setFormatter(logging.Formatter('%(message)s'))
for key2,signal in self.interfaces.items():
if fnmatch(key2,"_*"):
continue
if signal['val'].is_resolvable:
length = self.lengths[key2] - (len(hex(signal['val'].integer)))
self.logger.debug(f" {hex(signal['val'].integer)}{' '*length}|")
# signal['val'] = self.block_path._id(signal['signal'],False).value.integer
else:
length = self.lengths[key2] - (len('x'))
self.logger.debug(f" x{' '*length}|")
self.handler.terminator = "\n"
self._recv(self.interfaces)
"""method for setting up logger for WB model"""
def setup_logger(self):
self.logger = logging.getLogger(f'HouseKeeping{self.name}')
self.logger.setLevel(logging.DEBUG)
if not self.is_logger:
self.logger.setLevel(logging.INFO)
self.handler = logging.StreamHandler()
# return
else :
self.handler = logging.FileHandler(f"{self.name}.log",mode='w')
self.handler.addFilter(SimTimeContextFilter())
self.logger.addHandler(self.handler)
# get the sizes of signals
#for key,interface in self.interfaces.items():
for key,signal in self.interfaces.items():
if fnmatch(key,"_*"):
continue
signal['val'] = BinaryValue(value=0,n_bits=1)
size = signal['val'].n_bits
signal['val'] = BinaryValue(value = int(size) * '1',n_bits=size)
# set the logger file header
# set first line
self.handler.terminator = ""
self.logger.debug(f' timestamp level ')
length =0
for key2,signal in self.interfaces.items():
if fnmatch(key2,"_*"):
continue
length += max(ceil(signal['val'].n_bits/4)+2 , len(key2)) +3
length -= len(key)+1
self.logger.debug(f'| signals{" "*int(length)}')
self.handler.terminator = "\n"
self.logger.debug(f' ')
# set second line
self.handler.terminator = ""
self.logger.debug(f'{" "*20}|')
length =0
self.lengths = dict()
for key2,signal in self.interfaces.items():
if fnmatch(key2,"_*"):
continue
self.lengths[key2] = max((len(hex(signal['val'].integer))),len(key2)) +1
length = self.lengths[key2] - len(key2)
self.logger.debug(f'{key2}{" "*length} ')
self.handler.terminator = "\n"
class CSBmonitor(Monitor):
"""Observes single input """
def __init__(self, name, block_path,interfaces, clock,reset,is_logger = False, input=True, callback=None, event=None):
self.name = name
self.interfaces = interfaces
self.clock = clock
self.reset = reset
self.block_path = block_path
self.is_logger = is_logger
self.input = input
Monitor.__init__(self, callback, event)
async def _monitor_recv(self):
while True:
if Macros['GL']:
await RisingEdge(self.block_path.net67)
else:
await RisingEdge(self.block_path.hkspi.CSB)
self._recv(True)

371
verilog/dv/cocotb/wb_models/housekeepingWB/HK_models.py Normal file
View File

@ -0,0 +1,371 @@
from audioop import add
from ctypes import BigEndianStructure
from operator import truediv
from cocotb import top
import cocotb
from cocotb.binary import BinaryValue
from cocotb.triggers import Timer, RisingEdge, ReadOnly
import fnmatch
import copy
import logging
from cocotb.result import TestFailure
from cocotb_coverage.coverage import *
class HK_models():
def __init__(self,reg_model,expeceted_output,hk_hdl):
self.reg_model = reg_model
self.expeceted_output = expeceted_output
self.hk_hdl = hk_hdl
self.old_hold_val = 1
self.gpio_out_pre = BinaryValue(value=0,n_bits=38,bigEndian=False)
self.mgmt_gpio_oeb = BinaryValue(value=0,n_bits=38,bigEndian=False)
self.exp_out_wb = [] # expected output for wishbone
self.exp_out_uart_rx = [self.expeceted_output['UART']] # expected output for uart
self.exp_out_debug = [self.expeceted_output['debug']] # expected output for
self.exp_out_spi = [self.expeceted_output['SPI']] # expected output for
self.reset_spi_vals(True)
self.input_dis =3
self.regs_full_list()
self.intial_cov()
"""model for the wishbone interface with housekeeping"""
def wishbone_model(self,trans):
clock_signal = trans["_clk"]["signal"]
if trans["stb"]["val"] == 1 : # valid data
address = trans["adr"]["val"]
data = trans["data"]["val"]
# if ack isn't realsead don't care about the new input it must be the same as the old and the monitor checks that
if (self.old_hold_val == 0):
self.old_hold_val = trans["_hold"]["val"]
return
self.old_hold_val = trans["_hold"]["val"]
if trans["write_en"]["val"] ==1 : # write cycle
cocotb.log.debug(f'[HK_models][_valid_address] write enable for address: {hex(address)} and data: {hex(data)} ')
select = trans["sel"]["val"]
cocotb.scheduler.add(self._write_reg_wb(address,data,select,clock_signal))
else: #read cycle
self.write_exp_out_wb(self._read_reg_wb(address))
self.wishbone_last_trans = trans
"""model for the system interface with housekeeping"""
def system_model(self,trans):
self.reg_model['sys']['0x00'][0][6] = trans["vdd2_good"]["val"]
self.reg_model['sys']['0x00'][1][6] = trans["vdd1_good"]["val"]
self.reg_model['sys']['0x00'][2][6] = trans["vcc2_good"]["val"]
self.reg_model['sys']['0x00'][3][6] = trans["vcc1_good"]["val"]
"""model for the UART interface with housekeeping"""
def UART_model(self,trans):
# when transmiting TX the gpio data out should change to the tx value
if trans["enable"]["val"]:
self.gpio_out_pre[6]= trans["TX"]["val"].value
else:
gpio_data = self._read_reg_keys(["GPIO","0x0c"]) # mgmt_gpio_data[7:0]
self.gpio_out_pre[6]= int(gpio_data[len(gpio_data)-1 -6]) # mgmt_gpio_data[6]
# predecting the rx output value when the value UART is enble is the value drom pin [5]
gpio_in_size = trans["gpio_in"]["val"].n_bits -1
output = self.expeceted_output['UART']
output["RX"]["val"] = 0
if trans["enable"]["val"]:
output["RX"]["val"] = trans["gpio_in"]["val"][gpio_in_size-5] #gpio_in[5]
self.exp_out_uart_rx.append(output)
"""model for the debug interface with housekeeping"""
def debug_model(self,trans):
# when debug is enable gpio out [0] should follow debug_out
if trans["enable"]["val"]:
self.gpio_out_pre[0] = trans["data"]["val"].value
self.mgmt_gpio_oeb[0] = trans["data"]["val"].value
else:
gpio_data = self._read_reg_keys(["GPIO","0x0c"]) # mgmt_gpio_data[7:0]
self.gpio_out_pre[0]= int(gpio_data[len(gpio_data)-1 -0]) # mgmt_gpio_data[6]
gpio_data_en = self._read_reg_keys(["GPIO","0x24"]) # gpio_configure[0][7:0]
self.mgmt_gpio_oeb[0]= 1- int(gpio_data[len(gpio_data_en)-1 -self.input_dis]) # gpio_configure[0][3]
# predecting the debug in signal when debug mode is enbled taking the value from pin [0]
gpio_in_size = trans["gpio_in"]["val"].n_bits -1
output = self.expeceted_output['debug']
output["data"]["val"] = 0
if trans["enable"]["val"]:
output["data"]["val"] = trans["gpio_in"]["val"][gpio_in_size-0] # mgmt_gpio_in[0]
self.exp_out_debug.append(output)
"""model for the SPI interface with housekeeping"""
def spi_model(self,trans):
output = self.expeceted_output['SPI']
output["SDO"]["val"] = 0
cocotb.log.debug(f'[HK_models][spi_model] spi mode {self.spi_mode[0]} bit number {self.spi_mode[1]} command = {self.command_spi} address = {self.address_spi} write = {self.write_spi} stream = {self.spi_mode[2]}')
if self.spi_mode[0] == "command":
self._setCommand(trans['SDI']['val'].binstr)
self.exp_out_spi.append(output)
elif self.spi_mode[0] == "address":
self._setAddress(trans['SDI']['val'].binstr)
self.exp_out_spi.append(output)
elif self.spi_mode[0] == "write":
self._setWriteData(trans['SDI']['val'].binstr)
self.exp_out_spi.append(output)
elif self.spi_mode[0] == "read":
output["SDO"]["val"] = self._getReadData()
self.exp_out_spi.append(output)
elif self.spi_mode[0] == "read/write":
output["SDO"]["val"] = self._getReadData()
self.exp_out_spi.append(output)
elif self.spi_mode[0] == "noOP":
self._setWriteData(trans['SDI']['val'].binstr)
else:
raise TestFailure("[HK_models][spi_model] invalid command type")
"""reset the spi vals when CSB is going from low to high"""
def reset_spi_vals(self,trans):
cocotb.log.info(f"[HK_models][reset_spi_vals] CSB is disabled")
self.spi_mode = ["command",0,0] # [mode type, bit number, stream number]
self.command_spi = ['0']*8
self.address_spi = ['0']*8
self.write_spi = ['0']*8
self.read_spi = ['0']*8
def _setCommand(self,bit):
if bit not in ['0','1']:
cocotb.log.warning(f"[HK_models][_setCommand] incorrect bit size bit = {bit}")
self.command_spi[self.spi_mode[1]] = bit
self.spi_mode[1] += 1
self.spi_mode[2] = 0 # stream number
if self.spi_mode[1] >= 8:
self.spi_mode[0] = "address"
self.spi_mode[1] = 0
def _setAddress(self,bit):
if bit not in ['0','1']:
cocotb.log.warning(f"[HK_models][_setAddress] incorrect bit size bit = {bit}")
self.address_spi[self.spi_mode[1]] = bit
self.spi_mode[1] += 1
self.spi_mode[2] = 0 # stream number
if self.spi_mode[1] >= 8:
self.spi_mode[1] = 0
if self.command_spi[0:2] == ['0','0']:
self.spi_mode[0] = "noOP"
if self.command_spi[0:2] == ['1','0']:
self.spi_mode[0] = "write"
if self.command_spi[0:2] == ['0','1']:
self.spi_mode[0] = "read"
if self.command_spi[0:2] == ['1','1']:
self.spi_mode[0] = "read/write"
def _setWriteData(self,bit):
if bit not in ['0','1']:
cocotb.log.warning(f"[HK_models][_setWriteData] incorrect bit size bit = {bit}")
# return if write is write n-bytes command and number of bytes exceeds the required
if self.command_spi[2:5] != ['0','0','0']:
self.spi_mode_cov('write-n')
byte_num = int(''.join(self.command_spi[2:5]),2)
if byte_num <= self.spi_mode[2]: #number of written byte <= stream number
self.spi_mode[0] = "noOP"
return
else: self.spi_mode_cov('write')
self.write_spi[self.spi_mode[1]] = bit
self.spi_mode[1] += 1
if self.spi_mode[1] >= 8:
self.spi_mode[1] = 0
address = int(''.join(self.address_spi),2) + self.spi_mode[2]
data = ''.join(self.write_spi)
data = BinaryValue(value = data, n_bits =8)
is_valid, keys=self._valid_address_spi(address)
if is_valid:
self.reg_cov(keys[0],keys[1],is_read=False)
cocotb.log.debug(f'[HK_models][_valid_address] writing {data} to memory:{keys[0]} field: {keys[1]} through housekeeping SPI address = {address}')
self._write_fields(keys,data)
if self.command_spi[2:5] != ['0','0','0']:self.spi_mode_cov('write-n')
else: self.spi_mode_cov('write')
self.spi_mode[2] += 1 # stream number
def _getReadData(self):
# return if write is write n-bytes command and number of bytes exceeds the required
if self.command_spi[2:5] != ['0','0','0']:
byte_num = int(''.join(self.command_spi[2:5]),2)
if byte_num <= self.spi_mode[2]: #number of written byte <= stream number
self.spi_mode[0] = "noOP"
return
bit_num = self.spi_mode[1]
address = int(''.join(self.address_spi),2) + self.spi_mode[2]
is_valid, keys=self._valid_address_spi(address)
data = ''
if is_valid:
self.reg_cov(keys[0],keys[1])
cocotb.log.info(f'[HK_models][_getReadData] reading from memory:{keys[0]} field: {keys[1]} through SPI')
for field in self.reg_model[keys[0]][keys[1]]:
data = str(bin(field[6])[2:]).zfill(field[3]) + data
data = data.zfill(8)
cocotb.log.info(f'[HK_models][_getReadData] reading from memory:{keys[0]} field: {keys[1]} through SPI data {data} bit[{7-bit_num}] = {data[bit_num]}')
self.spi_mode[1] += 1
if self.spi_mode[1] >= 8:
self.spi_mode[1] = 0
self.spi_mode[2] += 1 # stream number
if self.command_spi[2:5] != ['0','0','0']:self.spi_mode_cov('read-n')
else: self.spi_mode_cov('read')
if data == '':
return 0
return int(data[bit_num],2)
def write_exp_out_wb(self,data):
output = self.expeceted_output['wishbone']
output['ack']['val'] = 1
output['_valid_cycle']['val'] = 1
output['data']['val'] = BinaryValue(value = data,n_bits = 32,bigEndian=False)
self.exp_out_wb.append(output)
"""write register through wishbone """
async def _write_reg_wb(self,address,data,select,clk):
old_data = self._read_reg_wb(address)
self.write_exp_out_wb(old_data)
if address == 0x2600000c: # mgmt_gpio_data is a special case as it got written completely at the end of the serial writing
for i in range(6):
await RisingEdge(self.hk_hdl._id(clk,False))
for i in range(3):
await RisingEdge(self.hk_hdl._id(clk,False))
for i,sel in enumerate(select.binstr):
temp_addr = BinaryValue(value=(address.value +i))
if sel is '1':
is_valid, keys=self._valid_address(temp_addr)
if is_valid:
self.reg_cov(keys[0],keys[1],is_SPI=False,is_read=False)
cocotb.log.debug(f'[HK_models][_valid_address] writing {data[(8*((4-i-1))):8*(4-i)-1]} to memory:{keys[0]} field: {keys[1]}')
temp_data = data[(8*((4-i-1))):8*(4-i)-1]
self._write_fields(keys,temp_data)
cocotb.log.debug(f" [HK_models][_valid_address] address {hex(address)} used for access housekeeping memory success")
if address != 0x2600000c:
for i in range(2):
await RisingEdge(self.hk_hdl._id(clk,False))
def _write_fields(self,keys,data):
for field in self.reg_model[keys[0]][keys[1]]:
if field[4] == "RW":
shift = field[2]
size = field[3]
cocotb.log.debug(f'[HK_models][_write_fields] before update field : {field[1]} data = {bin(field[6])} with data {data[shift:shift+size-1]} ')
field[6] = data[8-shift-size:8-shift-1]
cocotb.log.debug(f'[HK_models][_write_fields] after update field : {field[1]} data = {bin(field[6])} with data {data[shift:shift+size-1]} ')
"""read register value using keys return size binary value"""
def _read_reg_keys(self,keys:list):
size =0
data = ""
for field in self.reg_model[keys[0]][keys[1]]:
size += field[3]
data += bin(field[6])[2:].zfill(size)
return data
"""read register through wishbone """
def _read_reg_wb(self,address):
total_size = 32
data_string ="0"
data_out = list(bin(0)[2:].zfill(total_size))
for i in range(4):
temp_addr = BinaryValue(value=(address.value +i))
is_valid, keys=self._valid_address(temp_addr)
if is_valid:
self.reg_cov(keys[0],keys[1],is_SPI=False)
for field in self.reg_model[keys[0]][keys[1]]:
shift = field[2]
size = field[3]
first_index = ((8 *(4-i))) - shift-size
second_index = ((8 *(4-i))) - shift
data = bin(field[6])[2:].zfill(size)
cocotb.log.debug(f"[HK_models][_read_reg] memory:{keys[0]} shift:{keys[1]} field:{field[0]} data:{data} ")
for k,j in enumerate(range(first_index, second_index, 1)):
data_out[j] = data[k]
data_string = "".join(data_out)
cocotb.log.debug(f"[HK_models][_read_reg] register {hex(address)} has value {hex(int(data_string,2))} ")
return int(data_string,2)
"""return false if the address isn't exist inside housekeeping if the address exist return true and the key of address in JSON file"""
def _valid_address(self,address):
size = max(len(address),32)
address = address.binstr.zfill(size)
for key,memory in self.reg_model.items():
if fnmatch.fnmatch(key, "_*") :
continue
# remove the first 2 element 0b and
base_addr= bin(memory["base_addr"][1])[2:].zfill(size)
cocotb.log.debug(f'[HK_models][_valid_address] base address[:13]={hex(int(base_addr[size-32:size-13],2))} target address[:13]={hex(int(address[size-32:size-13],2))} shift={"{0:#0{1}x}".format(int(address[size-12:],2),4)}')
if base_addr[size-32:size-13] == address[size-32:size-13]:
if "{0:#0{1}x}".format(int(address[size-12:],2),4) in memory:
cocotb.log.debug(f'[HK_models][_valid_address] base address={hex(int(base_addr,2))} key {key}')
return True, [key,"{0:#0{1}x}".format(int(address[size-12:],2),4)]
cocotb.log.warning(f"[HK_models][_valid_address] address {hex(int(address,2))} used for access housekeeping memory isn't valid")
return False, None
"""return false if the address isn't exist inside housekeeping if the address exist return true and the key of address in JSON file"""
def _valid_address_spi(self,address):
for key,memory in self.reg_model.items():
if fnmatch.fnmatch(key, "_*") :
continue
for key2,reg in memory.items():
if key2 == "base_addr" :
continue
for field in reg:
if field[7] == address:
return True,[key,key2]
cocotb.log.warning(f"[HK_models][_valid_address_spi] address {hex(address)} for SPI housekeeping isn't valid")
return False, None
######################## coverage ############################
def regs_full_list(self):
bins = list()
labels = list()
for key,mem in self.reg_model.items():
if fnmatch.fnmatch(key, "_*"):
continue
for key2,fields in mem.items():
if key2=='base_addr':
continue
bins.append((key,key2))
labels.append((self.reg_model[key][key2][0][0]))
self.reg_bins = bins
self.reg_labels = labels
def intial_cov(self):
for i in [True,False]:
for j in [True,False]:
self.reg_cov(0,0,i,j)
self.spi_mode_cov(0)
def reg_cov(self,key1,key2,is_SPI=True,is_read=True):
s=''
if is_SPI:
s = "spi."
else:
s="wishbone."
if is_read:
s +="read"
else:
s+= "write"
@CoverPoint(f"top.caravel.housekeeping.regs.{s}",
xf = lambda key1,key2:(key1,key2),
bins = self.reg_bins,
bins_labels=self.reg_labels)
def cov(key1,key2):
pass
cov(key1,key2)
return (key1,key2)
def spi_mode_cov(self,mode):
@CoverPoint(f"top.caravel.housekeeping.spi.modes",
bins = ['noOP','write','read','read/write','write-n','read-n','read/write-n','Pass-m','pass-u'],
bins_labels=['No operation','Write in streaming mode','Read in streaming mode','Simultaneous Read/Write in streaming mode','Write in n-byte mode','Read in n-byte mode','Simultaneous Read/Write in n-byte mode','Pass-through (management) Read/Write streaming mode','Pass-through (user) Read/Write in streaming mode' ])
def cov(mode):
pass
cov(mode)
return mode

129
verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json Normal file
View File

@ -0,0 +1,129 @@
{
"_comment": "the list contain the fields in register with shift spcified [field name,name iniside housekeeping, shift, size,mode,reset,value(intial is reset value), SPI address map] the shift is from the base address like SPI, system and gpio base address",
"_comment2": "Base address is the first element and called first address",
"SPI":{ "base_addr": ["SPI_BASE_ADR",638582784],
"0x00": [["SPI status",null,0,8,"undefined",0,0,0]],
"0x06": [["Manufacturer ID",["mfgr_id",11,8],0,4,"RO",4,4,1]],
"0x05": [["Manufacturer ID",["mfgr_id",7,0],0,8,"RO",86,86,2]],
"0x04": [["Manufacturer ID",["prod_id",7,0],0,8,"RO",17,17,3]],
"0x0b": [["User project ID",["mask_rev",31,24],0,8,"RO",0,0,4]],
"0x0a": [["User project ID",["mask_rev",23,16],0,8,"RO",0,0,5]],
"0x09": [["User project ID",["mask_rev",15,8],0,8,"RO",0,0,6]],
"0x08": [["User project ID",["mask_rev",7,0],0,8,"RO",0,0,7]],
"0x0c": [["PLL enables","pll_ena",0,1,"RW",0,0,8],["PLL DCO enables","pll_dco_ena",1,1,"RW",1,1,8]],
"0x10": [["PLL bypass","pll_bypass",0,1,"RW",1,1,9]],
"0x14": [["CPU IRQ","irq_spi",0,1,"RW",0,0,10]],
"0x18": [["CPU reset","reset_reg",0,1,"RW",0,0,11]],
"0x28": [["CPU trap","trap",0,1,"NA",0,0,12]],
"0x1c": [["DCO trim",["pll_trim",7,0],0,8,"RW",255,255,13]],
"0x1d": [["DCO trim",["pll_trim",15,8],0,8,"RW",239,239,14]],
"0x1e": [["DCO trim",["pll_trim",23,16],0,8,"RW",255,255,15]],
"0x1f": [["DCO trim",["pll_trim",25,24],0,2,"RW",3,3,16]],
"0x20": [["PLL output divider","pll_sel",0,3,"RW",2,2,17],["PLL output divider 2","pll90_sel",3,3,"RW",2,2,17]],
"0x24": [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]],
"0x34": [["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",1,1,"RW",0,0,20]],
"0x30": [["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]]
},
"GPIO":{ "base_addr": ["GPIO_BASE_ADR",637534208],
"0x00": [["xfer","serial_xfer",0,1,"RW",0,0,19],["bit bang enable","serial_bb_enable",1,1,"RW",0,0,19],
["bit bang reset","serial_bb_resetn",2,1,"RW",0,0,19],["bit bang load","serial_bb_load",3,1,"RW",0,0,19],
["bit bang clock","serial_bb_clock",4,1,"RW",0,0,19],["bit bang data1","serial_bb_data_1",5,1,"RW",0,0,19],
["bit bang data1","serial_bb_data_2",6,1,"RW",0,0,19]],
"0x04": [["GPIO power control (reg_mprj_pwr)","pwr_ctrl_out",0,4,"RW",0,0,110]],
"0x0c": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",7,0],0,8,"RW",0,0,109]],
"0x0d": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",15,8],0,8,"RW",0,0,108]],
"0x0e": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",23,16],0,8,"RW",0,0,107]],
"0x0f": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",31,24],0,8,"RW",0,0,106]],
"0x10": [["GPIO data high(reg_mprj_datah)",["mgmt_gpio_data",37,32],0,5,"RW",0,0,105]],
"0x24": [["mprj_io[00](reg_mprj_io_0)",["gpio_configure[0]",7,0],0,8,"RW",3,3,30]],
"0x25": [["mprj_io[00](reg_mprj_io_0)",["gpio_configure[0]",12,8],0,5,"RW",24,24,29]],
"0x28": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",7,0],0,8,"RW",3,3,32]],
"0x29": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",12,8],0,5,"RW",24,24,31]],
"0x2c": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",7,0],0,8,"RW",3,3,34]],
"0x2d": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",12,8],0,5,"RW",4,4,33]],
"0x30": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",7,0],0,8,"RW",3,3,36]],
"0x31": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",12,8],0,5,"RW",4,4,35]],
"0x34": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",7,0],0,8,"RW",3,3,38]],
"0x35": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",12,8],0,5,"RW",4,4,37]],
"0x38": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",7,0],0,8,"RW",3,3,40]],
"0x39": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",12,8],0,5,"RW",4,4,39]],
"0x3c": [["mprj_io[06](reg_mprj_io_6)",["gpio_configure[6]",7,0],0,8,"RW",3,3,42]],
"0x3d": [["mprj_io[06](reg_mprj_io_6)",["gpio_configure[6]",12,8],0,5,"RW",4,4,41]],
"0x40": [["mprj_io[07](reg_mprj_io_7)",["gpio_configure[7]",7,0],0,8,"RW",3,3,44]],
"0x41": [["mprj_io[07](reg_mprj_io_7)",["gpio_configure[7]",12,8],0,5,"RW",4,4,43]],
"0x44": [["mprj_io[08](reg_mprj_io_8)",["gpio_configure[8]",7,0],0,8,"RW",3,3,46]],
"0x45": [["mprj_io[08](reg_mprj_io_8)",["gpio_configure[8]",12,8],0,5,"RW",4,4,45]],
"0x48": [["mprj_io[09](reg_mprj_io_9)",["gpio_configure[9]",7,0],0,8,"RW",3,3,48]],
"0x49": [["mprj_io[09](reg_mprj_io_9)",["gpio_configure[9]",12,8],0,5,"RW",4,4,47]],
"0x4c": [["mprj_io[10](reg_mprj_io_10)",["gpio_configure[10]",7,0],0,8,"RW",3,3,50]],
"0x4d": [["mprj_io[10](reg_mprj_io_10)",["gpio_configure[10]",12,8],0,5,"RW",4,4,49]],
"0x50": [["mprj_io[11](reg_mprj_io_11)",["gpio_configure[11]",7,0],0,8,"RW",3,3,52]],
"0x51": [["mprj_io[11](reg_mprj_io_11)",["gpio_configure[11]",12,8],0,5,"RW",4,4,51]],
"0x54": [["mprj_io[12](reg_mprj_io_12)",["gpio_configure[12]",7,0],0,8,"RW",3,3,54]],
"0x55": [["mprj_io[12](reg_mprj_io_12)",["gpio_configure[12]",12,8],0,5,"RW",4,4,53]],
"0x58": [["mprj_io[13](reg_mprj_io_13)",["gpio_configure[13]",7,0],0,8,"RW",3,3,56]],
"0x59": [["mprj_io[13](reg_mprj_io_13)",["gpio_configure[13]",12,8],0,5,"RW",4,4,55]],
"0x5c": [["mprj_io[14](reg_mprj_io_14)",["gpio_configure[14]",7,0],0,8,"RW",3,3,58]],
"0x5d": [["mprj_io[14](reg_mprj_io_14)",["gpio_configure[14]",12,8],0,5,"RW",4,4,57]],
"0x60": [["mprj_io[15](reg_mprj_io_15)",["gpio_configure[15]",7,0],0,8,"RW",3,3,60]],
"0x61": [["mprj_io[15](reg_mprj_io_15)",["gpio_configure[15]",12,8],0,5,"RW",4,4,59]],
"0x64": [["mprj_io[16](reg_mprj_io_16)",["gpio_configure[16]",7,0],0,8,"RW",3,3,62]],
"0x65": [["mprj_io[16](reg_mprj_io_16)",["gpio_configure[16]",12,8],0,5,"RW",4,4,61]],
"0x68": [["mprj_io[17](reg_mprj_io_17)",["gpio_configure[17]",7,0],0,8,"RW",3,3,64]],
"0x69": [["mprj_io[17](reg_mprj_io_17)",["gpio_configure[17]",12,8],0,5,"RW",4,4,63]],
"0x6c": [["mprj_io[18](reg_mprj_io_18)",["gpio_configure[18]",7,0],0,8,"RW",3,3,66]],
"0x6d": [["mprj_io[18](reg_mprj_io_18)",["gpio_configure[18]",12,8],0,5,"RW",4,4,65]],
"0x70": [["mprj_io[19](reg_mprj_io_19)",["gpio_configure[19]",7,0],0,8,"RW",3,3,68]],
"0x71": [["mprj_io[19](reg_mprj_io_19)",["gpio_configure[19]",12,8],0,5,"RW",4,4,67]],
"0x74": [["mprj_io[20](reg_mprj_io_20)",["gpio_configure[20]",7,0],0,8,"RW",3,3,70]],
"0x75": [["mprj_io[20](reg_mprj_io_20)",["gpio_configure[20]",12,8],0,5,"RW",4,4,69]],
"0x78": [["mprj_io[21](reg_mprj_io_21)",["gpio_configure[21]",7,0],0,8,"RW",3,3,72]],
"0x79": [["mprj_io[21](reg_mprj_io_21)",["gpio_configure[21]",12,8],0,5,"RW",4,4,71]],
"0x7c": [["mprj_io[22](reg_mprj_io_22)",["gpio_configure[22]",7,0],0,8,"RW",3,3,74]],
"0x7d": [["mprj_io[22](reg_mprj_io_22)",["gpio_configure[22]",12,8],0,5,"RW",4,4,73]],
"0x80": [["mprj_io[23](reg_mprj_io_23)",["gpio_configure[23]",7,0],0,8,"RW",3,3,76]],
"0x81": [["mprj_io[23](reg_mprj_io_23)",["gpio_configure[23]",12,8],0,5,"RW",4,4,75]],
"0x84": [["mprj_io[24](reg_mprj_io_24)",["gpio_configure[24]",7,0],0,8,"RW",3,3,78]],
"0x85": [["mprj_io[24](reg_mprj_io_24)",["gpio_configure[24]",12,8],0,5,"RW",4,4,77]],
"0x88": [["mprj_io[25](reg_mprj_io_25)",["gpio_configure[25]",7,0],0,8,"RW",3,3,80]],
"0x89": [["mprj_io[25](reg_mprj_io_25)",["gpio_configure[25]",12,8],0,5,"RW",4,4,79]],
"0x8c": [["mprj_io[26](reg_mprj_io_26)",["gpio_configure[26]",7,0],0,8,"RW",3,3,82]],
"0x8d": [["mprj_io[26](reg_mprj_io_26)",["gpio_configure[26]",12,8],0,5,"RW",4,4,81]],
"0x90": [["mprj_io[27](reg_mprj_io_27)",["gpio_configure[27]",7,0],0,8,"RW",3,3,84]],
"0x91": [["mprj_io[27](reg_mprj_io_27)",["gpio_configure[27]",12,8],0,5,"RW",4,4,83]],
"0x94": [["mprj_io[28](reg_mprj_io_28)",["gpio_configure[28]",7,0],0,8,"RW",3,3,86]],
"0x95": [["mprj_io[28](reg_mprj_io_28)",["gpio_configure[28]",12,8],0,5,"RW",4,4,85]],
"0x98": [["mprj_io[29](reg_mprj_io_29)",["gpio_configure[29]",7,0],0,8,"RW",3,3,88]],
"0x99": [["mprj_io[29](reg_mprj_io_29)",["gpio_configure[29]",12,8],0,5,"RW",4,4,87]],
"0x9c": [["mprj_io[30](reg_mprj_io_30)",["gpio_configure[30]",7,0],0,8,"RW",3,3,90]],
"0x9d": [["mprj_io[30](reg_mprj_io_30)",["gpio_configure[30]",12,8],0,5,"RW",4,4,89]],
"0xa0": [["mprj_io[31](reg_mprj_io_31)",["gpio_configure[31]",7,0],0,8,"RW",3,3,92]],
"0xa1": [["mprj_io[31](reg_mprj_io_31)",["gpio_configure[31]",12,8],0,5,"RW",4,4,91]],
"0xa4": [["mprj_io[32](reg_mprj_io_32)",["gpio_configure[32]",7,0],0,8,"RW",3,3,94]],
"0xa5": [["mprj_io[32](reg_mprj_io_32)",["gpio_configure[32]",12,8],0,5,"RW",4,4,93]],
"0xa8": [["mprj_io[33](reg_mprj_io_33)",["gpio_configure[33]",7,0],0,8,"RW",3,3,96]],
"0xa9": [["mprj_io[33](reg_mprj_io_33)",["gpio_configure[33]",12,8],0,5,"RW",4,4,95]],
"0xac": [["mprj_io[34](reg_mprj_io_34)",["gpio_configure[34]",7,0],0,8,"RW",3,3,98]],
"0xad": [["mprj_io[34](reg_mprj_io_34)",["gpio_configure[34]",12,8],0,5,"RW",4,4,97]],
"0xb0": [["mprj_io[35](reg_mprj_io_35)",["gpio_configure[35]",7,0],0,8,"RW",3,3,100]],
"0xb1": [["mprj_io[35](reg_mprj_io_35)",["gpio_configure[35]",12,8],0,5,"RW",4,4,99]],
"0xb4": [["mprj_io[36](reg_mprj_io_36)",["gpio_configure[36]",7,0],0,8,"RW",3,3,102]],
"0xb5": [["mprj_io[36](reg_mprj_io_36)",["gpio_configure[36]",12,8],0,5,"RW",24,24,101]],
"0xb8": [["mprj_io[37](reg_mprj_io_37)",["gpio_configure[37]",7,0],0,8,"RW",3,3,104]],
"0xb9": [["mprj_io[37](reg_mprj_io_37)",["gpio_configure[37]",12,8],0,5,"RW",24,24,103]]
},
"sys":{ "base_addr": ["SYS_BASE_ADR",639631360],
"0x00": [["user2 vdd good","usr2_vdd_pwrgood",0,1,"NA",0,0,26],["user1 vdd good","usr1_vdd_pwrgood",1,1,"NA",0,0,26],
["user2 vcc good","usr2_vcc_pwrgood",2,1,"RO",0,0,26],["user1 vcc good","usr1_vcc_pwrgood",3,1,"RO",0,0,26]],
"0x04": [["Trap output redirect","trap_output_dest",0,1,"RW",0,0,27],
["clock2 output redirect","clk2_output_dest",1,1,"RW",0,0,27],
["clock1 output redirect","clk1_output_dest",2,1,"RW",0,0,27]],
"0x0c": [["IRQ1 input redirect","irq_1_inputsrc",0,1,"RW",0,0,28],["IRQ2 redirect","irq_2_inputsrc",1,1,"RW",0,0,28]],
"0x10": [["Housekeeping SPI disable","hkspi_disable",0,1,"RW",0,0,111]]
}
}

92
verilog/dv/cocotb/wb_models/housekeepingWB/HK_scoreboard.py Normal file
View File

@ -0,0 +1,92 @@
from cocotb_bus.scoreboard import Scoreboard
from cocotb.utils import hexdump, hexdiffs
from cocotb.log import SimLog
from cocotb.result import TestFailure, TestSuccess
from cocotb_bus.monitors import Monitor
import cocotb
class HKScoreboard(Scoreboard):
def __init__(self, dut, reorder_depth=0, fail_immediately=True):
Scoreboard.__init__(self, dut, reorder_depth, fail_immediately)
def compare(self, got, exp, log, strict_type=True):
# Compare the types
if strict_type and type(got) != type(exp):
self.errors += 1
log.error("Received transaction type is different than expected")
log.info("Received: %s but expected %s" %
(str(type(got)), str(type(exp))))
if self._imm:
raise TestFailure("Received transaction of wrong type. "
"Set strict_type=False to avoid this.")
return
# Or convert to a string before comparison
elif not strict_type:
got, exp = str(got), str(exp)
# Compare directly
if self.dict_compare(got, exp):
self.errors += 1
# Try our best to print out something useful
strgot, strexp = str(got), str(exp)
log.error("Received transaction differed from expected output")
if not strict_type:
log.info("Expected:\n" + hexdump(strexp))
else:
log.info("Expected:\n" + repr(exp))
if not isinstance(exp, str):
try:
for word in exp:
log.info(str(word))
except Exception:
pass
if not strict_type:
log.info("Received:\n" + hexdump(strgot))
else:
log.info("Received:\n" + repr(got))
if not isinstance(got, str):
try:
for word in got:
log.info(str(word))
except Exception:
pass
log.warning("Difference:\n%s" % hexdiffs(strexp, strgot))
if self._imm:
raise TestFailure("Received transaction differed from expected "
"transaction")
else:
# Don't want to fail the test
# if we're passed something without __len__
try:
log.debug("Received expected transaction %d bytes" %
(len(got)))
log.debug(repr(got))
except Exception:
pass
def dict_compare(self,d1, d2):
d1_keys = set(d1.keys())
d2_keys = set(d2.keys())
shared_keys = d1_keys.intersection(d2_keys)
different_keys = d1_keys.symmetric_difference(d2_keys)
if different_keys is not None:
cocotb.log.info(f"[HKScoreboard][dict_compare] return False because different_keys \n {d1} \n {d2}")
self.print_expected()
return False
modified = {o : (d1[o], d2[o]) for o in shared_keys if d1[o] != d2[o]}
if modified is not None:
cocotb.log.info(f"[HKScoreboard][dict_compare] return False because modified \n {d1} \n {d2}")
self.print_expected()
return False
cocotb.log.info(f"[HKScoreboard][dict_compare] return True \n {d1} \n {d2}")
self.print_expected()
return True
def print_expected(self):
for val in self.expected.items():
cocotb.log.info(val)

167
verilog/dv/cocotb/wb_models/housekeepingWB/HKmonitor.py Normal file
View File

@ -0,0 +1,167 @@
import cocotb
from cocotb.triggers import Timer, RisingEdge, ReadOnly
from cocotb_bus.monitors import Monitor
from cocotb.log import SimLogFormatter, SimTimeContextFilter
from cocotb.binary import BinaryValue
from cocotb.result import TestFailure
from math import ceil
import copy
import logging
from fnmatch import fnmatch
class HKmonitor(Monitor):
"""Observes single input """
def __init__(self, name, block_path,interfaces, clock,reset,is_logger = False, callback=None, event=None):
self.name = name
self.interfaces = interfaces
self.clock = clock
self.reset = reset
self.block_path = block_path
self.is_logger = is_logger
self.setup_logger()
Monitor.__init__(self, callback, event)
async def _monitor_recv(self):
old_trans_hold = None
old_trans_no_valid = None
while True:
# Capture signal at rising edge of clock
if "_clk" in self.interfaces: # for interfaces with own clock
signal = self.block_path._id(self.interfaces['_clk']['signal'],False)
await RisingEdge(signal)
else:
await RisingEdge(self.clock)
# if self.reset.value.binstr == '0':
# continue
if "_valid_cycle" in self.interfaces: # for interfaces with valid signal
signal = self.block_path._id(self.interfaces['_valid_cycle']['signal'],False).value.binstr
if signal is not '1':
continue
if "_valid_cycle_n" in self.interfaces: # for interfaces with valid signal
signal = self.block_path._id(self.interfaces['_valid_cycle']['signal'],False).value.binstr
if signal is not '0':
continue
# update signal
for key2,signal in self.interfaces.items():
# if fnmatch(key2,"_*"):
# continue
signal['val'] = self.block_path._id(signal['signal'],False).value
# if no_valid signal exist trans didn't change so monitor will not monitor anything
# no_valid means if the signal didn't change no addition action would needed
if "_no_valid" in self.interfaces:
if old_trans_no_valid is None:
old_trans_no_valid = copy.deepcopy(self.interfaces)
elif (old_trans_no_valid == self.interfaces):
return
else:
old_trans_no_valid = copy.deepcopy(self.interfaces)
# logger
self.logger.debug(f' ')
self.handler.terminator = ""
self.handler.setFormatter(SimLogFormatter())
self.logger.debug(f'')
self.handler.setFormatter(logging.Formatter('%(message)s'))
for key2,signal in self.interfaces.items():
if fnmatch(key2,"_*"):
continue
if signal['val'].is_resolvable:
length = self.lengths[key2] - (len(hex(signal['val'].integer)))
self.logger.debug(f" {hex(signal['val'].integer)}{' '*length}|")
# signal['val'] = self.block_path._id(signal['signal'],False).value.integer
else:
length = self.lengths[key2] - (len('x'))
self.logger.debug(f" x{' '*length}|")
self.handler.terminator = "\n"
# special case in HKoutputsMonitorwishbone when writing to reg_mprj_datal(because it uses _buf) the data out is x's
# and in this case scoreboard raise obejection that the value is unresolved
if self.name == "HKoutputsMonitorwishbone":
if not self.interfaces['data']['val'].is_resolvable:
self.interfaces['data']['val'] = BinaryValue(value=0,n_bits=self.interfaces['data']['val'].n_bits)
cocotb.log.debug(f'[HKmonitor][_monitor_recv] interface at monitor {self.name} self.interfaces {self.interfaces}')
self._recv(self.interfaces)
## assertion that the values can't change until hold is released
if "_hold" in self.interfaces:
if old_trans_hold is None:
skip = False
old_trans_hold = copy.deepcopy(self.interfaces)
elif self.interfaces['_hold']['val'] == BinaryValue(value=1):
skip = True
elif skip:
old_trans_hold = copy.deepcopy(self.interfaces)
skip = False
else:
if old_trans_hold != self.interfaces:
cocotb.log.error(f'[HKmonitor][_monitor_recv] interface at monitor {self.name} change value before hold value is asserted \nold value {old_trans_hold} \nnew value {self.interfaces}')
raise TestFailure
"""method for setting up logger for WB model"""
def setup_logger(self):
self.logger = logging.getLogger(f'HouseKeeping{self.name}')
self.logger.setLevel(logging.DEBUG)
if not self.is_logger:
self.logger.setLevel(logging.INFO)
self.handler = logging.StreamHandler()
# return
else :
self.handler = logging.FileHandler(f"{self.name}.log",mode='w')
self.handler.addFilter(SimTimeContextFilter())
self.logger.addHandler(self.handler)
# get the sizes of signals
#for key,interface in self.interfaces.items():
for key,signal in self.interfaces.items():
if fnmatch(key,"_*"):
continue
signal['val'] = self.block_path._id(signal['signal'],False).value
size = signal['val'].n_bits
signal['val'] = BinaryValue(value = int(size) * '1',n_bits=size)
# set the logger file header
# set first line
self.handler.terminator = ""
self.logger.debug(f' timestamp level ')
length =0
for key2,signal in self.interfaces.items():
if fnmatch(key2,"_*"):
continue
length += max(ceil(signal['val'].n_bits/4)+2 , len(key2)) +3
length -= len(key)+1
self.logger.debug(f'| signals {" "*int(length)}')
self.handler.terminator = "\n"
self.logger.debug(f' ')
# set second line
self.handler.terminator = ""
self.logger.debug(f'{" "*20}|')
length =0
self.lengths = dict()
for key2,signal in self.interfaces.items():
if fnmatch(key2,"_*"):
continue
self.lengths[key2] = max((len(hex(signal['val'].integer))),len(key2)) +1
length = self.lengths[key2] - len(key2)
self.logger.debug(f'{key2}{" "*length} ')
self.handler.terminator = "\n"
class color:
PURPLE = '\033[95m'
CYAN = '\033[96m'
DARKCYAN = '\033[36m'
BLUE = '\033[94m'
GREEN = '\033[92m'
YELLOW = '\033[93m'
RED = '\033[91m'
BOLD = '\033[1m'
UNDERLINE = '\033[4m'
END = '\033[0m'

133
verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingIF.json Normal file
View File

@ -0,0 +1,133 @@
{
"inputs" : { "wishbone": {"adr": {"signal":"wb_adr_i","val":0},
"data": {"signal":"wb_dat_i","val":0},
"sel": {"signal":"wb_sel_i","val":0},
"write_en": {"signal":"wb_we_i","val":0},
"cycle_valid": {"signal":"wb_cyc_i","val":0},
"stb": {"signal":"wb_stb_i","val":0},
"_clk": {"signal":"wb_clk_i","val":0},
"_rst": {"signal":"wb_rstn_i","val":0},
"_hold": {"signal":"wb_ack_o","val":0},
"_valid_cycle":{"signal":"wb_cyc_i","val":0}},
"user_clk": {"user_clk": {"signal":"user_clock","val":0}},
"trap": {"user_clk": {"signal":"trap","val":0}},
"UART": {"TX": {"signal":"ser_tx","val":0},
"gpio_in": {"signal":"mgmt_gpio_in","val":0},
"enable": {"signal":"uart_enabled","val":0}},
"SPI": {"CSB": {"signal":"bin3","val":0},
"SCK": {"signal":"bin4","val":0},
"SDI": {"signal":"bin2","val":0},
"_clk": {"signal":"bin4","val":0},
"_valid_cycle_n":{"signal":"bin3","val":0}
},
"SPI_master": {"CSB": {"signal":"spi_csb","val":0},
"SCK": {"signal":"spi_sck","val":0},
"SDO": {"signal":"spi_sdo","val":0},
"SDO_en": {"signal":"spi_sdoenb","val":0},
"spi_enabled": {"signal":"spi_enabled","val":0},
"_clk": {"signal":"spi_sck","val":0},
"_valid_cycle_n":{"signal":"spi_csb","val":0}
},
"gpio_data": {"data": {"signal":"mgmt_gpio_in","val":0}},
"QSPI_mgmt": {"clk": {"signal":"spimemio_flash_clk","val":0},
"CSB": {"signal":"spimemio_flash_csb","val":0},
"io0_oen": {"signal":"spimemio_flash_io0_oeb","val":0},
"io1_oen": {"signal":"spimemio_flash_io1_oeb","val":0},
"io2_oen": {"signal":"spimemio_flash_io2_oeb","val":0},
"io3_oen": {"signal":"spimemio_flash_io3_oeb","val":0},
"data0": {"signal":"spimemio_flash_io0_do","val":0},
"data1": {"signal":"spimemio_flash_io1_do","val":0},
"data2": {"signal":"spimemio_flash_io2_do","val":0},
"data3": {"signal":"spimemio_flash_io3_do","val":0},
"qspi_en": {"signal":"qspi_enabled","val":0},
"_clk": {"signal":"spimemio_flash_clk","val":0}},
"debug": {"data": {"signal":"debug_out","val":0},
"out_en": {"signal":"debug_oeb","val":0},
"gpio_in": {"signal":"mgmt_gpio_in","val":0},
"enable": {"signal":"debug_mode","val":0}},
"QSPI_pad": {"data0": {"signal":"pad_flash_io0_di","val":0},
"data1": {"signal":"pad_flash_io1_di","val":0}},
"sram": {"data": {"signal":"pad_flash_io0_di","val":0}},
"system": {"vcc1_good": {"signal":"usr1_vcc_pwrgood","val":0},
"vcc2_good": {"signal":"usr2_vcc_pwrgood","val":0},
"vdd1_good": {"signal":"usr1_vdd_pwrgood","val":0},
"vdd2_good": {"signal":"usr2_vdd_pwrgood","val":0},
"_no_valid": {"signal":"usr2_vdd_pwrgood","val":0}},
"project_id": {"mask": {"signal":"mask_rev_in","val":0}}
},
"outputs" : { "wishbone": {"ack": {"signal":"wb_ack_o","val":0},
"data": {"signal":"wb_dat_o","val":0},
"_valid_cycle":{"signal":"wb_ack_o","val":0}},
"UART": {"RX": {"signal":"ser_rx","val":0}},
"SPI": {"CSB": {"signal":"bin3","val":0},
"SCK": {"signal":"bin4","val":0},
"SDO": {"signal":"bin1","val":0},
"_clk": {"signal":"bin4","val":0},
"_valid_cycle_n":{"signal":"bin3","val":0}
},
"SPI_master": {"SDI": {"signal":"spi_sdi","val":0},
"_clk": {"signal":"spi_sck","val":0}},
"clk_ctrl": {"pll_en": {"signal":"pll_ena","val":0},
"pll_dco_en": {"signal":"pll_dco_ena","val":0},
"pll_div": {"signal":"pll_div","val":0},
"pll_sel": {"signal":"pll_sel","val":0},
"pll90_sel": {"signal":"pll90_sel","val":0},
"pll_trim": {"signal":"pll_trim","val":0},
"pll_bypass": {"signal":"pll_bypass","val":0}},
"external": {"irq": {"signal":"irq","val":0},
"rst": {"signal":"reset","val":0}},
"gpio_loader":{"clk": {"signal":"serial_clock","val":0},
"load": {"signal":"serial_load","val":0},
"rst": {"signal":"serial_resetn","val":0},
"data_1": {"signal":"serial_data_1","val":0},
"data_2": {"signal":"serial_data_2","val":0}},
"gpio_data": {"data": {"signal":"mgmt_gpio_out","val":0},
"enable": {"signal":"mgmt_gpio_oeb","val":0}},
"pwr_ctrl": {"data": {"signal":"pwr_ctrl_out","val":0}},
"QSPI_mgmt": {"data0": {"signal":"spimemio_flash_io0_di","val":0},
"data1": {"signal":"spimemio_flash_io1_di","val":0},
"data2": {"signal":"spimemio_flash_io2_di","val":0},
"data3": {"signal":"spimemio_flash_io3_di","val":0}},
"debug": {"data": {"signal":"debug_in","val":0}},
"QSPI_pad": {"clk": {"signal":"pad_flash_clk","val":0},
"clk_en": {"signal":"pad_flash_clk_oeb","val":0},
"CSB": {"signal":"pad_flash_csb","val":0},
"CSB_en": {"signal":"pad_flash_csb_oeb","val":0},
"data0": {"signal":"pad_flash_io0_do","val":0},
"data0_oen": {"signal":"pad_flash_io0_oeb","val":0},
"data0_ien": {"signal":"pad_flash_io0_ieb","val":0},
"data1": {"signal":"pad_flash_io1_do","val":0},
"data1_oen": {"signal":"pad_flash_io1_oeb","val":0},
"data1_ien": {"signal":"pad_flash_io1_ieb","val":0},
"_clk": {"signal":"spimemio_flash_clk","val":0}},
"sram": {"clk": {"signal":"sram_ro_clk","val":0},
"CSB": {"signal":"sram_ro_csb","val":0},
"adr": {"signal":"sram_ro_addr","val":0}}
}
}

114
verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingWB.py Normal file
View File

@ -0,0 +1,114 @@
import json
import cocotb
from cocotb.triggers import Timer, RisingEdge, ReadOnly
from cocotb_bus.monitors import Monitor
from cocotb.log import SimLogFormatter, SimTimeContextFilter
from cocotb.binary import BinaryValue
from math import ceil
from wb_models.housekeepingWB.HKmonitor import HKmonitor
from wb_models.housekeepingWB.HKSPImonitor import HKSPImonitor
from wb_models.housekeepingWB.HKSPImonitor import CSBmonitor
from wb_models.housekeepingWB.HK_models import HK_models
from cocotb_bus.scoreboard import Scoreboard
import logging
import fnmatch
import copy
from cocotb.result import TestFailure
from interfaces.common import Macros
class HK_whiteBox:
def __init__(self,dut,loggers=False):
self.dut = dut
self.hk_hdl = dut.uut.housekeeping
# self.hkspi_hdl = dut.uut.housekeeping.hkspi
self.clk = self.dut.uut.mprj_clock
self.reset = self.dut.uut.resetb
self.logger = loggers
self.load_js()
self.setupModels()
self.Monitors()
cocotb.scheduler.add(self.reg_model_sb())
"""load json models"""
def load_js(self):
with open('wb_models/housekeepingWB/housekeepingIF.json') as f:
self.interface = json.load(f)
with open('wb_models/housekeepingWB/HK_regs.json') as f:
self.reg_model = json.load(f)
self.output_if = copy.deepcopy(self.interface['outputs'])
""""method to add the housekeeping monitors"""
def Monitors(self):
inputs = self.interface['inputs']
outputs = self.interface['outputs']
# wishbone
wishbone_mon_i = HKmonitor(f"HKinputsMonitorwishbone",self.hk_hdl,inputs['wishbone'],self.clk,self.reset,self.logger,callback=self.wb_models.wishbone_model)
wishbone_mon_o = HKmonitor(f"HKoutputsMonitorwishbone",self.hk_hdl,outputs['wishbone'],self.clk,self.reset,self.logger)
wishbone_sb = Scoreboard(SB_name("wishbone_sb"),fail_immediately=False)
wishbone_sb.add_interface(wishbone_mon_o, self.wb_models.exp_out_wb)
# system
system_mon_i = HKmonitor(f"HKinputsMonitorsystem",self.hk_hdl,inputs['system'],self.clk,self.reset,self.logger,callback=self.wb_models.system_model)
# UART
UART_mon_i = HKmonitor(f"HKinputsMonitorUART",self.hk_hdl,inputs['UART'],self.clk,self.reset,self.logger,callback=self.wb_models.UART_model)
UART_mon_o = HKmonitor(f"HKoutputsMonitorUART",self.hk_hdl,outputs['UART'],self.clk,self.reset,self.logger)
UART_sb = Scoreboard(SB_name("UART_sb"),fail_immediately=False)
UART_sb.add_interface(UART_mon_o, self.wb_models.exp_out_uart_rx)
# debug
debug_mon_i = HKmonitor(f"HKinputsMonitordebug",self.hk_hdl,inputs['debug'],self.clk,self.reset,self.logger,callback=self.wb_models.debug_model)
debug_mon_o = HKmonitor(f"HKoutputsMonitordebug",self.hk_hdl,outputs['debug'],self.clk,self.reset,self.logger)
debug_sb = Scoreboard(SB_name("debug_sb"),fail_immediately=False)
debug_sb.add_interface(debug_mon_o, self.wb_models.exp_out_debug)
# SPI
SPI_mon_i = HKSPImonitor(f"HKinputsMonitorSPI",self.hk_hdl,inputs['SPI'],self.clk,self.reset,self.logger,callback=self.wb_models.spi_model)
SPI_mon_o = HKSPImonitor(f"HKoutputsMonitorSPI",self.hk_hdl,outputs['SPI'],self.clk,self.reset,self.logger,input=False)
CSBmonitor(f"HKCSBmonitor",self.hk_hdl,outputs['SPI'],self.clk,self.reset,False,callback=self.wb_models.reset_spi_vals)
SPI_sb = Scoreboard(SB_name("SPI_sb"),fail_immediately=False)
SPI_sb.add_interface(SPI_mon_o, self.wb_models.exp_out_spi)
"""initialize all models needed"""
def setupModels(self):
with open('wb_models/housekeepingWB/HK_regs.json') as f:
self.reg_model = json.load(f)
self.wb_models = HK_models(self.reg_model,self.output_if,self.hk_hdl)
"""scoreboard for register model check the reg model with RTL every clock"""
async def reg_model_sb(self):
while True:
await RisingEdge(self.clk)
for key,memory_block in self.reg_model.items():
if fnmatch.fnmatch(key, "_*"):
continue
for reg_shift,reg in memory_block.items():
for field in reg:
if reg_shift == "base_addr":
continue
RTL_reg_name = field[1]
if RTL_reg_name == None:
cocotb.log.debug(f"[HK_whiteBox][reg_model_sb] register {field[1]} in {key} doesn't have a RTL register")
continue
if isinstance(field[1],list):
RTL_name = field[1][0]
first_index = int(field[1][1])
second_index= int(field[1][2])
if Macros['GL']:
if RTL_name in ["mfgr_id","prod_id","mask_rev","mgmt_gpio_data"]: continue #TODO: change with SDF only
if Macros['GL']:
if fnmatch.fnmatch (RTL_name,"gpio_configure*"): continue #TODO: update gpio_configure and mgmt_gpio_data to get each bit in the SDF case
RTL_reg_path = self.hk_hdl._id(RTL_name,False)
size = RTL_reg_path.value.n_bits-1
RTL_reg_val = RTL_reg_path.value[size-first_index:size-second_index]
else :
if field[1] in ["pwr_ctrl_out"]: continue #TODO: delete when reset value is spicified
RTL_reg_path = self.hk_hdl._id(field[1],False)
RTL_reg_val = RTL_reg_path.value
if (RTL_reg_val.integer != field[6]):
cocotb.log.error(f'[HK_whiteBox][reg_model_sb] mismatch in register {field[1]} in {key} expected val = {int(field[6])} actual val = {int(RTL_reg_val.binstr,2)} ' )
else:
cocotb.log.debug(f'[HK_whiteBox][reg_model_sb] match in register {field[1]} in {key} expected val = {field[6]} actual val = {RTL_reg_val.integer} ' )
class SB_name:
def __init__(self,name) -> None:
self._name=name

80
verilog/rtl/__user_project_gpio_example.v Normal file
View File

@ -0,0 +1,80 @@
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_project_la_example
*
* This is a user project for testing the gpio testing only
*
*-------------------------------------------------------------
*/
module user_project_gpio_example (
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output reg wbs_ack_o,
output reg[31:0] wbs_dat_o,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb
);
reg [31:0] io_l;
reg [5:0] io_h;
always @(posedge wb_clk_i or posedge wb_rst_i) begin
if (wb_rst_i) begin
io_l <=0;
io_h <=0;
wbs_dat_o <=0;
wbs_ack_o <=0;
end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0))begin // write
// write to io_l
io_l[7:0] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[0])? wbs_dat_i[7:0] :io_l[7:0];
io_l[15:8] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[1])? wbs_dat_i[15:8] :io_l[15:8];
io_l[23:16] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[2])? wbs_dat_i[23:16] :io_l[23:16];
io_l[31:24] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[3])? wbs_dat_i[31:24] :io_l[31:24];
// io_h
io_h[5:0] <= ((wbs_adr_i[3:0]==4'h4) && wbs_sel_i[0])? wbs_dat_i[5:0] :io_h[5:0];
wbs_ack_o <= 1;
end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0)) begin // read
wbs_dat_o <= (wbs_adr_i[3:0]==4'h0)? io_in[31:0] : io_in[`MPRJ_IO_PADS-1:32];
wbs_ack_o <= 1;
end else begin
wbs_ack_o <= 0;
wbs_dat_o <= 0;
end
end
assign io_out = {io_h,io_l};
assign io_oeb = 38'h0;
endmodule
`default_nettype wire

47
verilog/rtl/__user_project_la_example.v Normal file
View File

@ -0,0 +1,47 @@
// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_project_la_example
*
* This is a user project for testing the la only
*
*-------------------------------------------------------------
*/
module user_project_la_example (
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb
);
// LA
assign la_data_out[63:32] = la_oenb[31:0] ? 32'hz: la_data_in[31:0] ; // assign la0 to la1 if la0 output enable
assign la_data_out[31:0] = la_oenb[63:32] ? 32'hz: la_data_in[63:32] ; // assign la1 to la0 if la1 output enable
assign la_data_out[127:96] = la_oenb[95:64] ? 32'hz: la_data_in[95:64] ; // assign la2 to la3 if la2 output enable
assign la_data_out[95:64] = la_oenb[127:96] ? 32'hz: la_data_in[127:96] ; // assign la3 to la2 if la3 output enable
// // LA
// assign la_data_out[63:32] = la_oenb[31:0] ? la_data_in[31:0] : 32'hz ; // assign la0 to la1 if la0 output enable
// assign la_data_out[31:0] = la_oenb[63:32] ? la_data_in[63:32] : 32'hz ; // assign la1 to la0 if la1 output enable
// assign la_data_out[127:96] = la_oenb[95:64] ? la_data_in[95:64] : 32'hz ; // assign la2 to la3 if la2 output enable
// assign la_data_out[95:64] = la_oenb[127:96] ? la_data_in[127:96] : 32'hz ; // assign la3 to la2 if la3 output enable
endmodule
`default_nettype wire

75
verilog/rtl/__user_project_wrapper.v
View File

@ -79,6 +79,7 @@ module user_project_wrapper #(
);
// Dummy assignments so that we can take it through the openlane flow
`ifndef GPIO_TESTING
`ifdef SIM
// Needed for running GL simulation
assign io_out = 0;
@ -86,5 +87,79 @@ assign io_oeb = 0;
`else
assign io_out = io_in;
`endif
`endif // GPIO_TESTING
`ifdef LA_TESTING
user_project_la_example la_testing(la_data_in,la_data_out,la_oenb);
`endif
// splitting the address space to user address space and debug address space
// debug address space are the last 2 registers of user_project_wrapper address space
wire wbs_cyc_i_user;
wire wbs_ack_o_user;
wire [31:0] wbs_dat_o_user;
wire wbs_cyc_i_debug;
wire wbs_ack_o_debug;
`ifdef GPIO_TESTING
wire wbs_ack_o_gpio;
wire [31:0] wbs_dat_o_gpio;
`endif
wire [31:0] wbs_dat_o_debug;
// reserve the last 2 regs for debugging registers
`ifndef GPIO_TESTING
assign wbs_cyc_i_user = (wbs_adr_i[31:3] != 29'h601FFFF) ? wbs_cyc_i : 0;
assign wbs_cyc_i_debug = (wbs_adr_i[31:3] == 29'h601FFFF) ? wbs_cyc_i : 0;
`endif
`ifndef GPIO_TESTING
assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_o_debug;
assign wbs_dat_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_dat_o_debug : wbs_dat_o_user;
`endif
// reserve the last 4 regs for debugging registers in case of user gpio testing
`ifdef GPIO_TESTING
assign wbs_cyc_i_user = (wbs_adr_i[31:4] != 28'h300FFFF) ? wbs_cyc_i : 0;
assign wbs_cyc_i_debug = (wbs_adr_i[31:4] == 28'h300FFFF) ? wbs_cyc_i : 0;
`endif
`ifdef GPIO_TESTING
assign wbs_ack_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_ack_o_debug : wbs_ack_o_gpio : wbs_ack_o_debug;
assign wbs_dat_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_dat_o_debug : wbs_dat_o_gpio : wbs_dat_o_user;
`endif
`ifdef GPIO_TESTING
user_project_gpio_example gpio_testing(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_cyc_i(wbs_cyc_i_debug),
.wbs_stb_i(wbs_stb_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_ack_o(wbs_ack_o_gpio),
.wbs_dat_o(wbs_dat_o_gpio),
.io_in(io_in),
.io_out(io_out),
.io_oeb(io_oeb));
`endif
debug_regs debug(
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
.wbs_cyc_i(wbs_cyc_i_debug),
.wbs_stb_i(wbs_stb_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_ack_o(wbs_ack_o_debug),
.wbs_dat_o(wbs_dat_o_debug)
);
endmodule // user_project_wrapper

45
verilog/rtl/debug_regs.v Normal file
View File

@ -0,0 +1,45 @@
// module that has registers used for debug
module debug_regs (
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output reg wbs_ack_o,
output reg [31:0] wbs_dat_o);
reg [31:0] debug_reg_1;
reg [31:0] debug_reg_2;
// write
always @(posedge wb_clk_i or posedge wb_rst_i) begin
if (wb_rst_i) begin
debug_reg_1 <=0;
debug_reg_2 <=0;
wbs_dat_o <=0;
wbs_ack_o <=0;
end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8))begin // write
// write to reg1
debug_reg_1[7:0] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_1[7:0];
debug_reg_1[15:8] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_1[15:8];
debug_reg_1[23:16] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_1[23:16];
debug_reg_1[31:24] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_1[31:24];
// write to reg2
debug_reg_2[7:0] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_2[7:0];
debug_reg_2[15:8] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_2[15:8];
debug_reg_2[23:16] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_2[23:16];
debug_reg_2[31:24] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_2[31:24];
wbs_ack_o <= 1;
end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8)) begin // read
wbs_dat_o <= ((wbs_adr_i[3:0]==4'hC)) ? debug_reg_2 : debug_reg_1;
wbs_ack_o <= 1;
end else begin
wbs_ack_o <= 0;
wbs_dat_o <= 0;
end
end
endmodule
`default_nettype wire

Some files were not shown because too many files have changed in this diff Show More