From add4c5f6c87360896818a90f5e9b86457bca4a04 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 30 Sep 2022 01:42:36 -0700 Subject: [PATCH 01/76] Adding cocotb evironment with tests and scripts to run --- verilog/dv/cocotb/.gitignore | 10 + verilog/dv/cocotb/AN.DB/.vcs_lib_lock | 0 verilog/dv/cocotb/Makefile | 79 ++++ verilog/dv/cocotb/caravel.py | 417 ++++++++++++++++++ verilog/dv/cocotb/caravel_tests.py | 200 +++++++++ verilog/dv/cocotb/caravel_top.sv | 275 ++++++++++++ verilog/dv/cocotb/common.py | 79 ++++ verilog/dv/cocotb/cpu.py | 226 ++++++++++ verilog/dv/cocotb/defsParser.py | 87 ++++ verilog/dv/cocotb/hex_files/IRQ_external.hex | 70 +++ verilog/dv/cocotb/hex_files/IRQ_timer.hex | 71 +++ verilog/dv/cocotb/hex_files/IRQ_uart.hex | 87 ++++ .../dv/cocotb/hex_files/bitbang_cpu_all.hex | 238 ++++++++++ .../cocotb/hex_files/bitbang_cpu_all_0011.hex | 212 +++++++++ .../cocotb/hex_files/bitbang_cpu_all_01.hex | 211 +++++++++ .../cocotb/hex_files/bitbang_cpu_all_10.hex | 211 +++++++++ .../cocotb/hex_files/bitbang_cpu_all_1100.hex | 212 +++++++++ .../dv/cocotb/hex_files/bitbang_cpu_all_i.hex | 227 ++++++++++ .../dv/cocotb/hex_files/bitbang_cpu_all_o.hex | 238 ++++++++++ .../dv/cocotb/hex_files/bitbang_no_cpu.hex | 47 ++ .../cocotb/hex_files/bitbang_no_cpu_all.hex | 47 ++ .../cocotb/hex_files/bitbang_no_cpu_all_i.hex | 47 ++ .../cocotb/hex_files/bitbang_no_cpu_all_o.hex | 47 ++ .../dv/cocotb/hex_files/bitbang_no_cpu_i.hex | 47 ++ verilog/dv/cocotb/hex_files/bitbang_spi.hex | 47 ++ verilog/dv/cocotb/hex_files/cpu_drive.hex | 54 +++ verilog/dv/cocotb/hex_files/cpu_stress.hex | 168 +++++++ verilog/dv/cocotb/hex_files/gpio_all_i.hex | 218 +++++++++ verilog/dv/cocotb/hex_files/gpio_all_o.hex | 230 ++++++++++ verilog/dv/cocotb/hex_files/helloWorld.hex | 32 ++ .../dv/cocotb/hex_files/hk_regs_rst_spi.hex | 47 ++ .../dv/cocotb/hex_files/hk_regs_wr_spi.hex | 47 ++ verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex | 47 ++ verilog/dv/cocotb/hex_files/mem_stress.hex | 102 +++++ verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex | 66 +++ verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex | 54 +++ .../dv/cocotb/hex_files/timer0_oneshot.hex | 58 +++ .../dv/cocotb/hex_files/timer0_periodic.hex | 60 +++ verilog/dv/cocotb/hex_files/uart_tx.hex | 62 +++ verilog/dv/cocotb/logic_analyzer.py | 84 ++++ verilog/dv/cocotb/pli.tab | 1 + verilog/dv/cocotb/run.py | 303 +++++++++++++ verilog/dv/cocotb/tests.json | 160 +++++++ .../tests/bitbang/bitbang_cpu_all_0011.c | 62 +++ .../cocotb/tests/bitbang/bitbang_cpu_all_01.c | 60 +++ .../cocotb/tests/bitbang/bitbang_cpu_all_10.c | 60 +++ .../tests/bitbang/bitbang_cpu_all_1100.c | 62 +++ .../cocotb/tests/bitbang/bitbang_cpu_all_i.c | 83 ++++ .../cocotb/tests/bitbang/bitbang_cpu_all_o.c | 99 +++++ .../cocotb/tests/bitbang/bitbang_functions.c | 325 ++++++++++++++ .../cocotb/tests/bitbang/bitbang_functions.py | 355 +++++++++++++++ .../dv/cocotb/tests/bitbang/bitbang_no_cpu.c | 10 + .../tests/bitbang/bitbang_no_cpu_all_i.c | 10 + .../tests/bitbang/bitbang_no_cpu_all_o.c | 9 + verilog/dv/cocotb/tests/bitbang/bitbang_spi.c | 10 + .../dv/cocotb/tests/bitbang/bitbang_tests.py | 375 ++++++++++++++++ .../cocotb/tests/bitbang/bitbang_tests_cpu.py | 199 +++++++++ .../cocotb/tests/common_functions/Timeout.py | 32 ++ .../tests/common_functions/test_functions.py | 95 ++++ verilog/dv/cocotb/tests/cpu/cpu_stress.c | 156 +++++++ verilog/dv/cocotb/tests/cpu/cpu_stress.py | 43 ++ verilog/dv/cocotb/tests/gpio/gpio_all_i.c | 63 +++ verilog/dv/cocotb/tests/gpio/gpio_all_o.c | 79 ++++ verilog/dv/cocotb/tests/gpio/gpio_all_o.py | 83 ++++ .../dv/cocotb/tests/hello_world/helloWorld.c | 5 + .../dv/cocotb/tests/hello_world/helloWorld.py | 11 + .../housekeeping_regs/hk_regs_rst_spi.c | 10 + .../housekeeping_regs/hk_regs_wr_spi.c | 10 + .../housekeeping_regs/hk_regs_wr_wb.c | 10 + .../housekeeping_regs_tests.py | 189 ++++++++ verilog/dv/cocotb/tests/irq/IRQ_external.c | 103 +++++ verilog/dv/cocotb/tests/irq/IRQ_external.py | 75 ++++ verilog/dv/cocotb/tests/irq/IRQ_timer.c | 88 ++++ verilog/dv/cocotb/tests/irq/IRQ_timer.py | 51 +++ verilog/dv/cocotb/tests/irq/IRQ_uart.c | 89 ++++ verilog/dv/cocotb/tests/irq/IRQ_uart.py | 64 +++ verilog/dv/cocotb/tests/mem/mem_stress.c | 102 +++++ verilog/dv/cocotb/tests/mem/mem_stress.py | 51 +++ .../dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py | 105 +++++ .../dv/cocotb/tests/mgmt_gpio/mgmt_gpio_in.c | 67 +++ .../dv/cocotb/tests/mgmt_gpio/mgmt_gpio_out.c | 59 +++ .../cocotb/tests/temp_partial_test/partial.py | 47 ++ verilog/dv/cocotb/tests/timer/timer.py | 103 +++++ .../dv/cocotb/tests/timer/timer0_oneshot.c | 70 +++ .../dv/cocotb/tests/timer/timer0_periodic.c | 73 +++ verilog/dv/cocotb/tests/uart/uart.py | 56 +++ verilog/dv/cocotb/tests/uart/uart_tx.c | 53 +++ .../wb_models/housekeepingWB/HKSPImonitor.py | 157 +++++++ .../wb_models/housekeepingWB/HK_models.py | 371 ++++++++++++++++ .../wb_models/housekeepingWB/HK_regs.json | 129 ++++++ .../wb_models/housekeepingWB/HK_scoreboard.py | 92 ++++ .../wb_models/housekeepingWB/HKmonitor.py | 167 +++++++ .../housekeepingWB/housekeepingIF.json | 133 ++++++ .../housekeepingWB/housekeepingWB.py | 114 +++++ 94 files changed, 10149 insertions(+) create mode 100644 verilog/dv/cocotb/.gitignore create mode 100644 verilog/dv/cocotb/AN.DB/.vcs_lib_lock create mode 100644 verilog/dv/cocotb/Makefile create mode 100644 verilog/dv/cocotb/caravel.py create mode 100644 verilog/dv/cocotb/caravel_tests.py create mode 100644 verilog/dv/cocotb/caravel_top.sv create mode 100644 verilog/dv/cocotb/common.py create mode 100644 verilog/dv/cocotb/cpu.py create mode 100644 verilog/dv/cocotb/defsParser.py create mode 100755 verilog/dv/cocotb/hex_files/IRQ_external.hex create mode 100755 verilog/dv/cocotb/hex_files/IRQ_timer.hex create mode 100755 verilog/dv/cocotb/hex_files/IRQ_uart.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_0011.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_01.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_10.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_1100.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_i.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_o.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu_all.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_i.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_o.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu_i.hex create mode 100755 verilog/dv/cocotb/hex_files/bitbang_spi.hex create mode 100755 verilog/dv/cocotb/hex_files/cpu_drive.hex create mode 100755 verilog/dv/cocotb/hex_files/cpu_stress.hex create mode 100755 verilog/dv/cocotb/hex_files/gpio_all_i.hex create mode 100755 verilog/dv/cocotb/hex_files/gpio_all_o.hex create mode 100755 verilog/dv/cocotb/hex_files/helloWorld.hex create mode 100755 verilog/dv/cocotb/hex_files/hk_regs_rst_spi.hex create mode 100755 verilog/dv/cocotb/hex_files/hk_regs_wr_spi.hex create mode 100755 verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex create mode 100755 verilog/dv/cocotb/hex_files/mem_stress.hex create mode 100755 verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex create mode 100755 verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex create mode 100755 verilog/dv/cocotb/hex_files/timer0_oneshot.hex create mode 100755 verilog/dv/cocotb/hex_files/timer0_periodic.hex create mode 100755 verilog/dv/cocotb/hex_files/uart_tx.hex create mode 100644 verilog/dv/cocotb/logic_analyzer.py create mode 100644 verilog/dv/cocotb/pli.tab create mode 100644 verilog/dv/cocotb/run.py create mode 100644 verilog/dv/cocotb/tests.json create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_0011.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_01.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_10.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_1100.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_i.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_functions.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_functions.py create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_i.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_o.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_spi.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_tests.py create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py create mode 100644 verilog/dv/cocotb/tests/common_functions/Timeout.py create mode 100644 verilog/dv/cocotb/tests/common_functions/test_functions.py create mode 100644 verilog/dv/cocotb/tests/cpu/cpu_stress.c create mode 100644 verilog/dv/cocotb/tests/cpu/cpu_stress.py create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_all_i.c create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_all_o.c create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_all_o.py create mode 100644 verilog/dv/cocotb/tests/hello_world/helloWorld.c create mode 100644 verilog/dv/cocotb/tests/hello_world/helloWorld.py create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py create mode 100644 verilog/dv/cocotb/tests/irq/IRQ_external.c create mode 100644 verilog/dv/cocotb/tests/irq/IRQ_external.py create mode 100644 verilog/dv/cocotb/tests/irq/IRQ_timer.c create mode 100644 verilog/dv/cocotb/tests/irq/IRQ_timer.py create mode 100644 verilog/dv/cocotb/tests/irq/IRQ_uart.c create mode 100644 verilog/dv/cocotb/tests/irq/IRQ_uart.py create mode 100644 verilog/dv/cocotb/tests/mem/mem_stress.c create mode 100644 verilog/dv/cocotb/tests/mem/mem_stress.py create mode 100644 verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py create mode 100644 verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_in.c create mode 100644 verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_out.c create mode 100644 verilog/dv/cocotb/tests/temp_partial_test/partial.py create mode 100644 verilog/dv/cocotb/tests/timer/timer.py create mode 100644 verilog/dv/cocotb/tests/timer/timer0_oneshot.c create mode 100644 verilog/dv/cocotb/tests/timer/timer0_periodic.c create mode 100644 verilog/dv/cocotb/tests/uart/uart.py create mode 100644 verilog/dv/cocotb/tests/uart/uart_tx.c create mode 100644 verilog/dv/cocotb/wb_models/housekeepingWB/HKSPImonitor.py create mode 100644 verilog/dv/cocotb/wb_models/housekeepingWB/HK_models.py create mode 100644 verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json create mode 100644 verilog/dv/cocotb/wb_models/housekeepingWB/HK_scoreboard.py create mode 100644 verilog/dv/cocotb/wb_models/housekeepingWB/HKmonitor.py create mode 100644 verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingIF.json create mode 100644 verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingWB.py diff --git a/verilog/dv/cocotb/.gitignore b/verilog/dv/cocotb/.gitignore new file mode 100644 index 00000000..e9208974 --- /dev/null +++ b/verilog/dv/cocotb/.gitignore @@ -0,0 +1,10 @@ +*.log +sim_build +sim +__pycache__ +*. +./wb_models/housekeepingWB/__pycache__ +*.xml +*.yml +*.hexe +*.elf \ No newline at end of file diff --git a/verilog/dv/cocotb/AN.DB/.vcs_lib_lock b/verilog/dv/cocotb/AN.DB/.vcs_lib_lock new file mode 100644 index 00000000..e69de29b diff --git a/verilog/dv/cocotb/Makefile b/verilog/dv/cocotb/Makefile new file mode 100644 index 00000000..f1d0b6b3 --- /dev/null +++ b/verilog/dv/cocotb/Makefile @@ -0,0 +1,79 @@ +# SPDX-FileCopyrightText: 2020 Efabless Corporation +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# SPDX-License-Identifier: Apache-2.0 + + +PWDD := $(shell pwd) +BLOCKS := $(shell basename $(PWDD)) + +# ---- Include Partitioned Makefiles ---- +CONFIG = caravel_user_project +# TestName = temp_partial +# export COCOTB_ANSI_OUTPUT=0 # disable color in termianl +export GUI=1 +export COCOTB_REDUCED_LOG_FMT=1 +# Change this line if you want to use existing cocotb test modules: +# export PYTHONPATH := $(DESIGNS)/verilog/rtl/ +# export LIBPYTHON_LOC=$(cocotb-config --libpython) +#export VERILOG_PATH = ../../../ +#export CARAVEL_PATH = ../../../../../caravel/verilog/ +# include $(MCW_ROOT)/verilog/dv/make/env.makefile +# #export VERILOG_PATH = ../../../ +# include $(MCW_ROOT)/verilog/dv/make/var.makefile +# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile +# include $(MCW_ROOT)/verilog/dv/make/sim.makefile +TESTCASE=$(TestName) + +MODULE=caravel_tests +$(info $$MODULE is [$(MODULE)]) +cocotb: + rm -rf sim_build/ + mkdir sim_build/ + # change project_tb.v to match your testbench + #RTL + iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + -DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \ + -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ + -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv + #GL + # iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ + # -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \ + # -f$(VERILOG_PATH)/includes/includes.gl.caravel \ + # -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv + #CVC + + + # TESTCASE=$(TestName) MODULE=caravel_tests cvc64 +interp +acc+2 \ + # +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap\ + # +change_port_type +maxerrors 1\ + # +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY=#0 \ + # +define+TESTNAME=\"$(TestName)\" +define+RUNTAG=\"$(RUNTAG)\" +define+COCOTB_SIM=1\ + # -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \ + # -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) -o sim_build/sim.vvp + + + + # verilator --vpi --public-flat-rw --prefix Vtop \ + # -LDFLAGS "-Wl,-rpath,$(cocotb-config --prefix)/cocotb/libs \ + # -L$(cocotb-config --prefix)/cocotb/libs \ + # -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils" \ + # $(cocotb-config --share)/lib/verilator/verilator.cpp\ + # -y $(VERILOG_PATH)/includes/includes.rtl.caravel \ + # -y $(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) --cc -o sim_build/sim.vvp caravel_top.sv + # change this line to choose the comma separated test cases and the name of your python test module + + TESTCASE=$(TestName) MODULE=caravel_tests vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp + ! grep failure results.xml + diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py new file mode 100644 index 00000000..e1c85149 --- /dev/null +++ b/verilog/dv/cocotb/caravel.py @@ -0,0 +1,417 @@ +import random +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +import cocotb.simulator +from cocotb.handle import SimHandleBase +from cocotb.handle import Force +from cocotb_coverage.coverage import * +from cocotb.binary import BinaryValue +import enum +from cocotb.handle import ( + ConstantObject, + HierarchyArrayObject, + HierarchyObject, + ModifiableObject, + NonHierarchyIndexableObject, + SimHandle, +) + +from itertools import groupby, product + +import common +from common import GPIO_MODE +from common import MASK_GPIO_CTRL +from common import Macros + +def gpio_mode(gpios_values:list): + gpios=[] + for array in gpios_values: + gpio_value = GPIO_MODE(array[1]).name + for gpio in array[0]: + gpios.append((gpio,gpio_value)) + cocotb.log.info(f'[caravel][gpio_mode] gpios {gpios}') + return gpios + +Carvel_Coverage = coverage_section ( + + CoverPoint("top.caravel.gpio", vname="gpios mode", xf = lambda gpio ,gpio_mode: (gpio,gpio_mode) , + bins = list(product(range(38),[e.name for e in GPIO_MODE]))) + +) + +class Caravel_env: + def __init__(self,dut:SimHandleBase): + self.dut = dut + self.clk = dut.clock_tb + self.caravel_hdl = dut.uut + self.hk_hdl = dut.uut.housekeeping + + """start carvel by insert power then reset""" + async def start_up(self): + await self.power_up() + await self.reset() + await self.disable_bins() + await self.disable_csb() + common.fill_macros(self.dut.macros) # get macros value + + async def disable_bins(self): + for i in range(38): + common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) + + """setup the vdd and vcc power bins""" + async def power_up(self): + cocotb.log.info(f' [caravel] start powering up') + self.set_vdd(0) + self.set_vcc(0) + await ClockCycles(self.clk, 10) + cocotb.log.info(f' [caravel] power up -> connect vdd' ) + self.set_vdd(1) + # await ClockCycles(self.clk, 10) + cocotb.log.info(f' [caravel] power up -> connect vcc' ) + self.set_vcc(1) + await ClockCycles(self.clk, 10) + + """"reset caravel""" + async def reset(self): + cocotb.log.info(f' [caravel] start resetting') + self.dut.resetb_tb.value = 0 + await ClockCycles(self.clk, 20) + self.dut.resetb_tb.value = 1 + await ClockCycles(self.clk, 1) + cocotb.log.info(f' [caravel] finish resetting') + + + def set_vdd(self,value:bool): + self.dut.vddio_tb.value = value + self.dut.vssio_tb.value = 0 + self.dut.vddio_2_tb.value = value + self.dut.vssio_2_tb.value = 0 + self.dut.vdda_tb.value = value + self.dut.vssa_tb.value = 0 + self.dut.vdda1_tb.value = value + self.dut.vssa1_tb.value = 0 + self.dut.vdda1_2_tb.value = value + self.dut.vssa1_2_tb.value = 0 + self.dut.vdda2_tb.value = value + self.dut.vssa2_tb.value = 0 + + def set_vcc(self , value:bool): + self.dut.vccd_tb.value = value + self.dut.vssd_tb.value = 0 + self.dut.vccd1_tb.value = value + self.dut.vssd1_tb.value = 0 + self.dut.vccd2_tb.value = value + self.dut.vssd2_tb.value = 0 + + """drive csb signal bin E8 mprj[3]""" + async def drive_csb(self,bit): + self.drive_gpio_in((3,3),bit) + self.drive_gpio_in((2,2),0) + await ClockCycles(self.clk, 1) + + + """set the spi vsb signal high to disable housekeeping spi transmission bin E8 mprj[3]""" + async def disable_csb(self ): + cocotb.log.info(f' [caravel] disable housekeeping spi transmission') + await self.drive_csb(1) + + """set the spi vsb signal high impedance """ + async def release_csb(self ): + cocotb.log.info(f' [caravel] release housekeeping spi transmission') + await self.drive_csb('z') + + + """set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]""" + async def enable_csb(self ): + cocotb.log.info(f' [caravel] enable housekeeping spi transmission') + await self.drive_csb(0) + + + """return the value of mprj in bits used tp monitor the output gpios value""" + def monitor_gpio(self,bits:tuple): + mprj = self.dut.mprj_io_tb.value + size =mprj.n_bits -1 #size of bins array + mprj_out= self.dut.mprj_io_tb.value[size - bits[0]:size - bits[1]] + if(mprj_out.is_resolvable): + cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {hex(mprj_out)}') + else: + cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {mprj_out}') + return mprj_out + + """return the value of management gpio""" + def monitor_mgmt_gpio(self): + data = self.dut.gpio_tb.value + cocotb.log.debug(f' [caravel] Monitor mgmt gpio = {data}') + return data + + """change the configration of the gpios by overwrite their defaults value then reset + need to take at least 1 cycle for reset """ + ### dont use back door accessing + async def configure_gpio_defaults(self,gpios_values: list): + gpio_defaults = self.caravel_hdl.gpio_defaults.value + cocotb.log.info(f' [caravel] start cofigure gpio gpios ') + size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults + # list example [[(gpios),value],[(gpios),value],[(gpios),value]] + for array in gpios_values: + gpio_value = array[1] + for gpio in array[0]: + self.cov_configure_gpios(gpio,gpio_value.name) + gpio_defaults[size - (gpio*13 + 12): size -gpio*13] = gpio_value.value + #cocotb.log.info(f' [caravel] gpio_defaults[{size - (gpio*13 + 12)}:{size -gpio*13}] = {gpio_value.value} ') + self.caravel_hdl.gpio_defaults.value = gpio_defaults + #reset + self.caravel_hdl.gpio_resetn_1_shifted.value = 0 + self.caravel_hdl.gpio_resetn_2_shifted.value = 0 + await ClockCycles(self.clk, 1) + self.caravel_hdl.gpio_resetn_1_shifted.value = 1 + self.caravel_hdl.gpio_resetn_2_shifted.value = 1 + cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ') + self.print_gpios_ctrl_val() + + """change the configration of the gpios by overwrite the register value + in control registers and housekeeping regs, don't consume simulation cycles""" + ### dont use back door accessing + def configure_gpios_regs(self,gpios_values: list): + cocotb.log.info(f' [caravel] start cofigure gpio gpios ') + control_modules = self.control_blocks_paths() + # list example [[(gpios),value],[(gpios),value],[(gpios),value]] + for array in gpios_values: + gpio_value = array[1] + for gpio in array[0]: + self.cov_configure_gpios(gpio,gpio_value.name) + self.gpio_control_reg_write(control_modules[gpio],gpio_value.value) # for control blocks regs + self.caravel_hdl.housekeeping.gpio_configure[gpio].value = gpio_value.value # for house keeping regs + cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ') + self.print_gpios_ctrl_val() + self.print_gpios_HW_val() + + """dummy function for coverage sampling""" + @Carvel_Coverage + def cov_configure_gpios(self,gpio,gpio_mode): + cocotb.log.debug(f' [caravel] gpio [{gpio}] = {gpio_mode} ') + pass + + def print_gpios_default_val(self,print=1): + gpio_defaults = self.caravel_hdl.gpio_defaults.value + size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults + gpios = [] + for gpio in range(Macros['MPRJ_IO_PADS']): + gpio_value = gpio_defaults[size - (gpio*13 + 12): size -gpio*13] + gpio_enum = GPIO_MODE(gpio_value.integer) + gpios.append((gpio,gpio_enum)) + group_bins = groupby(gpios,key=lambda x: x[1]) + for key,value in group_bins: + gpios=[] + for gpio in list(value): + gpios.append(gpio[0]) + if (print): + cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ') + return gpios + + """print the values return in the gpio of control block mode in GPIO Mode format""" + def print_gpios_ctrl_val(self, print=1): + control_modules = self.control_blocks_paths() + gpios = [] + for i , gpio in enumerate(control_modules): + gpios.append((i,self.gpio_control_reg_read(gpio))) + group_bins = groupby(gpios,key=lambda x: x[1]) + for key,value in group_bins: + gpios=[] + for gpio in list(value): + gpios.append(gpio[0]) + if (print): + cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ') + return gpios + + def _check_gpio_ctrl_eq_HW(self): + assert self.print_gpios_ctrl_val(1) == self.print_gpios_HW_val(1), f'there is an issue while configuration the control block register value isn\'t the same as the house keeping gpio register' + + """print the values return in the gpio of housekeeping block mode in GPIO Mode format""" + def print_gpios_HW_val(self,print=1): + gpios = [] + for pin in range(Macros['MPRJ_IO_PADS']): + gpios.append((pin,GPIO_MODE(self.caravel_hdl.housekeeping.gpio_configure[pin].value))) + group_bins = groupby(gpios,key=lambda x: x[1]) + for key,value in group_bins: + gpios=[] + for gpio in list(value): + gpios.append(gpio[0]) + if (print): + cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ') + return gpios + + + """return the paths of the control blocks""" + def control_blocks_paths(self)-> list: + car = self.caravel_hdl + control_modules =[car._id("gpio_control_bidir_1[0]",False),car._id("gpio_control_bidir_1[1]",False)] + #add gpio_control_in_1a (GPIO 2 to 7) + for i in range(6): + control_modules.append(car._id(f'gpio_control_in_1a[{i}]',False)) + #add gpio_control_in_1 (GPIO 8 to 18) + for i in range(Macros['MPRJ_IO_PADS_1']-9+1): + control_modules.append(car._id(f'gpio_control_in_1[{i}]',False)) + #add gpio_control_in_2 (GPIO 19 to 34) + for i in range(Macros['MPRJ_IO_PADS_2']-4+1): + control_modules.append(car._id(f'gpio_control_in_2[{i}]',False)) + # Last three GPIOs (spi_sdo, flash_io2, and flash_io3) gpio_control_bidir_2 + for i in range(3): + control_modules.append(car._id(f'gpio_control_bidir_2[{i}]',False)) + return control_modules + + """read the control register and return a GPIO Mode it takes the path to the control reg""" + def gpio_control_reg_read(self,path:SimHandleBase) -> GPIO_MODE: + gpio_mgmt_en = path.mgmt_ena.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value + gpio_out_dis = path.gpio_outenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value + gpio_holdover = path.gpio_holdover.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value + gpio_in_dis = path.gpio_inenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value + gpio_mode_sel = path.gpio_ib_mode_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value + gpio_anlg_en = path.gpio_ana_en.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value + gpio_anlg_sel = path.gpio_ana_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value + gpio_anlg_pol = path.gpio_ana_pol.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value + gpio_slow_sel = path.gpio_slow_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value + gpio_vtrip_sel = path.gpio_vtrip_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value + gpio_dgtl_mode = path.gpio_dm.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value + control_reg = (gpio_mgmt_en | gpio_out_dis | gpio_holdover| gpio_in_dis | gpio_mode_sel | gpio_anlg_en + |gpio_anlg_sel|gpio_anlg_pol|gpio_slow_sel|gpio_vtrip_sel|gpio_dgtl_mode) + return(GPIO_MODE(control_reg)) + + """read the control register and return a GPIO Mode it takes the path to the control reg""" + def gpio_control_reg_write(self,path:SimHandleBase,data) : + bits =common.int_to_bin_list(data,14) + path.mgmt_ena.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value] + path.gpio_outenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value] + path.gpio_holdover.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value] + path.gpio_inenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value] + path.gpio_ib_mode_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value] + path.gpio_ana_en.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value] + path.gpio_ana_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value] + path.gpio_ana_pol.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value] + path.gpio_slow_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value] + path.gpio_vtrip_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value] + gpio_dm =bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value:MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value+3] + gpio_dm =sum(d * 2**i for i, d in enumerate(gpio_dm)) # convert list to binary int + path.gpio_dm.value = gpio_dm + + """drive the value of mprj bits with spicific data from input pad at the top""" + def release_gpio(self): + io = self.caravel_hdl.padframe.mprj_pads.io + mprj , n_bits = common.signal_valueZ_size(io) + io.value = mprj + cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}') + + """drive the value of mprj bits with spicific data from input pad at the top""" + def drive_gpio_in(self,bits,data): + # io = self.caravel_hdl.padframe.mprj_pads.io + # mprj , n_bits = common.signal_value_size(io) + # cocotb.log.debug(f' [caravel] before mprj with {mprj} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]') + # mprj[n_bits-1-bits[0]:n_bits-1-bits[1]] = data + # io.value = mprj + # cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}') + data_bits = [] + is_list = isinstance(bits, (list,tuple)) + if is_list : + cocotb.log.info(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}') + data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0] {data}') + await FallingEdge(self.dut.wb_ack_o) # wait for acknowledge + self.hk_hdl.wb_stb_i.value = 0 + self.hk_hdl.wb_cyc_i.value = 0 + cocotb.log.info(f'Monitor: End writing {hex(addr)} -> {data}') + + + """read from the house keeping registers by back door no need for commands and waiting for the data to show on mprj""" + async def hk_read_backdoor(self,addr): + await RisingEdge(self.clk) + self.hk_hdl.wb_stb_i.value = 1 + self.hk_hdl.wb_cyc_i.value = 1 + self.hk_hdl.wb_sel_i.value = 0 + self.hk_hdl.wb_we_i.value = 0 + self.hk_hdl.wb_adr_i.value = addr + cocotb.log.info(f' [housekeeping] Monitor: Start reading from {hex(addr)}') + await FallingEdge(self.hk_hdl.wb_ack_o) + self.hk_hdl.wb_stb_i.value = 0 + self.hk_hdl.wb_cyc_i.value = 0 + cocotb.log.info(f' [housekeeping] Monitor: read from {hex(addr)} value {(self.hk_hdl.wb_dat_o.value)}') + return self.hk_hdl.wb_dat_o.value + + + diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py new file mode 100644 index 00000000..2d4cd80d --- /dev/null +++ b/verilog/dv/cocotb/caravel_tests.py @@ -0,0 +1,200 @@ +from cgitb import handler +import random +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +import cocotb.simulator +from cocotb_coverage.coverage import * +from cocotb.binary import BinaryValue +import caravel +from logic_analyzer import LA +from caravel import GPIO_MODE, Caravel_env +from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox +import common +import logging +from cpu import RiskV +from cocotb.log import SimTimeContextFilter +from cocotb.log import SimLogFormatter +from defsParser import Regs +from tests.common_functions.Timeout import Timeout +from cocotb.result import TestSuccess +import inspect +import os +# tests +from tests.bitbang.bitbang_tests import * +from tests.bitbang.bitbang_tests_cpu import * +from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import * +from tests.temp_partial_test.partial import * +from tests.hello_world.helloWorld import * +from tests.cpu.cpu_stress import * +from tests.mem.mem_stress import * +from tests.irq.IRQ_external import * +from tests.irq.IRQ_timer import * +from tests.irq.IRQ_uart import * +from tests.gpio.gpio_all_o import * +from tests.mgmt_gpio.mgmt_gpio import * +from tests.timer.timer import * +from tests.uart.uart import * + + + + +# archive tests +@cocotb.test() +async def cpu_drive(dut): + TestName = inspect.stack()[0][3] + if not os.path.exists(f'sim/{TestName}'): + os.mkdir(f'sim/{TestName}') # create test folder + cocotb.log.setLevel(logging.INFO) + handler = logging.FileHandler(f"sim/{TestName}/{TestName}.log",mode='w') + handler.addFilter(SimTimeContextFilter()) + handler.setFormatter(SimLogFormatter()) + cocotb.log.addHandler(handler) + caravelEnv = caravel.Caravel_env(dut) + Timeout(caravelEnv.clk,1000000,0.1) + la = LA(dut) + clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk + cpu = RiskV(dut) + cpu.cpu_force_reset() + + cocotb.start_soon(clock.start()) # Start the clock + + await caravelEnv.start_up() + hk = HK_whiteBox(dut) + + reg = Regs() + time_out_count =0 + + await ClockCycles(caravelEnv.clk, 100) + address = reg.get_addr('reg_wb_enable') + await cpu.drive_data2address(address,1) + address = reg.get_addr('reg_debug_2') + await cpu.drive_data2address(address,0xdFF0) + await ClockCycles(caravelEnv.clk, 10) + cpu.cpu_release_reset() + await ClockCycles(caravelEnv.clk, 10) + + raise TestSuccess(f" TEST {TestName} passed") + + while True: + await ClockCycles(caravelEnv.clk, 1) + if (cpu.read_debug_reg1() == 0xFFF0): + break + cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xFFF0") + await ClockCycles(caravelEnv.clk, 10) + address = reg.get_addr('reg_debug_2') + await cpu.drive_data2address(address,0xdFF0) + await ClockCycles(caravelEnv.clk, 50) + # address = reg.get_addr('reg_mprj_io_0') + # await cpu.drive_data2address(address,0x0c03) + cocotb.log.info(f"[TEST][cpu_drive] wait debug reg1 = 0xddd0") + while True: + await ClockCycles(caravelEnv.clk, 1) + if (cpu.read_debug_reg1() == 0xddd0): + break + cocotb.log.info(f"[TEST][cpu_drive] debug reg1 = 0xddd0") + + await ClockCycles(caravelEnv.clk, 10) + + caravelEnv.print_gpios_HW_val() + coverage_db.export_to_yaml(filename="coverage.yalm") + + +@cocotb.test() +async def spi_drive(dut): + cocotb.log.setLevel(logging.INFO) + handler = logging.FileHandler(f"test.log",mode='w') + handler.addFilter(SimTimeContextFilter()) + handler.setFormatter(SimLogFormatter()) + cocotb.log.addHandler(handler) + caravelEnv = caravel.Caravel_env(dut) + + + la = LA(dut) + clock = Clock(caravelEnv.clk, 12.5, units="ns") # Create a 10ns period clock on port clk + cocotb.start_soon(clock.start()) # Start the clock + await caravelEnv.start_up() + hk = HK_whiteBox(dut,True) + + caravelEnv.enable_csb() + await ClockCycles(caravelEnv.clk,1) + # caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]]) + await ClockCycles(caravelEnv.clk,1) + await caravelEnv.hk_write_byte(0x40) # read command + # await caravelEnv.hk_write_byte(0x80) # command write + await caravelEnv.hk_write_byte(0x0) # address + # await caravelEnv.hk_write_byte(0x03) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + + read_data = await caravelEnv.hk_read_byte() # read value + print(read_data) + read_data = await caravelEnv.hk_read_byte() # read value + print(read_data) + read_data = await caravelEnv.hk_read_byte() # read value + print(read_data) + read_data = await caravelEnv.hk_read_byte() # read value + print(read_data) + read_data = await caravelEnv.hk_read_byte() # read value + print(read_data) + read_data = await caravelEnv.hk_read_byte() # read value + print(read_data) + read_data = await caravelEnv.hk_read_byte() # read value + print(read_data) + read_data = await caravelEnv.hk_read_byte(True) # read value + caravelEnv.disable_csb() + await ClockCycles(caravelEnv.clk,1) + caravelEnv.enable_csb() + await ClockCycles(caravelEnv.clk,1) + # caravelEnv.configure_gpios_regs([[tuple(range(0,6)),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT]]) + await ClockCycles(caravelEnv.clk,1) + await caravelEnv.hk_write_byte(0x40) # read command + # await caravelEnv.hk_write_byte(0x80) # command write + await caravelEnv.hk_write_byte(0x8) # address + # await caravelEnv.hk_write_byte(0x03) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + # await caravelEnv.hk_write_byte(0xaa) # data + + read_data = await caravelEnv.hk_read_byte() # read value + read_data = await caravelEnv.hk_read_byte() # read value + read_data = await caravelEnv.hk_read_byte() # read value + read_data = await caravelEnv.hk_read_byte() # read value + read_data = await caravelEnv.hk_read_byte() # read value + read_data = await caravelEnv.hk_read_byte() # read value + read_data = await caravelEnv.hk_read_byte() # read value + read_data = await caravelEnv.hk_read_byte() # read value + + # caravelEnv.drive_gpio_in([5,5],1) + await ClockCycles(caravelEnv.clk,40) + coverage_db.export_to_yaml(filename="coverage.yml") + coverage_db.export_to_xml(filename="coverage.xml") + return + + diff --git a/verilog/dv/cocotb/caravel_top.sv b/verilog/dv/cocotb/caravel_top.sv new file mode 100644 index 00000000..47138185 --- /dev/null +++ b/verilog/dv/cocotb/caravel_top.sv @@ -0,0 +1,275 @@ +`ifdef VCS + `ifndef GL + `include "caravel_mgmt_soc_litex/verilog/includes/rtl_caravel_vcs.v" + `else + `include "caravel_mgmt_soc_litex/verilog/includes/gl_caravel_vcs.v" + `endif + //`include "verilog/includes/user_project_vcs.v" +`endif +module caravel_top ; + +// parameter FILENAME = {"hex_files/",`TESTNAME,".hex"}; +parameter FILENAME={"hex_files/",`TESTNAME,".hex"}; +initial begin + `ifdef VCS + `ifdef ENABLE_SDF + $vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME , `SDF_POSTFIX, ".vpd"}); + `else + $vcdplusfile({`MAIN_PATH,"/sim/",`TAG,"/",`FTESTNAME,"/",`TESTNAME ,".vpd"}); + `endif + $vcdpluson(); + `else + $dumpfile ({"sim/",`TAG,"/",`SIM,"-",`TESTNAME,"/",`SIM,"-",`TESTNAME,".vcd"}); + $dumpvars (0, caravel_top); + `endif +end + + wire vddio_tb; // Common 3.3V padframe/ESD power + wire vddio_2_tb; // Common 3.3V padframe/ESD power + wire vssio_tb; // Common padframe/ESD ground + wire vssio_2_tb; // Common padframe/ESD ground + wire vdda_tb; // Management 3.3V power + wire vssa_tb; // Common analog ground + wire vccd_tb; // Management/Common 1.8V power + wire vssd_tb; // Common digital ground + wire vdda1_tb; // User area 1 3.3V power + wire vdda1_2_tb; // User area 1 3.3V power + wire vdda2_tb; // User area 2 3.3V power + wire vssa1_tb; // User area 1 analog ground + wire vssa1_2_tb; // User area 1 analog ground + wire vssa2_tb; // User area 2 analog ground + wire vccd1_tb; // User area 1 1.8V power + wire vccd2_tb; // User area 2 1.8V power + wire vssd1_tb; // User area 1 digital ground + wire vssd2_tb; // User area 2 digital ground + + wire gpio_tb; // Used for external LDO control + wire [38-1:0] mprj_io_tb; + reg clock_tb; // CMOS core clock input; not a crystal + wire resetb_tb; // Reset input (sense inverted) + + // Note that only two flash data pins are dedicated to the + // management SoC wrapper. The management SoC exports the + // quad SPI mode status to make use of the top two mprj_io + // pins for io2 and io3. + + wire flash_csb_tb; + wire flash_clk_tb; + wire flash_io0_tb; + wire flash_io1_tb; + + + +caravel uut ( + .vddio (vddio_tb), + .vddio_2 (vddio_2_tb), + .vssio (vssio_tb), + .vssio_2 (vssio_2_tb), + .vdda (vdda_tb), + .vssa (vssa_tb), + .vccd (vccd_tb), + .vssd (vssd_tb), + .vdda1 (vdda1_tb), + .vdda1_2 (vdda1_2_tb), + .vdda2 (vdda2_tb), + .vssa1 (vssa1_tb), + .vssa1_2 (vssa1_2_tb), + .vssa2 (vssa2_tb), + .vccd1 (vccd1_tb), + .vccd2 (vccd2_tb), + .vssd1 (vssd1_tb), + .vssd2 (vssd2_tb), + .clock (clock_tb), + .gpio (gpio_tb), + .mprj_io (mprj_io_tb), + .flash_csb(flash_csb_tb), + .flash_clk(flash_clk_tb), + .flash_io0(flash_io0_tb), + .flash_io1(flash_io1_tb), + .resetb (resetb_tb) + ); + + spiflash #( + FILENAME + ) spiflash ( + .csb(flash_csb_tb), + .clk(flash_clk_tb), + .io0(flash_io0_tb), + .io1(flash_io1_tb), + .io2(), // not used + .io3() // not used + ); + + mac macros(); + + + // make speical variables for the mprj input to assign the input without writing to the output gpios + // cocotb limitation #2587 + wire bin0; + wire bin0_en; + wire bin1; + wire bin1_en; + wire bin2; + wire bin2_en; + wire bin3; + wire bin3_en; + wire bin4; + wire bin4_en; + wire bin5; + wire bin5_en; + wire bin6; + wire bin6_en; + wire bin7; + wire bin7_en; + wire bin8; + wire bin8_en; + wire bin9; + wire bin9_en; + wire bin10; + wire bin10_en; + wire bin11; + wire bin11_en; + wire bin12; + wire bin12_en; + wire bin13; + wire bin13_en; + wire bin14; + wire bin14_en; + wire bin15; + wire bin15_en; + wire bin16; + wire bin16_en; + wire bin17; + wire bin17_en; + wire bin18; + wire bin18_en; + wire bin19; + wire bin19_en; + wire bin20; + wire bin20_en; + wire bin21; + wire bin21_en; + wire bin22; + wire bin22_en; + wire bin23; + wire bin23_en; + wire bin24; + wire bin24_en; + wire bin25; + wire bin25_en; + wire bin26; + wire bin26_en; + wire bin27; + wire bin27_en; + wire bin28; + wire bin28_en; + wire bin29; + wire bin29_en; + wire bin30; + wire bin30_en; + wire bin31; + wire bin31_en; + wire bin32; + wire bin32_en; + wire bin33; + wire bin33_en; + wire bin34; + wire bin34_en; + wire bin35; + wire bin35_en; + wire bin36; + wire bin36_en; + wire bin37; + wire bin37_en; + + + assign mprj_io_tb[0] = (bin0_en) ? bin0 : 1'bz; + assign mprj_io_tb[1] = (bin1_en) ? bin1 : 1'bz; + assign mprj_io_tb[2] = (bin2_en) ? bin2 : 1'bz; + assign mprj_io_tb[3] = (bin3_en) ? bin3 : 1'bz; + assign mprj_io_tb[4] = (bin4_en) ? bin4 : 1'bz; + + assign mprj_io_tb[5] = (bin5_en) ? bin5 : 1'bz; + assign mprj_io_tb[6] = (bin6_en) ? bin6 : 1'bz; + assign mprj_io_tb[7] = (bin7_en) ? bin7 : 1'bz; + assign mprj_io_tb[8] = (bin8_en) ? bin8 : 1'bz; + assign mprj_io_tb[9] = (bin9_en) ? bin9 : 1'bz; + + assign mprj_io_tb[10] = (bin10_en) ? bin10 : 1'bz; + assign mprj_io_tb[11] = (bin11_en) ? bin11 : 1'bz; + assign mprj_io_tb[12] = (bin12_en) ? bin12 : 1'bz; + assign mprj_io_tb[13] = (bin13_en) ? bin13 : 1'bz; + assign mprj_io_tb[14] = (bin14_en) ? bin14 : 1'bz; + + assign mprj_io_tb[15] = (bin15_en) ? bin15 : 1'bz; + assign mprj_io_tb[16] = (bin16_en) ? bin16 : 1'bz; + assign mprj_io_tb[17] = (bin17_en) ? bin17 : 1'bz; + assign mprj_io_tb[18] = (bin18_en) ? bin18 : 1'bz; + assign mprj_io_tb[19] = (bin19_en) ? bin19 : 1'bz; + + assign mprj_io_tb[20] = (bin20_en) ? bin20 : 1'bz; + assign mprj_io_tb[21] = (bin21_en) ? bin21 : 1'bz; + assign mprj_io_tb[22] = (bin22_en) ? bin22 : 1'bz; + assign mprj_io_tb[23] = (bin23_en) ? bin23 : 1'bz; + assign mprj_io_tb[24] = (bin24_en) ? bin24 : 1'bz; + + assign mprj_io_tb[25] = (bin25_en) ? bin25 : 1'bz; + assign mprj_io_tb[26] = (bin26_en) ? bin26 : 1'bz; + assign mprj_io_tb[27] = (bin27_en) ? bin27 : 1'bz; + assign mprj_io_tb[28] = (bin28_en) ? bin28 : 1'bz; + assign mprj_io_tb[29] = (bin29_en) ? bin29 : 1'bz; + + assign mprj_io_tb[30] = (bin30_en) ? bin30 : 1'bz; + assign mprj_io_tb[31] = (bin31_en) ? bin31 : 1'bz; + assign mprj_io_tb[32] = (bin32_en) ? bin32 : 1'bz; + assign mprj_io_tb[33] = (bin33_en) ? bin33 : 1'bz; + assign mprj_io_tb[34] = (bin34_en) ? bin34 : 1'bz; + + assign mprj_io_tb[35] = (bin35_en) ? bin35 : 1'bz; + assign mprj_io_tb[36] = (bin36_en) ? bin36 : 1'bz; + assign mprj_io_tb[37] = (bin37_en) ? bin37 : 1'bz; + +endmodule + +// module that has all needed macros by cocotb +module mac; + +reg [7:0] MPRJ_IO_PADS_1 = `ifdef MPRJ_IO_PADS_1 `MPRJ_IO_PADS_1 `else 0 `endif; /* number of user GPIO pads on user1 side */ +reg [7:0] MPRJ_IO_PADS_2 = `ifdef MPRJ_IO_PADS_2 `MPRJ_IO_PADS_2 `else 0 `endif; /* number of user GPIO pads on user2 side */ +reg [7:0] MPRJ_IO_PADS = `ifdef MPRJ_IO_PADS `MPRJ_IO_PADS `else 0 `endif; +reg [7:0] MPRJ_PWR_PADS_1 =`ifdef MPRJ_PWR_PADS_1 `MPRJ_PWR_PADS_1 `else 0 `endif; /* vdda1, vccd1 enable/disable control */ +reg [7:0] MPRJ_PWR_PADS_2 = `ifdef MPRJ_PWR_PADS_2 `MPRJ_PWR_PADS_2 `else 0 `endif; /* vdda2, vccd2 enable/disable control */ +reg [7:0] MPRJ_PWR_PADS =`ifdef MPRJ_PWR_PADS `MPRJ_PWR_PADS `else 0 `endif; +// Analog pads are only used by the "caravan" module and associated +// modules such as user_analog_project_wrapper and chip_io_alt. +reg [7:0] ANALOG_PADS_1 = `ifdef ANALOG_PADS_1 `ANALOG_PADS_1 `else 0 `endif; +reg [7:0] ANALOG_PADS_2 = `ifdef ANALOG_PADS_2 `ANALOG_PADS_2 `else 0 `endif; +reg [7:0] ANALOG_PADS = `ifdef ANALOG_PADS `ANALOG_PADS `else 0 `endif; + +// Type and size of soc_mem +reg USE_CUSTOM_DFFRAM = `ifdef USE_CUSTOM_DFFRAM 1 `else 0 `endif; +// don't change the following without double checking addr widths +reg [7:0] MEM_WORDS = `ifdef MEM_WORDS `MEM_WORDS `else 0 `endif; +// Number of columns in the custom memory; takes one of three values: +// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB +reg [7:0] DFFRAM_WSIZE = `ifdef DFFRAM_WSIZE `DFFRAM_WSIZE `else 0 `endif; +reg [7:0] DFFRAM_USE_LATCH = `ifdef DFFRAM_USE_LATCH `DFFRAM_USE_LATCH `else 0 `endif; + +// not really parameterized but just to easily keep track of the number +// of ram_block across different modules +reg [7:0] RAM_BLOCKS = `ifdef RAM_BLOCKS `RAM_BLOCKS `else 0 `endif; + +// Clock divisor default value +reg [7:0] CLK_DIV = `ifdef CLK_DIV `CLK_DIV `else 0 `endif; + +// GPIO control default mode and enable for most I/Os +// Most I/Os set to be user bidirectional pins on power-up. +reg [7:0] MGMT_INIT = `ifdef MGMT_INIT `MGMT_INIT `else 0 `endif; +reg [7:0] OENB_INIT = `ifdef OENB_INIT `OENB_INIT `else 0 `endif; +reg [7:0] DM_INIT = `ifdef DM_INIT `DM_INIT `else 0 `endif; + +// GL + +reg GL = `ifdef GL 1 `else 0 `endif; + +endmodule \ No newline at end of file diff --git a/verilog/dv/cocotb/common.py b/verilog/dv/cocotb/common.py new file mode 100644 index 00000000..76240f7e --- /dev/null +++ b/verilog/dv/cocotb/common.py @@ -0,0 +1,79 @@ +from cocotb.handle import SimHandleBase +from cocotb.binary import BinaryValue +from enum import Enum +import cocotb +"""return the value and the size of the signal""" +def signal_value_size(path:SimHandleBase): + value = path.value + size = value.n_bits + return value, size + + +""" +Create a binaryValue object with all Z that helps when drive to drive only the bits needed +return value with all z and the size +""" +def signal_valueZ_size(path:SimHandleBase): + value = path.value + size = value.n_bits + value = BinaryValue(value = int(size) * 'z',n_bits=size) + return value, size + +def int_to_bin_list(number:bin,number_of_bits)-> list: + data = bin(number) + data = data[2:].zfill(number_of_bits)[::-1] + bits = [int(bit) for bit in data] + return bits + +def drive_hdl(path,bits,data): + hdl , n_bits = signal_value_size(path) + is_list_of_lists = all(isinstance(x, list) for x in bits) + is_list_of_tuples = all(isinstance(x, tuple) for x in bits) + if is_list_of_lists | is_list_of_tuples: + for i,bits2 in enumerate(bits): + hdl[n_bits-1-bits2[0]:n_bits-1-bits2[1]] = data[i] + else: + hdl[n_bits-1-bits[0]:n_bits-1-bits[1]] = data + path.value = hdl + cocotb.log.debug(f' [common] drive { path._path } with {hdl}') + +"""Enum for GPIO modes valus used to configured the pins""" +class GPIO_MODE(Enum): + GPIO_MODE_MGMT_STD_INPUT_NOPULL = 0x0403 + GPIO_MODE_MGMT_STD_INPUT_PULLDOWN = 0x0803 + GPIO_MODE_MGMT_STD_INPUT_PULLUP = 0x0c03 + GPIO_MODE_MGMT_STD_OUTPUT = 0x1809 + GPIO_MODE_MGMT_STD_INPUT = 0x1803 # TODO: ask if this legal the default value for first 2 bin is like that + GPIO_MODE_MGMT_STD_BIDIRECTIONAL = 0x1801 + GPIO_MODE_MGMT_STD_ANALOG = 0x000b + GPIO_MODE_USER_STD_INPUT_NOPULL = 0x0402 + GPIO_MODE_USER_STD_INPUT_PULLDOWN = 0x0802 + GPIO_MODE_USER_STD_INPUT_PULLUP = 0x0c02 + GPIO_MODE_USER_STD_OUTPUT = 0x1808 + GPIO_MODE_USER_STD_BIDIRECTIONAL = 0x1800 + GPIO_MODE_USER_STD_OUT_MONITORED = 0x1802 + GPIO_MODE_USER_STD_ANALOG = 0x000a + +class MASK_GPIO_CTRL(Enum): + MASK_GPIO_CTRL_MGMT_EN = 0 + MASK_GPIO_CTRL_OUT_DIS = 1 + MASK_GPIO_CTRL_OVERRIDE = 2 + MASK_GPIO_CTRL_INP_DIS = 3 + MASK_GPIO_CTRL_MOD_SEL = 4 + MASK_GPIO_CTRL_ANLG_EN = 5 + MASK_GPIO_CTRL_ANLG_SEL = 6 + MASK_GPIO_CTRL_ANLG_POL = 7 + MASK_GPIO_CTRL_SLOW = 8 + MASK_GPIO_CTRL_TRIP = 9 + MASK_GPIO_CTRL_DGTL_MODE = 10 + +Macros= {} + +def fill_macros(macros_hdl): + Macros['MPRJ_IO_PADS_1'] = macros_hdl.MPRJ_IO_PADS_1.value.integer + Macros['MPRJ_IO_PADS_2'] = macros_hdl.MPRJ_IO_PADS_2.value.integer + Macros['MPRJ_IO_PADS'] = macros_hdl.MPRJ_IO_PADS.value.integer + Macros['GL'] = macros_hdl.GL.value.integer + + + diff --git a/verilog/dv/cocotb/cpu.py b/verilog/dv/cocotb/cpu.py new file mode 100644 index 00000000..a6f45bf7 --- /dev/null +++ b/verilog/dv/cocotb/cpu.py @@ -0,0 +1,226 @@ +from operator import add +import random +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +import cocotb.simulator +from cocotb.handle import SimHandleBase +from cocotb.handle import Force +from cocotb_coverage.coverage import * +from cocotb.binary import BinaryValue +import enum +from cocotb.handle import ( + ConstantObject, + HierarchyArrayObject, + HierarchyObject, + ModifiableObject, + NonHierarchyIndexableObject, + SimHandle, +) + +from itertools import groupby, product + +import common +from common import GPIO_MODE +from common import MASK_GPIO_CTRL +from common import Macros + +class RiskV: + def __init__(self,dut:SimHandleBase): + self.dut = dut + self.clk = dut.clock_tb + if not Macros['GL']: + self.cpu_hdl = dut.uut.soc.core.VexRiscv + else: + self.cpu_hdl = dut.uut.soc.core + self.debug_hdl = dut.uut.mprj.debug + self.force_reset = 0 + cocotb.scheduler.add(self.force_reset_fun()) + + + """ """ + async def drive_data_with_address(self,address,data,SEL=0xF): + self.cpu_hdl.dBusWishbone_CYC.value = 1 + self.cpu_hdl.iBusWishbone_CYC.value = 0 + self.cpu_hdl.dBusWishbone_STB.value = 1 + self.cpu_hdl.dBusWishbone_WE.value = 1 + self.cpu_hdl.dBusWishbone_SEL.value = SEL + self.cpu_hdl.dBusWishbone_ADR.value = address >> 2 + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data + await RisingEdge(self.cpu_hdl.dBusWishbone_ACK) + await ClockCycles(self.clk, 1) + self.cpu_hdl.dBusWishbone_CYC.value = BinaryValue(value = 'z') + self.cpu_hdl.iBusWishbone_CYC.value = BinaryValue(value = 'z') + self.cpu_hdl.dBusWishbone_STB.value = BinaryValue(value = 'z') + self.cpu_hdl.dBusWishbone_WE.value = BinaryValue(value = 'z') + self.cpu_hdl.dBusWishbone_SEL.value = BinaryValue(value = 'zzzz') + self.cpu_hdl.dBusWishbone_ADR.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_ADR)[0] + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_DAT_MOSI)[0] + + """ """ + async def drive_data2address(self,address,data,SEL=0xF): + cocotb.log.info(f"[RiskV][drive_data2address] start driving address {hex(address)} with {hex(data)}") + # print(dir(self.cpu_hdl)) + dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value + if not Macros['GL']: + iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value + dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value + dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value + if not Macros['GL']: + dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value + else: + dBusWishbone_SEL0 = self.cpu_hdl.net2121.value + dBusWishbone_SEL1 = self.cpu_hdl.net1979.value + dBusWishbone_SEL2 = self.cpu_hdl.net848.value + dBusWishbone_SEL3 = self.cpu_hdl.net1956.value + if not Macros['GL']: + dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value + dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value + self.cpu_hdl.dBusWishbone_CYC.value = 1 + + if not Macros['GL']: + self.cpu_hdl.iBusWishbone_CYC.value = 0 + self.cpu_hdl.dBusWishbone_STB.value = 1 + self.cpu_hdl.dBusWishbone_WE.value = 1 + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_SEL.value = SEL + else: + self.cpu_hdl.net2121.value = (SEL >>0 ) &1 + self.cpu_hdl.net1979.value = (SEL >>1 ) &1 + self.cpu_hdl.net848.value = (SEL >>2 ) &1 + self.cpu_hdl.net1956.value = (SEL >>3 ) &1 + + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_ADR.value = address >> 2 + else: + address_temp = address >> 2 + for i in range(30): + self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1 + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data + else: + for i in range(32): + self.cpu_hdl._id(f'dBusWishbone_DAT_MOSI[{i}]',False).value = (data >> i) & 1 + + if not Macros['GL']: + await RisingEdge(self.cpu_hdl.dBusWishbone_ACK) + else: + # await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False))) + await RisingEdge(self.cpu_hdl._id("_07019_",False) ) + + await ClockCycles(self.clk, 1) + self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI + self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC + self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB + self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE + self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL + + await ClockCycles(self.clk, 1) + cocotb.log.info(f"[RiskV][drive_data2address] finish driving address {hex(address)} with {hex(data)}") + + """ """ + async def read_address(self,address,SEL=0xF): + cocotb.log.info(f"[RiskV][read_address] start reading address {hex(address)}") + # print(dir(self.cpu_hdl)) + dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value + if not Macros['GL']: + iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value + dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value + dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value + if not Macros['GL']: + dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value + else: + dBusWishbone_SEL0 = self.cpu_hdl.net2121.value + dBusWishbone_SEL1 = self.cpu_hdl.net1979.value + dBusWishbone_SEL2 = self.cpu_hdl.net848.value + dBusWishbone_SEL3 = self.cpu_hdl.net1956.value + if not Macros['GL']: + dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value + dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value + self.cpu_hdl.dBusWishbone_CYC.value = 1 + + if not Macros['GL']: + self.cpu_hdl.iBusWishbone_CYC.value = 0 + self.cpu_hdl.dBusWishbone_STB.value = 1 + self.cpu_hdl.dBusWishbone_WE.value = 0 + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_SEL.value = SEL + else: + self.cpu_hdl.net2121.value = (SEL >>0 ) &1 + self.cpu_hdl.net1979.value = (SEL >>1 ) &1 + self.cpu_hdl.net848.value = (SEL >>2 ) &1 + self.cpu_hdl.net1956.value = (SEL >>3 ) &1 + + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_ADR.value = address >> 2 + else: + address_temp = address >> 2 + for i in range(30): + self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1 + + + if not Macros['GL']: + await RisingEdge(self.cpu_hdl.dBusWishbone_ACK) + else: + # await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False))) + await RisingEdge(self.cpu_hdl._id("_07019_",False) ) + + await ClockCycles(self.clk, 1) + self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI + self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC + self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB + self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE + self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL + data = self.cpu_hdl.dBusWishbone_DAT_MISO.value + await ClockCycles(self.clk, 1) + cocotb.log.info(f"[RiskV][read_address] finish reading address {hex(address)} data = {data}") + + # return data + return int(str(bin(data.integer)[2:]).zfill(32),2) + # return int(str(bin(data.integer)[2:]).zfill(32)[::-1],2) + + + def read_debug_reg1(self): + return self.debug_hdl.debug_reg_1.value.integer + def read_debug_reg2(self): + return self.debug_hdl.debug_reg_2.value.integer + + async def force_reset_fun(self): + first_time_force = True + first_time_release = True + while True: + if self.force_reset: + if first_time_force: + cocotb.log.info(f"[RiskV][force_reset_fun] Force CPU reset") + first_time_force = False + first_time_release = True + self.cpu_hdl.reset.value =1 + if not Macros['GL']: + common.drive_hdl(self.cpu_hdl.reset,(0,0),1) + else: + common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),1) + else: + if first_time_release: + first_time_force = True + first_time_release = False + + if not Macros['GL']: + common.drive_hdl(self.cpu_hdl.reset,(0,0),0) + else: + common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),0) + cocotb.log.info(f"[RiskV][force_reset_fun] release CPU reset") + + await ClockCycles(self.clk, 1) + def cpu_force_reset(self): + self.force_reset = True + + def cpu_release_reset(self): + self.force_reset = False + \ No newline at end of file diff --git a/verilog/dv/cocotb/defsParser.py b/verilog/dv/cocotb/defsParser.py new file mode 100644 index 00000000..6a0f9f4b --- /dev/null +++ b/verilog/dv/cocotb/defsParser.py @@ -0,0 +1,87 @@ +import re +import sys +from tokenize import group +from unittest.util import _MIN_COMMON_LEN +import string +import cocotb +import os +class Regs: + def __init__(self): + pass + + def get_addr(self,reg): + search1 = self.get_add_defs(reg) + # if all(c in string.hexdigits for c in search1[2:]): + return int(search1,16) + # return hex(self.get_hexa(search1)) + + + """get address from defs.h""" + def get_add_defs(self,reg): + pattern = re.compile(rf'#define {reg}\s*\(\*\(volatile uint32_t\*\)\s*(.*)\s*\)') + with open(f'{os.getenv("FIRMWARE_PATH")}/defs.h') as f: + for line in f: + m= re.search(pattern,line) + if m: + break + if m: + if not all(c in string.hexdigits for c in m.group(1)): + return hex(self.get_hexa(m.group(1))) + else: + return m.group(1) + else: + cocotb.log.info(f" [defsParser] can't find {reg} inside defs") + sys.exit() + + """get address from defs.h""" + def get_add_csr(self,reg): + pattern1 = re.compile(rf'#define {reg}\s*\(\*\(volatile uint32_t\*\)\s*(.*)\s*\)') + pattern2 = re.compile(rf'#define {reg}\s*(.*)') + m = False + with open(f'{os.getenv("FIRMWARE_PATH")}/../generated/csr.h') as f: + for line in f: + m1= re.search(pattern1,line) + m2= re.search(pattern2,line) + if m1: + m = m1 + break + if m2: + m=m2 + break + if m: + matched_str= m.group(1) + if matched_str[-1] == "L" and matched_str[-2].isnumeric: + matched_str = matched_str[:-1] + if not all(c in string.hexdigits for c in matched_str[2:]): + matched_str= hex(self.get_hexa(matched_str)) + + return matched_str + else: + cocotb.log.info(f" [defsParser] can't find {reg} inside csr") + sys.exit() + + + def get_hexa(self,s:string): + pattern2 = re.compile(r'\((.*)\s*\+\s*(.*)\)') + search_match = re.search(pattern2,s) + if search_match : + matches = [search_match.group(1),search_match.group(2)] + else: + matches = [s] + nothex = 1 + while nothex: + nothex = 0 + for i,match in enumerate(matches): + if not all(c in string.hexdigits for c in match[2:-1]): + matches[i]=self.get_add_csr(match) + nothex = 0 + else: + if match[-1] == "L" and match[-2].isnumeric: + matches[i]=matches[i][:-1] + + if len(matches) ==2: + return int(matches[0],16) + int(matches[1],16) + else: + return int(matches[0],16) + + diff --git a/verilog/dv/cocotb/hex_files/IRQ_external.hex b/verilog/dv/cocotb/hex_files/IRQ_external.hex new file mode 100755 index 00000000..b183a3ce --- /dev/null +++ b/verilog/dv/cocotb/hex_files/IRQ_external.hex @@ -0,0 +1,70 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 38 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 80 17 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 +23 26 A4 FE 83 27 C4 FE 63 86 07 00 73 60 04 30 +6F 00 80 00 73 70 04 30 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 81 00 +13 04 01 02 F3 27 00 BC 23 26 F4 FE 83 27 C4 FE +13 85 07 00 03 24 C1 01 13 01 01 02 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00 +23 2C 81 00 13 04 01 02 B7 47 00 F0 93 87 07 80 +13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF +23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 +B7 07 00 26 93 87 07 04 13 07 30 40 23 A0 E7 00 +B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00 +B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE +13 05 00 00 EF F0 DF F6 13 05 10 00 EF F0 9F F0 +EF F0 9F F3 93 07 05 00 93 E7 07 04 13 85 07 00 +EF F0 1F F5 B7 97 00 F0 93 87 47 81 13 07 10 00 +23 A0 E7 00 B7 07 10 30 93 87 C7 FF 13 07 A0 0A +23 A0 E7 00 23 10 00 00 A3 07 04 FE 93 07 80 02 +23 20 F4 FE 23 24 04 FE 6F 00 80 03 03 57 00 00 +93 07 10 00 63 10 F7 02 B7 07 10 30 93 87 87 FF +13 07 B0 01 23 A0 E7 00 93 07 10 00 A3 07 F4 FE +6F 00 C0 01 83 27 84 FE 93 87 17 00 23 24 F4 FE +03 27 84 FE 83 27 04 FE E3 42 F7 FC 83 47 F4 FE +93 C7 17 00 93 F7 F7 0F 63 8A 07 00 B7 07 10 30 +93 87 87 FF 13 07 E0 01 23 A0 E7 00 B7 07 10 30 +93 87 C7 FF 13 07 B0 0B 23 A0 E7 00 23 10 00 00 +A3 07 04 FE 23 22 04 FE 6F 00 80 03 03 57 00 00 +93 07 10 00 63 10 F7 02 B7 07 10 30 93 87 87 FF +13 07 E0 02 23 A0 E7 00 93 07 10 00 A3 07 F4 FE +6F 00 C0 01 83 27 44 FE 93 87 17 00 23 22 F4 FE +03 27 44 FE 83 27 04 FE E3 42 F7 FC 83 47 F4 FE +93 C7 17 00 93 F7 F7 0F 63 8A 07 00 B7 07 10 30 +93 87 87 FF 13 07 B0 02 23 A0 E7 00 B7 07 10 30 +93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/IRQ_timer.hex b/verilog/dv/cocotb/hex_files/IRQ_timer.hex new file mode 100755 index 00000000..52f883e1 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/IRQ_timer.hex @@ -0,0 +1,71 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 38 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 80 17 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 +23 26 A4 FE 83 27 C4 FE 63 86 07 00 73 60 04 30 +6F 00 80 00 73 70 04 30 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 81 00 +13 04 01 02 F3 27 00 BC 23 26 F4 FE 83 27 C4 FE +13 85 07 00 03 24 C1 01 13 01 01 02 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00 +23 2C 81 00 13 04 01 02 B7 47 00 F0 93 87 07 80 +13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF +23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 +13 05 00 00 EF F0 DF F9 13 05 10 00 EF F0 9F F3 +EF F0 9F F6 93 07 05 00 93 E7 17 00 13 85 07 00 +EF F0 1F F8 B7 07 10 30 93 87 C7 FF 13 07 A0 0A +23 A0 E7 00 23 10 00 00 B7 57 00 F0 93 87 87 00 +23 A0 07 00 B7 57 00 F0 13 07 E0 01 23 A0 E7 00 +B7 57 00 F0 93 87 C7 01 13 07 10 00 23 A0 E7 00 +B7 57 00 F0 93 87 87 00 13 07 10 00 23 A0 E7 00 +A3 07 04 FE 93 07 80 02 23 20 F4 FE 23 24 04 FE +6F 00 80 03 03 57 00 00 93 07 10 00 63 10 F7 02 +B7 07 10 30 93 87 87 FF 13 07 B0 01 23 A0 E7 00 +93 07 10 00 A3 07 F4 FE 6F 00 C0 01 83 27 84 FE +93 87 17 00 23 24 F4 FE 03 27 84 FE 83 27 04 FE +E3 42 F7 FC 83 47 F4 FE 93 C7 17 00 93 F7 F7 0F +63 8A 07 00 B7 07 10 30 93 87 87 FF 13 07 E0 01 +23 A0 E7 00 23 10 00 00 B7 07 10 30 93 87 C7 FF +13 07 B0 0B 23 A0 E7 00 B7 57 00 F0 93 87 87 00 +23 A0 07 00 23 10 00 00 A3 07 04 FE 23 22 04 FE +6F 00 80 03 03 57 00 00 93 07 10 00 63 10 F7 02 +B7 07 10 30 93 87 87 FF 13 07 E0 02 23 A0 E7 00 +93 07 10 00 A3 07 F4 FE 6F 00 C0 01 83 27 44 FE +93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE +E3 42 F7 FC 83 47 F4 FE 93 C7 17 00 93 F7 F7 0F +63 8A 07 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 +23 A0 E7 00 B7 07 10 30 93 87 C7 FF 13 07 F0 0F +23 A0 E7 00 13 00 00 00 83 20 C1 01 03 24 81 01 +13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/IRQ_uart.hex b/verilog/dv/cocotb/hex_files/IRQ_uart.hex new file mode 100755 index 00000000..9792671f --- /dev/null +++ b/verilog/dv/cocotb/hex_files/IRQ_uart.hex @@ -0,0 +1,87 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 47 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 23 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 +23 26 A4 FE 83 27 C4 FE 63 86 07 00 73 60 04 30 +6F 00 80 00 73 70 04 30 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 81 00 +13 04 01 02 F3 27 00 BC 23 26 F4 FE 83 27 C4 FE +13 85 07 00 03 24 C1 01 13 01 01 02 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00 +23 2C 81 00 13 04 01 02 93 07 05 00 A3 07 F4 FE +03 47 F4 FE 93 07 A0 00 63 16 F7 00 13 05 D0 00 +EF F0 9F FD 13 00 00 00 B7 67 00 F0 93 87 47 80 +03 A7 07 00 93 07 10 00 E3 08 F7 FE B7 67 00 F0 +93 87 07 80 03 47 F4 FE 23 A0 E7 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 +23 26 A4 FE 6F 00 C0 01 83 27 C4 FE 13 87 17 00 +23 26 E4 FE 83 C7 07 00 13 85 07 00 EF F0 DF F6 +83 27 C4 FE 83 C7 07 00 E3 90 07 FE 13 00 00 00 +13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 B7 47 00 F0 93 87 07 80 13 07 10 00 +23 A0 E7 00 B7 07 10 30 93 87 87 FF 23 A0 07 00 +B7 07 10 30 93 87 C7 FF 23 A0 07 00 B7 07 00 26 +93 87 C7 03 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 87 03 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 13 07 10 00 23 A0 E7 00 +13 00 00 00 B7 07 00 26 03 A7 07 00 93 07 10 00 +E3 0A F7 FE B7 67 00 F0 13 07 10 00 23 A0 E7 00 +B7 67 00 F0 93 87 47 81 13 07 10 00 23 A0 E7 00 +13 05 00 00 EF F0 DF E7 13 05 10 00 EF F0 9F E1 +EF F0 9F E4 93 07 05 00 93 E7 27 00 13 85 07 00 +EF F0 1F E6 23 10 00 00 B7 07 10 30 93 87 C7 FF +13 07 A0 0A 23 A0 E7 00 B7 07 00 10 13 85 07 54 +EF F0 1F ED A3 07 04 FE 93 07 40 06 23 20 F4 FE +23 24 04 FE 6F 00 80 03 03 57 00 00 93 07 10 00 +63 10 F7 02 B7 07 10 30 93 87 87 FF 13 07 B0 01 +23 A0 E7 00 93 07 10 00 A3 07 F4 FE 6F 00 C0 01 +83 27 84 FE 93 87 17 00 23 24 F4 FE 03 27 84 FE +83 27 04 FE E3 42 F7 FC 83 47 F4 FE 93 C7 17 00 +93 F7 F7 0F 63 8A 07 00 B7 07 10 30 93 87 87 FF +13 07 E0 01 23 A0 E7 00 B7 07 10 30 93 87 C7 FF +13 07 B0 0B 23 A0 E7 00 23 10 00 00 A3 07 04 FE +23 22 04 FE 6F 00 80 03 03 57 00 00 93 07 10 00 +63 10 F7 02 B7 07 10 30 93 87 87 FF 13 07 E0 02 +23 A0 E7 00 93 07 10 00 A3 07 F4 FE 6F 00 C0 01 +83 27 44 FE 93 87 17 00 23 22 F4 FE 03 27 44 FE +83 27 04 FE E3 42 F7 FC 83 47 F4 FE 93 C7 17 00 +93 F7 F7 0F 63 8A 07 00 B7 07 10 30 93 87 87 FF +13 07 B0 02 23 A0 E7 00 B7 07 10 30 93 87 C7 FF +13 07 F0 0F 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 +@0000053C +00 00 00 00 4D 00 00 00 00 00 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all.hex new file mode 100755 index 00000000..ab7f2105 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_cpu_all.hex @@ -0,0 +1,238 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 +13 06 C6 DF 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 90 07 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 06 +23 A0 E7 00 B7 07 00 26 13 07 60 07 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 60 01 +23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +B7 07 00 26 13 07 60 04 23 A0 E7 00 B7 07 00 26 +13 07 60 05 23 A0 E7 00 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 B7 07 00 26 13 07 60 02 23 A0 E7 00 +B7 07 00 26 13 07 60 03 23 A0 E7 00 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 00 +23 A0 E7 00 B7 07 00 26 13 07 E0 00 23 A0 E7 00 +B7 07 00 26 13 07 60 00 23 A0 E7 00 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 00 +23 A0 E7 00 B7 07 00 26 13 07 40 00 23 A0 E7 00 +B7 07 00 26 13 07 60 00 23 A0 E7 00 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC +83 27 C4 FD 23 24 F4 FE EF F0 DF EF EF F0 9F EF +23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 +EF F0 5F EE 83 27 84 FE 93 87 F7 FF 23 24 F4 FE +6F 00 80 00 EF F0 DF E9 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC +EF F0 1F E8 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 5F EB EF F0 1F EB 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF E9 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 1F E2 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 80 00 E3 F6 E7 FC EF F0 5F E0 +13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03 +67 80 00 00 13 01 01 FD 23 26 11 02 23 24 81 02 +13 04 01 03 23 2E A4 FC 83 27 C4 FD 23 24 F4 FE +EF F0 5F E0 EF F0 1F E0 23 26 04 FE 6F 00 00 03 +83 27 84 FE 63 8C 07 00 EF F0 DF DE 83 27 84 FE +93 87 F7 FF 23 24 F4 FE 6F 00 80 00 EF F0 5F DA +83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE +93 07 60 00 E3 F6 E7 FC EF F0 DF DB EF F0 5F D8 +EF F0 1F D8 EF F0 1F DB 13 00 00 00 83 20 C1 02 +03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC +83 27 C4 FD 23 24 F4 FE EF F0 5F D1 EF F0 1F D1 +23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 +EF F0 DF CF 83 27 84 FE 93 87 F7 FF 23 24 F4 FE +6F 00 80 00 EF F0 DF D1 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 60 00 E3 F6 E7 FC +EF F0 DF CC EF F0 DF CF EF F0 9F CF EF F0 1F CC +13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03 +67 80 00 00 13 01 01 FD 23 26 11 02 23 24 81 02 +13 04 01 03 23 2E A4 FC 83 27 C4 FD 23 24 F4 FE +EF F0 DF C8 EF F0 9F C8 23 26 04 FE 6F 00 00 03 +83 27 84 FE 63 8C 07 00 EF F0 5F C7 83 27 84 FE +93 87 F7 FF 23 24 F4 FE 6F 00 80 00 EF F0 5F C9 +83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE +93 07 60 00 E3 F6 E7 FC EF F0 DF CA EF F0 5F C7 +EF F0 9F CD EF F0 9F C3 13 00 00 00 83 20 C1 02 +03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC +83 27 C4 FD 23 24 F4 FE EF F0 5F C0 EF F0 1F C0 +23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 +EF F0 DF BE 83 27 84 FE 93 87 F7 FF 23 24 F4 FE +6F 00 80 00 EF F0 DF C0 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 60 00 E3 F6 E7 FC +EF F0 9F C5 EF F0 DF BE EF F0 DF C1 EF F0 1F BB +13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03 +67 80 00 00 13 01 01 FD 23 26 11 02 23 24 81 02 +13 04 01 03 23 2E A4 FC 83 27 C4 FD 23 24 F4 FE +EF F0 DF B7 EF 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03 27 C4 FE +93 07 60 00 E3 F6 E7 FC EF F0 1F AC EF F0 5F A5 +EF F0 DF A1 EF F0 9F A1 13 00 00 00 83 20 C1 02 +03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FF +23 26 11 00 23 24 81 00 13 04 01 01 EF F0 1F 9F +EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 EF F0 5F A1 +EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 EF F0 5F A0 +EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C EF F0 1F 9C +EF F0 DF A8 13 00 00 00 83 20 C1 00 03 24 81 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 EF F0 5F 99 EF F0 9F 9F +EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B EF F0 5F 9B +EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A EF F0 DF A0 +EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 EF F0 1F A3 +B7 07 00 26 93 87 87 0B 37 27 00 00 13 07 97 80 +23 A0 E7 00 13 00 00 00 83 20 C1 00 03 24 81 00 +13 01 01 01 67 80 00 00 13 01 01 FE 23 2E 11 00 +23 2C 81 00 13 04 01 02 B7 47 00 F0 93 87 07 80 +13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF +23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 +B7 07 00 26 93 87 87 0B 37 27 00 00 13 07 97 80 +23 A0 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07 01 03 27 C4 FE 23 A0 E7 00 +B7 07 10 30 93 87 C7 FF 93 06 50 02 03 27 84 FE +33 87 E6 40 23 A0 E7 00 B7 07 00 26 93 87 07 01 +23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 +83 27 C4 FE 93 D7 17 00 23 26 F4 FE 83 27 C4 FE +93 E7 07 02 23 26 F4 FE 83 27 84 FE 93 87 17 00 +23 24 F4 FE 03 27 84 FE 93 07 40 00 E3 FA E7 F8 +B7 07 00 80 23 26 F4 FE 23 24 04 FE 6F 00 80 08 +B7 07 00 26 93 87 07 01 13 07 F0 03 23 A0 E7 00 +B7 07 00 26 93 87 C7 00 03 27 C4 FE 23 A0 E7 00 +B7 07 10 30 93 87 C7 FF 93 06 00 02 03 27 84 FE +33 87 E6 40 23 A0 E7 00 B7 07 00 26 93 87 07 01 +23 A0 07 00 B7 07 00 26 93 87 C7 00 23 A0 07 00 +B7 07 10 30 93 87 C7 FF 23 A0 07 00 83 27 C4 FE +93 D7 17 00 23 26 F4 FE 03 27 C4 FE B7 07 00 80 +B3 67 F7 00 23 26 F4 FE 83 27 84 FE 93 87 17 00 +23 24 F4 FE 03 27 84 FE 93 07 F0 01 E3 FA E7 F6 +13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 +67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_0011.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_0011.hex new file mode 100755 index 00000000..6968b98d --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_0011.hex @@ -0,0 +1,212 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 +13 06 C6 C5 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 D0 07 6F 00 00 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E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 47 02 37 27 00 00 13 07 97 80 23 A0 E7 00 +23 26 04 FE 6F 00 00 02 EF F0 CF E1 EF F0 8F E1 +EF F0 0F DE EF F0 CF DD 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 60 0F E3 DE E7 FC +B7 07 10 30 93 87 87 FF 13 07 F0 0F 23 A0 E7 00 +13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 +67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_01.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_01.hex new file mode 100755 index 00000000..39ae0dc8 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_01.hex @@ -0,0 +1,211 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 +13 06 46 C5 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 +23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 +13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 +B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 +23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 +23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 +23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF +EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 +E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 +03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC +83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB +23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 +EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE +6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC +EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB +EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 +EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF +EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA +EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 +EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 +EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 +EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF +EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 +EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC +EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 +EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 +EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 +EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C +EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 +EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B +EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A +EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 +EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 +13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 B7 47 00 F0 +93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 +93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF +23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 0B 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 09 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 08 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 08 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 08 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 08 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 07 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 07 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 07 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 06 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 06 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 06 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 06 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 05 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 05 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 05 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 04 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 47 02 37 27 00 00 13 07 97 80 23 A0 E7 00 +23 26 04 FE 6F 00 80 01 EF F0 CF E1 EF F0 4F DE +83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE +93 07 60 0F E3 D2 E7 FE B7 07 10 30 93 87 87 FF +13 07 F0 0F 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_10.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_10.hex new file mode 100755 index 00000000..8b665aff --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_10.hex @@ -0,0 +1,211 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 +13 06 46 C5 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 +23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 +13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 +B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 +23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 +23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 +23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF +EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 +E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 +03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC +83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB +23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 +EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE +6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC +EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB +EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 +EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF +EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA +EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 +EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 +EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 +EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF +EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 +EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC 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30 93 87 87 FF 13 07 F0 0F 23 A0 E7 00 +13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 +67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_i.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_i.hex new file mode 100755 index 00000000..82d4bc13 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_i.hex @@ -0,0 +1,227 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 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05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 +23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 +13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 +B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 +23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 +23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 +23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF +EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 +E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 +03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC +83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB +23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 +EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE +6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC +EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB +EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 +EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 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F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC +EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 +EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 +EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 +EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C +EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 +EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B +EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A +EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 +EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 +13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 11 00 23 24 81 00 13 04 01 01 B7 47 00 F0 +93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 +93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF +23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 0B 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 0A 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 09 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 08 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 08 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 08 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 08 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 07 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 07 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 07 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 06 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 06 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 06 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 06 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 05 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 05 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 05 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 04 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 47 02 37 27 00 00 13 07 37 80 23 A0 E7 00 +13 05 00 00 EF F0 5F A5 13 05 00 00 EF F0 DF A4 +13 05 00 00 EF F0 5F A4 13 05 00 00 EF F0 DF A3 +13 05 00 00 EF F0 5F A3 13 05 00 00 EF F0 DF A2 +13 05 00 00 EF F0 5F A2 13 05 00 00 EF F0 DF A1 +13 05 00 00 EF F0 5F A1 13 05 00 00 EF F0 DF A0 +13 05 00 00 EF F0 5F A0 13 05 00 00 EF F0 DF 9F +13 05 00 00 EF F0 5F 9F 13 05 00 00 EF F0 DF 9E +13 05 00 00 EF F0 5F 9E 13 05 00 00 EF F0 DF 9D +13 05 00 00 EF F0 5F 9D 13 05 00 00 EF F0 DF 9C +13 05 00 00 EF F0 5F 9C EF F0 8F E2 B7 07 10 30 +93 87 87 FF 13 07 A0 0A 23 A0 E7 00 13 00 00 00 +B7 07 00 26 93 87 C7 00 03 A7 07 00 B7 07 67 8F +93 87 B7 D7 E3 16 F7 FE B7 07 10 30 93 87 87 FF +13 07 B0 0B 23 A0 E7 00 13 00 00 00 B7 07 00 26 +93 87 C7 00 03 A7 07 00 B7 97 A8 FF 93 87 A7 C5 +E3 16 F7 FE B7 07 10 30 93 87 87 FF 13 07 C0 0C +23 A0 E7 00 13 00 00 00 B7 07 00 26 93 87 C7 00 +03 A7 07 00 B7 67 53 C9 93 87 67 34 E3 16 F7 FE +B7 07 10 30 93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 +13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01 +67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_o.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_o.hex new file mode 100755 index 00000000..317c41ff --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_o.hex @@ -0,0 +1,238 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 +13 06 46 E0 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 +23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 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+63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 +E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 +03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC +83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB +23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 +EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE +6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC +EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB +EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 +EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF +EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA +EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 +EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 +EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 +EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF +EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 +EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC +EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 +EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 +EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 +EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C +EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 +EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B +EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A +EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 +EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 +13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 B7 47 00 F0 +93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 +93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF +23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 0B 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 09 37 27 00 00 13 07 97 80 23 A0 E7 00 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C7 04 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 04 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 47 02 37 27 00 00 13 07 97 80 23 A0 E7 00 +13 05 00 00 EF F0 DF 8B 13 05 00 00 EF F0 5F 8B +13 05 00 00 EF F0 DF 8A 13 05 00 00 EF F0 5F 8A +13 05 00 00 EF F0 DF 89 13 05 00 00 EF F0 5F 89 +13 05 00 00 EF F0 DF 88 13 05 00 00 EF F0 5F 88 +13 05 00 00 EF F0 DF 87 13 05 00 00 EF F0 5F 87 +13 05 00 00 EF F0 DF 86 13 05 00 00 EF F0 5F 86 +13 05 00 00 EF F0 DF 85 13 05 00 00 EF F0 5F 85 +13 05 00 00 EF F0 DF 84 13 05 00 00 EF F0 DF 8C +13 05 00 00 EF F0 DF 83 13 05 00 00 EF F0 5F 83 +13 05 00 00 EF F0 DF 82 EF F0 8F E2 B7 07 10 30 +93 87 87 FF 13 07 F0 0F 23 A0 E7 00 B7 07 00 26 +93 87 C7 00 23 A0 07 00 B7 07 00 26 93 87 07 01 +23 A0 07 00 93 07 00 02 23 26 F4 FE 23 24 04 FE +6F 00 80 06 B7 07 00 26 93 87 07 01 03 27 C4 FE +23 A0 E7 00 B7 07 10 30 93 87 C7 FF 93 06 50 02 +03 27 84 FE 33 87 E6 40 23 A0 E7 00 B7 07 00 26 +93 87 07 01 23 A0 07 00 B7 07 10 30 93 87 C7 FF +23 A0 07 00 83 27 C4 FE 93 D7 17 00 23 26 F4 FE +83 27 C4 FE 93 E7 07 02 23 26 F4 FE 83 27 84 FE +93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 40 00 +E3 FA E7 F8 B7 07 00 80 23 26 F4 FE 23 24 04 FE +6F 00 80 08 B7 07 00 26 93 87 07 01 13 07 F0 03 +23 A0 E7 00 B7 07 00 26 93 87 C7 00 03 27 C4 FE +23 A0 E7 00 B7 07 10 30 93 87 C7 FF 93 06 00 02 +03 27 84 FE 33 87 E6 40 23 A0 E7 00 B7 07 00 26 +93 87 07 01 23 A0 07 00 B7 07 00 26 93 87 C7 00 +23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 +83 27 C4 FE 93 D7 17 00 23 26 F4 FE 03 27 C4 FE +B7 07 00 80 B3 67 F7 00 23 26 F4 FE 83 27 84 FE +93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 F0 01 +E3 FA E7 F6 13 00 00 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu.hex new file mode 100755 index 00000000..a9528ab2 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_no_cpu.hex @@ -0,0 +1,47 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 20 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all.hex new file mode 100755 index 00000000..a9528ab2 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all.hex @@ -0,0 +1,47 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 20 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_i.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_i.hex new file mode 100755 index 00000000..100c12da --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_i.hex @@ -0,0 +1,47 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_o.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_o.hex new file mode 100755 index 00000000..100c12da --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_o.hex @@ -0,0 +1,47 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 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C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_i.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_i.hex new file mode 100755 index 00000000..a9528ab2 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_i.hex @@ -0,0 +1,47 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 20 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_spi.hex b/verilog/dv/cocotb/hex_files/bitbang_spi.hex new file mode 100755 index 00000000..100c12da --- /dev/null +++ b/verilog/dv/cocotb/hex_files/bitbang_spi.hex @@ -0,0 +1,47 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/cpu_drive.hex b/verilog/dv/cocotb/hex_files/cpu_drive.hex new file mode 100755 index 00000000..a6ad7e1e --- /dev/null +++ b/verilog/dv/cocotb/hex_files/cpu_drive.hex @@ -0,0 +1,54 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 27 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 B7 47 00 F0 93 87 07 80 +13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF +37 07 01 00 13 07 07 FF 23 A0 E7 00 B7 37 00 F0 +93 87 87 01 37 07 19 11 13 07 F7 FF 23 A0 E7 00 +13 00 00 00 B7 07 10 30 93 87 C7 FF 03 A7 07 00 +B7 E7 00 00 93 87 07 FF E3 16 F7 FE B7 07 10 30 +93 87 87 FF 37 E7 00 00 13 07 07 DD 23 A0 E7 00 +93 07 00 00 13 85 07 00 03 24 C1 00 13 01 01 01 +67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/cpu_stress.hex b/verilog/dv/cocotb/hex_files/cpu_stress.hex new file mode 100755 index 00000000..fe38edc5 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/cpu_stress.hex @@ -0,0 +1,168 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 03 17 16 00 00 +13 06 C6 95 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 03 +93 05 80 03 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 80 61 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 18 E0 02 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +23 2A 91 00 13 04 01 02 23 26 A4 FE 83 27 C4 FE +63 96 07 00 93 07 00 00 6F 00 40 04 03 27 C4 FE +93 07 10 00 63 16 F7 00 93 07 10 00 6F 00 00 03 +83 27 C4 FE 93 87 F7 FF 13 85 07 00 EF F0 9F FB +93 04 05 00 83 27 C4 FE 93 87 E7 FF 13 85 07 00 +EF F0 5F FA 93 07 05 00 B3 87 F4 00 13 85 07 00 +83 20 C1 01 03 24 81 01 83 24 41 01 13 01 01 02 +67 80 00 00 13 01 01 FD 23 26 11 02 23 24 81 02 +13 04 01 03 23 2E A4 FC 23 2C B4 FC 03 27 84 FD +93 07 10 00 63 D4 E7 0C 83 27 84 FD 93 87 F7 FF +93 85 07 00 03 25 C4 FD EF F0 DF FC 03 27 84 FD +B7 07 00 40 93 87 F7 FF B3 07 F7 00 93 97 27 00 +03 27 C4 FD B3 07 F7 00 83 A7 07 00 23 24 F4 FE +83 27 84 FD 93 87 E7 FF 23 26 F4 FE 6F 00 C0 03 +83 27 C4 FE 93 97 27 00 03 27 C4 FD 33 07 F7 00 +83 27 C4 FE 93 87 17 00 93 97 27 00 83 26 C4 FD +B3 87 F6 00 03 27 07 00 23 A0 E7 00 83 27 C4 FE +93 87 F7 FF 23 26 F4 FE 83 27 C4 FE 63 C0 07 02 +83 27 C4 FE 93 97 27 00 03 27 C4 FD B3 07 F7 00 +83 A7 07 00 03 27 84 FE E3 44 F7 FA 83 27 C4 FE +93 87 17 00 93 97 27 00 03 27 C4 FD B3 07 F7 00 +03 27 84 FE 23 A0 E7 00 6F 00 80 00 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 23 2C B4 FC 23 2A C4 FC 03 27 84 FD +83 27 44 FD 63 5C F7 18 83 27 84 FD 23 22 F4 FE +83 27 84 FD 23 26 F4 FE 83 27 44 FD 23 24 F4 FE +6F 00 80 0E 83 27 C4 FE 93 87 17 00 23 26 F4 FE +83 27 C4 FE 93 97 27 00 03 27 C4 FD B3 07 F7 00 +03 A7 07 00 83 27 44 FE 93 97 27 00 83 26 C4 FD +B3 87 F6 00 83 A7 07 00 63 C0 E7 02 03 27 C4 FE +83 27 44 FD E3 40 F7 FC 6F 00 00 01 83 27 84 FE +93 87 F7 FF 23 24 F4 FE 83 27 84 FE 93 97 27 00 +03 27 C4 FD B3 07 F7 00 03 A7 07 00 83 27 44 FE +93 97 27 00 83 26 C4 FD B3 87 F6 00 83 A7 07 00 +E3 C6 E7 FC 03 27 C4 FE 83 27 84 FE 63 5E F7 04 +83 27 C4 FE 93 97 27 00 03 27 C4 FD B3 07 F7 00 +83 A7 07 00 23 20 F4 FE 83 27 84 FE 93 97 27 00 +03 27 C4 FD 33 07 F7 00 83 27 C4 FE 93 97 27 00 +83 26 C4 FD B3 87 F6 00 03 27 07 00 23 A0 E7 00 +83 27 84 FE 93 97 27 00 03 27 C4 FD B3 07 F7 00 +03 27 04 FE 23 A0 E7 00 03 27 C4 FE 83 27 84 FE +E3 40 F7 F2 83 27 44 FE 93 97 27 00 03 27 C4 FD +B3 07 F7 00 83 A7 07 00 23 20 F4 FE 83 27 84 FE +93 97 27 00 03 27 C4 FD 33 07 F7 00 83 27 44 FE +93 97 27 00 83 26 C4 FD B3 87 F6 00 03 27 07 00 +23 A0 E7 00 83 27 84 FE 93 97 27 00 03 27 C4 FD +B3 07 F7 00 03 27 04 FE 23 A0 E7 00 83 27 84 FE +93 87 F7 FF 13 86 07 00 83 25 84 FD 03 25 C4 FD +EF F0 1F E6 83 27 84 FE 93 87 17 00 03 26 44 FD +93 85 07 00 03 25 C4 FD EF F0 9F E4 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +23 24 B4 FE 23 22 C4 FE 23 20 D4 FE 03 27 C4 FE +83 27 84 FE 33 07 F7 00 83 27 44 FE 33 07 F7 00 +83 27 04 FE B3 07 F7 00 13 85 07 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 26 A4 FE 23 24 B4 FE +23 22 C4 FE 23 20 D4 FE 23 2E E4 FC 83 26 04 FE +03 26 44 FE 83 25 84 FE 03 25 C4 FE EF F0 5F F8 +13 07 05 00 83 27 C4 FD B3 07 F7 00 13 85 07 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 26 A4 FE 23 24 B4 FE 23 22 C4 FE 23 20 D4 FE +23 2E E4 FC 23 2C F4 FC 03 27 C4 FD 83 26 04 FE +03 26 44 FE 83 25 84 FE 03 25 C4 FE EF F0 DF F6 +13 07 05 00 83 27 84 FD B3 07 F7 00 13 85 07 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 26 A4 FE 23 24 B4 FE 23 22 C4 FE 23 20 D4 FE +23 2E E4 FC 23 2C F4 FC 23 2A 04 FD 83 27 84 FD +03 27 C4 FD 83 26 04 FE 03 26 44 FE 83 25 84 FE +03 25 C4 FE EF F0 DF F5 13 07 05 00 83 27 44 FD +B3 07 F7 00 13 85 07 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 26 A4 FE 23 24 B4 FE +23 22 C4 FE 23 20 D4 FE 23 2E E4 FC 23 2C F4 FC +23 2A 04 FD 23 28 14 FD 03 28 44 FD 83 27 84 FD +03 27 C4 FD 83 26 04 FE 03 26 44 FE 83 25 84 FE +03 25 C4 FE EF F0 DF F4 13 07 05 00 83 27 04 FD +B3 07 F7 00 13 85 07 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FA 23 2E 11 04 +23 2C 81 04 13 04 01 06 B7 47 00 F0 93 87 07 80 +13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF +23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 +13 05 A0 00 EF F0 1F AA 23 2A A4 FC 03 27 44 FD +93 07 70 03 63 0C F7 00 B7 07 10 30 93 87 87 FF +13 07 E0 01 23 A0 E7 00 6F 00 40 01 B7 07 10 30 +93 87 87 FF 13 07 B0 01 23 A0 E7 00 23 26 04 FE +23 24 04 FE 6F 00 80 05 13 07 00 00 83 27 84 FE +93 97 27 00 B3 07 F7 00 03 A7 07 00 83 27 84 FE +93 97 27 00 93 87 07 FF B3 87 87 00 23 AC E7 FA +13 07 00 00 83 27 84 FE 93 97 27 00 B3 07 F7 00 +83 A7 07 00 03 27 C4 FE B3 07 F7 00 23 26 F4 FE +83 27 84 FE 93 87 17 00 23 24 F4 FE 03 27 84 FE +93 07 90 00 E3 D2 E7 FA 03 27 C4 FE 93 07 10 19 +63 0C F7 00 B7 07 10 30 93 87 87 FF 13 07 E0 02 +23 A0 E7 00 6F 00 40 01 B7 07 10 30 93 87 87 FF +13 07 B0 02 23 A0 E7 00 93 07 84 FA 93 05 A0 00 +13 85 07 00 EF F0 1F A4 23 22 04 FE 23 20 04 FE +6F 00 00 03 83 27 04 FE 93 97 27 00 93 87 07 FF +B3 87 87 00 83 A7 87 FB 03 27 44 FE B3 07 F7 00 +23 22 F4 FE 83 27 04 FE 93 87 17 00 23 20 F4 FE +03 27 04 FE 93 07 90 00 E3 D6 E7 FC 03 27 C4 FE +83 27 44 FE 63 0C F7 00 B7 07 10 30 93 87 87 FF +13 07 E0 03 23 A0 E7 00 6F 00 40 01 B7 07 10 30 +93 87 87 FF 13 07 B0 03 23 A0 E7 00 23 2E 04 FC +6F 00 80 05 13 07 00 00 83 27 C4 FD 93 97 27 00 +B3 07 F7 00 03 A7 07 00 83 27 C4 FD 93 97 27 00 +93 87 07 FF B3 87 87 00 23 AC E7 FA 13 07 00 00 +83 27 C4 FD 93 97 27 00 B3 07 F7 00 83 A7 07 00 +03 27 C4 FE B3 07 F7 00 23 26 F4 FE 83 27 C4 FD +93 87 17 00 23 2E F4 FC 03 27 C4 FD 93 07 90 00 +E3 D2 E7 FA 93 07 84 FA 13 06 90 00 93 05 00 00 +13 85 07 00 EF F0 DF A4 23 2C 04 FC 6F 00 00 03 +83 27 84 FD 93 97 27 00 93 87 07 FF B3 87 87 00 +83 A7 87 FB 03 27 44 FE B3 07 F7 00 23 22 F4 FE +83 27 84 FD 93 87 17 00 23 2C F4 FC 03 27 84 FD +93 07 90 00 E3 D6 E7 FC 03 27 C4 FE 83 27 44 FE +63 0C F7 00 B7 07 10 30 93 87 87 FF 13 07 E0 04 +23 A0 E7 00 6F 00 40 01 B7 07 10 30 93 87 87 FF +13 07 B0 04 23 A0 E7 00 93 08 00 05 13 08 60 04 +93 07 C0 03 13 07 20 03 93 06 80 02 13 06 E0 01 +93 05 40 01 13 05 A0 00 EF F0 1F CF 23 28 A4 FC +03 27 04 FD 93 07 80 16 63 0C F7 00 B7 07 10 30 +93 87 87 FF 13 07 E0 05 23 A0 E7 00 6F 00 40 01 +B7 07 10 30 93 87 87 FF 13 07 B0 05 23 A0 E7 00 +B7 07 10 30 93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 +13 00 00 00 83 20 C1 05 03 24 81 05 13 01 01 06 +67 80 00 00 +@00000A28 +01 00 00 00 28 00 00 00 02 00 00 00 05 00 00 00 +16 00 00 00 0B 00 00 00 5A 00 00 00 C8 00 00 00 +0A 00 00 00 14 00 00 00 19 00 00 00 00 00 00 00 diff --git a/verilog/dv/cocotb/hex_files/gpio_all_i.hex b/verilog/dv/cocotb/hex_files/gpio_all_i.hex new file mode 100755 index 00000000..b63b1fd4 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/gpio_all_i.hex @@ -0,0 +1,218 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 +13 06 46 CC 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 +23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 +13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 +B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 +23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 +23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 +13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 +23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF +EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 +E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 +03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC +83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB +23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 +EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE +6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC +EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB +EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 +EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF +EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA +EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 +EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 +EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 +EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF +EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 +EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC +EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 +EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 +EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 +EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C +EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 +EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B +EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A +EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 +EF F0 1F A3 B7 07 00 26 93 87 87 0B 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27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 47 04 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 04 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 C7 03 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 87 03 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 47 03 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 03 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 C7 02 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 87 02 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 47 02 37 27 00 00 +13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +13 07 10 00 23 A0 E7 00 13 00 00 00 B7 07 00 26 +03 A7 07 00 93 07 10 00 E3 0A F7 FE B7 07 10 30 +93 87 87 FF 13 07 A0 0A 23 A0 E7 00 13 00 00 00 +B7 07 00 26 93 87 C7 00 03 A7 07 00 B7 07 67 8F +93 87 B7 D7 E3 16 F7 FE B7 07 10 30 93 87 87 FF +13 07 B0 0B 23 A0 E7 00 13 00 00 00 B7 07 00 26 +93 87 C7 00 03 A7 07 00 B7 97 A8 FF 93 87 A7 C5 +E3 16 F7 FE B7 07 10 30 93 87 87 FF 13 07 C0 0C +23 A0 E7 00 13 00 00 00 B7 07 00 26 93 87 C7 00 +03 A7 07 00 B7 67 53 C9 93 87 67 34 E3 16 F7 FE +B7 07 10 30 93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/gpio_all_o.hex b/verilog/dv/cocotb/hex_files/gpio_all_o.hex new file mode 100755 index 00000000..66ca4b7f --- /dev/null +++ b/verilog/dv/cocotb/hex_files/gpio_all_o.hex @@ -0,0 +1,230 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 +13 06 C6 D7 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 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83 20 C1 02 +03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC +83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB +23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 +EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE +6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC +EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB +EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 +EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF +EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA +EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 +EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 +EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD +23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE +6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 +83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 +EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE +03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 +EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 +83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 +13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 +23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF +EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE +63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF +23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 +E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 +EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 +13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 +23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD 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01 02 B7 47 00 F0 93 87 07 80 +13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF +23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 +B7 07 00 26 93 87 87 0B 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 47 0B 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 0B +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 C7 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 87 0A 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 47 0A 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 0A +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 C7 09 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 87 09 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 47 09 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 09 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 C7 08 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 87 08 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 47 08 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 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00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 C7 03 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 87 03 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 47 03 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 03 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 C7 02 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 87 02 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 47 02 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +13 07 10 00 23 A0 E7 00 13 00 00 00 B7 07 00 26 +03 A7 07 00 93 07 10 00 E3 0A F7 FE B7 07 10 30 +93 87 87 FF 13 07 F0 0F 23 A0 E7 00 B7 07 00 26 +93 87 C7 00 23 A0 07 00 B7 07 00 26 93 87 07 01 +23 A0 07 00 93 07 00 02 23 26 F4 FE 23 24 04 FE +6F 00 80 06 B7 07 00 26 93 87 07 01 03 27 C4 FE +23 A0 E7 00 B7 07 10 30 93 87 C7 FF 93 06 50 02 +03 27 84 FE 33 87 E6 40 23 A0 E7 00 B7 07 00 26 +93 87 07 01 23 A0 07 00 B7 07 10 30 93 87 C7 FF +23 A0 07 00 83 27 C4 FE 93 D7 17 00 23 26 F4 FE +83 27 C4 FE 93 E7 07 02 23 26 F4 FE 83 27 84 FE +93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 40 00 +E3 FA E7 F8 B7 07 00 80 23 26 F4 FE 23 24 04 FE +6F 00 80 08 B7 07 00 26 93 87 07 01 13 07 F0 03 +23 A0 E7 00 B7 07 00 26 93 87 C7 00 03 27 C4 FE +23 A0 E7 00 B7 07 10 30 93 87 C7 FF 93 06 00 02 +03 27 84 FE 33 87 E6 40 23 A0 E7 00 B7 07 00 26 +93 87 07 01 23 A0 07 00 B7 07 00 26 93 87 C7 00 +23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 +83 27 C4 FE 93 D7 17 00 23 26 F4 FE 03 27 C4 FE +B7 07 00 80 B3 67 F7 00 23 26 F4 FE 83 27 84 FE +93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 F0 01 +E3 FA E7 F6 13 00 00 00 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/helloWorld.hex b/verilog/dv/cocotb/hex_files/helloWorld.hex new file mode 100755 index 00000000..8816cba9 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/helloWorld.hex @@ -0,0 +1,32 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 12 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 C0 0B 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 93 07 00 00 13 85 07 00 +03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/hk_regs_rst_spi.hex b/verilog/dv/cocotb/hex_files/hk_regs_rst_spi.hex new file mode 100755 index 00000000..100c12da --- /dev/null +++ b/verilog/dv/cocotb/hex_files/hk_regs_rst_spi.hex @@ -0,0 +1,47 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/hk_regs_wr_spi.hex b/verilog/dv/cocotb/hex_files/hk_regs_wr_spi.hex new file mode 100755 index 00000000..100c12da --- /dev/null +++ b/verilog/dv/cocotb/hex_files/hk_regs_wr_spi.hex @@ -0,0 +1,47 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex b/verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex new file mode 100755 index 00000000..100c12da --- /dev/null +++ b/verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex @@ -0,0 +1,47 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 +03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/mem_stress.hex b/verilog/dv/cocotb/hex_files/mem_stress.hex new file mode 100755 index 00000000..0e5f942d --- /dev/null +++ b/verilog/dv/cocotb/hex_files/mem_stress.hex @@ -0,0 +1,102 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 57 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 CA 23 2E 81 34 13 04 01 36 +B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 +B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 +93 87 C7 FF 23 A0 07 00 93 07 04 CA 23 2C F4 FC +93 07 04 CA 23 2A F4 FC 93 07 90 07 A3 09 F4 FC +B7 87 79 79 93 87 97 97 23 26 F4 FC B7 87 FF FF +93 C7 97 97 23 15 F4 FC 83 47 34 FD A3 07 F4 FE +23 20 04 FE 6F 00 80 06 83 47 F4 FE 13 87 07 00 +93 07 07 00 93 97 17 00 B3 87 E7 00 93 F7 F7 0F +93 87 57 00 93 F7 F7 0F 13 97 87 01 13 57 87 41 +83 07 34 FD B3 67 F7 00 93 97 87 01 93 D7 87 41 +13 F7 F7 0F 83 27 04 FE 93 87 07 FF B3 87 87 00 +23 88 E7 CA 83 47 F4 FE 93 87 B7 00 A3 07 F4 FE +83 27 04 FE 93 87 17 00 23 20 F4 FE 03 27 04 FE +93 07 F0 31 E3 DA E7 F8 83 47 34 FD A3 07 F4 FE +A3 0F 04 FC 23 20 04 FE 6F 00 C0 08 83 47 F4 FE +13 87 07 00 93 07 07 00 93 97 17 00 B3 87 E7 00 +93 F7 F7 0F 93 87 57 00 93 F7 F7 0F 13 97 87 01 +13 57 87 41 83 07 34 FD B3 67 F7 00 93 97 87 01 +93 D7 87 41 A3 04 F4 FC 83 27 04 FE 93 87 07 FF +B3 87 87 00 83 C7 07 CB 03 47 94 FC 63 00 F7 02 +B7 07 10 30 93 87 87 FF 13 07 E0 01 23 A0 E7 00 +93 07 10 00 A3 0F F4 FC 6F 00 80 02 83 47 F4 FE +93 87 B7 00 A3 07 F4 FE 83 27 04 FE 93 87 17 00 +23 20 F4 FE 03 27 04 FE 93 07 F0 31 E3 D8 E7 F6 +83 47 F4 FD 93 C7 17 00 93 F7 F7 0F 63 8A 07 00 +B7 07 10 30 93 87 87 FF 13 07 B0 01 23 A0 E7 00 +A3 0F 04 FC 83 27 C4 FC 23 24 F4 FE 23 20 04 FE +6F 00 C0 04 03 27 84 FE 93 07 07 00 93 97 17 00 +B3 87 E7 00 93 86 57 00 83 27 04 FE 93 97 27 00 +03 27 44 FD B3 07 F7 00 03 27 C4 FC 33 E7 E6 00 +23 A0 E7 00 83 27 84 FE 93 87 B7 00 23 24 F4 FE +83 27 04 FE 93 87 17 00 23 20 F4 FE 03 27 04 FE +93 07 70 0C E3 D8 E7 FA 83 27 C4 FC 23 24 F4 FE +23 20 04 FE 6F 00 40 07 03 27 84 FE 93 07 07 00 +93 97 17 00 B3 87 E7 00 93 87 57 00 03 27 C4 FC +B3 67 F7 00 23 22 F4 FC 83 27 04 FE 93 97 27 00 +03 27 44 FD B3 07 F7 00 83 A7 07 00 03 27 44 FC +63 00 F7 02 B7 07 10 30 93 87 87 FF 13 07 E0 02 +23 A0 E7 00 93 07 10 00 A3 0F F4 FC 6F 00 80 02 +83 27 84 FE 93 87 B7 00 23 24 F4 FE 83 27 04 FE +93 87 17 00 23 20 F4 FE 03 27 04 FE 93 07 70 0C +E3 D4 E7 F8 83 47 F4 FD 93 C7 17 00 93 F7 F7 0F +63 8A 07 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 +23 A0 E7 00 A3 0F 04 FC 83 57 A4 FC 23 13 F4 FE +23 20 04 FE 6F 00 80 07 83 57 64 FE 13 87 07 00 +93 07 07 00 93 97 17 00 B3 87 E7 00 93 97 07 01 +93 D7 07 01 93 87 57 00 93 97 07 01 93 D7 07 01 +13 97 07 01 13 57 07 41 83 17 A4 FC B3 67 F7 00 +93 96 07 01 93 D6 06 41 83 27 04 FE 93 97 17 00 +03 27 84 FD B3 07 F7 00 13 97 06 01 13 57 07 01 +23 90 E7 00 83 57 64 FE 93 87 B7 00 23 13 F4 FE +83 27 04 FE 93 87 17 00 23 20 F4 FE 03 27 04 FE +93 07 F0 18 E3 D2 E7 F8 83 57 A4 FC 23 13 F4 FE +23 20 04 FE 6F 00 80 09 83 57 64 FE 13 87 07 00 +93 07 07 00 93 97 17 00 B3 87 E7 00 93 97 07 01 +93 D7 07 01 93 87 57 00 93 97 07 01 93 D7 07 01 +13 97 07 01 13 57 07 41 83 17 A4 FC B3 67 F7 00 +93 97 07 01 93 D7 07 41 23 11 F4 FC 83 27 04 FE +93 97 17 00 03 27 84 FD B3 07 F7 00 83 D7 07 00 +03 57 24 FC 63 00 F7 02 B7 07 10 30 93 87 87 FF +13 07 E0 03 23 A0 E7 00 93 07 10 00 A3 0F F4 FC +6F 00 80 02 83 57 64 FE 93 87 B7 00 23 13 F4 FE +83 27 04 FE 93 87 17 00 23 20 F4 FE 03 27 04 FE +93 07 F0 18 E3 D2 E7 F6 83 47 F4 FD 93 C7 17 00 +93 F7 F7 0F 63 8A 07 00 B7 07 10 30 93 87 87 FF +13 07 B0 03 23 A0 E7 00 B7 07 10 30 93 87 C7 FF +13 07 F0 0F 23 A0 E7 00 13 00 00 00 03 24 C1 35 +13 01 01 36 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex b/verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex new file mode 100755 index 00000000..51a2dfb7 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex @@ -0,0 +1,66 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 34 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 +B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 +B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 +93 87 C7 FF 23 A0 07 00 B7 37 00 F0 93 87 07 80 +13 07 10 00 23 A0 E7 00 B7 37 00 F0 93 87 47 80 +23 A0 07 00 B7 37 00 F0 93 87 87 80 13 07 10 00 +23 A0 E7 00 B7 37 00 F0 93 87 C7 80 13 07 10 00 +23 A0 E7 00 B7 07 10 30 93 87 87 FF 13 07 A0 00 +23 A0 E7 00 23 26 04 FE 6F 00 C0 05 13 00 00 00 +B7 37 00 F0 93 87 07 81 83 A7 07 00 E3 8A 07 FE +B7 07 10 30 93 87 C7 FF 13 07 A0 0A 23 A0 E7 00 +13 00 00 00 B7 37 00 F0 93 87 07 81 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 07 10 30 93 87 C7 FF +13 07 B0 0B 23 A0 E7 00 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 90 00 E3 D0 E7 FA +B7 07 10 30 93 87 C7 FF 13 07 B0 01 23 A0 E7 00 +B7 07 10 30 93 87 87 FF 13 07 40 01 23 A0 E7 00 +23 24 04 FE 6F 00 C0 05 13 00 00 00 B7 37 00 F0 +93 87 07 81 83 A7 07 00 E3 8A 07 FE B7 07 10 30 +93 87 C7 FF 13 07 A0 0A 23 A0 E7 00 13 00 00 00 +B7 37 00 F0 93 87 07 81 03 A7 07 00 93 07 10 00 +E3 08 F7 FE B7 07 10 30 93 87 C7 FF 13 07 B0 0B +23 A0 E7 00 83 27 84 FE 93 87 17 00 23 24 F4 FE +03 27 84 FE 93 07 30 01 E3 D0 E7 FA B7 07 10 30 +93 87 C7 FF 13 07 B0 02 23 A0 E7 00 B7 37 00 F0 +93 87 07 81 83 A7 07 00 23 20 F4 FE B7 07 10 30 +93 87 87 FF 23 A0 07 00 23 22 04 FE 6F 00 40 03 +B7 37 00 F0 93 87 07 81 03 A7 07 00 83 27 04 FE +63 0A F7 00 B7 07 10 30 93 87 C7 FF 13 07 E0 0E +23 A0 E7 00 83 27 44 FE 93 87 17 00 23 22 F4 FE +03 27 44 FE 93 07 10 03 E3 D4 E7 FC B7 07 10 30 +93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 +03 24 C1 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex b/verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex new file mode 100755 index 00000000..03087382 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex @@ -0,0 +1,54 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 28 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 +B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 +B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 +93 87 C7 FF 23 A0 07 00 B7 37 00 F0 93 87 07 80 +13 07 10 00 23 A0 E7 00 B7 37 00 F0 93 87 47 80 +23 A0 07 00 B7 37 00 F0 93 87 87 80 13 07 10 00 +23 A0 E7 00 B7 37 00 F0 93 87 C7 80 13 07 10 00 +23 A0 E7 00 B7 07 10 30 93 87 87 FF 13 07 A0 00 +23 A0 E7 00 23 26 04 FE 6F 00 C0 02 B7 37 00 F0 +93 87 47 81 13 07 10 00 23 A0 E7 00 B7 37 00 F0 +93 87 47 81 23 A0 07 00 83 27 C4 FE 93 87 17 00 +23 26 F4 FE 03 27 C4 FE 93 07 90 00 E3 D8 E7 FC +B7 07 10 30 93 87 87 FF 13 07 40 01 23 A0 E7 00 +23 24 04 FE 6F 00 C0 02 B7 37 00 F0 93 87 47 81 +13 07 10 00 23 A0 E7 00 B7 37 00 F0 93 87 47 81 +23 A0 07 00 83 27 84 FE 93 87 17 00 23 24 F4 FE +03 27 84 FE 93 07 30 01 E3 D8 E7 FC B7 07 10 30 +93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 87 FF +23 A0 07 00 B7 07 10 30 93 87 87 FF 23 A0 07 00 +B7 07 10 30 93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 +13 00 00 00 03 24 C1 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/timer0_oneshot.hex b/verilog/dv/cocotb/hex_files/timer0_oneshot.hex new file mode 100755 index 00000000..79b4ae69 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/timer0_oneshot.hex @@ -0,0 +1,58 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 2B 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 +B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 +B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 +93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00 +23 A0 07 00 B7 57 00 F0 37 37 0F 00 23 A0 E7 00 +B7 57 00 F0 93 87 87 00 13 07 10 00 23 A0 E7 00 +B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 +B7 57 00 F0 93 87 07 01 83 A7 07 00 23 26 F4 FE +B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 +B7 57 00 F0 93 87 07 01 83 A7 07 00 23 22 F4 FE +03 27 44 FE 83 27 C4 FE 63 70 F7 02 83 27 44 FE +63 8C 07 00 B7 07 10 30 93 87 87 FF 13 07 B0 01 +23 A0 E7 00 6F 00 80 03 83 27 44 FE 63 90 07 02 +B7 07 10 30 93 87 87 FF 13 07 B0 02 23 A0 E7 00 +13 00 00 00 23 24 04 FE 6F 00 C0 02 B7 07 10 30 +93 87 87 FF 13 07 F0 01 23 A0 E7 00 83 27 44 FE +23 26 F4 FE 6F F0 DF F7 83 27 84 FE 93 87 17 00 +23 24 F4 FE 03 27 84 FE 93 07 90 00 E3 D6 E7 FE +B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 +B7 57 00 F0 93 87 07 01 83 A7 07 00 63 9C 07 00 +B7 07 10 30 93 87 87 FF 13 07 B0 03 23 A0 E7 00 +6F 00 40 01 B7 07 10 30 93 87 87 FF 13 07 F0 02 +23 A0 E7 00 B7 07 10 30 93 87 C7 FF 13 07 F0 0F +23 A0 E7 00 13 00 00 00 03 24 C1 01 13 01 01 02 +67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/timer0_periodic.hex b/verilog/dv/cocotb/hex_files/timer0_periodic.hex new file mode 100755 index 00000000..45cfd920 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/timer0_periodic.hex @@ -0,0 +1,60 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FD 23 26 81 02 13 04 01 03 +B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 +B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 +93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00 +23 A0 07 00 B7 57 00 F0 23 A0 07 00 B7 57 00 F0 +93 87 47 00 13 07 00 30 23 A0 E7 00 B7 57 00 F0 +93 87 87 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 +93 87 C7 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 +93 87 07 01 83 A7 07 00 23 26 F4 FE 23 24 04 FE +93 07 00 19 23 20 F4 FE 23 22 04 FE 6F 00 C0 0C +B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 +B7 57 00 F0 93 87 07 01 83 A7 07 00 23 2E F4 FC +03 27 C4 FD 83 27 C4 FE 63 F8 E7 06 83 27 84 FE +93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 10 00 +63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 01 +23 A0 E7 00 6F 00 40 04 03 27 84 FE 93 07 20 00 +63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 +23 A0 E7 00 6F 00 40 02 03 27 84 FE 93 07 30 00 +63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 03 +23 A0 E7 00 6F 00 00 04 03 27 C4 FD 83 27 C4 FE +63 7A F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 04 +23 A0 E7 00 83 27 C4 FD 23 26 F4 FE 83 27 44 FE +93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE +E3 48 F7 F2 83 27 84 FE 63 9A 07 00 B7 07 10 30 +93 87 87 FF 13 07 E0 0E 23 A0 E7 00 B7 07 10 30 +93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 +03 24 C1 02 13 01 01 03 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/uart_tx.hex b/verilog/dv/cocotb/hex_files/uart_tx.hex new file mode 100755 index 00000000..25ae4e61 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/uart_tx.hex @@ -0,0 +1,62 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 +13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE +93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD +13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 +93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 +03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE +83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE +83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 +83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 +13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 +B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 +B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 +93 87 C7 FF 23 A0 07 00 B7 07 00 26 93 87 C7 03 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +13 07 10 00 23 A0 E7 00 13 00 00 00 B7 07 00 26 +03 A7 07 00 93 07 10 00 E3 0A F7 FE B7 67 00 F0 +13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF +13 07 A0 0A 23 A0 E7 00 B7 07 00 10 13 85 07 39 +EF F0 DF F1 23 26 04 FE 6F 00 00 01 83 27 C4 FE +93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 F0 09 +E3 D6 E7 FE 13 00 00 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 +@0000038C +00 00 00 00 4D 6F 6E 69 74 6F 72 3A 20 54 65 73 +74 20 55 41 52 54 20 28 52 54 4C 29 20 70 61 73 +73 65 64 00 diff --git a/verilog/dv/cocotb/logic_analyzer.py b/verilog/dv/cocotb/logic_analyzer.py new file mode 100644 index 00000000..61e9298c --- /dev/null +++ b/verilog/dv/cocotb/logic_analyzer.py @@ -0,0 +1,84 @@ +import random +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +import cocotb.simulator +from cocotb.handle import SimHandleBase +from cocotb.handle import Force +from cocotb_coverage.coverage import * +from cocotb.binary import BinaryValue +import enum +from cocotb.handle import ( + ConstantObject, + HierarchyArrayObject, + HierarchyObject, + ModifiableObject, + NonHierarchyIndexableObject, + SimHandle, +) + +from itertools import groupby, product + +import common +from common import GPIO_MODE +from common import MASK_GPIO_CTRL +from common import Macros + +class LA: + def __init__(self,dut:SimHandleBase): + self.dut = dut + self.clk = dut.clock_tb + self.core_hdl = dut.uut.soc.core + + + """ Configure the value of LA probes [0:127] + writing 1 to any bit means bit acts as outputs from the cpu + writing 0 to any bit means bit acts as inputs to the cpu """ + async def configure_la_en(self, bits,data): + self.__drive_la_iena(bits,data) + self.__drive_la_oenb(bits,data) + await ClockCycles(self.clk, 1) + + + + def __drive_la_iena(self, bits,data): + iena , n_bits = common.signal_value_size(self.core_hdl.la_ien_storage) + cocotb.log.debug(f' [LA] before change iena with {iena} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]') + iena[n_bits-1-bits[0]:n_bits-1-bits[1]] = data + self.core_hdl.la_ien_storage.value = iena + cocotb.log.info(f' [LA] drive reg_la_iena with {hex(iena)}') + + def __drive_la_oenb(self, bits,data): + oenb , n_bits = common.signal_value_size(self.core_hdl.la_oe_storage) + cocotb.log.debug(f' [LA] before change oenb with {oenb} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]') + oenb[n_bits-1-bits[0]:n_bits-1-bits[1]] = data + self.core_hdl.la_oe_storage.value = oenb + cocotb.log.info(f' [LA] drive reg_la_oenb with {hex(oenb)}') + + """ update the value of LA data input from cpu to user project """ + def drive_la_data_to_user(self,bits,data): + la , n_bits = common.signal_value_size(self.core_hdl.la_out_storage) + cocotb.log.debug(f' [LA] before la data update with LA ={la} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]') + la[n_bits-1-bits[0]:n_bits-1-bits[1]] = data + self.core_hdl.la_out_storage.value = la + cocotb.log.info(f' [LA] drive_la_data_to_user: drive data {hex(la)} to user project') + + """return the value of LA data output from user project tp cpu""" + def check_la_user_out(self): + LA_out = self.core_hdl.la_input.value + if(LA_out.is_resolvable): + cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}') + else: + cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}') + return LA_out + + + """return the value of LA data output from user project tp cpu""" + def check_la_ctrl_reg(self): + LA_out = self.dut.uut.la_oenb_mprj.value + if(LA_out.is_resolvable): + cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {hex(LA_out)}') + else: + cocotb.log.info(f' [LA] Monitor : reg_la_data_out from user = {LA_out}') + return LA_out \ No newline at end of file diff --git a/verilog/dv/cocotb/pli.tab b/verilog/dv/cocotb/pli.tab new file mode 100644 index 00000000..5ac9e794 --- /dev/null +++ b/verilog/dv/cocotb/pli.tab @@ -0,0 +1 @@ +acc+=rw,wn:* \ No newline at end of file diff --git a/verilog/dv/cocotb/run.py b/verilog/dv/cocotb/run.py new file mode 100644 index 00000000..9eef36ea --- /dev/null +++ b/verilog/dv/cocotb/run.py @@ -0,0 +1,303 @@ +#!/usr/bin/python3 +# -*- coding: utf-8 -*- +import collections +import json +import sys +import os +from pathlib import Path +import json +from fnmatch import fnmatch +from datetime import datetime +import random +from pathlib import Path + +def go_up(path, n): + for i in range(n): + path = os.path.dirname(path) + return path +# search pattern in file +def search_str(file_path, word): + with open(file_path, 'r') as file: + # read all content of a file + content = file.read() + # check if string present in a file + if word in content: + return "passed" + else: + return "failed" + + +class RunTest: + def __init__(self,test_name,sim) -> None: + self.cocotb_path = os.getcwd() + self.test_name = test_name + self.sim_type = sim + self.create_log_file() + self.hex_generate() + self.runTest() + + # create and open full terminal log to be able to use it before run the test + def create_log_file(self): + self.cd_cocotb() + os.chdir(f"sim/{os.getenv('RUNTAG')}") + test_dir = f"{self.sim_type}-{self.test_name}" + os.makedirs(f"{test_dir}",exist_ok=True) + self.cd_cocotb() + self.sim_path = f"sim/{os.getenv('RUNTAG')}/{test_dir}/" + terminal_log=f"{self.sim_path}/fullTerminal.log" + test_log=f"{self.sim_path}/{self.test_name}.log" + self.full_terminal = open(test_log, "w") + + # iverilog function + # def runTest(self): + # print(f"Start running test: {self.sim_type}-{self.test_name}") + # os.system(f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} ") + # self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") + # Path(f'{self.sim_path}/{self.passed}').touch() + + # vcs function + def runTest(self): + print(f"Start running test: {self.sim_type}-{self.test_name}") + dirs = f'+incdir+\\\"{go_up(self.cocotb_path,4)}\\\" ' + macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS' + # shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex') + # if os.path.exists(f'{self.test_full_dir}/test_data'): + # shutil.copyfile(f'{self.test_full_dir}/test_data',f'{self.sim_path}/test_data') + if (self.sim_type=="GL_SDF"): + macros = f'{macros} +define+ENABLE_SDF +define+SIM=GL_SDF +define+GL +define+SDF_POSTFIX=\\\"-{self.corner}\\\"' + os.makedirs(f"annotation_logs",exist_ok=True) + elif(self.sim_type=="GL"): + macros = f'{macros} +define+GL +define+SIM=GL' + elif (self.sim_type=="RTL"): + macros = f'{macros} +define+SIM=\\\"RTL\\\"' + else: + print(f"Fatal: incorrect simulation type {self.sim_type}") + + os.environ["TESTCASE"] = f"{self.test_name}" + os.environ["MODULE"] = f"caravel_tests" + os.environ["SIM"] = self.sim_type + + os.system(f"vlogan -full64 -sverilog +error+25 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ") + os.system(f"vcs -cm line -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") + self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") + Path(f'{self.sim_path}/{self.passed}').touch() + + def find(self,name, path): + for root, dirs, files in os.walk(path): + if name in files: + return os.path.join(root, name) + print(f"Test {name} doesn't exist or don't have a C file ") + + def test_path(self): + test_name = self.test_name + test_name += ".c" + tests_path = os.path.abspath(f"{self.cocotb_path}/tests") + test_file = self.find(test_name,tests_path) + test_path = os.path.dirname(test_file) + return (test_path) + + def hex_generate(self): + #open docker + test_path =self.test_path() + self.cd_make() + elf_out = f"{self.cocotb_path}/hex_files/{self.test_name}.elf" + c_file = f"{test_path}/{self.test_name}.c" + hex_file = f"{self.cocotb_path}/hex_files/{self.test_name}.hex" + GCC_PATH = "/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937/bin/" + GCC_PREFIX = "riscv32-unknown-linux-gnu" + SOURCE_FILES = f"{os.getenv('FIRMWARE_PATH')}/crt0_vex.S {os.getenv('FIRMWARE_PATH')}/isr.c" + LINKER_SCRIPT = f"{os.getenv('FIRMWARE_PATH')}/sections.lds" + CPUFLAGS = f"-march=rv32i -mabi=ilp32 -D__vexriscv__ " + verilog_path = f"{os.getenv('VERILOG_PATH')}" + test_dir = f"{os.getenv('VERILOG_PATH')}/dv/tests-caravel/mem" # linker script include // TODO: to fix this in the future from the mgmt repo + print(test_dir) + elf_command = (f"{GCC_PATH}/{GCC_PREFIX}-gcc -g -I{verilog_path}/dv/firmware -I{verilog_path}/dv/generated -I{verilog_path}/dv/ " + f"-I{verilog_path}/common {CPUFLAGS} -Wl,-Bstatic,-T,{LINKER_SCRIPT}," + f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}") + hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} " + sed_command = f"sed -ie 's/@10/@00/g' {hex_file}" + os.system(f"docker run -it -v /home:/home efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '") + self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n") + self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n") + self.full_terminal.write(os.path.expandvars(sed_command)+"\n"+"\n") + self.cd_cocotb() + self.full_terminal.close() + + + def cd_make(self): + os.chdir(f"{os.getenv('VERILOG_PATH')}/dv/make") + + def cd_cocotb(self): + os.chdir(self.cocotb_path) + +class RunRegression: + def __init__(self,regression,test,type_arg,testlist) -> None: + self.regression_arg = regression + self.test_arg = test + self.testlist_arg = testlist + if type_arg is None: + type_arg = "RTL" + self.type_arg = type_arg + self.write_command_log() + with open('tests.json') as f: + self.tests_json = json.load(f) + self.tests_json = self.tests_json["Tests"] + self.get_tests() + self.run_regression() + + def get_tests(self): + self.tests = collections.defaultdict(lambda : collections.defaultdict(dict)) #key is testname and value is list of sim types + self.unknown_tests = 0 + self.passed_tests = 0 + self.failed_tests = 0 + # regression + if self.regression_arg is not None: + sim_types = ("RTL","GL","GL_SDF") + for test,test_elements in self.tests_json.items(): + if fnmatch(test,"_*"): + continue + for sim_type in sim_types: + if self.regression_arg in test_elements[sim_type]: + self.add_new_test(test_name=test,sim_type = sim_type) + if (len(self.tests)==0): + print(f"fatal:{self.regression_arg} is not a valid regression name please input a valid regression \ncheck tests.json for more info") + sys.exit() + #test + if self.test_arg is not None: + if isinstance(self.test_arg,list): + for test in self.test_arg: + if test in self.tests_json: + if isinstance(self.type_arg,list): + for sim_type in self.type_arg: + self.add_new_test(test_name=test,sim_type = sim_type) + else: + self.add_new_test(test_name=test,sim_type = self.type_arg) + + else: + if self.test_arg in self.tests_json: + if isinstance(self.type_arg,list): + for sim_type in self.type_arg: + self.add_new_test(test_name=self.test_arg,sim_type = sim_type) + else: + self.add_new_test(test_name=self.test_arg,sim_type = self.type_arg) + # testlist TODO: add logic for test list + if self.testlist_arg is not None: + print(f'fatal: code for test list isnt added yet') + sys.exit() + + + self.update_reg_log() + + def add_new_test(self,test_name,sim_type): + self.tests[test_name][sim_type]["status"]= "pending" + self.tests[test_name][sim_type]["starttime"]= "-" + self.tests[test_name][sim_type]["endtime"]= "-" + self.tests[test_name][sim_type]["duration"] = "-" + self.tests[test_name][sim_type]["pass"]= "-" + self.unknown_tests +=1 + + def run_regression(self): + for test,sim_types in self.tests.items(): + for sim_type,status in sim_types.items(): # TODO: add multithreading or multiprocessing here + start_time = datetime.now() + self.tests[test][sim_type]["starttime"] = datetime.now().strftime("%H:%M:%S(%a)") + self.tests[test][sim_type]["duration"] = "-" + self.tests[test][sim_type]["status"] = "running" + self.update_reg_log() + test_run = RunTest(test,sim_type) + self.tests[test][sim_type]["status"] = "done" + self.tests[test][sim_type]["endtime"] = datetime.now().strftime("%H:%M:%S(%a)") + self.tests[test][sim_type]["duration"] = ("%.10s" % (datetime.now() - start_time)) + self.tests[test][sim_type]["pass"]= test_run.passed + if test_run.passed == "passed": + self.passed_tests +=1 + elif test_run.passed == "failed": + self.failed_tests +=1 + self.unknown_tests -=1 + self.update_reg_log() + #TODO: add send mail here + + + def update_reg_log(self): + file_name=f"sim/{os.getenv('RUNTAG')}/runs.log" + f = open(file_name, "w") + f.write(f"{'Test':<25} {'status':<10} {'start':<15} {'end':<15} {'duration':<13} {'p/f':<5}\n") + for test,sim_types in self.tests.items(): + for sim_type,status in sim_types.items(): + new_test_name= f"{sim_type}-{test}" + f.write(f"{new_test_name:<25} {status['status']:<10} {status['starttime']:<15} {status['endtime']:<15} {status['duration']:<13} {status['pass']:<5}\n") + f.write(f"\n\nTotal: ({self.passed_tests})passed ({self.failed_tests})failed ({self.unknown_tests})unknown ") + f.close() + + def write_command_log(self): + file_name=f"sim/{os.getenv('RUNTAG')}/command.log" + f = open(file_name, "w") + f.write(f"{' '.join(sys.argv)}") + f.close() + +class main(): + def __init__(self,args) -> None: + self.regression = args.regression + self.test = args.test + self.testlist = args.testlist + self.type = args.sim + self.tag = args.tag + self.maxerr = args.maxerr + self.check_valid_args() + self.set_tag() + self.def_env_vars() + RunRegression(self.regression,self.test,self.type,self.testlist) + + def check_valid_args(self): + if all(v is None for v in [self.regression, self.test, self.testlist]): + print ("Fatal: Should provide at least one of the following options regression, test or testlist for more info use --help") + sys.exit() + if not set(self.type).issubset(["RTL","GL","GL_SDF"]): + print (f"Fatal: {self.type} isnt a correct type for -sim it should be one or combination of the following RTL, GL or GL_SDF") + sys.exit() + def set_tag(self): + self.TAG = None # tag will be set in the main phase and other functions will use it + if self.tag is not None: + self.TAG = self.tag + elif self.regression is not None: + self.TAG = f'{self.regression}_{datetime.now().strftime("%H_%M_%S_%d_%m")}' + else: + self.TAG = f'run{random.randint(0,1000)}_{datetime.now().strftime("%H_%M_%S_%d_%m")}' + Path(f"sim/{self.TAG}").mkdir(parents=True, exist_ok=True) + print(f"Run tag: {self.TAG}") + + def def_env_vars(self): + cocotb_path = os.getcwd() + repo_path = go_up(cocotb_path,4) + os.environ["CARAVEL_ROOT"] = f"{repo_path}/caravel" + os.environ["CARAVEL_VERILOG_PATH"] = f"{repo_path}/caravel/verilog" + os.environ["MCW_ROOT"] = f"{repo_path}/caravel_mgmt_soc_litex/" + os.environ["VERILOG_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog" + os.environ["CARAVEL_PATH"] = f"{os.getenv('CARAVEL_VERILOG_PATH')}" + os.environ["USER_PROJECT_VERILOG"] = f"{repo_path}/verilog/" + os.environ["GCC_PATH"] = "/ciic/tools/rv32/bin" + os.environ["FIRMWARE_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog/dv/firmware" + os.environ["RUNTAG"] = f"{self.TAG}" + print(self.maxerr) + os.environ["ERRORMAX"] = f"{self.maxerr}" + + + +import argparse +parser = argparse.ArgumentParser(description='Run cocotb tests') +parser.add_argument('-regression','-r', help='name of regression can found in tests.json') +parser.add_argument('-test','-t', nargs='+' ,help='name of test if no --sim provided RTL will be run ') +parser.add_argument('-sim', nargs='+' ,help='Simulation type to be run RTL,GL&GL_SDF provided only when run -test ') +parser.add_argument('-testlist','-tl', help='path of testlist to be run ') +parser.add_argument('-tag', help='provide tag of the run default would be regression name and if no regression is provided would be run___') +parser.add_argument('-maxerr', help='max number of errors for every test before simulation breaks default = 3') +args = parser.parse_args() +if args.sim == None: + args.sim= ["RTL"] +print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}") +main(args) + + + + + diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json new file mode 100644 index 00000000..f83fac8e --- /dev/null +++ b/verilog/dv/cocotb/tests.json @@ -0,0 +1,160 @@ +{ + "Tests": { + "_comment0" :"level is priorty of the test low is better, SW spcify if the test uses SW, RTL regressions run this test in RTL ", + "_comment1" :"GL regressions run this test in gatelevel, GL_SDF regression run this test with SDF included" + + ,"bitbang_no_cpu_all_o" :{"level":0, + "SW":false, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":[], + "GL_SDF":[], + "description":"test disable CPU and control the wishbone to configure gpio[4:37] as mgmt output using bitbang and check them"} + ,"bitbang_cpu_all_o" :{"level":0, + "SW":true, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"configure all gpios as mgmt output using bitbang and check them"} + ,"gpio_all_o" :{"level":0, + "SW":true, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"configure all gpios as mgmt output using automatic approach firmware and check them"} + ,"gpio_all_i" :{"level":0, + "SW":true, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"configure all gpios as mgmt output using automatic approach firmware and check them"} + ,"bitbang_cpu_all_10" :{"level":0, + "SW":true, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"shift all the register with 10"} + ,"bitbang_cpu_all_01" :{"level":0, + "SW":true, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"shift all the register with 01"} + ,"bitbang_cpu_all_1100" :{"level":0, + "SW":true, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"shift all the register with 1100"} + ,"bitbang_cpu_all_0011" :{"level":0, + "SW":true, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"shift all the register with 0011"} + ,"bitbang_no_cpu_all_i" :{"level":0, + "SW":false, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":[], + "GL_SDF":[], + "description":"test disable CPU and control the wishbone to configure gpio[0:31] as mgmt input using bitbang and check them"} + ,"bitbang_cpu_all_i" :{"level":0, + "SW":true, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":" configure gpio[0:37] as mgmt input using bitbang and check them"} + + ,"bitbang_spi" :{"level":0, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "SW":false, + "description":"Same as bitbang_no_cpu_all but configure the gpio using the SPI not the firmware"} + + ,"hk_regs_wr_wb" :{"level":0, + "SW":false, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"write then read (the written value) from random housekeeping registers through the firmware but without using CPU, the SPI and system regs can't be read using firmware so the test only GPIO regs inside housekeeping "} + ,"hk_regs_wr_spi" :{"level":0, + "SW":false, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"write then read(the written value) from random housekeeping registers through the SPI housekeeping"} + ,"hk_regs_rst_spi" :{"level":0, + "SW":false, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"check reset value of house keeping registers by reading them trough the spi housekeeping"} + ,"helloWorld" :{"level":3, + "SW":false, + "RTL":[], + "GL":[], + "GL_SDF":[], + "description":"hello world test"} + + ,"cpu_stress" :{"level":2, + "SW":true, + "RTL":["nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"stress the cpu with heavy processing"} + ,"mem_stress" :{"level":2, + "SW":true, + "RTL":["nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"Memory stress tests write and read from 800 bytes 200 words and 400 half words"} + ,"IRQ_external" :{"level":2, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"test external interrupt by mprj 7"} + ,"IRQ_timer" :{"level":2, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"test timer0 interrupt"} + ,"IRQ_uart" :{"level":2, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"test timer0 interrupt"} + ,"mgmt_gpio_out" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"tests blinking of mgmt gpio bit as an output"} + ,"mgmt_gpio_in" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"tests blinking of mgmt gpio bit as an output"} + ,"timer0_oneshot" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"check timer0 oneshot mode"} + ,"timer0_periodic" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"check timer0 periodic mode"} + ,"uart_tx" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"test uart transmit"} + } +} \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_0011.c b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_0011.c new file mode 100644 index 00000000..28a0c4a9 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_0011.c @@ -0,0 +1,62 @@ +#include +#include +#include "bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_3 = 0x1803 ; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + + // bitbang + for(int i =0;i<19*13;i++){ + clock00(); + clock00(); + clock11(); + clock11(); + } + reg_debug_1 = 0xFF; // finish configuration + + +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_01.c b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_01.c new file mode 100644 index 00000000..3dfb8cb3 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_01.c @@ -0,0 +1,60 @@ +#include +#include +#include "bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_3 = 0x1803 ; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + + // bitbang + for(int i =0;i<19*13;i++){ + clock00(); + clock11(); + } + reg_debug_1 = 0xFF; // finish configuration + + +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_10.c b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_10.c new file mode 100644 index 00000000..93abbb00 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_10.c @@ -0,0 +1,60 @@ +#include +#include +#include "bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_3 = 0x1803 ; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + + // bitbang + for(int i =0;i<19*13;i++){ + clock11(); + clock00(); + } + reg_debug_1 = 0xFF; // finish configuration + + +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_1100.c b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_1100.c new file mode 100644 index 00000000..c6f62bb1 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_1100.c @@ -0,0 +1,62 @@ +#include +#include +#include "bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_3 = 0x1803 ; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + + // bitbang + for(int i =0;i<19*13;i++){ + clock11(); + clock11(); + clock00(); + clock00(); + } + reg_debug_1 = 0xFF; // finish configuration + + +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_i.c b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_i.c new file mode 100644 index 00000000..e3f49723 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_i.c @@ -0,0 +1,83 @@ +#include +#include +#include "bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = 0x1803; + reg_mprj_io_36 = 0x1803; + reg_mprj_io_35 = 0x1803; + reg_mprj_io_34 = 0x1803; + reg_mprj_io_33 = 0x1803; + reg_mprj_io_32 = 0x1803; + reg_mprj_io_31 = 0x1803; + reg_mprj_io_30 = 0x1803; + reg_mprj_io_29 = 0x1803; + reg_mprj_io_28 = 0x1803; + reg_mprj_io_27 = 0x1803; + reg_mprj_io_26 = 0x1803; + reg_mprj_io_25 = 0x1803; + reg_mprj_io_24 = 0x1803; + reg_mprj_io_23 = 0x1803; + reg_mprj_io_22 = 0x1803; + reg_mprj_io_21 = 0x1803; + reg_mprj_io_20 = 0x1803; + reg_mprj_io_19 = 0x1803; + reg_mprj_io_18 = 0x1803; + reg_mprj_io_17 = 0x1803; + reg_mprj_io_16 = 0x1803; + reg_mprj_io_15 = 0x1803; + reg_mprj_io_14 = 0x1803; + reg_mprj_io_13 = 0x1803; + reg_mprj_io_12 = 0x1803; + reg_mprj_io_11 = 0x1803; + reg_mprj_io_10 = 0x1803; + reg_mprj_io_9 = 0x1803; + reg_mprj_io_8 = 0x1803; + reg_mprj_io_7 = 0x1803; + reg_mprj_io_6 = 0x1803; + reg_mprj_io_5 = 0x1803; + reg_mprj_io_4 = 0x1803; + reg_mprj_io_3 = 0x1803; + reg_mprj_io_2 = 0x1803; + reg_mprj_io_1 = 0x1803; + reg_mprj_io_0 = 0x1803; + reg_mprj_io_0 = 0x1803; + + // bitbang + //Configure all as input except reg_mprj_io_3 + clock_in_right_i_left_i_standard(0); // 18 and 19 + clock_in_right_i_left_i_standard(0); // 17 and 20 + clock_in_right_i_left_i_standard(0); // 16 and 21 + clock_in_right_i_left_i_standard(0); // 15 and 22 + clock_in_right_i_left_i_standard(0); // 14 and 23 + clock_in_right_i_left_i_standard(0); // 13 and 24 + clock_in_right_i_left_i_standard(0); // 12 and 25 + clock_in_right_i_left_i_standard(0); // 11 and 26 + clock_in_right_i_left_i_standard(0); // 10 and 27 + clock_in_right_i_left_i_standard(0); // 9 and 28 + clock_in_right_i_left_i_standard(0); // 8 and 29 + clock_in_right_i_left_i_standard(0); // 7 and 30 + clock_in_right_i_left_i_standard(0); // 6 and 31 + clock_in_right_i_left_i_standard(0); // 5 and 32 + clock_in_right_i_left_i_standard(0); // 4 and 33 + clock_in_right_i_left_i_standard(0); // 3 and 34 + clock_in_right_i_left_i_standard(0); // 2 and 35 + clock_in_right_i_left_i_standard(0); // 1 and 36 + clock_in_right_i_left_i_standard(0); // 0 and 37 + load(); // load + reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal + while (reg_mprj_datal != 0x8F66FD7B); + reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal + while (reg_mprj_datal != 0xFFA88C5A); + reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal + while (reg_mprj_datal != 0xC9536346); + + reg_debug_2 = 0xFF; + +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c new file mode 100644 index 00000000..5a30bae6 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_o.c @@ -0,0 +1,99 @@ +#include +#include +#include "bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_3 = 0x1803 ; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + + // bitbang + // Configure all as output except reg_mprj_io_3 + clock_in_right_o_left_o_standard(0); // 18 and 19 + clock_in_right_o_left_o_standard(0); // 17 and 20 + clock_in_right_o_left_o_standard(0); // 16 and 21 + clock_in_right_o_left_o_standard(0); // 15 and 22 + clock_in_right_o_left_o_standard(0); // 14 and 23 + clock_in_right_o_left_o_standard(0); // 13 and 24 + clock_in_right_o_left_o_standard(0); // 12 and 25 + clock_in_right_o_left_o_standard(0); // 11 and 26 + clock_in_right_o_left_o_standard(0); // 10 and 27 + clock_in_right_o_left_o_standard(0); // 9 and 28 + clock_in_right_o_left_o_standard(0); // 8 and 29 + clock_in_right_o_left_o_standard(0); // 7 and 30 + clock_in_right_o_left_o_standard(0); // 6 and 31 + clock_in_right_o_left_o_standard(0); // 5 and 32 + clock_in_right_o_left_o_standard(0); // 4 and 33 + clock_in_right_o_left_i_standard(0); // 3 and 34 + clock_in_right_o_left_o_standard(0); // 2 and 35 + clock_in_right_o_left_o_standard(0); // 1 and 36 + clock_in_right_o_left_o_standard(0); // 0 and 37 + load(); + reg_debug_1 = 0xFF; // finish configuration + reg_mprj_datal = 0x0; + reg_mprj_datah = 0x0; + i = 0x20; + for (j = 0; j < 5; j++) { + reg_mprj_datah = i; + reg_debug_2 = 37-j; + reg_mprj_datah = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x20; + } + i = 0x80000000; + for (j = 0; j < 32; j++) { + reg_mprj_datah = 0x3f; + reg_mprj_datal = i; + reg_debug_2 = 32-j; + reg_mprj_datah = 0x00; + reg_mprj_datal = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x80000000; + } + +} + + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_functions.c b/verilog/dv/cocotb/tests/bitbang/bitbang_functions.c new file mode 100644 index 00000000..53c2f936 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_functions.c @@ -0,0 +1,325 @@ + + +void clock11() +{ + reg_mprj_xfer = 0x66; reg_mprj_xfer = 0x76; +} + +void clock00() +{ + reg_mprj_xfer = 0x06; reg_mprj_xfer = 0x16; +} + +// -------------------------------------------------------- + +void clock10() +{ + reg_mprj_xfer = 0x46; reg_mprj_xfer = 0x56; +} + +void clock01() +{ + reg_mprj_xfer = 0x26; reg_mprj_xfer = 0x36; +} + +// -------------------------------------------------------- +// Load registers +// -------------------------------------------------------- + +void load() +{ + reg_mprj_xfer = 0x06; + reg_mprj_xfer = 0x0e; reg_mprj_xfer = 0x06; // Apply load +} + +// -------------------------------------------------------- +// Enable bit-bang mode and clear registers +// -------------------------------------------------------- + +void clear_registers() +{ + reg_mprj_xfer = 0x06; // Enable bit-bang mode + reg_mprj_xfer = 0x04; reg_mprj_xfer = 0x06; // Pulse reset +} + +// -------------------------------------------------------- +// Clock in an input + output configuration. The value +// passed in "ddhold" is the number of data-dependent hold +// violations up to this point. +// -------------------------------------------------------- + +/* Clock in data on the left side. Assume standard hold + * violation, so clock in12 times and assume that the + * next data to be clocked will start with "1", enforced + * by the code. + * + * Left side = GPIOs 37 to19 + */ + +void clock_in_left_short(uint32_t ddhold) +{ + uint32_t count; + uint32_t holds = ddhold; + + clock10(); + clock10(); + + for (count = 0; count < 9; count++) { + if (holds != 0) { + clock10(); + holds--; + } + else + clock00(); + } + + clock00(); +} + +/* Clock in data on the right side. Assume standard hold + * violation, so clock in12 times and assume that the + * next data to be clocked will start with "1", enforced + * by the code. + * + * Right side = GPIOs 0 to18 + */ + +void clock_in_right_short(uint32_t ddhold) +{ + uint32_t count; + uint32_t holds = ddhold; + + clock01(); + clock01(); + + for (count = 0; count < 9; count++) { + if (holds != 0) { + clock01(); + holds--; + } + else + clock00(); + } + + clock00(); +} + +/* Clock in data on the left side. Clock the normal13 times, + * which is correct for no hold violation or for a data- + * dependent hold violation (for the latter, ddhold must be + * incremented before calling the subroutine). + * + * Left side = GPIOs 37 to19 + */ + +void clock_in_left_standard(uint32_t ddhold){ + uint32_t count; + uint32_t holds = ddhold; + + clock10(); + clock10(); + + for (count = 0; count < 7; count++) { + if (holds != 0) { + clock10(); + holds--; + } + else + clock00(); + } + + clock10(); + clock00(); + clock00(); + clock10(); +} +void clock_in_right_o_left_o_standard(uint32_t ddhold){ + uint32_t count; + uint32_t holds = ddhold; + + clock11(); + clock11(); + + for (count = 0; count < 7; count++) { + if (holds != 0) { + clock11(); + holds--; + } + else + clock00(); + } + + clock11(); + clock00(); + clock00(); + clock11(); +} + +void clock_in_right_o_left_i_standard(uint32_t ddhold){ + uint32_t count; + uint32_t holds = ddhold; + + clock11(); + clock11(); + + for (count = 0; count < 7; count++) { + if (holds != 0) { + clock11(); + holds--; + } + else + clock00(); + } + + clock10(); + clock00(); + clock01(); + clock11(); +} + +void clock_in_right_i_left_o_standard(uint32_t ddhold){ + uint32_t count; + uint32_t holds = ddhold; + + clock11(); + clock11(); + + for (count = 0; count < 7; count++) { + if (holds != 0) { + clock11(); + holds--; + } + else + clock00(); + } + + clock01(); + clock00(); + clock10(); + clock11(); +} + +void clock_in_right_i_left_i_standard(uint32_t ddhold){ + uint32_t count; + uint32_t holds = ddhold; + + clock11(); + clock11(); + + for (count = 0; count < 7; count++) { + if (holds != 0) { + clock11(); + holds--; + } + else + clock00(); + } + + clock00(); + clock00(); + clock11(); + clock11(); +} + +/* Clock in data on the right side. Clock the normal13 times, + * which is correct for no hold violation or for a data- + * dependent hold violation (for the latter, ddhold must be + * incremented before calling the subroutine). + * + * Right side = GPIOs 0 to18 + */ + +void clock_in_right_standard(uint32_t ddhold){ + uint32_t count; + uint32_t holds = ddhold; + + clock11(); + clock11(); + + for (count = 0; count < 7; count++) { + if (holds != 0) { + clock01(); + holds--; + } + else + clock00(); + } + + clock10(); + clock00(); + clock01(); + clock11(); +} + +void clock_in_right_i_left_io_standard(uint32_t ddhold){ + uint32_t count; + uint32_t holds = ddhold; + + clock11(); + clock11(); + + for (count = 0; count < 7; count++) { + if (holds != 0) { + clock11(); + holds--; + } + else + clock00(); + } + + clock01(); + clock00(); + clock11(); + clock11(); +} +// -------------------------------------------------------- +// Clock in data for GPIO 0 and 37 (fixed) and apply load. +// -------------------------------------------------------- + +void clock_in_end(){ + // Right side: GPIO 0 configured disabled + // Left side: GPIO 37 configured as input + clock11(); + clock10(); + clock00(); + clock00(); + clock00(); + clock00(); + clock00(); + clock00(); + clock00(); + clock01(); + clock00(); + clock11(); + clock11(); + + load(); +} + +// -------------------------------------------------------- +// Same as above, except that GPIO is configured as an +// output for a quick sanity check. +// -------------------------------------------------------- + +void clock_in_end_output() +{ + // Right side: GPIO 0 configured disabled + // Left side: GPIO 37 configured as output + clock11(); + clock10(); + clock00(); + clock00(); + clock00(); + clock00(); + clock00(); + clock00(); + clock00(); + clock01(); + clock00(); + clock01(); + clock11(); + + load(); + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; +} diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_functions.py b/verilog/dv/cocotb/tests/bitbang/bitbang_functions.py new file mode 100644 index 00000000..225f8b43 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_functions.py @@ -0,0 +1,355 @@ +from defsParser import Regs + +reg = Regs() + + +""" +reg_mprj_xfer contain +bit 0 : busy +bit 1 : bitbang enable +bit 2 : bitbang reset active low +bit 3 : bitbang load registers +bit 4 : bitbang clock +bit 5 : serial data 1 +bit 6 : serial data 2 +""" + +"""shift the 2 registers with 2 ones""" +async def clock11(cpu): + reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer') + await cpu.drive_data2address(reg_mprj_xfer_addr,0x66) # 0110_0110 + await cpu.drive_data2address(reg_mprj_xfer_addr,0x76) # 0111_0110 + +"""shift the 2 registers with 2 zeros""" +async def clock00(cpu): + reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer') + await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # 0000_0110 + await cpu.drive_data2address(reg_mprj_xfer_addr,0x16) # 0001_0110 + +"""shift the 2 registers with 1 in the left side and zero in right side""" +async def clock01(cpu): + reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer') + await cpu.drive_data2address(reg_mprj_xfer_addr,0x26) # 0010_0110 + await cpu.drive_data2address(reg_mprj_xfer_addr,0x36) # 0011_0110 + +"""shift the 2 registers with 1 in the left side and zero in right side""" +async def clock10(cpu): + reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer') + await cpu.drive_data2address(reg_mprj_xfer_addr,0x46) # 0100_0110 + await cpu.drive_data2address(reg_mprj_xfer_addr,0x56) # 0101_0110 + +"""enable the serial loader bit to load registers""" +async def load(cpu): + reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer') + await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang + await cpu.drive_data2address(reg_mprj_xfer_addr,0x0e) # enable loader + await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang + +"""Enable bit-bang mode and clear registers""" +async def clear_registers(cpu): + reg_mprj_xfer_addr = reg.get_addr('reg_mprj_xfer') + await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang + await cpu.drive_data2address(reg_mprj_xfer_addr,0x04) # reset + await cpu.drive_data2address(reg_mprj_xfer_addr,0x06) # enable bit bang + +""" +-------------------------------------------------------- +Clock in an input + output configuration. The value +passed in "ddhold" is the number of data-dependent hold +violations up to this point. +-------------------------------------------------------- + + * Clock in data on the left side. Assume standard hold + * violation, so clock in 12 times and assume that the + * next data to be clocked will start with "1", enforced + * by the code. + * + * Left side = GPIOs 37 to 19 + + """ +async def clock_in_left_short(cpu,ddhold): + await clock10(cpu) + await clock10(cpu) + + for i in range(9): + if ddhold != 0: + await clock10(cpu) + ddhold -=1 + else: + await clock00(cpu) + + await clock00(cpu) + +async def clock_in_right_short(cpu,ddhold): + await clock01(cpu) + await clock01(cpu) + + for i in range(9): + if ddhold != 0: + await clock01(cpu) + ddhold -=1 + else: + await clock00(cpu) + + await clock00(cpu) + +async def clock_in_left_standard(cpu,ddhold): + await clock10(cpu) + await clock10(cpu) + + for i in range(7): + if ddhold != 0: + await clock10(cpu) + ddhold -=1 + else: + await clock00(cpu) + + await clock10(cpu) + await clock00(cpu) + await clock00(cpu) + await clock10(cpu) + +"""right output left input""" +async def clock_in_right_o_left_i_standard(cpu,ddhold): + await clock11(cpu) + await clock11(cpu) + + for i in range(7): + if ddhold != 0: + await clock01(cpu) + ddhold -=1 + else: + await clock00(cpu) + + await clock10(cpu) + await clock00(cpu) + await clock01(cpu) + await clock11(cpu) + +"""right input left output""" +async def clock_in_right_i_left_o_standard(cpu,ddhold): + await clock11(cpu) + await clock11(cpu) + + for i in range(7): + if ddhold != 0: + await clock10(cpu) + ddhold -=1 + else: + await clock00(cpu) + + await clock01(cpu) + await clock00(cpu) + await clock10(cpu) + await clock11(cpu) + +"""right input left output""" +async def clock_in_right_i_left_i_standard(cpu,ddhold): + await clock11(cpu) + await clock11(cpu) + + for i in range(7): + if ddhold != 0: + await clock01(cpu) + ddhold -=1 + else: + await clock00(cpu) + + await clock00(cpu) + await clock00(cpu) + await clock11(cpu) + await clock11(cpu) + +"""right output left output""" +async def clock_in_right_o_left_o_standard(cpu,ddhold): + await clock11(cpu) + await clock11(cpu) + + for i in range(7): + if ddhold != 0: + await clock01(cpu) + ddhold -=1 + else: + await clock00(cpu) + + await clock11(cpu) + await clock00(cpu) + await clock00(cpu) + await clock11(cpu) + +async def clock_in_end_output(cpu): + # Right side: GPIO 0 configured disabled + # /Left side: GPIO 37 configured as output + await clock11(cpu) + await clock11(cpu) + await clock00(cpu) + await clock00(cpu) + await clock00(cpu) + await clock00(cpu) + await clock00(cpu) + await clock00(cpu) + await clock00(cpu) + await clock00(cpu) + await clock00(cpu) + await clock01(cpu) + await clock11(cpu) + await load(cpu) + reg_mprj_io_37_addr = reg.get_addr('reg_mprj_io_37') + await cpu.drive_data2address(reg_mprj_io_37_addr,0x1809) + + +async def clock11_spi(caravelEnv): + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x66) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x76) # 11 + await caravelEnv.disable_csb() + +async def clock00_spi(caravelEnv): + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x06) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x16) # 00 + await caravelEnv.disable_csb() + +async def clock01_spi(caravelEnv): + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x26) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x36) # 01 + await caravelEnv.disable_csb() + +async def clock10_spi(caravelEnv): + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x46) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x56) # 10 + await caravelEnv.disable_csb() + +async def load_spi(caravelEnv): + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x0e) # load enable + await caravelEnv.disable_csb() + + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(0x13) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(0x16) # 00 + await caravelEnv.disable_csb() + +"""right output left input""" +async def clock_in_right_o_left_i_standard_spi(caravelEnv,ddhold): + await clock11_spi(caravelEnv) + await clock11_spi(caravelEnv) + + for i in range(7): + if ddhold != 0: + await clock01_spi(caravelEnv) + ddhold -=1 + else: + await clock00_spi(caravelEnv) + + await clock10_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock01_spi(caravelEnv) + await clock11_spi(caravelEnv) + +"""right input left output""" +async def clock_in_right_i_left_o_standard_spi(caravelEnv,ddhold): + await clock11_spi(caravelEnv) + await clock11_spi(caravelEnv) + + for i in range(7): + if ddhold != 0: + await clock10_spi(caravelEnv) + ddhold -=1 + else: + await clock00_spi(caravelEnv) + + await clock01_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock10_spi(caravelEnv) + await clock11_spi(caravelEnv) + +"""right input left output""" +async def clock_in_right_i_left_i_standard_spi(caravelEnv,ddhold): + await clock11_spi(caravelEnv) + await clock11_spi(caravelEnv) + + for i in range(7): + if ddhold != 0: + await clock01_spi(caravelEnv) + ddhold -=1 + else: + await clock00_spi(caravelEnv) + + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock11_spi(caravelEnv) + await clock11_spi(caravelEnv) + +"""right output left output""" +async def clock_in_right_o_left_o_standard_spi(caravelEnv,ddhold): + await clock11_spi(caravelEnv) + await clock11_spi(caravelEnv) + + for i in range(7): + if ddhold != 0: + await clock01_spi(caravelEnv) + ddhold -=1 + else: + await clock00_spi(caravelEnv) + + await clock11_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock11_spi(caravelEnv) + +async def clock_in_end_output_spi(caravelEnv): + # Right side: GPIO 0 configured disabled + # /Left side: GPIO 37 configured as output + await clock11_spi(caravelEnv) + await clock11_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock00_spi(caravelEnv) + await clock01_spi(caravelEnv) + await clock11_spi(caravelEnv) + await load_spi(caravelEnv) diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu.c b/verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu.c new file mode 100644 index 00000000..1aa21f5b --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu.c @@ -0,0 +1,10 @@ +#include +#include + +// Empty C code + +void main() +{ + return; +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_i.c b/verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_i.c new file mode 100644 index 00000000..1aa21f5b --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_i.c @@ -0,0 +1,10 @@ +#include +#include + +// Empty C code + +void main() +{ + return; +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_o.c b/verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_o.c new file mode 100644 index 00000000..59a806fe --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_no_cpu_all_o.c @@ -0,0 +1,9 @@ +#include +#include + +// Empty C code + +void main() +{ + return; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_spi.c b/verilog/dv/cocotb/tests/bitbang/bitbang_spi.c new file mode 100644 index 00000000..1aa21f5b --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_spi.c @@ -0,0 +1,10 @@ +#include +#include + +// Empty C code + +void main() +{ + return; +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py new file mode 100644 index 00000000..a0232e90 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py @@ -0,0 +1,375 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +reg = Regs() + +@cocotb.test() +@repot_test +async def bitbang_no_cpu_all_o(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + + + #Configure all as output except reg_mprj_io_3 + await clear_registers(cpu) + await clock_in_right_o_left_o_standard(cpu,0) # 18 and 19 + await clock_in_right_o_left_o_standard(cpu,0) # 17 and 20 + await clock_in_right_o_left_o_standard(cpu,0) # 16 and 21 + await clock_in_right_o_left_o_standard(cpu,0) # 15 and 22 + await clock_in_right_o_left_o_standard(cpu,0) # 14 and 23 + await clock_in_right_o_left_o_standard(cpu,0) # 13 and 24 + await clock_in_right_o_left_o_standard(cpu,0) # 12 and 25 + await clock_in_right_o_left_o_standard(cpu,0) # 11 and 26 + await clock_in_right_o_left_o_standard(cpu,0) # 10 and 27 + await clock_in_right_o_left_o_standard(cpu,0) # 9 and 28 + await clock_in_right_o_left_o_standard(cpu,0) # 8 and 29 + await clock_in_right_o_left_o_standard(cpu,0) # 7 and 30 + await clock_in_right_o_left_o_standard(cpu,0) # 6 and 31 + await clock_in_right_o_left_o_standard(cpu,0) # 5 and 32 + await clock_in_right_o_left_o_standard(cpu,0) # 4 and 33 + await clock_in_right_o_left_i_standard(cpu,0) # 3 and 34 + await clock_in_right_o_left_i_standard(cpu,0) # 2 and 35 + await clock_in_right_o_left_i_standard(cpu,0) # 1 and 36 + await clock_in_end_output(cpu) # 0 and 37 and load + + await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) + + i= 0x20 + for j in range(5): + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),i) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} int {caravelEnv.monitor_gpio((37,4)).integer} i = {i}') + if caravelEnv.monitor_gpio((37,4)).integer != i << 28: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}') + # for k in range(250): + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0) + if caravelEnv.monitor_gpio((37,4)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x20 + await ClockCycles(caravelEnv.clk, 1) + + i= 0x80000000 + for j in range(32): + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3f) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),i) + if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)}') + if caravelEnv.monitor_gpio((31,4)).integer != i>>4 : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {i>>4}') + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} type {int(caravelEnv.monitor_gpio((37,4)))} i = {i}') + await ClockCycles(caravelEnv.clk, 1) + + # await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0) + await ClockCycles(caravelEnv.clk, 1) + + if caravelEnv.monitor_gpio((37,4)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x80000000 + + + await ClockCycles(caravelEnv.clk, 1000) + + + +@cocotb.test() +@repot_test +async def bitbang_no_cpu_all_i(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + + + #Configure all as input except reg_mprj_io_3 + await clear_registers(cpu) + await clock_in_right_i_left_i_standard(cpu,0) # 18 and 19 + await clock_in_right_i_left_i_standard(cpu,0) # 17 and 20 + await clock_in_right_i_left_i_standard(cpu,0) # 16 and 21 + await clock_in_right_i_left_i_standard(cpu,0) # 15 and 22 + await clock_in_right_i_left_i_standard(cpu,0) # 14 and 23 + await clock_in_right_i_left_i_standard(cpu,0) # 13 and 24 + await clock_in_right_i_left_i_standard(cpu,0) # 12 and 25 + await clock_in_right_i_left_i_standard(cpu,0) # 11 and 26 + await clock_in_right_i_left_i_standard(cpu,0) # 10 and 27 + await clock_in_right_i_left_i_standard(cpu,0) # 9 and 28 + await clock_in_right_i_left_i_standard(cpu,0) # 8 and 29 + await clock_in_right_i_left_i_standard(cpu,0) # 7 and 30 + await clock_in_right_i_left_i_standard(cpu,0) # 6 and 31 + await clock_in_right_i_left_i_standard(cpu,0) # 5 and 32 + await clock_in_right_i_left_i_standard(cpu,0) # 4 and 33 + await clock_in_right_i_left_i_standard(cpu,0) # 3 and 34 + await clock_in_right_i_left_i_standard(cpu,0) # 2 and 35 + await clock_in_right_i_left_i_standard(cpu,0) # 1 and 36 + await clock_in_right_i_left_i_standard(cpu,0) # 0 and 37 + await load(cpu) # load + + caravelEnv.drive_gpio_in((31,0),0x8F66FD7B) + await ClockCycles(caravelEnv.clk, 100) + reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal')) + # value_masked = reg_mprj_datal & mask_input + if reg_mprj_datal == 0x8F66FD7B: + cocotb.log.info(f'[TEST] Passed with value 0x8F66FD7B') + else: + cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0x8F66FD7B)}') + await ClockCycles(caravelEnv.clk, 100) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x1B) + x = caravelEnv.monitor_gpio((37,32)) + print(f"xxxxxxxx {x}") + await ClockCycles(caravelEnv.clk, 100) + + caravelEnv.drive_gpio_in((31,0),0xFFA88C5A) + await ClockCycles(caravelEnv.clk, 100) + reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal')) + # value_masked = reg_mprj_datal & mask_input + if reg_mprj_datal == 0xFFA88C5A: + cocotb.log.info(f'[TEST] Passed with value 0xFFA88C5A') + else: + cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xFFA88C5A)}') + + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x2B) + await ClockCycles(caravelEnv.clk, 100) + + caravelEnv.drive_gpio_in((31,0),0xC9536346) + await ClockCycles(caravelEnv.clk, 100) + reg_mprj_datal = await cpu.read_address(reg.get_addr('reg_mprj_datal')) + # value_masked = reg_mprj_datal & mask_input + if reg_mprj_datal == 0xC9536346: + cocotb.log.info(f'[TEST] Passed with value 0xC9536346') + else: + cocotb.log.error(f'[TEST] fail with value mprj = {bin(reg_mprj_datal)} instead of {bin(0xC9536346)}') + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3B) + await ClockCycles(caravelEnv.clk, 100) + + + + +"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" +@cocotb.test() +@repot_test +async def io_ports(dut): + caravelEnv = await test_configure(dut) + cpu = RiskV(dut) + cpu.cpu_force_reset() + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value) + + # Apply configuration + await cpu.drive_data2address(reg.get_addr('reg_mprj_xfer'),1) + + while True: + if await cpu.read_address(reg.get_addr('reg_mprj_xfer')) != 1 : + break + +"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI.""" +@cocotb.test() +@repot_test +async def bitbang_spi(dut): + caravelEnv = await test_configure(dut) + # Apply data 0x1809 (management standard output) to first block of + # user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards) + cpu = RiskV(dut) + cpu.cpu_force_reset() + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) + + + #Configure all as output except reg_mprj_io_3 + await clear_registers(cpu) + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 18 and 19 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 17 and 20 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 16 and 21 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 15 and 22 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 14 and 23 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 13 and 24 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 12 and 25 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 11 and 26 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 10 and 27 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 9 and 28 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 8 and 29 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 7 and 30 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 6 and 31 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 5 and 32 + await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 4 and 33 + await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 3 and 34 + await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 2 and 35 + await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 1 and 36 + await clock_in_end_output_spi(caravelEnv) # 0 and 37 and load + + await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) + + i= 0x20 + for j in range(5): + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),i) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} int {caravelEnv.monitor_gpio((37,5)).integer} i = {i}') + if caravelEnv.monitor_gpio((37,5)).integer != i << 27: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,5))} instead of {bin(i << 27)}') + # for k in range(250): + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0) + if caravelEnv.monitor_gpio((37,5)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x20 + await ClockCycles(caravelEnv.clk, 1) + + i= 0x80000000 + for j in range(32): + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3f) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),i) + if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)}') + if caravelEnv.monitor_gpio((31,5)).integer != i>>5 : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,5))} instead of {i>>5}') + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} type {int(caravelEnv.monitor_gpio((37,5)))} i = {i}') + await ClockCycles(caravelEnv.clk, 1) + + # await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0) + await ClockCycles(caravelEnv.clk, 1) + + if caravelEnv.monitor_gpio((37,5)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x80000000 + + + await ClockCycles(caravelEnv.clk, 1000) + + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py new file mode 100644 index 00000000..7260f281 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -0,0 +1,199 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +reg = Regs() + +@cocotb.test() +@repot_test +async def bitbang_cpu_all_o(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + await wait_reg1(cpu,caravelEnv,0xFF) + cocotb.log.info("[TEST] finish configuring using bitbang") + i= 0x20 + for j in range(5): + await wait_reg2(cpu,caravelEnv,37-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}') + if caravelEnv.monitor_gpio((37,4)).integer != i << 28: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,4)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + i = i >> 1 + i |= 0x20 + + i= 0x80000000 + for j in range(32): + await wait_reg2(cpu,caravelEnv,32-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}') + if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ') + if caravelEnv.monitor_gpio((31,4)).integer != i>>4 : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,4)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x80000000 + + + await ClockCycles(caravelEnv.clk, 10) + + +@cocotb.test() +@repot_test +async def bitbang_cpu_all_10(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + uut = dut.uut + await wait_reg1(cpu,caravelEnv,0xFF) + gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]") + + gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]") + type = True # type of shifting 01 or 10 + for gpio in gpios_l: + shift(uut._id(gpio,False),type) + type = not type + type = True # type of shifting 01 or 10 + for gpio in reversed(gpios_h): + shift(uut._id(gpio,False),type) + type = not type + + +def shift(gpio,shift_type): + if shift_type: + bits = "0101010101010" + else: + bits = "1010101010101" + fail = False + cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}") + for i in range(13): + if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]: + fail = True + cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}") + if not fail: + cocotb.log.info(f"[TEST] gpio {gpio} passed") + +@cocotb.test() +@repot_test +async def bitbang_cpu_all_01(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + uut = dut.uut + await wait_reg1(cpu,caravelEnv,0xFF) + gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]") + + gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]") + type = False # type of shifting 01 or 10 + for gpio in gpios_l: + shift(uut._id(gpio,False),type) + type = not type + type = False # type of shifting 01 or 10 + for gpio in reversed(gpios_h): + shift(uut._id(gpio,False),type) + type = not type + +@cocotb.test() +@repot_test +async def bitbang_cpu_all_0011(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + uut = dut.uut + await wait_reg1(cpu,caravelEnv,0xFF) + gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]") + + gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]") + type = 0 # type of shifting 01 or 10 + for gpio in gpios_l: + shift_2(uut._id(gpio,False),type) + type = (type + 1) %4 + type = 0 # type of shifting 01 or 10 + for gpio in reversed(gpios_h): + shift_2(uut._id(gpio,False),type) + type = (type + 1) %4 + +@cocotb.test() +@repot_test +async def bitbang_cpu_all_1100(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + uut = dut.uut + await wait_reg1(cpu,caravelEnv,0xFF) + gpios_l = ("gpio_control_bidir_1[0]","gpio_control_bidir_1[1]","gpio_control_in_1a[0]","gpio_control_in_1a[1]","gpio_control_in_1a[2]","gpio_control_in_1a[3]","gpio_control_in_1a[4]","gpio_control_in_1a[5]","gpio_control_in_1[0]","gpio_control_in_1[1]","gpio_control_in_1[2]","gpio_control_in_1[3]","gpio_control_in_1[4]","gpio_control_in_1[5]","gpio_control_in_1[6]","gpio_control_in_1[7]","gpio_control_in_1[8]","gpio_control_in_1[9]","gpio_control_in_1[10]") + + gpios_h= ("gpio_control_in_2[0]","gpio_control_in_2[1]","gpio_control_in_2[2]","gpio_control_in_2[3]","gpio_control_in_2[4]","gpio_control_in_2[5]","gpio_control_in_2[6]","gpio_control_in_2[7]","gpio_control_in_2[8]","gpio_control_in_2[9]","gpio_control_in_2[10]","gpio_control_in_2[11]","gpio_control_in_2[12]","gpio_control_in_2[13]","gpio_control_in_2[14]","gpio_control_in_2[15]","gpio_control_bidir_2[0]","gpio_control_bidir_2[1]","gpio_control_bidir_2[2]") + type = 2 # type of shifting 01 or 10 + for gpio in gpios_l: + shift_2(uut._id(gpio,False),type) + type = (type + 1) %4 + type = 2 # type of shifting 01 or 10 + for gpio in reversed(gpios_h): + shift_2(uut._id(gpio,False),type) + type = (type + 1) %4 + +def shift_2(gpio,shift_type): + if shift_type == 0: + bits = "1001100110011" + elif shift_type == 1: + bits = "1100110011001" + elif shift_type == 2: + bits = "0110011001100" + elif shift_type == 3: + bits = "0011001100110" + fail = False + cocotb.log.info(f"[TEST] gpio {gpio} shift {gpio._id(f'shift_register',False).value} expected {bits}") + for i in range(13): + if gpio._id(f"shift_register",False).value.binstr[i] != bits[i]: + fail = True + cocotb.log.error(f"[TEST] wrong shift register {i} in {gpio}") + if not fail: + cocotb.log.info(f"[TEST] gpio {gpio} passed") + + +@cocotb.test() +@repot_test +async def bitbang_cpu_all_i(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + uut = dut.uut + await wait_reg1(cpu,caravelEnv,0xAA) + cocotb.log.info(f"[TEST] configuration finished") + data_in = 0x8F66FD7B + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xBB) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + data_in = 0xFFA88C5A + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xCC) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + data_in = 0xC9536346 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + + await wait_reg2(cpu,caravelEnv,0xFF) + cocotb.log.info(f"[TEST] finish") + diff --git a/verilog/dv/cocotb/tests/common_functions/Timeout.py b/verilog/dv/cocotb/tests/common_functions/Timeout.py new file mode 100644 index 00000000..beea7307 --- /dev/null +++ b/verilog/dv/cocotb/tests/common_functions/Timeout.py @@ -0,0 +1,32 @@ + +# from turtle import st +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cocotb.result import SimTimeoutError +import cocotb +import time +"""class to handle timeout inside the tests. after the provided number of cycles (cycle_num) are exceeded test would fail + precision would determine when to log timeout warning for example if cycle_num=1000 and percision = 10% so after each 1000*10% = 100 cycle log would be printed +""" +class Timeout: + def __init__(self,clk,cycle_num,precision=0.20): + self.clk = clk + self.cycle_num = cycle_num + self.cycle_precision = precision * cycle_num + cocotb.scheduler.add(self._timeout_check()) + + + async def _timeout_check(self): + number_of_cycles = 0 + for i in range(0,self.cycle_num): + await ClockCycles(self.clk,1) + number_of_cycles +=1 + if number_of_cycles %self.cycle_precision ==0: + cocotb.log.warning(f"simulation are only {self.cycle_num-number_of_cycles} cycles away from TIMEOUT ") + + raise SimTimeoutError(f"simulation exceeds the max number of cycles {self.cycle_num}") + + pass + + + diff --git a/verilog/dv/cocotb/tests/common_functions/test_functions.py b/verilog/dv/cocotb/tests/common_functions/test_functions.py new file mode 100644 index 00000000..78de0932 --- /dev/null +++ b/verilog/dv/cocotb/tests/common_functions/test_functions.py @@ -0,0 +1,95 @@ + +import random +import cocotb +from cocotb.clock import Clock +import cocotb.log +import caravel +from logic_analyzer import LA +from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox +import common +import logging +from cpu import RiskV +from cocotb.log import SimTimeContextFilter +from cocotb.log import SimLogFormatter +from tests.common_functions.Timeout import Timeout +import os +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles + +"""configure the test log file location and log verbosity + configure the test clock + configure the test timeout + configure whitbox models + start up the test connecting power vdd to the design then reset and disable the CSB bit + return the caravel environmnet with clock and start up +""" +async def test_configure(dut,timeout_cycles=1000000,clk=12.5,timeout_precision=0.2,num_error=3): + caravelEnv = caravel.Caravel_env(dut) + Timeout(caravelEnv.clk,timeout_cycles,timeout_precision) + if os.getenv('ERRORMAX') != 'None': + num_error = int(os.getenv('ERRORMAX')) + cocotb.scheduler.add(max_num_error(num_error,caravelEnv.clk)) + clock = Clock(caravelEnv.clk, clk, units="ns") # Create a 10ns period clock on port clk + cocotb.start_soon(clock.start()) # Start the clock + await caravelEnv.start_up() + await ClockCycles(caravelEnv.clk, 10) + # HK_whiteBox(dut) + return caravelEnv + +class CallCounted: + """Decorator to determine number of calls for a method""" + + def __init__(self,method): + self.method=method + self.counter=0 + + def __call__(self,*args,**kwargs): + self.counter+=1 + return self.method(*args,**kwargs) + + +def repot_test(func): + async def wrapper_func(*args, **kwargs): + ## configure logging + COCOTB_ANSI_OUTPUT=0 + + TestName = func.__name__ + cocotb.log.setLevel(logging.INFO) + cocotb.log.error = CallCounted(cocotb.log.error) + cocotb.log.critical = CallCounted(cocotb.log.critical) + cocotb.log.warning = CallCounted(cocotb.log.warning) + handler = logging.FileHandler(f"sim/{os.getenv('RUNTAG')}/{os.getenv('SIM')}-{TestName}/{TestName}.log",mode='w') + handler.addFilter(SimTimeContextFilter()) + handler.setFormatter(SimLogFormatter()) + cocotb.log.addHandler(handler) + ## call test + await func(*args, **kwargs) + ## report after finish simulation + msg = f'with ({cocotb.log.critical.counter})criticals ({cocotb.log.error.counter})errors ({cocotb.log.warning.counter})warnings ' + if cocotb.log.error.counter > 0 or cocotb.log.critical.counter >0: + raise cocotb.result.TestComplete(f'Test failed {msg}') + else: + raise cocotb.result.TestComplete(f'Test passed {msg}') + return retval + return wrapper_func + +async def max_num_error(num_error,clk): + while True: + await ClockCycles(clk,1) + if cocotb.log.error.counter + cocotb.log.critical.counter > num_error: + msg = f'Test failed with max number of errors {num_error} ({cocotb.log.critical.counter})criticals ({cocotb.log.error.counter})errors ({cocotb.log.warning.counter})warnings ' + raise cocotb.result.TestFailure(msg) + + +async def wait_reg1(cpu,caravelEnv,data): + while (True): + if cpu.read_debug_reg1() == data: + return + await ClockCycles(caravelEnv.clk,10) + + +async def wait_reg2(cpu,caravelEnv,data): + while (True): + if cpu.read_debug_reg2() == data: + return + await ClockCycles(caravelEnv.clk,10) + \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/cpu/cpu_stress.c b/verilog/dv/cocotb/tests/cpu/cpu_stress.c new file mode 100644 index 00000000..c7cc56b9 --- /dev/null +++ b/verilog/dv/cocotb/tests/cpu/cpu_stress.c @@ -0,0 +1,156 @@ +#include + +int A[]={1, 40, 2, 5, 22, 11, 90, 200, 10, 20, 25}; + +// int factorial(int n) { +// int fac=1; +// for(int i=1; i<=n;++i){ +// fac = fac * i; +// } +// return fac; +// } + +int fibbonacci(int n) { + if(n == 0){ + return 0; + } else if(n == 1) { + return 1; + } else { + return (fibbonacci(n-1) + fibbonacci(n-2)); + } +} + +void recursiveInsertionSort(int arr[], int n){ + if (n <= 1) + return; + recursiveInsertionSort( arr, n-1 ); + int nth = arr[n-1]; + int j = n-2; + while (j >= 0 && arr[j] > nth){ + arr[j+1] = arr[j]; + j--; + } + arr[j+1] = nth; +} + + +void quick_sort(int number[],int first,int last){ + int i, j, pivot, temp; + + if(firstnumber[pivot]) + j--; + if(i 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i.c new file mode 100644 index 00000000..dd6c9c22 --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i.c @@ -0,0 +1,63 @@ +#include +#include +#include "../bitbang/bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = 0x1803; + reg_mprj_io_36 = 0x1803; + reg_mprj_io_35 = 0x1803; + reg_mprj_io_34 = 0x1803; + reg_mprj_io_33 = 0x1803; + reg_mprj_io_32 = 0x1803; + reg_mprj_io_31 = 0x1803; + reg_mprj_io_30 = 0x1803; + reg_mprj_io_29 = 0x1803; + reg_mprj_io_28 = 0x1803; + reg_mprj_io_27 = 0x1803; + reg_mprj_io_26 = 0x1803; + reg_mprj_io_25 = 0x1803; + reg_mprj_io_24 = 0x1803; + reg_mprj_io_23 = 0x1803; + reg_mprj_io_22 = 0x1803; + reg_mprj_io_21 = 0x1803; + reg_mprj_io_20 = 0x1803; + reg_mprj_io_19 = 0x1803; + reg_mprj_io_18 = 0x1803; + reg_mprj_io_17 = 0x1803; + reg_mprj_io_16 = 0x1803; + reg_mprj_io_15 = 0x1803; + reg_mprj_io_14 = 0x1803; + reg_mprj_io_13 = 0x1803; + reg_mprj_io_12 = 0x1803; + reg_mprj_io_11 = 0x1803; + reg_mprj_io_10 = 0x1803; + reg_mprj_io_9 = 0x1803; + reg_mprj_io_8 = 0x1803; + reg_mprj_io_7 = 0x1803; + reg_mprj_io_6 = 0x1803; + reg_mprj_io_5 = 0x1803; + reg_mprj_io_4 = 0x1803; + reg_mprj_io_3 = 0x1803; + reg_mprj_io_2 = 0x1803; + reg_mprj_io_1 = 0x1803; + reg_mprj_io_0 = 0x1803; + reg_mprj_io_0 = 0x1803; + + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal + while (reg_mprj_datal != 0x8F66FD7B); + reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal + while (reg_mprj_datal != 0xFFA88C5A); + reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal + while (reg_mprj_datal != 0xC9536346); + + reg_debug_2 = 0xFF; +} + diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_o.c b/verilog/dv/cocotb/tests/gpio/gpio_all_o.c new file mode 100644 index 00000000..14014a89 --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_o.c @@ -0,0 +1,79 @@ +#include +#include +#include "../bitbang/bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_3 = 0x1803 ; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_debug_1 = 0xFF; // finish configuration + reg_mprj_datal = 0x0; + reg_mprj_datah = 0x0; + i = 0x20; + for (j = 0; j < 5; j++) { + reg_mprj_datah = i; + reg_debug_2 = 37-j; + reg_mprj_datah = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x20; + } + i = 0x80000000; + for (j = 0; j < 32; j++) { + reg_mprj_datah = 0x3f; + reg_mprj_datal = i; + reg_debug_2 = 32-j; + reg_mprj_datah = 0x00; + reg_mprj_datal = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x80000000; + } + +} + diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_o.py b/verilog/dv/cocotb/tests/gpio/gpio_all_o.py new file mode 100644 index 00000000..6757cf15 --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_o.py @@ -0,0 +1,83 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +reg = Regs() + +@cocotb.test() +@repot_test +async def gpio_all_o(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + await wait_reg1(cpu,caravelEnv,0xFF) + cocotb.log.info("[TEST] finish configuring using bitbang") + i= 0x20 + for j in range(5): + await wait_reg2(cpu,caravelEnv,37-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}') + if caravelEnv.monitor_gpio((37,4)).integer != i << 28: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,4)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + i = i >> 1 + i |= 0x20 + + i= 0x80000000 + for j in range(32): + await wait_reg2(cpu,caravelEnv,32-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}') + if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ') + if caravelEnv.monitor_gpio((31,4)).integer != i>>4 : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,4)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x80000000 + + + await ClockCycles(caravelEnv.clk, 10) + + +@cocotb.test() +@repot_test +async def gpio_all_i(dut): + caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + uut = dut.uut + await wait_reg1(cpu,caravelEnv,0xAA) + cocotb.log.info(f"[TEST] configuration finished") + data_in = 0x8F66FD7B + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xBB) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + data_in = 0xFFA88C5A + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xCC) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + data_in = 0xC9536346 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + + await wait_reg2(cpu,caravelEnv,0xFF) + cocotb.log.info(f"[TEST] finish") + + + diff --git a/verilog/dv/cocotb/tests/hello_world/helloWorld.c b/verilog/dv/cocotb/tests/hello_world/helloWorld.c new file mode 100644 index 00000000..ad547c3c --- /dev/null +++ b/verilog/dv/cocotb/tests/hello_world/helloWorld.c @@ -0,0 +1,5 @@ + +int main(){ + // do nothing + return 0; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/hello_world/helloWorld.py b/verilog/dv/cocotb/tests/hello_world/helloWorld.py new file mode 100644 index 00000000..878a127a --- /dev/null +++ b/verilog/dv/cocotb/tests/hello_world/helloWorld.py @@ -0,0 +1,11 @@ +import cocotb +from tests.common_functions.test_functions import * + +@cocotb.test() +@repot_test + +async def helloWorld(dut): + caravelEnv = await test_configure(dut) + cocotb.log.info("[Test] Hello world") + caravelEnv.print_gpios_ctrl_val() + caravelEnv.print_gpios_HW_val() \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c new file mode 100644 index 00000000..1aa21f5b --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_rst_spi.c @@ -0,0 +1,10 @@ +#include +#include + +// Empty C code + +void main() +{ + return; +} + diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c new file mode 100644 index 00000000..1aa21f5b --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_spi.c @@ -0,0 +1,10 @@ +#include +#include + +// Empty C code + +void main() +{ + return; +} + diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c new file mode 100644 index 00000000..1aa21f5b --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb.c @@ -0,0 +1,10 @@ +#include +#include + +// Empty C code + +void main() +{ + return; +} + diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py new file mode 100644 index 00000000..6786bb82 --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -0,0 +1,189 @@ +from json.encoder import INFINITY +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE +import json + +reg = Regs() + + +'''randomly write then read housekeeping regs through wishbone''' +@cocotb.test() +@repot_test +async def hk_regs_wr_wb(dut): + caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY) + cpu = RiskV(dut) + cpu.cpu_force_reset() + with open('wb_models/housekeepingWB/HK_regs.json') as f: + regs = json.load(f) + await ClockCycles(caravelEnv.clk, 10) + # write then read + for i in range(random.randint(7, 20)): + bits_num = 32 + mem = random.choice(['GPIO']) # can't access 'SPI' and 'sys' register from cpu / read or write + key = random.choice(list(regs[mem].keys())) + if key == 'base_addr': + continue + key_num = int(key,16) & 0xFC + key = generate_key_from_num(key_num) + address = (int(key,16) + regs[mem]['base_addr'][1]) + if address in [0x26000010,0x2600000c]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value + continue + data_in = random.getrandbits(bits_num) + cocotb.log.info(f"[TEST] Writing {bin(data_in)} to {regs[mem][key][0][0]} address {hex(address)} through wishbone") + await cpu.drive_data2address(address,data_in) + #calculate the expected value for each bit + data_exp = '' + keys = [generate_key_from_num(key_num+3),generate_key_from_num(key_num+2),generate_key_from_num(key_num+1),generate_key_from_num(key_num)] + for count , k in enumerate(keys): + for i in range(int(bits_num/len(keys)) * (count),int(bits_num/len(keys)) * (count+1)): + bit_exist = False + if k in regs[mem].keys(): + for field in regs[mem][k]: + field_shift = field[2] + field_size = field[3] + field_access = field[4] + i_temp = (bits_num -1 -i) % (bits_num/4) + if field_shift <= i_temp and i_temp <= (field_shift + field_size-1): + if field_access == "RW": + data_exp += bin(data_in)[2:].zfill(bits_num)[i] + bit_exist = True + break + if not bit_exist: + data_exp += '0' + + cocotb.log.info(f"[TEST] expected data calculated = {data_exp}") + data_out = await cpu.read_address(address) + cocotb.log.info(f"[TEST] Read {bin(data_out)} from {regs[mem][key][0][0]} address {hex(address)} through wishbone") + if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from {regs[mem][key][0][0]} address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}") + else: cocotb.log.debug(f"[TEST] read the right value {hex(data_out)} from {regs[mem][key][0][0]} address {address} ") + +'''randomly write then read housekeeping regs through SPI''' +@cocotb.test() +@repot_test +async def hk_regs_wr_spi(dut): + caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY) + + with open('wb_models/housekeepingWB/HK_regs.json') as f: + regs = json.load(f) + # write then read single byte + for i in range(random.randint(10, 40)): + bits_num = 8 # byte testing + mem = random.choice(['GPIO','SPI','sys']) + key = random.choice(list(regs[mem].keys())) + if key == 'base_addr': + continue + address = regs[mem][key][0][7] + if address in [0x69,0x6A,0x6B,0x6C]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value + continue + data_in = random.getrandbits(bits_num) + cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI") + await write_reg_spi(caravelEnv,address=address,data=data_in) + #calculate the expected value for each bit + data_exp = '' + for i in range(bits_num): + bit_exist = False + for field in regs[mem][key]: + field_shift = field[2] + field_size = field[3] + field_access = field[4] + reset_val = field[5] + i_temp = bits_num -1 -i + if field_shift <= i_temp and i_temp <= (field_shift + field_size-1): + if field_access == "RW": + data_exp += bin(data_in)[2:].zfill(bits_num)[i] + bit_exist = True + break + else : # read only get the value from reset + data_exp += bin(reset_val)[2:].zfill(bits_num)[i] + if not bit_exist: + data_exp += '0' + + cocotb.log.info(f"[TEST] expected data calculated = {data_exp}") + data_out = await read_reg_spi(caravelEnv,address=address) + cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through SPI") + if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from [{regs[mem][key][0][0]}] address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}") + else: cocotb.log.debug(f"[TEST] read the right value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ") + +'''check reset value of house keeping register''' +@cocotb.test() +@repot_test +async def hk_regs_rst_spi(dut): + caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY) + + with open('wb_models/housekeepingWB/HK_regs.json') as f: + regs = json.load(f) + # read + bits_num = 8 # byte testing + mems = ['GPIO','SPI','sys'] + + for mem in mems: + keys = [k for k in regs[mem].keys()] + for key in keys: + if key == 'base_addr': + continue + address = regs[mem][key][0][7] + if address in [0x69,0x6A,0x6B,0x6C,0x6D,0x1A]: # skip testing reg_mprj_datal, reg_mprj_datah and usr2_vdd_pwrgood because when reading them it's getting the gpio input value + continue + #calculate the expected value for each bit for reset value + data_exp = '' + # for i in range(bits_num): + bit_exist = False + for field in regs[mem][key]: + field_shift = field[2] + field_size = field[3] + field_access = field[4] + reset_val = field[5] + i_temp = bits_num -1 #-i + # if field_shift <= i_temp and i_temp <= (field_shift + field_size-1): + data_exp = bin(reset_val)[2:].zfill(field_size) + data_exp + print (f'reset = {bin(reset_val)[2:].zfill(bits_num)} data exp = {data_exp} i temp = {i_temp} shift {field_shift} size {field_size}') + # bit_exist = True + # break + # if not bit_exist: + # data_exp += '0' + + cocotb.log.info(f"[TEST] expected reset value for [{regs[mem][key][0][0]}] is {data_exp}") + data_out = await read_reg_spi(caravelEnv,address=address) + cocotb.log.info(f"[TEST] Read {bin(data_out)} from [{regs[mem][key][0][0]}] address {hex(address)} through wishbone") + if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong reset value read from [{regs[mem][key][0][0]}] address {address} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}") + else: cocotb.log.info(f"[TEST] read the right reset value {hex(data_out)} from [{regs[mem][key][0][0]}] address {address} ") + + + + +async def write_reg_spi(caravelEnv,address,data): + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + + +async def read_reg_spi(caravelEnv,address): + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x40) # read stream command + await caravelEnv.hk_write_byte(address) # Address + data = await caravelEnv.hk_read_byte() # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + return data + + +def generate_key_from_num(num): + hex_string = hex(num) + hex_list = [i for i in hex_string] + if len(hex_list)==3: + hex_list.insert(2,'0') + hex_string = "".join(hex_list) + return hex_string + + + + diff --git a/verilog/dv/cocotb/tests/irq/IRQ_external.c b/verilog/dv/cocotb/tests/irq/IRQ_external.c new file mode 100644 index 00000000..b717d875 --- /dev/null +++ b/verilog/dv/cocotb/tests/irq/IRQ_external.c @@ -0,0 +1,103 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include + +/* +Testing timer interrupts +Enable interrupt for IRQ external pin mprj_io[7] -> should be drived to 1 by the environment +**NOTE** housekeeping SPI should used to update register irq_1_inputsrc to 1 see verilog code + + @wait for environment to make mprj[7] high + send packet size = 1 + + @received interrupt correctly test pass + send packet size = 5 + + @ timeout test fail + send packet size = 9 + + @ end test + send packet size = 3 + send packet size = 3 + send packet size = 3 + +*/ + +extern uint16_t flag; + +void main(){ + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + // setting bit 7 as input + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + + // automatic bitbang approach + if(1){ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + } + irq_setmask(0); + irq_setie(1); + irq_setmask(irq_getmask() | (1 << USER_IRQ_4_INTERRUPT)); + reg_user4_irq_en =1; + + // test interrrupt happen when mprj[7] is asserted + reg_debug_2 = 0xAA; //wait for environment to make mprj[7] high + flag = 0; + // Loop, waiting for the interrupt to change reg_mprj_datah + bool is_pass = false; + int timeout = 40; + + for (int i = 0; i < timeout; i++){ + if (flag == 1){ + reg_debug_1 = 0x1B; //test pass irq sent at mprj 7 + is_pass = true; + break; + } + } + if (!is_pass){ + reg_debug_1 = 0x1E; // timeout + } + + // test interrupt doesn't happened when mprj[7] is deasserted + reg_debug_2 = 0xBB; + flag = 0; + // Loop, waiting for the interrupt to change reg_mprj_datah + is_pass = false; + + for (int i = 0; i < timeout; i++){ + if (flag == 1){ + reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened + is_pass = true; + break; + } + } + if (!is_pass){ + reg_debug_1 = 0x2B; // test pass + } + + // test finish + reg_debug_2 = 0xFF; +} diff --git a/verilog/dv/cocotb/tests/irq/IRQ_external.py b/verilog/dv/cocotb/tests/irq/IRQ_external.py new file mode 100644 index 00000000..a1d959a0 --- /dev/null +++ b/verilog/dv/cocotb/tests/irq/IRQ_external.py @@ -0,0 +1,75 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +async def write_reg_spi(caravelEnv,address,data): + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + +reg = Regs() +"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" +@cocotb.test() +@repot_test +async def IRQ_external(dut): + caravelEnv = await test_configure(dut,timeout_cycles=18613481) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start IRQ_external test") + pass_list = (0x1B,0x2B) + fail_list = (0x1E,0x2E) + phases_fails = 2 + phases_passes = 0 + reg1 =0 # buffer + reg2 = 0 #buffer + await ClockCycles(caravelEnv.clk,10) + + await write_reg_spi(caravelEnv,0x1c,1) + await ClockCycles(caravelEnv.clk,10) + cocotb.log.info(f"irq 1 = {dut.uut.housekeeping.irq_1_inputsrc.value}") + + while True: + if reg2 != cpu.read_debug_reg2(): + reg2 = cpu.read_debug_reg2() + if reg2 == 0xFF: # test finish + break + if reg2 == 0xAA: # assert mprj 7 + caravelEnv.drive_gpio_in((7,7),0) + await ClockCycles(caravelEnv.clk,10) + caravelEnv.drive_gpio_in((7,7),1) + + if reg2 == 0xBB: # deassert mprj 7 + caravelEnv.drive_gpio_in((7,7),0) + + if reg1 != cpu.read_debug_reg1(): + reg1 = cpu.read_debug_reg1() + if reg1 in pass_list: # pass phase + phases_passes +=1 + phases_fails -=1 + if reg1 == 0x1B: + cocotb.log.info(f"[TEST] Pass interrupt is detected when mprj 7 asserted") + elif reg1 == 0x2B: + cocotb.log.info(f"[TEST] Pass interrupt isn't detected when mprj 7 deasserted") + elif reg1 in fail_list: # pass phase + if reg1 == 0x1E: + cocotb.log.info(f"[TEST] Failed interrupt isn't detected when mprj 7 asserted") + elif reg1 == 0x2E: + cocotb.log.error(f"[TEST] Failed interrupt is detected when mprj 7 deasserted") + else: + cocotb.log.error(f"[TEST] debug register 1 has illegal value") + await ClockCycles(caravelEnv.clk,10) + + if phases_fails != 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/irq/IRQ_timer.c b/verilog/dv/cocotb/tests/irq/IRQ_timer.c new file mode 100644 index 00000000..34a9523e --- /dev/null +++ b/verilog/dv/cocotb/tests/irq/IRQ_timer.c @@ -0,0 +1,88 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include + +#include + + +extern uint16_t flag; + +void main(){ + uint16_t data; + int i; + + + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + irq_setmask(0); + irq_setie(1); + + + irq_setmask(irq_getmask() | (1 << TIMER0_INTERRUPT)); + reg_debug_2 = 0xAA; //wait for timer to send irq + + flag = 0; + /* Configure timer for a single-shot countdown */ + reg_timer0_config = 0; + reg_timer0_data = 30; + reg_timer0_irq_en = 1; + reg_timer0_config = 1; + + // Loop, waiting for the interrupt to change reg_mprj_datah + bool is_pass = false; + int timeout = 40; + + for (int i = 0; i < timeout; i++){ + if (flag == 1){ + reg_debug_1 = 0x1B; //test pass irq sent at timer0 + is_pass = true; + break; + } + } + if (!is_pass){ + reg_debug_1 = 0x1E; // timeout + } + flag = 0; + // test interrupt doesn't happened when timer isnt used + reg_debug_2 = 0xBB; + reg_timer0_config = 0; // disable counter + flag = 0; + // Loop, waiting for the interrupt to change reg_mprj_datah + is_pass = false; + + for (int i = 0; i < timeout; i++){ + if (flag == 1){ + reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened + is_pass = true; + break; + } + } + if (!is_pass){ + reg_debug_1 = 0x2B; // test pass + } + + // test finish + reg_debug_2 = 0xFF; + +} + diff --git a/verilog/dv/cocotb/tests/irq/IRQ_timer.py b/verilog/dv/cocotb/tests/irq/IRQ_timer.py new file mode 100644 index 00000000..250f68c8 --- /dev/null +++ b/verilog/dv/cocotb/tests/irq/IRQ_timer.py @@ -0,0 +1,51 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +reg = Regs() +"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" +@cocotb.test() +@repot_test +async def IRQ_timer(dut): + caravelEnv = await test_configure(dut,timeout_cycles=18613481) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start IRQ_timer test") + pass_list = (0x1B,0x2B) + fail_list = (0x1E,0x2E) + phases_fails = 2 + phases_passes = 0 + reg1 =0 # buffer + while True: + if cpu.read_debug_reg2() == 0xFF: # test finish + break + if reg1 != cpu.read_debug_reg1(): + reg1 = cpu.read_debug_reg1() + if reg1 in pass_list: # pass phase + phases_passes +=1 + phases_fails -=1 + if reg1 == 0x1B: + cocotb.log.info(f"[TEST] Pass interrupt is detected when timer is used") + elif reg1 == 0x2B: + cocotb.log.info(f"[TEST] Pass interrupt isn't detected when timer isnt used") + elif reg1 in fail_list: # pass phase + if reg1 == 0x1E: + cocotb.log.info(f"[TEST] Failed interrupt isn't detected when timer is used") + elif reg1 == 0x2E: + cocotb.log.error(f"[TEST] Failed interrupt is detected when timer isnt used") + else: + cocotb.log.error(f"[TEST] debug register 1 has illegal value") + await ClockCycles(caravelEnv.clk,10) + + if phases_fails != 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/irq/IRQ_uart.c b/verilog/dv/cocotb/tests/irq/IRQ_uart.c new file mode 100644 index 00000000..dfd10990 --- /dev/null +++ b/verilog/dv/cocotb/tests/irq/IRQ_uart.c @@ -0,0 +1,89 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ +#include + +#include +#include +#include +#include +#include + + + + +extern uint16_t flag; + +void main(){ + + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = 0x1803; + + if(1){ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + } + reg_uart_enable = 1; + reg_uart_irq_en =1; + irq_setmask(0); + irq_setie(1); + + + irq_setmask(irq_getmask() | (1 << UART_INTERRUPT)); + flag = 0; + + reg_debug_2 = 0xAA; //start sending data through the uart + print("M"); + + // Loop, waiting for the interrupt to change reg_mprj_datah + bool is_pass = false; + int timeout = 100; + + for (int i = 0; i < timeout; i++){ + if (flag == 1){ + reg_debug_1 = 0x1B; //test pass irq sent + is_pass = true; + break; + } + } + if (!is_pass){ + reg_debug_1 = 0x1E; // timeout + } + // test interrupt doesn't happened nothing sent at uart + reg_debug_2 = 0xBB; + flag = 0; + // Loop, waiting for the interrupt to change reg_mprj_datah + is_pass = false; + + for (int i = 0; i < timeout; i++){ + if (flag == 1){ + reg_debug_1 = 0x2E; //test fail interrupt isn't suppose to happened + is_pass = true; + break; + } + } + if (!is_pass){ + reg_debug_1 = 0x2B; // test pass + } + // test finish + reg_debug_2 = 0xFF; + +} + diff --git a/verilog/dv/cocotb/tests/irq/IRQ_uart.py b/verilog/dv/cocotb/tests/irq/IRQ_uart.py new file mode 100644 index 00000000..0917239e --- /dev/null +++ b/verilog/dv/cocotb/tests/irq/IRQ_uart.py @@ -0,0 +1,64 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +async def write_reg_spi(caravelEnv,address,data): + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + +reg = Regs() +"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" +@cocotb.test() +@repot_test +async def IRQ_uart(dut): + caravelEnv = await test_configure(dut,timeout_cycles=18613481) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start IRQ_uart test") + pass_list = (0x1B,0x2B) + fail_list = (0x1E,0x2E) + phases_fails = 2 + phases_passes = 0 + reg1 =0 # buffer + reg2 = 0 #buffer + while True: + if reg2 != cpu.read_debug_reg2(): + reg2 = cpu.read_debug_reg2() + if reg2 == 0xFF: # test finish + break + if reg2 == 0xAA: + cocotb.log.info(f"[TEST] start sending through uart") + + if reg1 != cpu.read_debug_reg1(): + reg1 = cpu.read_debug_reg1() + if reg1 in pass_list: # pass phase + phases_passes +=1 + phases_fails -=1 + if reg1 == 0x1B: + cocotb.log.info(f"[TEST] Pass interrupt is detected when uart is sending data") + elif reg1 == 0x2B: + cocotb.log.info(f"[TEST] Pass interrupt isn't detected when uart isnt sending data") + elif reg1 in fail_list: # pass phase + if reg1 == 0x1E: + cocotb.log.info(f"[TEST] Failed interrupt isn't detected uart is sending data") + elif reg1 == 0x2E: + cocotb.log.error(f"[TEST] Failed interrupt is detected uart isnt sending data") + else: + cocotb.log.error(f"[TEST] debug register 1 has illegal value") + await ClockCycles(caravelEnv.clk,10) + + if phases_fails != 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/mem/mem_stress.c b/verilog/dv/cocotb/tests/mem/mem_stress.c new file mode 100644 index 00000000..83fe1ef5 --- /dev/null +++ b/verilog/dv/cocotb/tests/mem/mem_stress.c @@ -0,0 +1,102 @@ +#include + +/* + @ start of test + send packet with size = 1 + @ pass bytes + send packet with size = 2 + @ pass int + send packet with size = 3 + @ pass short + send packet with size = 4 + @ error reading + send packet with size = 9 + @ test finish + send packet with size = 7 + send packet with size = 7 + send packet with size = 7 + +*/ +#define BYTE_SIZE 800 +#define SHORT_SIZE BYTE_SIZE/2 +#define INT_SIZE BYTE_SIZE/4 +void main() +{ + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + unsigned char dff_bytes[BYTE_SIZE]; + unsigned short *dff_shorts=(unsigned short *) dff_bytes; + unsigned int *dff_ints=(unsigned int *) dff_bytes; + unsigned char magic = 0x79; + unsigned int magic_int = 0x79797979; + unsigned short magic_short = 0x7979; + unsigned char magic1; + unsigned int magic1_int; + unsigned short magic1_short; + int i; + magic1 = magic; + for ( i=0; i 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + +def phase_to_type(phase): + if phase == "1": + return "800 Bytes" + elif phase == "2": + return "200 Words" + elif phase == "3": + return "400 Halfwords" \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py new file mode 100644 index 00000000..1f67643b --- /dev/null +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py @@ -0,0 +1,105 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +reg = Regs() +"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" +@cocotb.test() +@repot_test +async def mgmt_gpio_out(dut): + caravelEnv = await test_configure(dut,timeout_cycles=18613481) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start mgmt_gpio_out test") + phases_fails = 2 + phases_passes = 0 + reg1 =0 # buffer + reg2 = 0 #buffer + + while True: + if reg2 != cpu.read_debug_reg2(): + reg2 = cpu.read_debug_reg2() + if reg2 == 0xFF: # test finish + break + if reg1 != cpu.read_debug_reg1(): + reg1 = cpu.read_debug_reg1() + cocotb.log.info(f"[TEST] waiting for {reg1} blinks") + for i in range(reg1): + while (True): + if caravelEnv.monitor_mgmt_gpio() == 0: + break + if reg1 != cpu.read_debug_reg1(): + cocotb.log.error("[TEST] error failing to catch all blinking ") + return + await ClockCycles(caravelEnv.clk,10) + + while (True): + if caravelEnv.monitor_mgmt_gpio() == 1: + break + if reg1 != cpu.read_debug_reg1(): + cocotb.log.error("[TEST] error failing to catch all blinking ") + return + await ClockCycles(caravelEnv.clk,10) + cocotb.log.info("[TEST] passing sending {reg1} blinks ") + phases_fails -=1 + await ClockCycles(caravelEnv.clk,10) + + if phases_fails != 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + + +@cocotb.test() +@repot_test +async def mgmt_gpio_in(dut): + caravelEnv = await test_configure(dut,timeout_cycles=18613481) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start mgmt_gpio_in test") + phases_fails = 3 + phases_passes = 0 + pass_list = (0x1B,0x2B,0xFF) + fail_list = tuple([0xEE]) + reg1 =0 # buffer + reg2 = 0 #buffer + + while True: + if reg2 != cpu.read_debug_reg2(): + reg2 = cpu.read_debug_reg2() + if reg2 in pass_list: + cocotb.log.info (f"[TEST] reg2 = {reg2}") + phases_passes +=1 + phases_fails -=1 + if reg2 == 0xFF: # test finish + break + elif reg2 == 0x1B: + cocotb.log.info(f"[TEST] pass sending 10 blink ") + elif reg2 == 0x2B: + cocotb.log.info(f"[TEST] pass sending 20 blink ") + if reg2 in fail_list: + cocotb.log.error(f"[TEST] gpio change without sending anything") + if reg1 != cpu.read_debug_reg1(): + reg1 = cpu.read_debug_reg1() + cocotb.log.info(f"[TEST] start sending {reg1} blinks") + for i in range(reg1): + caravelEnv.drive_mgmt_gpio(1) + await wait_reg2(cpu,caravelEnv,0XAA) + caravelEnv.drive_mgmt_gpio(0) + await wait_reg2(cpu,caravelEnv,0XBB) + cocotb.log.info(f"[TEST] finish sending {reg1} blinks ") + await ClockCycles(caravelEnv.clk,10) + + if phases_fails != 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_in.c b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_in.c new file mode 100644 index 00000000..584f0ed9 --- /dev/null +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_in.c @@ -0,0 +1,67 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +// -------------------------------------------------------- + +/* + * Management SoC GPIO Pin Test + * Tests writing to the GPIO pin. + */ + +void main() +{ + int temp_in; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_gpio_mode1 = 1; + reg_gpio_mode0 = 0; // for full swing + + reg_gpio_ien = 1; + reg_gpio_oe = 1; + + reg_debug_1 = 10; // wait for 10 blinks + for (int i = 0; i < 10; i++) { + while(reg_gpio_in == 0); + reg_debug_2 = 0XAA; // 1 is recieved + while(reg_gpio_in == 1); + reg_debug_2 = 0XBB; // 0 is recieved + } + reg_debug_2 = 0x1B; + reg_debug_1 = 20; + for (int i = 0; i < 20; i++) { + while(reg_gpio_in == 0); + reg_debug_2 = 0XAA; // 1 is recieved + while(reg_gpio_in == 1); + reg_debug_2 = 0XBB; // 0 is recieved + } + reg_debug_2 = 0x2B; + temp_in = reg_gpio_in; + reg_debug_1 = 0; + for (int i =0; i<50;i++){ // timeout + if (temp_in != reg_gpio_in) + reg_debug_2 = 0xEE; //finish test + + } + reg_debug_2 = 0xFF; //finish test + + +} + diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_out.c b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_out.c new file mode 100644 index 00000000..d31db357 --- /dev/null +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_out.c @@ -0,0 +1,59 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +// -------------------------------------------------------- + +/* + * Management SoC GPIO Pin Test + * Tests writing to the GPIO pin. + */ + +void main() +{ + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_gpio_mode1 = 1; + reg_gpio_mode0 = 0; // for full swing + + reg_gpio_ien = 1; + reg_gpio_oe = 1; + + reg_debug_1 = 10; + for (int i = 0; i < 10; i++) { + /* Fast blink for simulation */ + reg_gpio_out = 1; + reg_gpio_out = 0; + } + reg_debug_1 = 20; + for (int i = 0; i < 20; i++) { + /* Fast blink for simulation */ + reg_gpio_out = 1; + reg_gpio_out = 0; + } + reg_debug_1 = 0; + reg_debug_1 = 0; // for more delay + reg_debug_1 = 0; + + reg_debug_2 = 0xFF; //finish test + + +} + diff --git a/verilog/dv/cocotb/tests/temp_partial_test/partial.py b/verilog/dv/cocotb/tests/temp_partial_test/partial.py new file mode 100644 index 00000000..422d4aae --- /dev/null +++ b/verilog/dv/cocotb/tests/temp_partial_test/partial.py @@ -0,0 +1,47 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +reg = Regs() +"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" +@cocotb.test() +@repot_test +async def temp_partial(dut): + caravelEnv = await test_configure(dut,timeout_cycles=70000) + # Apply data 0x1809 (management standard output) to first block of + # user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + while True: + if cpu.read_debug_reg2() == 0xAA: + break + await ClockCycles(caravelEnv.clk,1) + cpu.cpu_force_reset() + + await ClockCycles(caravelEnv.clk,100) + + await cpu.drive_data2address(reg.get_addr('reg_wb_enable'),1) + await cpu.drive_data2address(reg.get_addr('reg_debug_1'),0xAA) + # await cpu.drive_data2address(reg.get_addr('reg_debug_2'),0xBB) + await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0) + + # await ClockCycles(caravelEnv.clk,100) + + cpu.cpu_release_reset() + + while True: + if cpu.read_debug_reg2() == 0xBB: + break + await ClockCycles(caravelEnv.clk,1) + + await ClockCycles(caravelEnv.clk,100) + \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/timer/timer.py b/verilog/dv/cocotb/tests/timer/timer.py new file mode 100644 index 00000000..8a616df9 --- /dev/null +++ b/verilog/dv/cocotb/tests/timer/timer.py @@ -0,0 +1,103 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +reg = Regs() +"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" +@cocotb.test() +@repot_test +async def timer0_oneshot(dut): + caravelEnv = await test_configure(dut,timeout_cycles=1000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start timer0_oneshot test") + cocotb.log.info(f"[TEST] Configure timer as oneshot") + pass_list = (0x1B,0x2B,0x3B) + fail_list = (0x1E,0x2E) + phases_fails = 3 + phases_passes = 0 + reg1 =0 # buffer + while True: + if cpu.read_debug_reg2() == 0xFF: # test finish + break + if reg1 != cpu.read_debug_reg1(): + reg1 = cpu.read_debug_reg1() + if reg1 in pass_list: # pass phase + phases_passes +=1 + phases_fails -=1 + if reg1 == 0x1B: + cocotb.log.info(f"[TEST] Pass timer0 value is decreasing") + elif reg1 == 0x2B: + cocotb.log.info(f"[TEST] Pass timer0 value reach 0") + elif reg1 == 0x3B: + cocotb.log.info(f"[TEST] Pass timer0 isn't changing after it reachs 0") + elif reg1 in fail_list: # pass phase + if reg1 == 0x1E: + cocotb.log.info(f"[TEST] Failed timer0 value increasing not decresing in oneshot mode") + elif reg1 == 0x2E: + cocotb.log.error(f"[TEST] Failed timer0 is changing before it reachs 0 in oneshot mode") + else: + cocotb.log.error(f"[TEST] debug register 1 has illegal value") + await ClockCycles(caravelEnv.clk,10) + + if phases_fails != 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + +@cocotb.test() +@repot_test +async def timer0_periodic(dut): + caravelEnv = await test_configure(dut,timeout_cycles=1000000000) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start timer0_periodic test") + cocotb.log.info(f"[TEST] Configure timer as periodic") + pass_list = (0x1B,0x2B,0x3B,0x4B) + fail_list = (0xEE) + phases_fails = 4 + phases_passes = 0 + reg1 =0 # buffer + fourB_happened = False + while True: + if cpu.read_debug_reg2() == 0xFF: # test finish + break + if reg1 != cpu.read_debug_reg1(): + reg1 = cpu.read_debug_reg1() + if reg1 in pass_list: # pass phase + phases_passes +=1 + phases_fails -=1 + if reg1 == 0x1B: + cocotb.log.info(f"[TEST] Pass timer0 first rollover") + elif reg1 == 0x2B: + cocotb.log.info(f"[TEST] Pass timer0 second rollover") + elif reg1 == 0x3B: + cocotb.log.info(f"[TEST] Pass timer0 third rollover") + elif reg1 == 0x4B: + if fourB_happened: # this phase happened one time before + phases_passes -=1 + phases_fails +=1 + else: + cocotb.log.info(f"[TEST] Pass timer0 counter value decreases") + fourB_happened = True + elif reg1 in fail_list: # pass phase + if reg1 == 0xEE: + cocotb.log.info(f"[TEST] Failed timer0 value hasn't rollovered in periodic mode") + else: + cocotb.log.error(f"[TEST] debug register 1 has illegal value") + + await ClockCycles(caravelEnv.clk,10) + + if phases_fails != 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/timer/timer0_oneshot.c b/verilog/dv/cocotb/tests/timer/timer0_oneshot.c new file mode 100644 index 00000000..e48e8745 --- /dev/null +++ b/verilog/dv/cocotb/tests/timer/timer0_oneshot.c @@ -0,0 +1,70 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +/* +Testing timer interrupts +Enable interrupt for timer0 and configure it as countdown 1 shot wait for interrupt +*/ + + +void main(){ + uint32_t value; + uint32_t old_value; + + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + /* Configure timer for a single-shot countdown */ + reg_timer0_config = 0; // disable + reg_timer0_data = 0xF3000; + reg_timer0_config = 1; // enable + + // Loop, waiting for the interrupt to change reg_mprj_datah + // test path if counter value stop updated after reach 0 and also the value is always decrementing + reg_timer0_update = 1; // update reg_timer0_value with new counter value + old_value = reg_timer0_value; + // value us decrementing until it reachs zero + while (1) { + reg_timer0_update = 1; // update reg_timer0_value with new counter value + value = reg_timer0_value; + if (value < old_value && value != 0){ + reg_debug_1 = 0x1B; // value decrease + } + else if (value == 0){ + reg_debug_1 = 0x2B; // value reach 0 + break; + }else{ + reg_debug_1 = 0x1F; // value updated incorrectly + } + old_value = value; + } + // check 10 times that value don't change from 0 + for (int i = 0; i < 10; i++); + reg_timer0_update = 1; // update reg_timer0_value with new counter value + + if (reg_timer0_value == 0){ + reg_debug_1 = 0x3B; //timer updated correctly + }else{ + reg_debug_1 = 0x2F; //timer updated incorrectly + } + reg_debug_2 = 0xFF; // finish test +} + diff --git a/verilog/dv/cocotb/tests/timer/timer0_periodic.c b/verilog/dv/cocotb/tests/timer/timer0_periodic.c new file mode 100644 index 00000000..9edabf7a --- /dev/null +++ b/verilog/dv/cocotb/tests/timer/timer0_periodic.c @@ -0,0 +1,73 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/* +Testing timer interrupts +Enable interrupt for timer0 and configure it as countdown 1 shot +wait for interrupt + +*/ + + +void main(){ + uint32_t value; + uint32_t old_value; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + /* Configure timer for a single-shot countdown */ + reg_timer0_config = 0; // disable + reg_timer0_data = 0; + reg_timer0_data_periodic = 0x300; + reg_timer0_config = 1; // enable + + // Loop, waiting for the interrupt to change reg_mprj_datah + // test path if counter value stop updated after reach 0 and also the value is always decrementing + reg_timer0_update = 1; // update reg_timer0_value with new counter value + old_value = reg_timer0_value; + // value us decrementing until it reachs zero + int rollover = 0; + int timeout = 400; + for (int i = 0; i < timeout; i++){ + reg_timer0_update = 1; // update reg_timer0_value with new counter value + value = reg_timer0_value; + if (value > old_value){ + rollover++; + if (rollover==1) + reg_debug_1 = 0x1B; // timer rollover + else if (rollover==2) + reg_debug_1 = 0x2B; //timer rollover second time + else if (rollover==3){ + reg_debug_1 = 0x3B; //timer rollover second time + break; + } + } + if (value < old_value){ + reg_debug_1 = 0x4B; // value decreases + } + old_value = value; + } + + if (rollover ==0){ + reg_debug_1 = 0xEE; // counter didn't rollover + } + reg_debug_2 = 0xFF; // finish test + +} + diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py new file mode 100644 index 00000000..729c6be9 --- /dev/null +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -0,0 +1,56 @@ +from curses import baudrate +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE + +baud_rate = 9600 +number_of_bits = 8 +bit_rate_ns = round((10**9)/(baud_rate*number_of_bits) ) + +reg = Regs() + + +@cocotb.test() +@repot_test +async def uart_tx(dut): + caravelEnv = await test_configure(dut,timeout_cycles=18613481) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start uart test") + expected_data = "Monitor: Test UART (RTL) passed" + + await wait_reg1(cpu,caravelEnv,0XAA) + + cocotb.log.info (f"[TEST] start sending on uart") + counter =0 + data_out ='' + while True: + if counter %8 == 0: + if counter != 0: + data_out = data_out+chr(int(char,2)) + cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_data}'") + if data_out == expected_data: + cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{data_out}'") + break + await start_of_tx(caravelEnv) + char = '' + # if temp != caravelEnv.monitor_gpio((6,6)) + char = caravelEnv.monitor_gpio((6,6)).binstr + char + cocotb.log.debug (f"[TEST] bit[{counter}] = {caravelEnv.monitor_gpio((6,6))} data out = {char} ") + await Timer(bit_rate_ns, units='ns') + counter +=1 + +async def start_of_tx(caravelEnv): + while (True): # wait for the start of the transimission it 1 then 0 + if (caravelEnv.monitor_gpio((6,6)).integer == 0): + break + await Timer(bit_rate_ns, units='ns') + await Timer(bit_rate_ns, units='ns') diff --git a/verilog/dv/cocotb/tests/uart/uart_tx.c b/verilog/dv/cocotb/tests/uart/uart_tx.c new file mode 100644 index 00000000..9628767a --- /dev/null +++ b/verilog/dv/cocotb/tests/uart/uart_tx.c @@ -0,0 +1,53 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +// -------------------------------------------------------- + +void main() +{ + int j; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + + // Set clock to 64 kbaud and enable the UART. It is important to do this + // before applying the configuration, or else the Tx line initializes as + // zero, which indicates the start of a byte to the receiver. + + + // Now, apply the configuration + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + +// reg_uart_clkdiv = 625; + reg_uart_enable = 1; + + reg_debug_1 = 0xAA; + // This should appear at the output, received by the testbench UART. + // (Makes simulation time long.) +// print("test msg\n"); + print("Monitor: Test UART (RTL) passed"); + + // Allow transmission to complete before signalling that the program + // has ended. + for (j = 0; j < 160; j++); +} diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/HKSPImonitor.py b/verilog/dv/cocotb/wb_models/housekeepingWB/HKSPImonitor.py new file mode 100644 index 00000000..baa2003e --- /dev/null +++ b/verilog/dv/cocotb/wb_models/housekeepingWB/HKSPImonitor.py @@ -0,0 +1,157 @@ + +from fnmatch import fnmatch +import cocotb +from cocotb.triggers import Timer, FallingEdge,RisingEdge, ReadOnly +from cocotb_bus.monitors import Monitor +from cocotb.log import SimLogFormatter, SimTimeContextFilter +from cocotb.binary import BinaryValue +from cocotb.result import TestFailure +from math import ceil +import copy +import logging +from wb_models.housekeepingWB.HKmonitor import HKmonitor +from common import Macros + + +class HKSPImonitor(Monitor): + """Observes single input """ + def __init__(self, name, block_path,interfaces, clock,reset,is_logger = False, input=True, callback=None, event=None): + self.name = name + self.interfaces = interfaces + self.clock = clock + self.reset = reset + self.block_path = block_path + self.is_logger = is_logger + self.input = input + self.setup_logger() + Monitor.__init__(self, callback, event) + + + async def _monitor_recv(self): + old_trans_hold = None + old_trans_no_valid = None + while True: + if Macros['GL']: + await RisingEdge(self.block_path.clknet_0_mgmt_gpio_in) # the main reason for doing all this can't use mgmt_gpio_in[4] as signal + else : + await RisingEdge(self.block_path.hkspi.SCK) # the main reason for doing all this can't use mgmt_gpio_in[4] as signal + cocotb.log.debug(f'reset {self.reset.value.binstr }') + + if self.reset.value.binstr == '0': + continue + + mgmt_gpio_in = self.block_path.mgmt_gpio_in.value + gpio_size = mgmt_gpio_in.n_bits-1 + CSB = mgmt_gpio_in[gpio_size-3] + if CSB.binstr == '1': + continue + SCK = mgmt_gpio_in[gpio_size-4] + SDI = mgmt_gpio_in[gpio_size-2] + SDO = self.block_path.mgmt_gpio_out.value[gpio_size-1] + if not self.input: + if self.block_path.hkspi.SCK.value.binstr != '0': + continue + # update signal + self.interfaces['CSB']['val'] = CSB + self.interfaces['SCK']['val'] = SCK + + if self.input: + self.interfaces['SDI']['val'] = SDI + else : + self.interfaces['SDO']['val'] = SDO + + # logger + self.logger.debug(f' ') + self.handler.terminator = "" + self.handler.setFormatter(SimLogFormatter()) + self.logger.debug(f'') + self.handler.setFormatter(logging.Formatter('%(message)s')) + for key2,signal in self.interfaces.items(): + if fnmatch(key2,"_*"): + continue + if signal['val'].is_resolvable: + length = self.lengths[key2] - (len(hex(signal['val'].integer))) + self.logger.debug(f" {hex(signal['val'].integer)}{' '*length}|") + # signal['val'] = self.block_path._id(signal['signal'],False).value.integer + else: + length = self.lengths[key2] - (len('x')) + self.logger.debug(f" x{' '*length}|") + self.handler.terminator = "\n" + self._recv(self.interfaces) + + + + + """method for setting up logger for WB model""" + def setup_logger(self): + self.logger = logging.getLogger(f'HouseKeeping{self.name}') + self.logger.setLevel(logging.DEBUG) + if not self.is_logger: + self.logger.setLevel(logging.INFO) + self.handler = logging.StreamHandler() + # return + else : + self.handler = logging.FileHandler(f"{self.name}.log",mode='w') + self.handler.addFilter(SimTimeContextFilter()) + self.logger.addHandler(self.handler) + # get the sizes of signals + #for key,interface in self.interfaces.items(): + for key,signal in self.interfaces.items(): + if fnmatch(key,"_*"): + continue + signal['val'] = BinaryValue(value=0,n_bits=1) + size = signal['val'].n_bits + signal['val'] = BinaryValue(value = int(size) * '1',n_bits=size) + # set the logger file header + # set first line + self.handler.terminator = "" + self.logger.debug(f' timestamp level ') + length =0 + for key2,signal in self.interfaces.items(): + if fnmatch(key2,"_*"): + continue + length += max(ceil(signal['val'].n_bits/4)+2 , len(key2)) +3 + length -= len(key)+1 + self.logger.debug(f'| signals{" "*int(length)}') + self.handler.terminator = "\n" + self.logger.debug(f' ') + # set second line + self.handler.terminator = "" + self.logger.debug(f'{" "*20}|') + length =0 + self.lengths = dict() + for key2,signal in self.interfaces.items(): + if fnmatch(key2,"_*"): + continue + self.lengths[key2] = max((len(hex(signal['val'].integer))),len(key2)) +1 + length = self.lengths[key2] - len(key2) + self.logger.debug(f'{key2}{" "*length} ') + self.handler.terminator = "\n" + + + +class CSBmonitor(Monitor): + """Observes single input """ + def __init__(self, name, block_path,interfaces, clock,reset,is_logger = False, input=True, callback=None, event=None): + self.name = name + self.interfaces = interfaces + self.clock = clock + self.reset = reset + self.block_path = block_path + self.is_logger = is_logger + self.input = input + Monitor.__init__(self, callback, event) + + + async def _monitor_recv(self): + + while True: + if Macros['GL']: + await RisingEdge(self.block_path.net67) + else: + await RisingEdge(self.block_path.hkspi.CSB) + + self._recv(True) + + + \ No newline at end of file diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/HK_models.py b/verilog/dv/cocotb/wb_models/housekeepingWB/HK_models.py new file mode 100644 index 00000000..42a98598 --- /dev/null +++ b/verilog/dv/cocotb/wb_models/housekeepingWB/HK_models.py @@ -0,0 +1,371 @@ +from audioop import add +from ctypes import BigEndianStructure +from operator import truediv +from cocotb import top +import cocotb +from cocotb.binary import BinaryValue +from cocotb.triggers import Timer, RisingEdge, ReadOnly +import fnmatch +import copy +import logging +from cocotb.result import TestFailure +from cocotb_coverage.coverage import * + +class HK_models(): + def __init__(self,reg_model,expeceted_output,hk_hdl): + self.reg_model = reg_model + self.expeceted_output = expeceted_output + self.hk_hdl = hk_hdl + self.old_hold_val = 1 + self.gpio_out_pre = BinaryValue(value=0,n_bits=38,bigEndian=False) + self.mgmt_gpio_oeb = BinaryValue(value=0,n_bits=38,bigEndian=False) + self.exp_out_wb = [] # expected output for wishbone + self.exp_out_uart_rx = [self.expeceted_output['UART']] # expected output for uart + self.exp_out_debug = [self.expeceted_output['debug']] # expected output for + self.exp_out_spi = [self.expeceted_output['SPI']] # expected output for + self.reset_spi_vals(True) + self.input_dis =3 + self.regs_full_list() + self.intial_cov() + + + + """model for the wishbone interface with housekeeping""" + def wishbone_model(self,trans): + clock_signal = trans["_clk"]["signal"] + if trans["stb"]["val"] == 1 : # valid data + address = trans["adr"]["val"] + data = trans["data"]["val"] + # if ack isn't realsead don't care about the new input it must be the same as the old and the monitor checks that + if (self.old_hold_val == 0): + self.old_hold_val = trans["_hold"]["val"] + return + self.old_hold_val = trans["_hold"]["val"] + if trans["write_en"]["val"] ==1 : # write cycle + cocotb.log.debug(f'[HK_models][_valid_address] write enable for address: {hex(address)} and data: {hex(data)} ') + select = trans["sel"]["val"] + cocotb.scheduler.add(self._write_reg_wb(address,data,select,clock_signal)) + else: #read cycle + self.write_exp_out_wb(self._read_reg_wb(address)) + self.wishbone_last_trans = trans + + """model for the system interface with housekeeping""" + def system_model(self,trans): + self.reg_model['sys']['0x00'][0][6] = trans["vdd2_good"]["val"] + self.reg_model['sys']['0x00'][1][6] = trans["vdd1_good"]["val"] + self.reg_model['sys']['0x00'][2][6] = trans["vcc2_good"]["val"] + self.reg_model['sys']['0x00'][3][6] = trans["vcc1_good"]["val"] + + + """model for the UART interface with housekeeping""" + def UART_model(self,trans): + # when transmiting TX the gpio data out should change to the tx value + if trans["enable"]["val"]: + self.gpio_out_pre[6]= trans["TX"]["val"].value + else: + gpio_data = self._read_reg_keys(["GPIO","0x0c"]) # mgmt_gpio_data[7:0] + self.gpio_out_pre[6]= int(gpio_data[len(gpio_data)-1 -6]) # mgmt_gpio_data[6] + # predecting the rx output value when the value UART is enble is the value drom pin [5] + gpio_in_size = trans["gpio_in"]["val"].n_bits -1 + output = self.expeceted_output['UART'] + output["RX"]["val"] = 0 + if trans["enable"]["val"]: + output["RX"]["val"] = trans["gpio_in"]["val"][gpio_in_size-5] #gpio_in[5] + self.exp_out_uart_rx.append(output) + + + """model for the debug interface with housekeeping""" + def debug_model(self,trans): + # when debug is enable gpio out [0] should follow debug_out + if trans["enable"]["val"]: + self.gpio_out_pre[0] = trans["data"]["val"].value + self.mgmt_gpio_oeb[0] = trans["data"]["val"].value + else: + gpio_data = self._read_reg_keys(["GPIO","0x0c"]) # mgmt_gpio_data[7:0] + self.gpio_out_pre[0]= int(gpio_data[len(gpio_data)-1 -0]) # mgmt_gpio_data[6] + gpio_data_en = self._read_reg_keys(["GPIO","0x24"]) # gpio_configure[0][7:0] + self.mgmt_gpio_oeb[0]= 1- int(gpio_data[len(gpio_data_en)-1 -self.input_dis]) # gpio_configure[0][3] + + # predecting the debug in signal when debug mode is enbled taking the value from pin [0] + gpio_in_size = trans["gpio_in"]["val"].n_bits -1 + output = self.expeceted_output['debug'] + output["data"]["val"] = 0 + if trans["enable"]["val"]: + output["data"]["val"] = trans["gpio_in"]["val"][gpio_in_size-0] # mgmt_gpio_in[0] + self.exp_out_debug.append(output) + + """model for the SPI interface with housekeeping""" + def spi_model(self,trans): + output = self.expeceted_output['SPI'] + output["SDO"]["val"] = 0 + cocotb.log.debug(f'[HK_models][spi_model] spi mode {self.spi_mode[0]} bit number {self.spi_mode[1]} command = {self.command_spi} address = {self.address_spi} write = {self.write_spi} stream = {self.spi_mode[2]}') + if self.spi_mode[0] == "command": + self._setCommand(trans['SDI']['val'].binstr) + self.exp_out_spi.append(output) + elif self.spi_mode[0] == "address": + self._setAddress(trans['SDI']['val'].binstr) + self.exp_out_spi.append(output) + elif self.spi_mode[0] == "write": + self._setWriteData(trans['SDI']['val'].binstr) + self.exp_out_spi.append(output) + elif self.spi_mode[0] == "read": + output["SDO"]["val"] = self._getReadData() + self.exp_out_spi.append(output) + elif self.spi_mode[0] == "read/write": + output["SDO"]["val"] = self._getReadData() + self.exp_out_spi.append(output) + elif self.spi_mode[0] == "noOP": + self._setWriteData(trans['SDI']['val'].binstr) + else: + raise TestFailure("[HK_models][spi_model] invalid command type") + + + """reset the spi vals when CSB is going from low to high""" + def reset_spi_vals(self,trans): + cocotb.log.info(f"[HK_models][reset_spi_vals] CSB is disabled") + self.spi_mode = ["command",0,0] # [mode type, bit number, stream number] + self.command_spi = ['0']*8 + self.address_spi = ['0']*8 + self.write_spi = ['0']*8 + self.read_spi = ['0']*8 + + def _setCommand(self,bit): + if bit not in ['0','1']: + cocotb.log.warning(f"[HK_models][_setCommand] incorrect bit size bit = {bit}") + self.command_spi[self.spi_mode[1]] = bit + self.spi_mode[1] += 1 + self.spi_mode[2] = 0 # stream number + if self.spi_mode[1] >= 8: + self.spi_mode[0] = "address" + self.spi_mode[1] = 0 + + def _setAddress(self,bit): + if bit not in ['0','1']: + cocotb.log.warning(f"[HK_models][_setAddress] incorrect bit size bit = {bit}") + self.address_spi[self.spi_mode[1]] = bit + self.spi_mode[1] += 1 + self.spi_mode[2] = 0 # stream number + if self.spi_mode[1] >= 8: + self.spi_mode[1] = 0 + if self.command_spi[0:2] == ['0','0']: + self.spi_mode[0] = "noOP" + if self.command_spi[0:2] == ['1','0']: + self.spi_mode[0] = "write" + if self.command_spi[0:2] == ['0','1']: + self.spi_mode[0] = "read" + if self.command_spi[0:2] == ['1','1']: + self.spi_mode[0] = "read/write" + + def _setWriteData(self,bit): + if bit not in ['0','1']: + cocotb.log.warning(f"[HK_models][_setWriteData] incorrect bit size bit = {bit}") + # return if write is write n-bytes command and number of bytes exceeds the required + if self.command_spi[2:5] != ['0','0','0']: + self.spi_mode_cov('write-n') + byte_num = int(''.join(self.command_spi[2:5]),2) + if byte_num <= self.spi_mode[2]: #number of written byte <= stream number + self.spi_mode[0] = "noOP" + return + else: self.spi_mode_cov('write') + self.write_spi[self.spi_mode[1]] = bit + self.spi_mode[1] += 1 + if self.spi_mode[1] >= 8: + self.spi_mode[1] = 0 + address = int(''.join(self.address_spi),2) + self.spi_mode[2] + data = ''.join(self.write_spi) + data = BinaryValue(value = data, n_bits =8) + is_valid, keys=self._valid_address_spi(address) + if is_valid: + self.reg_cov(keys[0],keys[1],is_read=False) + cocotb.log.debug(f'[HK_models][_valid_address] writing {data} to memory:{keys[0]} field: {keys[1]} through housekeeping SPI address = {address}') + self._write_fields(keys,data) + if self.command_spi[2:5] != ['0','0','0']:self.spi_mode_cov('write-n') + else: self.spi_mode_cov('write') + self.spi_mode[2] += 1 # stream number + + + def _getReadData(self): + # return if write is write n-bytes command and number of bytes exceeds the required + if self.command_spi[2:5] != ['0','0','0']: + byte_num = int(''.join(self.command_spi[2:5]),2) + if byte_num <= self.spi_mode[2]: #number of written byte <= stream number + self.spi_mode[0] = "noOP" + return + bit_num = self.spi_mode[1] + address = int(''.join(self.address_spi),2) + self.spi_mode[2] + is_valid, keys=self._valid_address_spi(address) + data = '' + if is_valid: + self.reg_cov(keys[0],keys[1]) + cocotb.log.info(f'[HK_models][_getReadData] reading from memory:{keys[0]} field: {keys[1]} through SPI') + for field in self.reg_model[keys[0]][keys[1]]: + data = str(bin(field[6])[2:]).zfill(field[3]) + data + data = data.zfill(8) + cocotb.log.info(f'[HK_models][_getReadData] reading from memory:{keys[0]} field: {keys[1]} through SPI data {data} bit[{7-bit_num}] = {data[bit_num]}') + + self.spi_mode[1] += 1 + if self.spi_mode[1] >= 8: + self.spi_mode[1] = 0 + self.spi_mode[2] += 1 # stream number + if self.command_spi[2:5] != ['0','0','0']:self.spi_mode_cov('read-n') + else: self.spi_mode_cov('read') + + if data == '': + return 0 + return int(data[bit_num],2) + + + def write_exp_out_wb(self,data): + output = self.expeceted_output['wishbone'] + output['ack']['val'] = 1 + output['_valid_cycle']['val'] = 1 + output['data']['val'] = BinaryValue(value = data,n_bits = 32,bigEndian=False) + self.exp_out_wb.append(output) + + """write register through wishbone """ + async def _write_reg_wb(self,address,data,select,clk): + old_data = self._read_reg_wb(address) + self.write_exp_out_wb(old_data) + + if address == 0x2600000c: # mgmt_gpio_data is a special case as it got written completely at the end of the serial writing + for i in range(6): + await RisingEdge(self.hk_hdl._id(clk,False)) + + for i in range(3): + await RisingEdge(self.hk_hdl._id(clk,False)) + + for i,sel in enumerate(select.binstr): + temp_addr = BinaryValue(value=(address.value +i)) + if sel is '1': + is_valid, keys=self._valid_address(temp_addr) + if is_valid: + self.reg_cov(keys[0],keys[1],is_SPI=False,is_read=False) + cocotb.log.debug(f'[HK_models][_valid_address] writing {data[(8*((4-i-1))):8*(4-i)-1]} to memory:{keys[0]} field: {keys[1]}') + temp_data = data[(8*((4-i-1))):8*(4-i)-1] + self._write_fields(keys,temp_data) + cocotb.log.debug(f" [HK_models][_valid_address] address {hex(address)} used for access housekeeping memory success") + if address != 0x2600000c: + for i in range(2): + await RisingEdge(self.hk_hdl._id(clk,False)) + + def _write_fields(self,keys,data): + for field in self.reg_model[keys[0]][keys[1]]: + if field[4] == "RW": + shift = field[2] + size = field[3] + cocotb.log.debug(f'[HK_models][_write_fields] before update field : {field[1]} data = {bin(field[6])} with data {data[shift:shift+size-1]} ') + field[6] = data[8-shift-size:8-shift-1] + cocotb.log.debug(f'[HK_models][_write_fields] after update field : {field[1]} data = {bin(field[6])} with data {data[shift:shift+size-1]} ') + """read register value using keys return size binary value""" + def _read_reg_keys(self,keys:list): + size =0 + data = "" + for field in self.reg_model[keys[0]][keys[1]]: + size += field[3] + data += bin(field[6])[2:].zfill(size) + return data + + + """read register through wishbone """ + def _read_reg_wb(self,address): + total_size = 32 + data_string ="0" + data_out = list(bin(0)[2:].zfill(total_size)) + for i in range(4): + temp_addr = BinaryValue(value=(address.value +i)) + is_valid, keys=self._valid_address(temp_addr) + if is_valid: + self.reg_cov(keys[0],keys[1],is_SPI=False) + for field in self.reg_model[keys[0]][keys[1]]: + shift = field[2] + size = field[3] + first_index = ((8 *(4-i))) - shift-size + second_index = ((8 *(4-i))) - shift + data = bin(field[6])[2:].zfill(size) + cocotb.log.debug(f"[HK_models][_read_reg] memory:{keys[0]} shift:{keys[1]} field:{field[0]} data:{data} ") + for k,j in enumerate(range(first_index, second_index, 1)): + data_out[j] = data[k] + data_string = "".join(data_out) + cocotb.log.debug(f"[HK_models][_read_reg] register {hex(address)} has value {hex(int(data_string,2))} ") + return int(data_string,2) + + """return false if the address isn't exist inside housekeeping if the address exist return true and the key of address in JSON file""" + def _valid_address(self,address): + size = max(len(address),32) + address = address.binstr.zfill(size) + for key,memory in self.reg_model.items(): + if fnmatch.fnmatch(key, "_*") : + continue + # remove the first 2 element 0b and + base_addr= bin(memory["base_addr"][1])[2:].zfill(size) + cocotb.log.debug(f'[HK_models][_valid_address] base address[:13]={hex(int(base_addr[size-32:size-13],2))} target address[:13]={hex(int(address[size-32:size-13],2))} shift={"{0:#0{1}x}".format(int(address[size-12:],2),4)}') + if base_addr[size-32:size-13] == address[size-32:size-13]: + if "{0:#0{1}x}".format(int(address[size-12:],2),4) in memory: + cocotb.log.debug(f'[HK_models][_valid_address] base address={hex(int(base_addr,2))} key {key}') + return True, [key,"{0:#0{1}x}".format(int(address[size-12:],2),4)] + cocotb.log.warning(f"[HK_models][_valid_address] address {hex(int(address,2))} used for access housekeeping memory isn't valid") + return False, None + + """return false if the address isn't exist inside housekeeping if the address exist return true and the key of address in JSON file""" + def _valid_address_spi(self,address): + for key,memory in self.reg_model.items(): + if fnmatch.fnmatch(key, "_*") : + continue + for key2,reg in memory.items(): + if key2 == "base_addr" : + continue + for field in reg: + if field[7] == address: + return True,[key,key2] + cocotb.log.warning(f"[HK_models][_valid_address_spi] address {hex(address)} for SPI housekeeping isn't valid") + return False, None + + +######################## coverage ############################ + def regs_full_list(self): + bins = list() + labels = list() + for key,mem in self.reg_model.items(): + if fnmatch.fnmatch(key, "_*"): + continue + for key2,fields in mem.items(): + if key2=='base_addr': + continue + bins.append((key,key2)) + labels.append((self.reg_model[key][key2][0][0])) + self.reg_bins = bins + self.reg_labels = labels + def intial_cov(self): + for i in [True,False]: + for j in [True,False]: + self.reg_cov(0,0,i,j) + self.spi_mode_cov(0) + + def reg_cov(self,key1,key2,is_SPI=True,is_read=True): + s='' + if is_SPI: + s = "spi." + else: + s="wishbone." + if is_read: + s +="read" + else: + s+= "write" + @CoverPoint(f"top.caravel.housekeeping.regs.{s}", + xf = lambda key1,key2:(key1,key2), + bins = self.reg_bins, + bins_labels=self.reg_labels) + def cov(key1,key2): + pass + cov(key1,key2) + return (key1,key2) + + + def spi_mode_cov(self,mode): + @CoverPoint(f"top.caravel.housekeeping.spi.modes", + bins = ['noOP','write','read','read/write','write-n','read-n','read/write-n','Pass-m','pass-u'], + bins_labels=['No operation','Write in streaming mode','Read in streaming mode','Simultaneous Read/Write in streaming mode','Write in n-byte mode','Read in n-byte mode','Simultaneous Read/Write in n-byte mode','Pass-through (management) Read/Write streaming mode','Pass-through (user) Read/Write in streaming mode' ]) + def cov(mode): + pass + cov(mode) + return mode \ No newline at end of file diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json b/verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json new file mode 100644 index 00000000..d8b73813 --- /dev/null +++ b/verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json @@ -0,0 +1,129 @@ +{ + "_comment": "the list contain the fields in register with shift spcified [field name,name iniside housekeeping, shift, size,mode,reset,value(intial is reset value), SPI address map] the shift is from the base address like SPI, system and gpio base address", + "_comment2": "Base address is the first element and called first address", + + + "SPI":{ "base_addr": ["SPI_BASE_ADR",638582784], + "0x00": [["SPI status",null,0,8,"undefined",0,0,0]], + "0x06": [["Manufacturer ID",["mfgr_id",11,8],0,4,"RO",4,4,1]], + "0x05": [["Manufacturer ID",["mfgr_id",7,0],0,8,"RO",86,86,2]], + "0x04": [["Manufacturer ID",["prod_id",7,0],0,8,"RO",17,17,3]], + "0x0b": [["User project ID",["mask_rev",31,24],0,8,"RO",0,0,4]], + "0x0a": [["User project ID",["mask_rev",23,16],0,8,"RO",0,0,5]], + "0x09": [["User project ID",["mask_rev",15,8],0,8,"RO",0,0,6]], + "0x08": [["User project ID",["mask_rev",7,0],0,8,"RO",0,0,7]], + "0x0c": [["PLL enables","pll_ena",0,1,"RW",0,0,8],["PLL DCO enables","pll_dco_ena",1,1,"RW",1,1,8]], + "0x10": [["PLL bypass","pll_bypass",0,1,"RW",1,1,9]], + "0x14": [["CPU IRQ","irq_spi",0,1,"RW",0,0,10]], + "0x18": [["CPU reset","reset_reg",0,1,"RW",0,0,11]], + "0x28": [["CPU trap","trap",0,1,"RW",0,0,12]], + "0x1c": [["DCO trim",["pll_trim",7,0],0,8,"RW",255,255,13]], + "0x1d": [["DCO trim",["pll_trim",15,8],0,8,"RW",239,239,14]], + "0x1e": [["DCO trim",["pll_trim",23,16],0,8,"RW",255,255,15]], + "0x1f": [["DCO trim",["pll_trim",25,24],0,2,"RW",3,3,16]], + "0x20": [["PLL output divider","pll_sel",0,3,"RW",2,2,17],["PLL output divider 2","pll90_sel",3,3,"RW",2,2,17]], + "0x24": [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]], + "0x34": [["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",0,1,"RW",0,0,20]], + "0x30": [["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]] + }, + + "GPIO":{ "base_addr": ["GPIO_BASE_ADR",637534208], + "0x00": [["xfer","serial_xfer",0,1,"RW",0,0,19],["bit bang enable","serial_bb_enable",1,1,"RW",0,0,19], + ["bit bang reset","serial_bb_resetn",2,1,"RW",0,0,19],["bit bang load","serial_bb_load",3,1,"RW",0,0,19], + ["bit bang clock","serial_bb_clock",4,1,"RW",0,0,19],["bit bang data1","serial_bb_data_1",5,1,"RW",0,0,19], + ["bit bang data1","serial_bb_data_2",6,1,"RW",0,0,19]], + "0x04": [["GPIO power control (reg_mprj_pwr)","pwr_ctrl_out",0,4,"RW",0,0,110]], + "0x0c": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",7,0],0,8,"RW",0,0,109]], + "0x0d": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",15,8],0,8,"RW",0,0,108]], + "0x0e": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",23,16],0,8,"RW",0,0,107]], + "0x0f": [["GPIO data low(reg_mprj_datal)",["mgmt_gpio_data",31,24],0,8,"RW",0,0,106]], + "0x10": [["GPIO data high(reg_mprj_datah)",["mgmt_gpio_data",37,32],0,5,"RW",0,0,105]], + "0x24": [["mprj_io[00](reg_mprj_io_0)",["gpio_configure[0]",7,0],0,8,"RW",3,3,30]], + "0x25": [["mprj_io[00](reg_mprj_io_0)",["gpio_configure[0]",12,8],0,5,"RW",24,24,29]], + "0x28": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",7,0],0,8,"RW",3,3,32]], + "0x29": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",12,8],0,5,"RW",24,24,31]], + "0x2c": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",7,0],0,8,"RW",3,3,34]], + "0x2d": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",12,8],0,5,"RW",4,4,33]], + "0x30": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",7,0],0,8,"RW",3,3,36]], + "0x31": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",12,8],0,5,"RW",4,4,35]], + "0x34": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",7,0],0,8,"RW",3,3,38]], + "0x35": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",12,8],0,5,"RW",4,4,37]], + "0x38": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",7,0],0,8,"RW",3,3,40]], + "0x39": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",12,8],0,5,"RW",4,4,39]], + "0x3c": [["mprj_io[06](reg_mprj_io_6)",["gpio_configure[6]",7,0],0,8,"RW",3,3,42]], + "0x3d": [["mprj_io[06](reg_mprj_io_6)",["gpio_configure[6]",12,8],0,5,"RW",4,4,41]], + "0x40": [["mprj_io[07](reg_mprj_io_7)",["gpio_configure[7]",7,0],0,8,"RW",3,3,44]], + "0x41": [["mprj_io[07](reg_mprj_io_7)",["gpio_configure[7]",12,8],0,5,"RW",4,4,43]], + "0x44": [["mprj_io[08](reg_mprj_io_8)",["gpio_configure[8]",7,0],0,8,"RW",3,3,46]], + "0x45": [["mprj_io[08](reg_mprj_io_8)",["gpio_configure[8]",12,8],0,5,"RW",4,4,45]], + "0x48": [["mprj_io[09](reg_mprj_io_9)",["gpio_configure[9]",7,0],0,8,"RW",3,3,48]], + "0x49": [["mprj_io[09](reg_mprj_io_9)",["gpio_configure[9]",12,8],0,5,"RW",4,4,47]], + "0x4c": [["mprj_io[10](reg_mprj_io_10)",["gpio_configure[10]",7,0],0,8,"RW",3,3,50]], + "0x4d": [["mprj_io[10](reg_mprj_io_10)",["gpio_configure[10]",12,8],0,5,"RW",4,4,49]], + "0x50": [["mprj_io[11](reg_mprj_io_11)",["gpio_configure[11]",7,0],0,8,"RW",3,3,52]], + "0x51": [["mprj_io[11](reg_mprj_io_11)",["gpio_configure[11]",12,8],0,5,"RW",4,4,51]], + "0x54": [["mprj_io[12](reg_mprj_io_12)",["gpio_configure[12]",7,0],0,8,"RW",3,3,54]], + "0x55": [["mprj_io[12](reg_mprj_io_12)",["gpio_configure[12]",12,8],0,5,"RW",4,4,53]], + "0x58": [["mprj_io[13](reg_mprj_io_13)",["gpio_configure[13]",7,0],0,8,"RW",3,3,56]], + "0x59": [["mprj_io[13](reg_mprj_io_13)",["gpio_configure[13]",12,8],0,5,"RW",4,4,55]], + "0x5c": [["mprj_io[14](reg_mprj_io_14)",["gpio_configure[14]",7,0],0,8,"RW",3,3,58]], + "0x5d": [["mprj_io[14](reg_mprj_io_14)",["gpio_configure[14]",12,8],0,5,"RW",4,4,57]], + "0x60": [["mprj_io[15](reg_mprj_io_15)",["gpio_configure[15]",7,0],0,8,"RW",3,3,60]], + "0x61": [["mprj_io[15](reg_mprj_io_15)",["gpio_configure[15]",12,8],0,5,"RW",4,4,59]], + "0x64": [["mprj_io[16](reg_mprj_io_16)",["gpio_configure[16]",7,0],0,8,"RW",3,3,62]], + "0x65": [["mprj_io[16](reg_mprj_io_16)",["gpio_configure[16]",12,8],0,5,"RW",4,4,61]], + "0x68": [["mprj_io[17](reg_mprj_io_17)",["gpio_configure[17]",7,0],0,8,"RW",3,3,64]], + "0x69": [["mprj_io[17](reg_mprj_io_17)",["gpio_configure[17]",12,8],0,5,"RW",4,4,63]], + "0x6c": [["mprj_io[18](reg_mprj_io_18)",["gpio_configure[18]",7,0],0,8,"RW",3,3,66]], + "0x6d": [["mprj_io[18](reg_mprj_io_18)",["gpio_configure[18]",12,8],0,5,"RW",4,4,65]], + "0x70": [["mprj_io[19](reg_mprj_io_19)",["gpio_configure[19]",7,0],0,8,"RW",3,3,68]], + "0x71": [["mprj_io[19](reg_mprj_io_19)",["gpio_configure[19]",12,8],0,5,"RW",4,4,67]], + "0x74": [["mprj_io[20](reg_mprj_io_20)",["gpio_configure[20]",7,0],0,8,"RW",3,3,70]], + "0x75": [["mprj_io[20](reg_mprj_io_20)",["gpio_configure[20]",12,8],0,5,"RW",4,4,69]], + "0x78": [["mprj_io[21](reg_mprj_io_21)",["gpio_configure[21]",7,0],0,8,"RW",3,3,72]], + "0x79": [["mprj_io[21](reg_mprj_io_21)",["gpio_configure[21]",12,8],0,5,"RW",4,4,71]], + "0x7c": [["mprj_io[22](reg_mprj_io_22)",["gpio_configure[22]",7,0],0,8,"RW",3,3,74]], + "0x7d": [["mprj_io[22](reg_mprj_io_22)",["gpio_configure[22]",12,8],0,5,"RW",4,4,73]], + "0x80": [["mprj_io[23](reg_mprj_io_23)",["gpio_configure[23]",7,0],0,8,"RW",3,3,76]], + "0x81": [["mprj_io[23](reg_mprj_io_23)",["gpio_configure[23]",12,8],0,5,"RW",4,4,75]], + "0x84": [["mprj_io[24](reg_mprj_io_24)",["gpio_configure[24]",7,0],0,8,"RW",3,3,78]], + "0x85": [["mprj_io[24](reg_mprj_io_24)",["gpio_configure[24]",12,8],0,5,"RW",4,4,77]], + "0x88": [["mprj_io[25](reg_mprj_io_25)",["gpio_configure[25]",7,0],0,8,"RW",3,3,80]], + "0x89": [["mprj_io[25](reg_mprj_io_25)",["gpio_configure[25]",12,8],0,5,"RW",4,4,79]], + "0x8c": [["mprj_io[26](reg_mprj_io_26)",["gpio_configure[26]",7,0],0,8,"RW",3,3,82]], + "0x8d": [["mprj_io[26](reg_mprj_io_26)",["gpio_configure[26]",12,8],0,5,"RW",4,4,81]], + "0x90": [["mprj_io[27](reg_mprj_io_27)",["gpio_configure[27]",7,0],0,8,"RW",3,3,84]], + "0x91": [["mprj_io[27](reg_mprj_io_27)",["gpio_configure[27]",12,8],0,5,"RW",4,4,83]], + "0x94": [["mprj_io[28](reg_mprj_io_28)",["gpio_configure[28]",7,0],0,8,"RW",3,3,86]], + "0x95": [["mprj_io[28](reg_mprj_io_28)",["gpio_configure[28]",12,8],0,5,"RW",4,4,85]], + "0x98": [["mprj_io[29](reg_mprj_io_29)",["gpio_configure[29]",7,0],0,8,"RW",3,3,88]], + "0x99": [["mprj_io[29](reg_mprj_io_29)",["gpio_configure[29]",12,8],0,5,"RW",4,4,87]], + "0x9c": [["mprj_io[30](reg_mprj_io_30)",["gpio_configure[30]",7,0],0,8,"RW",3,3,90]], + "0x9d": [["mprj_io[30](reg_mprj_io_30)",["gpio_configure[30]",12,8],0,5,"RW",4,4,89]], + "0xa0": [["mprj_io[31](reg_mprj_io_31)",["gpio_configure[31]",7,0],0,8,"RW",3,3,92]], + "0xa1": [["mprj_io[31](reg_mprj_io_31)",["gpio_configure[31]",12,8],0,5,"RW",4,4,91]], + "0xa4": [["mprj_io[32](reg_mprj_io_32)",["gpio_configure[32]",7,0],0,8,"RW",3,3,94]], + "0xa5": [["mprj_io[32](reg_mprj_io_32)",["gpio_configure[32]",12,8],0,5,"RW",4,4,93]], + "0xa8": [["mprj_io[33](reg_mprj_io_33)",["gpio_configure[33]",7,0],0,8,"RW",3,3,96]], + "0xa9": [["mprj_io[33](reg_mprj_io_33)",["gpio_configure[33]",12,8],0,5,"RW",4,4,95]], + "0xac": [["mprj_io[34](reg_mprj_io_34)",["gpio_configure[34]",7,0],0,8,"RW",3,3,98]], + "0xad": [["mprj_io[34](reg_mprj_io_34)",["gpio_configure[34]",12,8],0,5,"RW",4,4,97]], + "0xb0": [["mprj_io[35](reg_mprj_io_35)",["gpio_configure[35]",7,0],0,8,"RW",3,3,100]], + "0xb1": [["mprj_io[35](reg_mprj_io_35)",["gpio_configure[35]",12,8],0,5,"RW",4,4,99]], + "0xb4": [["mprj_io[36](reg_mprj_io_36)",["gpio_configure[36]",7,0],0,8,"RW",3,3,102]], + "0xb5": [["mprj_io[36](reg_mprj_io_36)",["gpio_configure[36]",12,8],0,5,"RW",24,24,101]], + "0xb8": [["mprj_io[37](reg_mprj_io_37)",["gpio_configure[37]",7,0],0,8,"RW",3,3,104]], + "0xb9": [["mprj_io[37](reg_mprj_io_37)",["gpio_configure[37]",12,8],0,5,"RW",24,24,103]] + }, + + "sys":{ "base_addr": ["SYS_BASE_ADR",639631360], + "0x00": [["user2 vdd good","usr2_vdd_pwrgood",0,1,"RO",0,0,26],["user1 vdd good","usr1_vdd_pwrgood",1,1,"RO",0,0,26], + ["user2 vcc good","usr2_vcc_pwrgood",2,1,"RO",0,0,26],["user1 vcc good","usr1_vcc_pwrgood",3,1,"RO",0,0,26]], + "0x04": [["Trap output redirect","trap_output_dest",0,1,"RW",0,0,27], + ["clock2 output redirect","clk2_output_dest",1,1,"RW",0,0,27], + ["clock1 output redirect","clk1_output_dest",2,1,"RW",0,0,27]], + "0x0c": [["IRQ1 input redirect","irq_1_inputsrc",0,1,"RW",0,0,28],["IRQ2 redirect","irq_2_inputsrc",1,1,"RW",0,0,28]], + "0x10": [["Housekeeping SPI disable","hkspi_disable",0,1,"RW",0,0,111]] + } + +} \ No newline at end of file diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/HK_scoreboard.py b/verilog/dv/cocotb/wb_models/housekeepingWB/HK_scoreboard.py new file mode 100644 index 00000000..71d55a11 --- /dev/null +++ b/verilog/dv/cocotb/wb_models/housekeepingWB/HK_scoreboard.py @@ -0,0 +1,92 @@ +from cocotb_bus.scoreboard import Scoreboard +from cocotb.utils import hexdump, hexdiffs +from cocotb.log import SimLog +from cocotb.result import TestFailure, TestSuccess +from cocotb_bus.monitors import Monitor +import cocotb + + +class HKScoreboard(Scoreboard): + def __init__(self, dut, reorder_depth=0, fail_immediately=True): + + Scoreboard.__init__(self, dut, reorder_depth, fail_immediately) + + def compare(self, got, exp, log, strict_type=True): + # Compare the types + if strict_type and type(got) != type(exp): + self.errors += 1 + log.error("Received transaction type is different than expected") + log.info("Received: %s but expected %s" % + (str(type(got)), str(type(exp)))) + if self._imm: + raise TestFailure("Received transaction of wrong type. " + "Set strict_type=False to avoid this.") + return + # Or convert to a string before comparison + elif not strict_type: + got, exp = str(got), str(exp) + + # Compare directly + if self.dict_compare(got, exp): + self.errors += 1 + + # Try our best to print out something useful + strgot, strexp = str(got), str(exp) + + log.error("Received transaction differed from expected output") + if not strict_type: + log.info("Expected:\n" + hexdump(strexp)) + else: + log.info("Expected:\n" + repr(exp)) + if not isinstance(exp, str): + try: + for word in exp: + log.info(str(word)) + except Exception: + pass + if not strict_type: + log.info("Received:\n" + hexdump(strgot)) + else: + log.info("Received:\n" + repr(got)) + if not isinstance(got, str): + try: + for word in got: + log.info(str(word)) + except Exception: + pass + log.warning("Difference:\n%s" % hexdiffs(strexp, strgot)) + if self._imm: + raise TestFailure("Received transaction differed from expected " + "transaction") + else: + # Don't want to fail the test + # if we're passed something without __len__ + try: + log.debug("Received expected transaction %d bytes" % + (len(got))) + log.debug(repr(got)) + except Exception: + pass + + def dict_compare(self,d1, d2): + d1_keys = set(d1.keys()) + d2_keys = set(d2.keys()) + shared_keys = d1_keys.intersection(d2_keys) + different_keys = d1_keys.symmetric_difference(d2_keys) + if different_keys is not None: + cocotb.log.info(f"[HKScoreboard][dict_compare] return False because different_keys \n {d1} \n {d2}") + self.print_expected() + return False + modified = {o : (d1[o], d2[o]) for o in shared_keys if d1[o] != d2[o]} + if modified is not None: + cocotb.log.info(f"[HKScoreboard][dict_compare] return False because modified \n {d1} \n {d2}") + self.print_expected() + return False + cocotb.log.info(f"[HKScoreboard][dict_compare] return True \n {d1} \n {d2}") + self.print_expected() + return True + + + def print_expected(self): + for val in self.expected.items(): + cocotb.log.info(val) diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/HKmonitor.py b/verilog/dv/cocotb/wb_models/housekeepingWB/HKmonitor.py new file mode 100644 index 00000000..7b867790 --- /dev/null +++ b/verilog/dv/cocotb/wb_models/housekeepingWB/HKmonitor.py @@ -0,0 +1,167 @@ + +import cocotb +from cocotb.triggers import Timer, RisingEdge, ReadOnly +from cocotb_bus.monitors import Monitor +from cocotb.log import SimLogFormatter, SimTimeContextFilter +from cocotb.binary import BinaryValue +from cocotb.result import TestFailure +from math import ceil +import copy +import logging +from fnmatch import fnmatch + + +class HKmonitor(Monitor): + """Observes single input """ + def __init__(self, name, block_path,interfaces, clock,reset,is_logger = False, callback=None, event=None): + self.name = name + self.interfaces = interfaces + self.clock = clock + self.reset = reset + self.block_path = block_path + self.is_logger = is_logger + self.setup_logger() + Monitor.__init__(self, callback, event) + + + async def _monitor_recv(self): + old_trans_hold = None + old_trans_no_valid = None + while True: + # Capture signal at rising edge of clock + if "_clk" in self.interfaces: # for interfaces with own clock + signal = self.block_path._id(self.interfaces['_clk']['signal'],False) + await RisingEdge(signal) + else: + await RisingEdge(self.clock) + + + # if self.reset.value.binstr == '0': + # continue + + if "_valid_cycle" in self.interfaces: # for interfaces with valid signal + signal = self.block_path._id(self.interfaces['_valid_cycle']['signal'],False).value.binstr + if signal is not '1': + continue + + if "_valid_cycle_n" in self.interfaces: # for interfaces with valid signal + signal = self.block_path._id(self.interfaces['_valid_cycle']['signal'],False).value.binstr + if signal is not '0': + continue + + # update signal + for key2,signal in self.interfaces.items(): + # if fnmatch(key2,"_*"): + # continue + signal['val'] = self.block_path._id(signal['signal'],False).value + + # if no_valid signal exist trans didn't change so monitor will not monitor anything + # no_valid means if the signal didn't change no addition action would needed + if "_no_valid" in self.interfaces: + if old_trans_no_valid is None: + old_trans_no_valid = copy.deepcopy(self.interfaces) + elif (old_trans_no_valid == self.interfaces): + return + else: + old_trans_no_valid = copy.deepcopy(self.interfaces) + + # logger + self.logger.debug(f' ') + self.handler.terminator = "" + self.handler.setFormatter(SimLogFormatter()) + self.logger.debug(f'') + self.handler.setFormatter(logging.Formatter('%(message)s')) + for key2,signal in self.interfaces.items(): + if fnmatch(key2,"_*"): + continue + if signal['val'].is_resolvable: + length = self.lengths[key2] - (len(hex(signal['val'].integer))) + self.logger.debug(f" {hex(signal['val'].integer)}{' '*length}|") + # signal['val'] = self.block_path._id(signal['signal'],False).value.integer + else: + length = self.lengths[key2] - (len('x')) + self.logger.debug(f" x{' '*length}|") + self.handler.terminator = "\n" + + # special case in HKoutputsMonitorwishbone when writing to reg_mprj_datal(because it uses _buf) the data out is x's + # and in this case scoreboard raise obejection that the value is unresolved + if self.name == "HKoutputsMonitorwishbone": + if not self.interfaces['data']['val'].is_resolvable: + self.interfaces['data']['val'] = BinaryValue(value=0,n_bits=self.interfaces['data']['val'].n_bits) + cocotb.log.debug(f'[HKmonitor][_monitor_recv] interface at monitor {self.name} self.interfaces {self.interfaces}') + self._recv(self.interfaces) + + ## assertion that the values can't change until hold is released + if "_hold" in self.interfaces: + if old_trans_hold is None: + skip = False + old_trans_hold = copy.deepcopy(self.interfaces) + elif self.interfaces['_hold']['val'] == BinaryValue(value=1): + skip = True + elif skip: + old_trans_hold = copy.deepcopy(self.interfaces) + skip = False + else: + if old_trans_hold != self.interfaces: + cocotb.log.error(f'[HKmonitor][_monitor_recv] interface at monitor {self.name} change value before hold value is asserted \nold value {old_trans_hold} \nnew value {self.interfaces}') + raise TestFailure + + + """method for setting up logger for WB model""" + def setup_logger(self): + self.logger = logging.getLogger(f'HouseKeeping{self.name}') + self.logger.setLevel(logging.DEBUG) + if not self.is_logger: + self.logger.setLevel(logging.INFO) + self.handler = logging.StreamHandler() + # return + else : + self.handler = logging.FileHandler(f"{self.name}.log",mode='w') + self.handler.addFilter(SimTimeContextFilter()) + self.logger.addHandler(self.handler) + # get the sizes of signals + #for key,interface in self.interfaces.items(): + for key,signal in self.interfaces.items(): + if fnmatch(key,"_*"): + continue + signal['val'] = self.block_path._id(signal['signal'],False).value + size = signal['val'].n_bits + signal['val'] = BinaryValue(value = int(size) * '1',n_bits=size) + # set the logger file header + # set first line + self.handler.terminator = "" + self.logger.debug(f' timestamp level ') + length =0 + for key2,signal in self.interfaces.items(): + if fnmatch(key2,"_*"): + continue + length += max(ceil(signal['val'].n_bits/4)+2 , len(key2)) +3 + length -= len(key)+1 + self.logger.debug(f'| signals {" "*int(length)}') + self.handler.terminator = "\n" + self.logger.debug(f' ') + # set second line + self.handler.terminator = "" + self.logger.debug(f'{" "*20}|') + length =0 + self.lengths = dict() + for key2,signal in self.interfaces.items(): + if fnmatch(key2,"_*"): + continue + self.lengths[key2] = max((len(hex(signal['val'].integer))),len(key2)) +1 + length = self.lengths[key2] - len(key2) + self.logger.debug(f'{key2}{" "*length} ') + self.handler.terminator = "\n" + + +class color: + PURPLE = '\033[95m' + CYAN = '\033[96m' + DARKCYAN = '\033[36m' + BLUE = '\033[94m' + GREEN = '\033[92m' + YELLOW = '\033[93m' + RED = '\033[91m' + BOLD = '\033[1m' + UNDERLINE = '\033[4m' + END = '\033[0m' \ No newline at end of file diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingIF.json b/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingIF.json new file mode 100644 index 00000000..658a54eb --- /dev/null +++ b/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingIF.json @@ -0,0 +1,133 @@ +{ + "inputs" : { "wishbone": {"adr": {"signal":"wb_adr_i","val":0}, + "data": {"signal":"wb_dat_i","val":0}, + "sel": {"signal":"wb_sel_i","val":0}, + "write_en": {"signal":"wb_we_i","val":0}, + "cycle_valid": {"signal":"wb_cyc_i","val":0}, + "stb": {"signal":"wb_stb_i","val":0}, + "_clk": {"signal":"wb_clk_i","val":0}, + "_rst": {"signal":"wb_rstn_i","val":0}, + "_hold": {"signal":"wb_ack_o","val":0}, + "_valid_cycle":{"signal":"wb_cyc_i","val":0}}, + + "user_clk": {"user_clk": {"signal":"user_clock","val":0}}, + "trap": {"user_clk": {"signal":"trap","val":0}}, + + "UART": {"TX": {"signal":"ser_tx","val":0}, + "gpio_in": {"signal":"mgmt_gpio_in","val":0}, + "enable": {"signal":"uart_enabled","val":0}}, + + "SPI": {"CSB": {"signal":"bin3","val":0}, + "SCK": {"signal":"bin4","val":0}, + "SDI": {"signal":"bin2","val":0}, + "_clk": {"signal":"bin4","val":0}, + "_valid_cycle_n":{"signal":"bin3","val":0} + }, + + "SPI_master": {"CSB": {"signal":"spi_csb","val":0}, + "SCK": {"signal":"spi_sck","val":0}, + "SDO": {"signal":"spi_sdo","val":0}, + "SDO_en": {"signal":"spi_sdoenb","val":0}, + "spi_enabled": {"signal":"spi_enabled","val":0}, + "_clk": {"signal":"spi_sck","val":0}, + "_valid_cycle_n":{"signal":"spi_csb","val":0} + }, + + "gpio_data": {"data": {"signal":"mgmt_gpio_in","val":0}}, + + "QSPI_mgmt": {"clk": {"signal":"spimemio_flash_clk","val":0}, + "CSB": {"signal":"spimemio_flash_csb","val":0}, + "io0_oen": {"signal":"spimemio_flash_io0_oeb","val":0}, + "io1_oen": {"signal":"spimemio_flash_io1_oeb","val":0}, + "io2_oen": {"signal":"spimemio_flash_io2_oeb","val":0}, + "io3_oen": {"signal":"spimemio_flash_io3_oeb","val":0}, + "data0": {"signal":"spimemio_flash_io0_do","val":0}, + "data1": {"signal":"spimemio_flash_io1_do","val":0}, + "data2": {"signal":"spimemio_flash_io2_do","val":0}, + "data3": {"signal":"spimemio_flash_io3_do","val":0}, + "qspi_en": {"signal":"qspi_enabled","val":0}, + "_clk": {"signal":"spimemio_flash_clk","val":0}}, + + "debug": {"data": {"signal":"debug_out","val":0}, + "out_en": {"signal":"debug_oeb","val":0}, + "gpio_in": {"signal":"mgmt_gpio_in","val":0}, + "enable": {"signal":"debug_mode","val":0}}, + + "QSPI_pad": {"data0": {"signal":"pad_flash_io0_di","val":0}, + "data1": {"signal":"pad_flash_io1_di","val":0}}, + + "sram": {"data": {"signal":"pad_flash_io0_di","val":0}}, + + "system": {"vcc1_good": {"signal":"usr1_vcc_pwrgood","val":0}, + "vcc2_good": {"signal":"usr2_vcc_pwrgood","val":0}, + "vdd1_good": {"signal":"usr1_vdd_pwrgood","val":0}, + "vdd2_good": {"signal":"usr2_vdd_pwrgood","val":0}, + "_no_valid": {"signal":"usr2_vdd_pwrgood","val":0}}, + + "project_id": {"mask": {"signal":"mask_rev_in","val":0}} + + }, + + "outputs" : { "wishbone": {"ack": {"signal":"wb_ack_o","val":0}, + "data": {"signal":"wb_dat_o","val":0}, + "_valid_cycle":{"signal":"wb_ack_o","val":0}}, + + "UART": {"RX": {"signal":"ser_rx","val":0}}, + + "SPI": {"CSB": {"signal":"bin3","val":0}, + "SCK": {"signal":"bin4","val":0}, + "SDO": {"signal":"bin1","val":0}, + "_clk": {"signal":"bin4","val":0}, + "_valid_cycle_n":{"signal":"bin3","val":0} + }, + + "SPI_master": {"SDI": {"signal":"spi_sdi","val":0}, + "_clk": {"signal":"spi_sck","val":0}}, + + "clk_ctrl": {"pll_en": {"signal":"pll_ena","val":0}, + "pll_dco_en": {"signal":"pll_dco_ena","val":0}, + "pll_div": {"signal":"pll_div","val":0}, + "pll_sel": {"signal":"pll_sel","val":0}, + "pll90_sel": {"signal":"pll90_sel","val":0}, + "pll_trim": {"signal":"pll_trim","val":0}, + "pll_bypass": {"signal":"pll_bypass","val":0}}, + + "external": {"irq": {"signal":"irq","val":0}, + "rst": {"signal":"reset","val":0}}, + + "gpio_loader":{"clk": {"signal":"serial_clock","val":0}, + "load": {"signal":"serial_load","val":0}, + "rst": {"signal":"serial_resetn","val":0}, + "data_1": {"signal":"serial_data_1","val":0}, + "data_2": {"signal":"serial_data_2","val":0}}, + + "gpio_data": {"data": {"signal":"mgmt_gpio_out","val":0}, + "enable": {"signal":"mgmt_gpio_oeb","val":0}}, + + "pwr_ctrl": {"data": {"signal":"pwr_ctrl_out","val":0}}, + + "QSPI_mgmt": {"data0": {"signal":"spimemio_flash_io0_di","val":0}, + "data1": {"signal":"spimemio_flash_io1_di","val":0}, + "data2": {"signal":"spimemio_flash_io2_di","val":0}, + "data3": {"signal":"spimemio_flash_io3_di","val":0}}, + + "debug": {"data": {"signal":"debug_in","val":0}}, + + "QSPI_pad": {"clk": {"signal":"pad_flash_clk","val":0}, + "clk_en": {"signal":"pad_flash_clk_oeb","val":0}, + "CSB": {"signal":"pad_flash_csb","val":0}, + "CSB_en": {"signal":"pad_flash_csb_oeb","val":0}, + "data0": {"signal":"pad_flash_io0_do","val":0}, + "data0_oen": {"signal":"pad_flash_io0_oeb","val":0}, + "data0_ien": {"signal":"pad_flash_io0_ieb","val":0}, + "data1": {"signal":"pad_flash_io1_do","val":0}, + "data1_oen": {"signal":"pad_flash_io1_oeb","val":0}, + "data1_ien": {"signal":"pad_flash_io1_ieb","val":0}, + "_clk": {"signal":"spimemio_flash_clk","val":0}}, + + "sram": {"clk": {"signal":"sram_ro_clk","val":0}, + "CSB": {"signal":"sram_ro_csb","val":0}, + "adr": {"signal":"sram_ro_addr","val":0}} + } + + } \ No newline at end of file diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingWB.py b/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingWB.py new file mode 100644 index 00000000..7d717ce0 --- /dev/null +++ b/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingWB.py @@ -0,0 +1,114 @@ +import json +import cocotb +from cocotb.triggers import Timer, RisingEdge, ReadOnly +from cocotb_bus.monitors import Monitor +from cocotb.log import SimLogFormatter, SimTimeContextFilter +from cocotb.binary import BinaryValue +from math import ceil +from wb_models.housekeepingWB.HKmonitor import HKmonitor +from wb_models.housekeepingWB.HKSPImonitor import HKSPImonitor +from wb_models.housekeepingWB.HKSPImonitor import CSBmonitor +from wb_models.housekeepingWB.HK_models import HK_models +from cocotb_bus.scoreboard import Scoreboard +import logging +import fnmatch +import copy +from cocotb.result import TestFailure +from common import Macros + + +class HK_whiteBox: + def __init__(self,dut,loggers=False): + self.dut = dut + self.hk_hdl = dut.uut.housekeeping + # self.hkspi_hdl = dut.uut.housekeeping.hkspi + self.clk = self.dut.uut.mprj_clock + self.reset = self.dut.uut.resetb + self.logger = loggers + self.load_js() + self.setupModels() + self.Monitors() + cocotb.scheduler.add(self.reg_model_sb()) + """load json models""" + def load_js(self): + with open('wb_models/housekeepingWB/housekeepingIF.json') as f: + self.interface = json.load(f) + with open('wb_models/housekeepingWB/HK_regs.json') as f: + self.reg_model = json.load(f) + self.output_if = copy.deepcopy(self.interface['outputs']) + + """"method to add the housekeeping monitors""" + def Monitors(self): + inputs = self.interface['inputs'] + outputs = self.interface['outputs'] + # wishbone + wishbone_mon_i = HKmonitor(f"HKinputsMonitorwishbone",self.hk_hdl,inputs['wishbone'],self.clk,self.reset,self.logger,callback=self.wb_models.wishbone_model) + wishbone_mon_o = HKmonitor(f"HKoutputsMonitorwishbone",self.hk_hdl,outputs['wishbone'],self.clk,self.reset,self.logger) + wishbone_sb = Scoreboard(SB_name("wishbone_sb"),fail_immediately=False) + wishbone_sb.add_interface(wishbone_mon_o, self.wb_models.exp_out_wb) + # system + system_mon_i = HKmonitor(f"HKinputsMonitorsystem",self.hk_hdl,inputs['system'],self.clk,self.reset,self.logger,callback=self.wb_models.system_model) + # UART + UART_mon_i = HKmonitor(f"HKinputsMonitorUART",self.hk_hdl,inputs['UART'],self.clk,self.reset,self.logger,callback=self.wb_models.UART_model) + UART_mon_o = HKmonitor(f"HKoutputsMonitorUART",self.hk_hdl,outputs['UART'],self.clk,self.reset,self.logger) + UART_sb = Scoreboard(SB_name("UART_sb"),fail_immediately=False) + UART_sb.add_interface(UART_mon_o, self.wb_models.exp_out_uart_rx) + + # debug + debug_mon_i = HKmonitor(f"HKinputsMonitordebug",self.hk_hdl,inputs['debug'],self.clk,self.reset,self.logger,callback=self.wb_models.debug_model) + debug_mon_o = HKmonitor(f"HKoutputsMonitordebug",self.hk_hdl,outputs['debug'],self.clk,self.reset,self.logger) + debug_sb = Scoreboard(SB_name("debug_sb"),fail_immediately=False) + debug_sb.add_interface(debug_mon_o, self.wb_models.exp_out_debug) + + # SPI + SPI_mon_i = HKSPImonitor(f"HKinputsMonitorSPI",self.hk_hdl,inputs['SPI'],self.clk,self.reset,self.logger,callback=self.wb_models.spi_model) + SPI_mon_o = HKSPImonitor(f"HKoutputsMonitorSPI",self.hk_hdl,outputs['SPI'],self.clk,self.reset,self.logger,input=False) + CSBmonitor(f"HKCSBmonitor",self.hk_hdl,outputs['SPI'],self.clk,self.reset,False,callback=self.wb_models.reset_spi_vals) + SPI_sb = Scoreboard(SB_name("SPI_sb"),fail_immediately=False) + SPI_sb.add_interface(SPI_mon_o, self.wb_models.exp_out_spi) + + """initialize all models needed""" + def setupModels(self): + with open('wb_models/housekeepingWB/HK_regs.json') as f: + self.reg_model = json.load(f) + self.wb_models = HK_models(self.reg_model,self.output_if,self.hk_hdl) + + """scoreboard for register model check the reg model with RTL every clock""" + async def reg_model_sb(self): + while True: + await RisingEdge(self.clk) + for key,memory_block in self.reg_model.items(): + if fnmatch.fnmatch(key, "_*"): + continue + for reg_shift,reg in memory_block.items(): + for field in reg: + if reg_shift == "base_addr": + continue + RTL_reg_name = field[1] + if RTL_reg_name == None: + cocotb.log.debug(f"[HK_whiteBox][reg_model_sb] register {field[1]} in {key} doesn't have a RTL register") + continue + if isinstance(field[1],list): + RTL_name = field[1][0] + first_index = int(field[1][1]) + second_index= int(field[1][2]) + if Macros['GL']: + if RTL_name in ["mfgr_id","prod_id","mask_rev","mgmt_gpio_data"]: continue #TODO: change with SDF only + if Macros['GL']: + if fnmatch.fnmatch (RTL_name,"gpio_configure*"): continue #TODO: update gpio_configure and mgmt_gpio_data to get each bit in the SDF case + RTL_reg_path = self.hk_hdl._id(RTL_name,False) + size = RTL_reg_path.value.n_bits-1 + RTL_reg_val = RTL_reg_path.value[size-first_index:size-second_index] + else : + if field[1] in ["pwr_ctrl_out"]: continue #TODO: delete when reset value is spicified + RTL_reg_path = self.hk_hdl._id(field[1],False) + RTL_reg_val = RTL_reg_path.value + if (RTL_reg_val.integer != field[6]): + cocotb.log.error(f'[HK_whiteBox][reg_model_sb] mismatch in register {field[1]} in {key} expected val = {int(field[6])} actual val = {int(RTL_reg_val.binstr,2)} ' ) + else: + cocotb.log.debug(f'[HK_whiteBox][reg_model_sb] match in register {field[1]} in {key} expected val = {field[6]} actual val = {RTL_reg_val.integer} ' ) + +class SB_name: + def __init__(self,name) -> None: + self._name=name + From fc8369443c03bf47726630997b26d9987cd5fba5 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 30 Sep 2022 01:57:20 -0700 Subject: [PATCH 02/76] fix bug move some housekeeping initialization wires and regs before they are used --- verilog/rtl/housekeeping.v | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/verilog/rtl/housekeeping.v b/verilog/rtl/housekeeping.v index 76a5807e..3ffa0a42 100644 --- a/verilog/rtl/housekeeping.v +++ b/verilog/rtl/housekeeping.v @@ -300,6 +300,13 @@ module housekeeping #( assign spimemio_flash_io0_di = (pass_thru_mgmt_delay) ? 1'b0 : pad_flash_io0_di; assign spimemio_flash_io1_di = (pass_thru_mgmt) ? 1'b0 : pad_flash_io1_di; + + wire [11:0] mfgr_id; + wire [7:0] prod_id; + wire [31:0] mask_rev; + + reg serial_busy; + // Wishbone bus "back door" to SPI registers. This section of code // (1) Maps SPI byte addresses to memory map 32-bit addresses // (2) Applies signals to the housekeeping SPI to mux in the SPI address, @@ -635,6 +642,15 @@ module housekeeping #( endcase end endfunction + + // SPI is considered active when the GPIO for CSB is set to input and + // CSB is low. SPI is considered "busy" when rdstb or wrstb are high, + // indicating that the SPI will read or write a byte on the next SCK + // transition. + + wire spi_is_enabled = (~gpio_configure[3][INP_DIS]) & (~hkspi_disable); + wire spi_is_active = spi_is_enabled && (mgmt_gpio_in[3] == 1'b0); + wire spi_is_busy = spi_is_active && (rdstb || wrstb); /* Wishbone back-door state machine and address translation */ @@ -766,14 +782,7 @@ module housekeeping #( .pass_thru_user_reset(pass_thru_user_reset) ); - // SPI is considered active when the GPIO for CSB is set to input and - // CSB is low. SPI is considered "busy" when rdstb or wrstb are high, - // indicating that the SPI will read or write a byte on the next SCK - // transition. - wire spi_is_enabled = (~gpio_configure[3][INP_DIS]) & (~hkspi_disable); - wire spi_is_active = spi_is_enabled && (mgmt_gpio_in[3] == 1'b0); - wire spi_is_busy = spi_is_active && (rdstb || wrstb); // GPIO data handling to and from the management SoC @@ -869,7 +878,6 @@ module housekeeping #( reg serial_clock_pre; reg serial_resetn_pre; reg serial_load_pre; - reg serial_busy; wire serial_data_1; wire serial_data_2; wire serial_clock; @@ -980,10 +988,6 @@ module housekeeping #( // SPI Identification - wire [11:0] mfgr_id; - wire [7:0] prod_id; - wire [31:0] mask_rev; - assign mfgr_id = 12'h456; // Hard-coded assign prod_id = 8'h11; // Hard-coded assign mask_rev = mask_rev_in; // Copy in to out. From f8c8d831d01e0f9e5547dd16afdd85a115fcebc7 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 30 Sep 2022 02:11:57 -0700 Subject: [PATCH 03/76] Add RTL for 2 debug regs used to test and located inside user_project_wrapper --- verilog/rtl/__user_project_wrapper.v | 31 +++++++++++++++++++ verilog/rtl/debug_regs.v | 45 ++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 verilog/rtl/debug_regs.v diff --git a/verilog/rtl/__user_project_wrapper.v b/verilog/rtl/__user_project_wrapper.v index 98ff3a83..9395fb07 100644 --- a/verilog/rtl/__user_project_wrapper.v +++ b/verilog/rtl/__user_project_wrapper.v @@ -87,4 +87,35 @@ assign io_oeb = 0; assign io_out = io_in; `endif +// splitting the address space to user address space and debug address space +// debug address space are the last 2 registers of user_project_wrapper address space +wire wbs_cyc_i_user; +wire wbs_ack_o_user; +wire [31:0] wbs_dat_o_user; + +wire wbs_cyc_i_debug; +wire wbs_ack_o_debug; +wire [31:0] wbs_dat_o_debug; + +// reserve the last 2 regs for debugging registers +assign wbs_cyc_i_user = (wbs_adr_i[19:3] != 17'h1ffff) ? wbs_cyc_i : 0; +assign wbs_cyc_i_debug = (wbs_adr_i[19:3] == 17'h1ffff) ? wbs_cyc_i : 0; + +assign wbs_ack_o = (wbs_adr_i[19:3] == 17'h1ffff) ? wbs_ack_o_debug : wbs_ack_o_debug; +assign wbs_dat_o = (wbs_adr_i[19:3] == 17'h1ffff) ? wbs_dat_o_debug : wbs_dat_o_user; + + +debug_regs debug( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wbs_cyc_i(wbs_cyc_i_debug), + .wbs_stb_i(wbs_stb_i), + .wbs_we_i(wbs_we_i), + .wbs_sel_i(wbs_sel_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_ack_o(wbs_ack_o_debug), + .wbs_dat_o(wbs_dat_o_debug) +); + endmodule // user_project_wrapper diff --git a/verilog/rtl/debug_regs.v b/verilog/rtl/debug_regs.v new file mode 100644 index 00000000..df1aaa13 --- /dev/null +++ b/verilog/rtl/debug_regs.v @@ -0,0 +1,45 @@ +// module that has registers used for debug +module debug_regs ( + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output reg wbs_ack_o, + output reg [31:0] wbs_dat_o); + + reg [31:0] debug_reg_1; + reg [31:0] debug_reg_2; + + // write + always @(posedge wb_clk_i or posedge wb_rst_i) begin + if (wb_rst_i) begin + debug_reg_1 <=0; + debug_reg_2 <=0; + wbs_dat_o <=0; + wbs_ack_o <=0; + end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o)begin // write + // write to reg1 + debug_reg_1[7:0] <= (!wbs_adr_i[2] && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_1[7:0]; + debug_reg_1[15:8] <= (!wbs_adr_i[2] && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_1[15:8]; + debug_reg_1[23:16] <= (!wbs_adr_i[2] && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_1[23:16]; + debug_reg_1[31:24] <= (!wbs_adr_i[2] && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_1[31:24]; + // write to reg2 + debug_reg_2[7:0] <= (wbs_adr_i[2] && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_2[7:0]; + debug_reg_2[15:8] <= (wbs_adr_i[2] && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_2[15:8]; + debug_reg_2[23:16] <= (wbs_adr_i[2] && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_2[23:16]; + debug_reg_2[31:24] <= (wbs_adr_i[2] && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_2[31:24]; + wbs_ack_o <= 1; + end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o) begin // read + wbs_dat_o <= (wbs_adr_i[3]) ? debug_reg_2 : debug_reg_1; + wbs_ack_o <= 1; + end else begin + wbs_ack_o <= 0; + wbs_dat_o <= 0; + end + end +endmodule +`default_nettype wire \ No newline at end of file From f08c22023cab0c4b688331a4ccde76fbdaadc659 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 30 Sep 2022 09:35:22 +0000 Subject: [PATCH 04/76] Apply automatic changes to Manifest and README.rst --- manifest | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/manifest b/manifest index 9ddf9351..e432f18c 100644 --- a/manifest +++ b/manifest @@ -1,7 +1,7 @@ 535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v -b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v +d1c5814b58ece3ee2cccdf95dd332529f653fc2e verilog/rtl/__user_project_wrapper.v 6576abded424d948d2a7e71c2b4a4df1eda77238 verilog/rtl/caravan.v a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v @@ -11,12 +11,13 @@ cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v 54de41c59139783d39654e1f0a86e2880cb7b076 verilog/rtl/chip_io_alt.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v +f03d9a8496376951855b507cfbcd4afe104e36ac verilog/rtl/debug_regs.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v 60d2384a91301fec5721953d87931193681822c4 verilog/rtl/gpio_control_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v -cf97aef32db28c44e3750e201867d5bf9243e151 verilog/rtl/housekeeping.v +98563c0c63ce5057e95b1901b5e97bcfe9878cb1 verilog/rtl/housekeeping.v 3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v 0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v 3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v From 7546ce10c78a37848adaaa382331c2afbdda68f3 Mon Sep 17 00:00:00 2001 From: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Date: Fri, 30 Sep 2022 11:42:47 +0200 Subject: [PATCH 05/76] simple readme --- verilog/dv/cocotb/README.md | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 verilog/dv/cocotb/README.md diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md new file mode 100644 index 00000000..5512fc70 --- /dev/null +++ b/verilog/dv/cocotb/README.md @@ -0,0 +1,21 @@ +# How to run test: + +Navigate to the cocotb directory and run the following command +## To run test : + >python3 run.py -t -sim -tag + + Or + + >python3 run.py --test -sim -tag + +## To run regression + >python3 run.py -r -tag + + Or + + >python3 run.py --regression -tag + +## Notes +> Tests and regressions can be used in the same command + +> Tests and regressions can be found under cocotb/tests.json From f2ca45358b58270a2439b538bf92427bf57a9228 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 30 Sep 2022 02:49:03 -0700 Subject: [PATCH 06/76] remove AN.DB folder from git hub --- verilog/dv/cocotb/.gitignore | 3 ++- verilog/dv/cocotb/AN.DB/.vcs_lib_lock | 0 2 files changed, 2 insertions(+), 1 deletion(-) delete mode 100644 verilog/dv/cocotb/AN.DB/.vcs_lib_lock diff --git a/verilog/dv/cocotb/.gitignore b/verilog/dv/cocotb/.gitignore index e9208974..907c648c 100644 --- a/verilog/dv/cocotb/.gitignore +++ b/verilog/dv/cocotb/.gitignore @@ -7,4 +7,5 @@ __pycache__ *.xml *.yml *.hexe -*.elf \ No newline at end of file +*.elf +AN.DB \ No newline at end of file diff --git a/verilog/dv/cocotb/AN.DB/.vcs_lib_lock b/verilog/dv/cocotb/AN.DB/.vcs_lib_lock deleted file mode 100644 index e69de29b..00000000 From 407b0be30619051f19c16a32a0e44064eea1ef00 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 01:48:55 -0700 Subject: [PATCH 07/76] Update script to return fatal error when hex generation fails --- verilog/dv/cocotb/run.py | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/verilog/dv/cocotb/run.py b/verilog/dv/cocotb/run.py index 9eef36ea..162dbf3d 100644 --- a/verilog/dv/cocotb/run.py +++ b/verilog/dv/cocotb/run.py @@ -116,13 +116,15 @@ class RunTest: f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}") hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} " sed_command = f"sed -ie 's/@10/@00/g' {hex_file}" - os.system(f"docker run -it -v /home:/home efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '") + hex_gen_state = os.system(f"docker run -it -v /home:/home efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '") self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n") self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n") self.full_terminal.write(os.path.expandvars(sed_command)+"\n"+"\n") self.cd_cocotb() self.full_terminal.close() - + if hex_gen_state != 0 : + print(f"fatal: Error when generating hex") + sys.exit() def cd_make(self): os.chdir(f"{os.getenv('VERILOG_PATH')}/dv/make") From 18b4f365255cc9b1af8fc3f68395b96464b3466f Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 02:23:47 -0700 Subject: [PATCH 08/76] add test uart_rx --- .../dv/cocotb/hex_files/timer0_periodic.hex | 118 +++++++++--------- verilog/dv/cocotb/hex_files/uart_rx.hex | 77 ++++++++++++ verilog/dv/cocotb/tests.json | 6 + verilog/dv/cocotb/tests/uart/uart.py | 76 ++++++++++- verilog/dv/cocotb/tests/uart/uart_rx.c | 63 ++++++++++ 5 files changed, 276 insertions(+), 64 deletions(-) create mode 100755 verilog/dv/cocotb/hex_files/uart_rx.hex create mode 100644 verilog/dv/cocotb/tests/uart/uart_rx.c diff --git a/verilog/dv/cocotb/hex_files/timer0_periodic.hex b/verilog/dv/cocotb/hex_files/timer0_periodic.hex index 45cfd920..d839cf32 100755 --- a/verilog/dv/cocotb/hex_files/timer0_periodic.hex +++ b/verilog/dv/cocotb/hex_files/timer0_periodic.hex @@ -1,60 +1,60 @@ @00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FD 23 26 81 02 13 04 01 03 -B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 -B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 -93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00 -23 A0 07 00 B7 57 00 F0 23 A0 07 00 B7 57 00 F0 -93 87 47 00 13 07 00 30 23 A0 E7 00 B7 57 00 F0 -93 87 87 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 -93 87 C7 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 -93 87 07 01 83 A7 07 00 23 26 F4 FE 23 24 04 FE -93 07 00 19 23 20 F4 FE 23 22 04 FE 6F 00 C0 0C -B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 -B7 57 00 F0 93 87 07 01 83 A7 07 00 23 2E F4 FC -03 27 C4 FD 83 27 C4 FE 63 F8 E7 06 83 27 84 FE -93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 10 00 -63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 01 -23 A0 E7 00 6F 00 40 04 03 27 84 FE 93 07 20 00 -63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 -23 A0 E7 00 6F 00 40 02 03 27 84 FE 93 07 30 00 -63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 03 -23 A0 E7 00 6F 00 00 04 03 27 C4 FD 83 27 C4 FE -63 7A F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 04 -23 A0 E7 00 83 27 C4 FD 23 26 F4 FE 83 27 44 FE -93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE -E3 48 F7 F2 83 27 84 FE 63 9A 07 00 B7 07 10 30 -93 87 87 FF 13 07 E0 0E 23 A0 E7 00 B7 07 10 30 -93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 -03 24 C1 02 13 01 01 03 67 80 00 00 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FD 23 26 81 02 13 04 01 03 +B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 +B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 +93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00 +23 A0 07 00 B7 57 00 F0 23 A0 07 00 B7 57 00 F0 +93 87 47 00 13 07 00 30 23 A0 E7 00 B7 57 00 F0 +93 87 87 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 +93 87 C7 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 +93 87 07 01 83 A7 07 00 23 26 F4 FE 23 24 04 FE +93 07 00 19 23 20 F4 FE 23 22 04 FE 6F 00 C0 0C +B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 +B7 57 00 F0 93 87 07 01 83 A7 07 00 23 2E F4 FC +03 27 C4 FD 83 27 C4 FE 63 F8 E7 06 83 27 84 FE +93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 10 00 +63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 01 +23 A0 E7 00 6F 00 40 04 03 27 84 FE 93 07 20 00 +63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 +23 A0 E7 00 6F 00 40 02 03 27 84 FE 93 07 30 00 +63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 03 +23 A0 E7 00 6F 00 00 04 03 27 C4 FD 83 27 C4 FE +63 7A F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 04 +23 A0 E7 00 83 27 C4 FD 23 26 F4 FE 83 27 44 FE +93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE +E3 48 F7 F2 83 27 84 FE 63 9A 07 00 B7 07 10 30 +93 87 87 FF 13 07 E0 0E 23 A0 E7 00 B7 07 10 30 +93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 +03 24 C1 02 13 01 01 03 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/uart_rx.hex b/verilog/dv/cocotb/hex_files/uart_rx.hex new file mode 100755 index 00000000..db6552a6 --- /dev/null +++ b/verilog/dv/cocotb/hex_files/uart_rx.hex @@ -0,0 +1,77 @@ +@00000000 +6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 +23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE +23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE +23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD +23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD +13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 +03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 +03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 +03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 +03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 +17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 +73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 +13 06 C6 3C 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 +93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 +6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 +EF 00 40 28 6F 00 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 +13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE +83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 +13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 +23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC +B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 +B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 +13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 +03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF +23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 +13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 +13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 +67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 +23 26 A4 FE 83 27 C4 FE 83 A7 07 00 13 85 07 00 +03 24 C1 01 13 01 01 02 67 80 00 00 13 01 01 FF +23 26 11 00 23 24 81 00 13 04 01 01 B7 67 00 F0 +13 85 87 80 EF F0 1F FC 93 07 05 00 13 85 07 00 +83 20 C1 00 03 24 81 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 +93 07 05 00 A3 07 F4 FE 03 47 F4 FE 93 07 A0 00 +63 16 F7 00 13 05 D0 00 EF F0 9F FD 13 00 00 00 +B7 67 00 F0 93 87 47 80 03 A7 07 00 93 07 10 00 +E3 08 F7 FE B7 67 00 F0 93 87 07 80 03 47 F4 FE +23 A0 E7 00 13 00 00 00 83 20 C1 01 03 24 81 01 +13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00 +23 2C 81 00 13 04 01 02 23 26 A4 FE 6F 00 C0 01 +83 27 C4 FE 13 87 17 00 23 26 E4 FE 83 C7 07 00 +13 85 07 00 EF F0 DF F6 83 27 C4 FE 83 C7 07 00 +E3 90 07 FE 13 00 00 00 13 00 00 00 83 20 C1 01 +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE +23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +13 00 00 00 EF F0 9F EF 13 07 05 00 93 07 10 00 +E3 0A F7 FE B7 67 00 F0 93 87 07 80 83 A7 07 00 +03 27 C4 FE 03 47 07 00 63 9C E7 00 B7 07 10 30 +93 87 87 FF 13 07 B0 01 23 A0 E7 00 6F 00 40 01 +B7 07 10 30 93 87 87 FF 13 07 E0 01 23 A0 E7 00 +13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 +67 80 00 00 13 01 01 FF 23 26 11 00 23 24 81 00 +13 04 01 01 B7 47 00 F0 93 87 07 80 13 07 10 00 +23 A0 E7 00 B7 07 10 30 93 87 87 FF 23 A0 07 00 +B7 07 10 30 93 87 C7 FF 23 A0 07 00 B7 07 00 26 +93 87 C7 03 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 87 03 13 07 30 40 23 A0 E7 00 +B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00 +B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE +B7 67 00 F0 13 07 10 00 23 A0 E7 00 B7 07 10 30 +93 87 87 FF 13 07 A0 0A 23 A0 E7 00 B7 07 00 10 +13 85 87 48 EF F0 9F EE B7 07 10 30 93 87 87 FF +13 07 B0 0B 23 A0 E7 00 B7 07 00 10 13 85 C7 48 +EF F0 DF EC B7 07 10 30 93 87 87 FF 13 07 C0 0C +23 A0 E7 00 B7 07 00 10 13 85 07 49 EF F0 1F EB +13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01 +67 80 00 00 +@00000484 +00 00 00 00 42 00 00 00 4D 00 00 00 41 00 00 00 +00 00 00 00 diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index f83fac8e..5d04ea74 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -156,5 +156,11 @@ "GL":["nightly","weekly","tape_out"], "GL_SDF":["weekly","tape_out"], "description":"test uart transmit"} + ,"uart_rx" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"test uart reception"} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 729c6be9..e46854d0 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -13,7 +13,8 @@ from caravel import GPIO_MODE baud_rate = 9600 number_of_bits = 8 bit_rate_ns = round((10**9)/(baud_rate*number_of_bits) ) - +clk = 12.5 +bit_time = 10**5 * clk / (96) reg = Regs() @@ -25,19 +26,19 @@ async def uart_tx(dut): cpu.cpu_force_reset() cpu.cpu_release_reset() cocotb.log.info(f"[TEST] Start uart test") - expected_data = "Monitor: Test UART (RTL) passed" + expected_msg = "Monitor: Test UART (RTL) passed" await wait_reg1(cpu,caravelEnv,0XAA) - cocotb.log.info (f"[TEST] start sending on uart") + cocotb.log.info (f"[TEST] start receiving from uart") counter =0 data_out ='' while True: if counter %8 == 0: if counter != 0: data_out = data_out+chr(int(char,2)) - cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_data}'") - if data_out == expected_data: + cocotb.log.info (f"[TEST] msg is:'{data_out}' expected '{expected_msg}'") + if data_out == expected_msg: cocotb.log.info (f"[TEST] Pass recieve the full expected msg '{data_out}'") break await start_of_tx(caravelEnv) @@ -54,3 +55,68 @@ async def start_of_tx(caravelEnv): break await Timer(bit_rate_ns, units='ns') await Timer(bit_rate_ns, units='ns') + + +@cocotb.test() +@repot_test +async def uart_rx(dut): + caravelEnv = await test_configure(dut,timeout_cycles=95844) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start uart test") + caravelEnv.drive_gpio_in((5,5),1) + + # send first char + await wait_reg1(cpu,caravelEnv,0XAA) + await uart_send_char(caravelEnv,"B") + await uart_check_char_recieved(caravelEnv,cpu) + # send second char + await wait_reg1(cpu,caravelEnv,0XBB) + await uart_send_char(caravelEnv,"M") + await uart_check_char_recieved(caravelEnv,cpu) + # send third char + cocotb.log.info(f"[TEST] here") + await wait_reg1(cpu,caravelEnv,0XCC) + cocotb.log.info(f"[TEST] here") + await uart_send_char(caravelEnv,"A") + await uart_check_char_recieved(caravelEnv,cpu) + + + +async def uart_send_char(caravelEnv,char): + char_bits = [int(x) for x in '{:08b}'.format(ord(char))] + cocotb.log.info (f"[TEST] start sending on uart {char}") + #send start bit + caravelEnv.drive_gpio_in((5,5),0) + await Timer(bit_rate_ns, units='ns') + #send bits + for i in range(8): + caravelEnv.drive_gpio_in((5,5),char_bits[i]) + await Timer(bit_rate_ns, units='ns') + + # stop of frame + caravelEnv.drive_gpio_in((5,5),1) + await Timer(bit_rate_ns, units='ns') + await Timer(bit_rate_ns, units='ns') + # insert 4 bit delay just for debugging + await Timer(bit_rate_ns, units='ns') + await Timer(bit_rate_ns, units='ns') + await Timer(bit_rate_ns, units='ns') + await Timer(bit_rate_ns, units='ns') + + +async def uart_check_char_recieved(caravelEnv,cpu): + # check cpu recieved the correct character + while True: + reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr + reg1 = cpu.read_debug_reg1() + cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}") + if reg1 == 0x1B: + cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}") + return + if reg1 == 0x1E: + cocotb.log.error(f"[TEST] Failed Pass cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") + return + + await ClockCycles(caravelEnv.clk,1) \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/uart/uart_rx.c b/verilog/dv/cocotb/tests/uart/uart_rx.c new file mode 100644 index 00000000..16779691 --- /dev/null +++ b/verilog/dv/cocotb/tests/uart/uart_rx.c @@ -0,0 +1,63 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +// -------------------------------------------------------- + +void wait_for_char(char *c){ + + while (uart_rxempty_read() == 1); + if (reg_uart_data == *c){ + reg_debug_1 = 0x1B; // recieved the correct character + }else{ + reg_debug_1 = 0x1E; // timeout didn't recieve the character + } + +} + +void main(){ + int j; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + + // Set clock to 64 kbaud and enable the UART. It is important to do this + // before applying the configuration, or else the Tx line initializes as + // zero, which indicates the start of a byte to the receiver. + + + // Now, apply the configuration + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_uart_enable = 1; + + reg_debug_1 = 0xAA; // start sending B + wait_for_char("B"); + + reg_debug_1 = 0xBB; // start sending M + wait_for_char("M"); + + reg_debug_1 = 0xCC; // start sending A + wait_for_char("A"); + +} From 68c88b116afaeba8345e023fb911cceea75a9201 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 02:52:30 -0700 Subject: [PATCH 09/76] increase the clock period to 25ns --- verilog/dv/cocotb/tests/common_functions/test_functions.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/dv/cocotb/tests/common_functions/test_functions.py b/verilog/dv/cocotb/tests/common_functions/test_functions.py index 78de0932..de619163 100644 --- a/verilog/dv/cocotb/tests/common_functions/test_functions.py +++ b/verilog/dv/cocotb/tests/common_functions/test_functions.py @@ -22,7 +22,7 @@ from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles start up the test connecting power vdd to the design then reset and disable the CSB bit return the caravel environmnet with clock and start up """ -async def test_configure(dut,timeout_cycles=1000000,clk=12.5,timeout_precision=0.2,num_error=3): +async def test_configure(dut,timeout_cycles=1000000,clk=25,timeout_precision=0.2,num_error=3): caravelEnv = caravel.Caravel_env(dut) Timeout(caravelEnv.clk,timeout_cycles,timeout_precision) if os.getenv('ERRORMAX') != 'None': @@ -33,7 +33,7 @@ async def test_configure(dut,timeout_cycles=1000000,clk=12.5,timeout_precision=0 await caravelEnv.start_up() await ClockCycles(caravelEnv.clk, 10) # HK_whiteBox(dut) - return caravelEnv + return caravelEnv,clock class CallCounted: """Decorator to determine number of calls for a method""" From 9615629a4207c8d21ee3dac9bfa4122d9a283414 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 02:53:24 -0700 Subject: [PATCH 10/76] fix bug bit time calculation --- verilog/dv/cocotb/tests/uart/uart.py | 47 +++++++++++++++------------- 1 file changed, 25 insertions(+), 22 deletions(-) diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index e46854d0..7c3324d9 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -10,24 +10,25 @@ from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * from caravel import GPIO_MODE -baud_rate = 9600 -number_of_bits = 8 -bit_rate_ns = round((10**9)/(baud_rate*number_of_bits) ) -clk = 12.5 -bit_time = 10**5 * clk / (96) + +bit_time_ns = 0 reg = Regs() @cocotb.test() @repot_test async def uart_tx(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv,clock = await test_configure(dut,timeout_cycles=18613481) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() cocotb.log.info(f"[TEST] Start uart test") expected_msg = "Monitor: Test UART (RTL) passed" - + # calculate bit time + clk = clock.period/1000 + global bit_time_ns + bit_time_ns = round(10**5 * clk / (96)) + # wait for start of sending await wait_reg1(cpu,caravelEnv,0XAA) cocotb.log.info (f"[TEST] start receiving from uart") @@ -46,27 +47,31 @@ async def uart_tx(dut): # if temp != caravelEnv.monitor_gpio((6,6)) char = caravelEnv.monitor_gpio((6,6)).binstr + char cocotb.log.debug (f"[TEST] bit[{counter}] = {caravelEnv.monitor_gpio((6,6))} data out = {char} ") - await Timer(bit_rate_ns, units='ns') + await Timer(bit_time_ns, units='ns') counter +=1 async def start_of_tx(caravelEnv): while (True): # wait for the start of the transimission it 1 then 0 if (caravelEnv.monitor_gpio((6,6)).integer == 0): break - await Timer(bit_rate_ns, units='ns') - await Timer(bit_rate_ns, units='ns') + await Timer(bit_time_ns, units='ns') + await Timer(bit_time_ns, units='ns') @cocotb.test() @repot_test async def uart_rx(dut): - caravelEnv = await test_configure(dut,timeout_cycles=95844) + caravelEnv,clock = await test_configure(dut,timeout_cycles=95844) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() cocotb.log.info(f"[TEST] Start uart test") caravelEnv.drive_gpio_in((5,5),1) - + # calculate bit time + clk = clock.period/1000 + global bit_time_ns + bit_time_ns = round(10**5 * clk / (96)) + print (clk) # send first char await wait_reg1(cpu,caravelEnv,0XAA) await uart_send_char(caravelEnv,"B") @@ -76,9 +81,7 @@ async def uart_rx(dut): await uart_send_char(caravelEnv,"M") await uart_check_char_recieved(caravelEnv,cpu) # send third char - cocotb.log.info(f"[TEST] here") await wait_reg1(cpu,caravelEnv,0XCC) - cocotb.log.info(f"[TEST] here") await uart_send_char(caravelEnv,"A") await uart_check_char_recieved(caravelEnv,cpu) @@ -89,21 +92,21 @@ async def uart_send_char(caravelEnv,char): cocotb.log.info (f"[TEST] start sending on uart {char}") #send start bit caravelEnv.drive_gpio_in((5,5),0) - await Timer(bit_rate_ns, units='ns') + await Timer(bit_time_ns, units='ns') #send bits for i in range(8): caravelEnv.drive_gpio_in((5,5),char_bits[i]) - await Timer(bit_rate_ns, units='ns') + await Timer(bit_time_ns, units='ns') # stop of frame caravelEnv.drive_gpio_in((5,5),1) - await Timer(bit_rate_ns, units='ns') - await Timer(bit_rate_ns, units='ns') + await Timer(bit_time_ns, units='ns') + await Timer(bit_time_ns, units='ns') # insert 4 bit delay just for debugging - await Timer(bit_rate_ns, units='ns') - await Timer(bit_rate_ns, units='ns') - await Timer(bit_rate_ns, units='ns') - await Timer(bit_rate_ns, units='ns') + await Timer(bit_time_ns, units='ns') + await Timer(bit_time_ns, units='ns') + await Timer(bit_time_ns, units='ns') + await Timer(bit_time_ns, units='ns') async def uart_check_char_recieved(caravelEnv,cpu): From 555488c832f90a54616d659fbe9af484cdf40afe Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 04:11:46 -0700 Subject: [PATCH 11/76] fix timeout values to the passing number of cycles required + 10% --- verilog/dv/cocotb/tests/bitbang/bitbang_tests.py | 6 +++--- verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py | 10 +++++----- verilog/dv/cocotb/tests/cpu/cpu_stress.py | 2 +- .../dv/cocotb/tests/gpio/{gpio_all_o.py => gpio.py} | 4 ++-- .../housekeeping_regs/housekeeping_regs_tests.py | 2 +- verilog/dv/cocotb/tests/irq/IRQ_external.py | 2 +- verilog/dv/cocotb/tests/irq/IRQ_timer.py | 2 +- verilog/dv/cocotb/tests/mem/mem_stress.py | 2 +- verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py | 4 ++-- verilog/dv/cocotb/tests/timer/timer.py | 4 ++-- verilog/dv/cocotb/tests/uart/uart.py | 2 +- verilog/dv/cocotb/tests/uart/uart_rx.c | 5 ----- 12 files changed, 20 insertions(+), 25 deletions(-) rename verilog/dv/cocotb/tests/gpio/{gpio_all_o.py => gpio.py} (95%) diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py index a0232e90..75349be4 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def bitbang_no_cpu_all_o(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000) + caravelEnv = await test_configure(dut,timeout_cycles=10206) cpu = RiskV(dut) cpu.cpu_force_reset() await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) @@ -128,7 +128,7 @@ async def bitbang_no_cpu_all_o(dut): @cocotb.test() @repot_test async def bitbang_no_cpu_all_i(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000) + caravelEnv = await test_configure(dut,timeout_cycles=8005) cpu = RiskV(dut) cpu.cpu_force_reset() await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) @@ -261,7 +261,7 @@ async def io_ports(dut): @cocotb.test() @repot_test async def bitbang_spi(dut): - caravelEnv = await test_configure(dut) + caravelEnv = await test_configure(dut,timeout_cycles=18910) # Apply data 0x1809 (management standard output) to first block of # user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards) cpu = RiskV(dut) diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py index 7260f281..d5a5584d 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def bitbang_cpu_all_o(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=2075459) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -55,7 +55,7 @@ async def bitbang_cpu_all_o(dut): @cocotb.test() @repot_test async def bitbang_cpu_all_10(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=2863378) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -91,7 +91,7 @@ def shift(gpio,shift_type): @cocotb.test() @repot_test async def bitbang_cpu_all_01(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=2863378) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -112,7 +112,7 @@ async def bitbang_cpu_all_01(dut): @cocotb.test() @repot_test async def bitbang_cpu_all_0011(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=5065204) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -173,7 +173,7 @@ def shift_2(gpio,shift_type): @cocotb.test() @repot_test async def bitbang_cpu_all_i(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=1691295) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/cpu/cpu_stress.py b/verilog/dv/cocotb/tests/cpu/cpu_stress.py index b572bb2e..50bb7b42 100644 --- a/verilog/dv/cocotb/tests/cpu/cpu_stress.py +++ b/verilog/dv/cocotb/tests/cpu/cpu_stress.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def cpu_stress(dut): - caravelEnv = await test_configure(dut,timeout_cycles=1492434) + caravelEnv = await test_configure(dut,timeout_cycles=1492541) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_o.py b/verilog/dv/cocotb/tests/gpio/gpio.py similarity index 95% rename from verilog/dv/cocotb/tests/gpio/gpio_all_o.py rename to verilog/dv/cocotb/tests/gpio/gpio.py index 6757cf15..ad0bc24e 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_o.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def gpio_all_o(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=264012) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -55,7 +55,7 @@ async def gpio_all_o(dut): @cocotb.test() @repot_test async def gpio_all_i(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv = await test_configure(dut,timeout_cycles=45464) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py index 6786bb82..be69fee6 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -18,7 +18,7 @@ reg = Regs() @cocotb.test() @repot_test async def hk_regs_wr_wb(dut): - caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY) + caravelEnv = await test_configure(dut,timeout_cycles=237,num_error=INFINITY) cpu = RiskV(dut) cpu.cpu_force_reset() with open('wb_models/housekeepingWB/HK_regs.json') as f: diff --git a/verilog/dv/cocotb/tests/irq/IRQ_external.py b/verilog/dv/cocotb/tests/irq/IRQ_external.py index a1d959a0..91fda43d 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_external.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_external.py @@ -21,7 +21,7 @@ reg = Regs() @cocotb.test() @repot_test async def IRQ_external(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=164360) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/irq/IRQ_timer.py b/verilog/dv/cocotb/tests/irq/IRQ_timer.py index 250f68c8..0f27ce01 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_timer.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_timer.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def IRQ_timer(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=166519) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/mem/mem_stress.py b/verilog/dv/cocotb/tests/mem/mem_stress.py index 70595f20..63d6ad46 100644 --- a/verilog/dv/cocotb/tests/mem/mem_stress.py +++ b/verilog/dv/cocotb/tests/mem/mem_stress.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def mem_stress(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=18164004) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py index 1f67643b..32050500 100644 --- a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def mgmt_gpio_out(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=99562) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -61,7 +61,7 @@ async def mgmt_gpio_out(dut): @cocotb.test() @repot_test async def mgmt_gpio_in(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv = await test_configure(dut,timeout_cycles=326525) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/timer/timer.py b/verilog/dv/cocotb/tests/timer/timer.py index 8a616df9..ee471562 100644 --- a/verilog/dv/cocotb/tests/timer/timer.py +++ b/verilog/dv/cocotb/tests/timer/timer.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def timer0_oneshot(dut): - caravelEnv = await test_configure(dut,timeout_cycles=1000000000) + caravelEnv = await test_configure(dut,timeout_cycles=1114136) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -56,7 +56,7 @@ async def timer0_oneshot(dut): @cocotb.test() @repot_test async def timer0_periodic(dut): - caravelEnv = await test_configure(dut,timeout_cycles=1000000000) + caravelEnv = await test_configure(dut,timeout_cycles=58257) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 7c3324d9..1e86e100 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -18,7 +18,7 @@ reg = Regs() @cocotb.test() @repot_test async def uart_tx(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=18613481) + caravelEnv,clock = await test_configure(dut,timeout_cycles=375862) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/uart/uart_rx.c b/verilog/dv/cocotb/tests/uart/uart_rx.c index 16779691..8a0ec37d 100644 --- a/verilog/dv/cocotb/tests/uart/uart_rx.c +++ b/verilog/dv/cocotb/tests/uart/uart_rx.c @@ -40,11 +40,6 @@ void main(){ reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; - // Set clock to 64 kbaud and enable the UART. It is important to do this - // before applying the configuration, or else the Tx line initializes as - // zero, which indicates the start of a byte to the receiver. - - // Now, apply the configuration reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); From d12fac2ad1f194221f47201d5a69db83f7e24008 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 12:28:52 -0700 Subject: [PATCH 12/76] update run script to delete vcs files before test run --- verilog/dv/cocotb/run.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/run.py b/verilog/dv/cocotb/run.py index 162dbf3d..ac6e28b8 100644 --- a/verilog/dv/cocotb/run.py +++ b/verilog/dv/cocotb/run.py @@ -81,7 +81,7 @@ class RunTest: os.system(f"vcs -cm line -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() - + os.system("rm AN.DB/ cm.log results.xml ucli.key -r") def find(self,name, path): for root, dirs, files in os.walk(path): if name in files: From 53e868abdf210e845766ed0394dfe19eb0442da3 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 12:34:53 -0700 Subject: [PATCH 13/76] add clock to the output od configuration function --- .../dv/cocotb/tests/bitbang/bitbang_tests.py | 123 +----------------- .../cocotb/tests/bitbang/bitbang_tests_cpu.py | 3 +- verilog/dv/cocotb/tests/cpu/cpu_stress.py | 2 +- verilog/dv/cocotb/tests/gpio/gpio.py | 4 +- .../dv/cocotb/tests/hello_world/helloWorld.py | 2 +- .../housekeeping_regs_tests.py | 6 +- verilog/dv/cocotb/tests/irq/IRQ_external.py | 2 +- verilog/dv/cocotb/tests/irq/IRQ_timer.py | 2 +- verilog/dv/cocotb/tests/irq/IRQ_uart.py | 2 +- verilog/dv/cocotb/tests/mem/mem_stress.py | 2 +- .../dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py | 4 +- .../cocotb/tests/temp_partial_test/partial.py | 2 +- verilog/dv/cocotb/tests/timer/timer.py | 4 +- 13 files changed, 21 insertions(+), 137 deletions(-) diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py index 75349be4..3a9b3b13 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def bitbang_no_cpu_all_o(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10206) + caravelEnv,clock = await test_configure(dut,timeout_cycles=10206) cpu = RiskV(dut) cpu.cpu_force_reset() await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) @@ -128,7 +128,7 @@ async def bitbang_no_cpu_all_o(dut): @cocotb.test() @repot_test async def bitbang_no_cpu_all_i(dut): - caravelEnv = await test_configure(dut,timeout_cycles=8005) + caravelEnv,clock = await test_configure(dut,timeout_cycles=8005) cpu = RiskV(dut) cpu.cpu_force_reset() await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) @@ -238,7 +238,7 @@ async def bitbang_no_cpu_all_i(dut): @cocotb.test() @repot_test async def io_ports(dut): - caravelEnv = await test_configure(dut) + caravelEnv,clock = await test_configure(dut) cpu = RiskV(dut) cpu.cpu_force_reset() await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_USER_STD_OUTPUT.value) @@ -256,120 +256,3 @@ async def io_ports(dut): while True: if await cpu.read_address(reg.get_addr('reg_mprj_xfer')) != 1 : break - -"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI.""" -@cocotb.test() -@repot_test -async def bitbang_spi(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18910) - # Apply data 0x1809 (management standard output) to first block of - # user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards) - cpu = RiskV(dut) - cpu.cpu_force_reset() - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_36'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_35'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_34'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_33'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_32'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_31'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_30'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_29'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_28'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_27'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_26'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_25'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_24'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_23'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_22'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_21'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_20'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_19'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_18'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_17'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_16'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_15'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_14'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_13'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_12'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_11'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_10'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_9'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_8'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_7'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_6'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_5'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_4'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_3'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_2'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_1'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) - await cpu.drive_data2address(reg.get_addr('reg_mprj_io_0'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) - - - #Configure all as output except reg_mprj_io_3 - await clear_registers(cpu) - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 18 and 19 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 17 and 20 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 16 and 21 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 15 and 22 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 14 and 23 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 13 and 24 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 12 and 25 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 11 and 26 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 10 and 27 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 9 and 28 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 8 and 29 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 7 and 30 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 6 and 31 - await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 5 and 32 - await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 4 and 33 - await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 3 and 34 - await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 2 and 35 - await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 1 and 36 - await clock_in_end_output_spi(caravelEnv) # 0 and 37 and load - - await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0) - await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) - - i= 0x20 - for j in range(5): - await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),i) - cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} int {caravelEnv.monitor_gpio((37,5)).integer} i = {i}') - if caravelEnv.monitor_gpio((37,5)).integer != i << 27: - cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,5))} instead of {bin(i << 27)}') - # for k in range(250): - await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0) - if caravelEnv.monitor_gpio((37,5)).integer != 0: - cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}') - - i = i >> 1 - i |= 0x20 - await ClockCycles(caravelEnv.clk, 1) - - i= 0x80000000 - for j in range(32): - await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x3f) - await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),i) - if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: - cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)}') - if caravelEnv.monitor_gpio((31,5)).integer != i>>5 : - cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,5))} instead of {i>>5}') - cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} type {int(caravelEnv.monitor_gpio((37,5)))} i = {i}') - await ClockCycles(caravelEnv.clk, 1) - - # await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) - await cpu.drive_data2address(reg.get_addr('reg_mprj_datah'),0x0) - await cpu.drive_data2address(reg.get_addr('reg_mprj_datal'),0x0) - await ClockCycles(caravelEnv.clk, 1) - - if caravelEnv.monitor_gpio((37,5)).integer != 0: - cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') - - i = i >> 1 - i |= 0x80000000 - - - await ClockCycles(caravelEnv.clk, 1000) - - diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py index d5a5584d..241f2e28 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -8,13 +8,14 @@ from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * from caravel import GPIO_MODE +from common import Macros reg = Regs() @cocotb.test() @repot_test async def bitbang_cpu_all_o(dut): - caravelEnv = await test_configure(dut,timeout_cycles=2075459) + caravelEnv,clock = await test_configure(dut,timeout_cycles=2075459) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/cpu/cpu_stress.py b/verilog/dv/cocotb/tests/cpu/cpu_stress.py index 50bb7b42..29a45080 100644 --- a/verilog/dv/cocotb/tests/cpu/cpu_stress.py +++ b/verilog/dv/cocotb/tests/cpu/cpu_stress.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def cpu_stress(dut): - caravelEnv = await test_configure(dut,timeout_cycles=1492541) + caravelEnv,clock = await test_configure(dut,timeout_cycles=1492541) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index ad0bc24e..9ebcd824 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def gpio_all_o(dut): - caravelEnv = await test_configure(dut,timeout_cycles=264012) + caravelEnv,clock = await test_configure(dut,timeout_cycles=264012) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -55,7 +55,7 @@ async def gpio_all_o(dut): @cocotb.test() @repot_test async def gpio_all_i(dut): - caravelEnv = await test_configure(dut,timeout_cycles=45464) + caravelEnv,clock = await test_configure(dut,timeout_cycles=45464) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/hello_world/helloWorld.py b/verilog/dv/cocotb/tests/hello_world/helloWorld.py index 878a127a..f3aefbc3 100644 --- a/verilog/dv/cocotb/tests/hello_world/helloWorld.py +++ b/verilog/dv/cocotb/tests/hello_world/helloWorld.py @@ -5,7 +5,7 @@ from tests.common_functions.test_functions import * @repot_test async def helloWorld(dut): - caravelEnv = await test_configure(dut) + caravelEnv,clock = await test_configure(dut) cocotb.log.info("[Test] Hello world") caravelEnv.print_gpios_ctrl_val() caravelEnv.print_gpios_HW_val() \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py index be69fee6..6d3fc77c 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -18,7 +18,7 @@ reg = Regs() @cocotb.test() @repot_test async def hk_regs_wr_wb(dut): - caravelEnv = await test_configure(dut,timeout_cycles=237,num_error=INFINITY) + caravelEnv,clock = await test_configure(dut,timeout_cycles=237,num_error=INFINITY) cpu = RiskV(dut) cpu.cpu_force_reset() with open('wb_models/housekeepingWB/HK_regs.json') as f: @@ -69,7 +69,7 @@ async def hk_regs_wr_wb(dut): @cocotb.test() @repot_test async def hk_regs_wr_spi(dut): - caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY) + caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY) with open('wb_models/housekeepingWB/HK_regs.json') as f: regs = json.load(f) @@ -116,7 +116,7 @@ async def hk_regs_wr_spi(dut): @cocotb.test() @repot_test async def hk_regs_rst_spi(dut): - caravelEnv = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY) + caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY) with open('wb_models/housekeepingWB/HK_regs.json') as f: regs = json.load(f) diff --git a/verilog/dv/cocotb/tests/irq/IRQ_external.py b/verilog/dv/cocotb/tests/irq/IRQ_external.py index 91fda43d..8db198f9 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_external.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_external.py @@ -21,7 +21,7 @@ reg = Regs() @cocotb.test() @repot_test async def IRQ_external(dut): - caravelEnv = await test_configure(dut,timeout_cycles=164360) + caravelEnv,clock = await test_configure(dut,timeout_cycles=164360) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/irq/IRQ_timer.py b/verilog/dv/cocotb/tests/irq/IRQ_timer.py index 0f27ce01..348b3994 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_timer.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_timer.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def IRQ_timer(dut): - caravelEnv = await test_configure(dut,timeout_cycles=166519) + caravelEnv,clock = await test_configure(dut,timeout_cycles=166519) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/irq/IRQ_uart.py b/verilog/dv/cocotb/tests/irq/IRQ_uart.py index 0917239e..20863626 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_uart.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_uart.py @@ -21,7 +21,7 @@ reg = Regs() @cocotb.test() @repot_test async def IRQ_uart(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18613481) + caravelEnv,clock = await test_configure(dut,timeout_cycles=18613481) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/mem/mem_stress.py b/verilog/dv/cocotb/tests/mem/mem_stress.py index 63d6ad46..a668591c 100644 --- a/verilog/dv/cocotb/tests/mem/mem_stress.py +++ b/verilog/dv/cocotb/tests/mem/mem_stress.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def mem_stress(dut): - caravelEnv = await test_configure(dut,timeout_cycles=18164004) + caravelEnv,clock = await test_configure(dut,timeout_cycles=18164004) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py index 32050500..9f513e67 100644 --- a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def mgmt_gpio_out(dut): - caravelEnv = await test_configure(dut,timeout_cycles=99562) + caravelEnv,clock = await test_configure(dut,timeout_cycles=99562) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -61,7 +61,7 @@ async def mgmt_gpio_out(dut): @cocotb.test() @repot_test async def mgmt_gpio_in(dut): - caravelEnv = await test_configure(dut,timeout_cycles=326525) + caravelEnv,clock = await test_configure(dut,timeout_cycles=326525) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() diff --git a/verilog/dv/cocotb/tests/temp_partial_test/partial.py b/verilog/dv/cocotb/tests/temp_partial_test/partial.py index 422d4aae..bb5a0469 100644 --- a/verilog/dv/cocotb/tests/temp_partial_test/partial.py +++ b/verilog/dv/cocotb/tests/temp_partial_test/partial.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def temp_partial(dut): - caravelEnv = await test_configure(dut,timeout_cycles=70000) + caravelEnv,clock = await test_configure(dut,timeout_cycles=70000) # Apply data 0x1809 (management standard output) to first block of # user 1 and user 2 (GPIO 0 and 37) bits 0, 1, 9, and 12 are "1" (data go in backwards) cpu = RiskV(dut) diff --git a/verilog/dv/cocotb/tests/timer/timer.py b/verilog/dv/cocotb/tests/timer/timer.py index ee471562..75f99981 100644 --- a/verilog/dv/cocotb/tests/timer/timer.py +++ b/verilog/dv/cocotb/tests/timer/timer.py @@ -14,7 +14,7 @@ reg = Regs() @cocotb.test() @repot_test async def timer0_oneshot(dut): - caravelEnv = await test_configure(dut,timeout_cycles=1114136) + caravelEnv,clock = await test_configure(dut,timeout_cycles=1114136) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -56,7 +56,7 @@ async def timer0_oneshot(dut): @cocotb.test() @repot_test async def timer0_periodic(dut): - caravelEnv = await test_configure(dut,timeout_cycles=58257) + caravelEnv,clock = await test_configure(dut,timeout_cycles=58257) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() From 199d5c0f5c4a9e86715bf4848430a91eee7b6ba3 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 12:36:02 -0700 Subject: [PATCH 14/76] fix bug assert csb before reset for the GL sim to work --- verilog/dv/cocotb/caravel.py | 6 ++++-- verilog/dv/cocotb/caravel_tests.py | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py index e1c85149..8c4f36a4 100644 --- a/verilog/dv/cocotb/caravel.py +++ b/verilog/dv/cocotb/caravel.py @@ -51,14 +51,16 @@ class Caravel_env: """start carvel by insert power then reset""" async def start_up(self): await self.power_up() + await self.disable_csb() await self.reset() await self.disable_bins() - await self.disable_csb() common.fill_macros(self.dut.macros) # get macros value async def disable_bins(self): for i in range(38): - common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) + if i == 3: + continue + common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) """setup the vdd and vcc power bins""" async def power_up(self): diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index 2d4cd80d..8579ed11 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -32,7 +32,7 @@ from tests.mem.mem_stress import * from tests.irq.IRQ_external import * from tests.irq.IRQ_timer import * from tests.irq.IRQ_uart import * -from tests.gpio.gpio_all_o import * +from tests.gpio.gpio import * from tests.mgmt_gpio.mgmt_gpio import * from tests.timer.timer import * from tests.uart.uart import * From 1c48f527b8906b18e47a2ef819df020a44047232 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 1 Oct 2022 12:39:54 -0700 Subject: [PATCH 15/76] add bitbang_spi_o tests --- verilog/dv/cocotb/cpu.py | 6 ++ verilog/dv/cocotb/hex_files/bitbang_spi.hex | 78 ++++++++++++++++++- verilog/dv/cocotb/hex_files/uart_rx.hex | 27 ++++--- verilog/dv/cocotb/tests.json | 6 +- verilog/dv/cocotb/tests/bitbang/bitbang_spi.c | 10 --- .../dv/cocotb/tests/bitbang/bitbang_spi_o.c | 78 +++++++++++++++++++ .../cocotb/tests/bitbang/bitbang_tests_cpu.py | 73 ++++++++++++++++- 7 files changed, 247 insertions(+), 31 deletions(-) delete mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_spi.c create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c diff --git a/verilog/dv/cocotb/cpu.py b/verilog/dv/cocotb/cpu.py index a6f45bf7..b9da137b 100644 --- a/verilog/dv/cocotb/cpu.py +++ b/verilog/dv/cocotb/cpu.py @@ -191,6 +191,12 @@ class RiskV: return self.debug_hdl.debug_reg_1.value.integer def read_debug_reg2(self): return self.debug_hdl.debug_reg_2.value.integer + + # writing debug registers using backdoor because in GL cpu can't be disabled for now because of different netlist names + def write_debug_reg1_backdoor(self,data): + self.debug_hdl.debug_reg_1.value = data + def write_debug_reg2_backdoor(self,data): + self.debug_hdl.debug_reg_2.value = data async def force_reset_fun(self): first_time_force = True diff --git a/verilog/dv/cocotb/hex_files/bitbang_spi.hex b/verilog/dv/cocotb/hex_files/bitbang_spi.hex index 100c12da..d9d01260 100755 --- a/verilog/dv/cocotb/hex_files/bitbang_spi.hex +++ b/verilog/dv/cocotb/hex_files/bitbang_spi.hex @@ -12,7 +12,7 @@ 03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 06 46 69 63 0C B5 00 83 26 06 00 23 20 D5 00 13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 @@ -43,5 +43,77 @@ B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE 83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 +13 01 01 FE 23 2E 81 00 13 04 01 02 B7 47 00 F0 +93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 +93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF +23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 0B 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 09 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 08 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 08 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 08 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 08 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 07 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 07 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 07 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 06 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 06 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 06 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 06 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 05 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 05 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 05 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 +93 87 07 04 37 27 00 00 13 07 97 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 97 80 +23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 +37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 +93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 +B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 37 80 +23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 +13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 +37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 10 30 +93 87 87 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 +B7 07 10 30 93 87 C7 FF 03 A7 07 00 93 07 F0 0F +E3 18 F7 FE B7 07 00 26 93 87 C7 00 23 A0 07 00 +B7 07 00 26 93 87 07 01 23 A0 07 00 93 07 00 02 +23 26 F4 FE 23 24 04 FE 6F 00 80 06 B7 07 00 26 +93 87 07 01 03 27 C4 FE 23 A0 E7 00 13 07 50 02 +83 27 84 FE 33 07 F7 40 B7 07 10 30 93 87 C7 FF +23 A0 E7 00 B7 07 00 26 93 87 07 01 23 A0 07 00 +B7 07 10 30 93 87 C7 FF 23 A0 07 00 83 27 C4 FE +93 D7 17 40 23 26 F4 FE 83 27 C4 FE 93 E7 07 02 +23 26 F4 FE 83 27 84 FE 93 87 17 00 23 24 F4 FE +03 27 84 FE 93 07 40 00 E3 DA E7 F8 B7 07 00 80 +23 26 F4 FE 23 24 04 FE 6F 00 80 08 B7 07 00 26 +93 87 07 01 13 07 F0 03 23 A0 E7 00 B7 07 00 26 +93 87 C7 00 03 27 C4 FE 23 A0 E7 00 13 07 00 02 +83 27 84 FE 33 07 F7 40 B7 07 10 30 93 87 C7 FF +23 A0 E7 00 B7 07 00 26 93 87 07 01 23 A0 07 00 +B7 07 00 26 93 87 C7 00 23 A0 07 00 B7 07 10 30 +93 87 C7 FF 23 A0 07 00 83 27 C4 FE 93 D7 17 40 +23 26 F4 FE 03 27 C4 FE B7 07 00 80 B3 67 F7 00 +23 26 F4 FE 83 27 84 FE 93 87 17 00 23 24 F4 FE +03 27 84 FE 93 07 F0 01 E3 DA E7 F6 13 00 00 00 +13 00 00 00 03 24 C1 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/uart_rx.hex b/verilog/dv/cocotb/hex_files/uart_rx.hex index db6552a6..d688718a 100755 --- a/verilog/dv/cocotb/hex_files/uart_rx.hex +++ b/verilog/dv/cocotb/hex_files/uart_rx.hex @@ -12,11 +12,11 @@ 03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 3C 63 0C B5 00 83 26 06 00 23 20 D5 00 +13 06 C6 41 63 0C B5 00 83 26 06 00 23 20 D5 00 13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 28 6F 00 00 00 13 01 01 FF 23 26 81 00 +EF 00 40 2D 6F 00 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 @@ -48,14 +48,19 @@ E3 08 F7 FE B7 67 00 F0 93 87 07 80 03 47 F4 FE 83 27 C4 FE 13 87 17 00 23 26 E4 FE 83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE 83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE +03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FD +23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC 13 00 00 00 EF F0 9F EF 13 07 05 00 93 07 10 00 E3 0A F7 FE B7 67 00 F0 93 87 07 80 83 A7 07 00 -03 27 C4 FE 03 47 07 00 63 9C E7 00 B7 07 10 30 +03 27 C4 FD 03 47 07 00 63 9C E7 00 B7 07 10 30 93 87 87 FF 13 07 B0 01 23 A0 E7 00 6F 00 40 01 B7 07 10 30 93 87 87 FF 13 07 E0 01 23 A0 E7 00 -13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 +B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE +B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE +B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE +B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE +B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE +13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF 23 A0 07 00 @@ -66,12 +71,12 @@ B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00 B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE B7 67 00 F0 13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF 13 07 A0 0A 23 A0 E7 00 B7 07 00 10 -13 85 87 48 EF F0 9F EE B7 07 10 30 93 87 87 FF -13 07 B0 0B 23 A0 E7 00 B7 07 00 10 13 85 C7 48 -EF F0 DF EC B7 07 10 30 93 87 87 FF 13 07 C0 0C -23 A0 E7 00 B7 07 00 10 13 85 07 49 EF F0 1F EB +13 85 87 4D EF F0 9F E9 B7 07 10 30 93 87 87 FF +13 07 B0 0B 23 A0 E7 00 B7 07 00 10 13 85 C7 4D +EF F0 DF E7 B7 07 10 30 93 87 87 FF 13 07 C0 0C +23 A0 E7 00 B7 07 00 10 13 85 07 4E EF F0 1F E6 13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01 67 80 00 00 -@00000484 +@000004D4 00 00 00 00 42 00 00 00 4D 00 00 00 41 00 00 00 00 00 00 00 diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 5d04ea74..f2cd2ee0 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -64,12 +64,12 @@ "GL_SDF":["weekly","tape_out"], "description":" configure gpio[0:37] as mgmt input using bitbang and check them"} - ,"bitbang_spi" :{"level":0, + ,"bitbang_spi_o" :{"level":0, "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], "GL":["push_gl","nightly","weekly","tape_out"], "GL_SDF":["weekly","tape_out"], - "SW":false, - "description":"Same as bitbang_no_cpu_all but configure the gpio using the SPI not the firmware"} + "SW":true, + "description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"} ,"hk_regs_wr_wb" :{"level":0, "SW":false, diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_spi.c b/verilog/dv/cocotb/tests/bitbang/bitbang_spi.c deleted file mode 100644 index 1aa21f5b..00000000 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_spi.c +++ /dev/null @@ -1,10 +0,0 @@ -#include -#include - -// Empty C code - -void main() -{ - return; -} - diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c new file mode 100644 index 00000000..1957f212 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_o.c @@ -0,0 +1,78 @@ +#include +#include + +// Empty C code + +void main() +{ + int i,j; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_4 = 0x1803; + reg_mprj_io_3 = 0x1803; + reg_mprj_io_2 = 0x1803; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + + reg_debug_1 = 0xFF; // finish configuration + while (reg_debug_2 != 0xFF); // finish bit bang + reg_mprj_datal = 0x0; + reg_mprj_datah = 0x0; + i = 0x20; + for (j = 0; j < 5; j++) { + reg_mprj_datah = i; + reg_debug_2 = 37-j; + reg_mprj_datah = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x20; + } + i = 0x80000000; + for (j = 0; j < 32; j++) { + reg_mprj_datah = 0x3f; + reg_mprj_datal = i; + reg_debug_2 = 32-j; + reg_mprj_datah = 0x00; + reg_mprj_datal = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x80000000; + } + +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py index 241f2e28..4c910271 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -92,7 +92,7 @@ def shift(gpio,shift_type): @cocotb.test() @repot_test async def bitbang_cpu_all_01(dut): - caravelEnv = await test_configure(dut,timeout_cycles=2863378) + caravelEnv,clock = await test_configure(dut,timeout_cycles=2863378) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -113,7 +113,7 @@ async def bitbang_cpu_all_01(dut): @cocotb.test() @repot_test async def bitbang_cpu_all_0011(dut): - caravelEnv = await test_configure(dut,timeout_cycles=5065204) + caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -134,7 +134,7 @@ async def bitbang_cpu_all_0011(dut): @cocotb.test() @repot_test async def bitbang_cpu_all_1100(dut): - caravelEnv = await test_configure(dut,timeout_cycles=10000000000) + caravelEnv,clock = await test_configure(dut,timeout_cycles=10000000000) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -174,7 +174,7 @@ def shift_2(gpio,shift_type): @cocotb.test() @repot_test async def bitbang_cpu_all_i(dut): - caravelEnv = await test_configure(dut,timeout_cycles=1691295) + caravelEnv,clock = await test_configure(dut,timeout_cycles=1691295) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -198,3 +198,68 @@ async def bitbang_cpu_all_i(dut): await wait_reg2(cpu,caravelEnv,0xFF) cocotb.log.info(f"[TEST] finish") + + +"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI.""" +@cocotb.test() +@repot_test +async def bitbang_spi_o(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=639757) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured + #Configure all as output except reg_mprj_io_3 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 18 and 19 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 17 and 20 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 16 and 21 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 15 and 22 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 14 and 23 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 13 and 24 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 12 and 25 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 11 and 26 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 10 and 27 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 9 and 28 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 8 and 29 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 7 and 30 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 6 and 31 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 5 and 32 + await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 4 and 33 + await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 3 and 34 + await clock_in_right_o_left_i_standard_spi(caravelEnv,0) # 2 and 35 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 1 and 36 + await clock_in_right_o_left_o_standard_spi(caravelEnv,0) # 0 and 37 + await load_spi(caravelEnv) # load + + cpu.write_debug_reg2_backdoor(0xFF) + cocotb.log.info("[TEST] finish configuring using bitbang") + i= 0x20 + for j in range(5): + await wait_reg2(cpu,caravelEnv,37-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}') + if caravelEnv.monitor_gpio((37,5)).integer != i << 27: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,5))} instead of {bin(i << 28)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,5)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}') + i = i >> 1 + i |= 0x20 + + i= 0x80000000 + for j in range(32): + await wait_reg2(cpu,caravelEnv,32-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,5))} j = {j}') + if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ') + if caravelEnv.monitor_gpio((31,5)).integer != i>>5 : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,5)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,5))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x80000000 + + + await ClockCycles(caravelEnv.clk, 10) \ No newline at end of file From 9e0be5473d8595d0f064eb489f8c246b9ffa5d58 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 04:20:32 -0700 Subject: [PATCH 16/76] remove hex files from directory --- verilog/dv/cocotb/.gitignore | 2 +- verilog/dv/cocotb/hex_files/IRQ_external.hex | 70 ------ verilog/dv/cocotb/hex_files/IRQ_timer.hex | 71 ------ verilog/dv/cocotb/hex_files/IRQ_uart.hex | 87 ------- .../dv/cocotb/hex_files/bitbang_cpu_all.hex | 238 ------------------ .../cocotb/hex_files/bitbang_cpu_all_0011.hex | 212 ---------------- .../cocotb/hex_files/bitbang_cpu_all_01.hex | 211 ---------------- .../cocotb/hex_files/bitbang_cpu_all_10.hex | 211 ---------------- .../cocotb/hex_files/bitbang_cpu_all_1100.hex | 212 ---------------- .../dv/cocotb/hex_files/bitbang_cpu_all_i.hex | 227 ----------------- .../dv/cocotb/hex_files/bitbang_cpu_all_o.hex | 238 ------------------ .../dv/cocotb/hex_files/bitbang_no_cpu.hex | 47 ---- .../cocotb/hex_files/bitbang_no_cpu_all.hex | 47 ---- .../cocotb/hex_files/bitbang_no_cpu_all_i.hex | 47 ---- .../cocotb/hex_files/bitbang_no_cpu_all_o.hex | 47 ---- .../dv/cocotb/hex_files/bitbang_no_cpu_i.hex | 47 ---- verilog/dv/cocotb/hex_files/bitbang_spi.hex | 47 ---- verilog/dv/cocotb/hex_files/cpu_drive.hex | 54 ---- verilog/dv/cocotb/hex_files/cpu_stress.hex | 168 ------------- verilog/dv/cocotb/hex_files/gpio_all_i.hex | 218 ---------------- verilog/dv/cocotb/hex_files/gpio_all_o.hex | 230 ----------------- verilog/dv/cocotb/hex_files/helloWorld.hex | 32 --- .../dv/cocotb/hex_files/hk_regs_rst_spi.hex | 47 ---- .../dv/cocotb/hex_files/hk_regs_wr_spi.hex | 47 ---- verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex | 47 ---- verilog/dv/cocotb/hex_files/mem_stress.hex | 102 -------- verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex | 66 ----- verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex | 54 ---- .../dv/cocotb/hex_files/timer0_oneshot.hex | 58 ----- .../dv/cocotb/hex_files/timer0_periodic.hex | 60 ----- verilog/dv/cocotb/hex_files/uart_tx.hex | 62 ----- 31 files changed, 1 insertion(+), 3305 deletions(-) delete mode 100755 verilog/dv/cocotb/hex_files/IRQ_external.hex delete mode 100755 verilog/dv/cocotb/hex_files/IRQ_timer.hex delete mode 100755 verilog/dv/cocotb/hex_files/IRQ_uart.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_0011.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_01.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_10.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_1100.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_i.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_cpu_all_o.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu_all.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_i.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_o.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_no_cpu_i.hex delete mode 100755 verilog/dv/cocotb/hex_files/bitbang_spi.hex delete mode 100755 verilog/dv/cocotb/hex_files/cpu_drive.hex delete mode 100755 verilog/dv/cocotb/hex_files/cpu_stress.hex delete mode 100755 verilog/dv/cocotb/hex_files/gpio_all_i.hex delete mode 100755 verilog/dv/cocotb/hex_files/gpio_all_o.hex delete mode 100755 verilog/dv/cocotb/hex_files/helloWorld.hex delete mode 100755 verilog/dv/cocotb/hex_files/hk_regs_rst_spi.hex delete mode 100755 verilog/dv/cocotb/hex_files/hk_regs_wr_spi.hex delete mode 100755 verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex delete mode 100755 verilog/dv/cocotb/hex_files/mem_stress.hex delete mode 100755 verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex delete mode 100755 verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex delete mode 100755 verilog/dv/cocotb/hex_files/timer0_oneshot.hex delete mode 100755 verilog/dv/cocotb/hex_files/timer0_periodic.hex delete mode 100755 verilog/dv/cocotb/hex_files/uart_tx.hex diff --git a/verilog/dv/cocotb/.gitignore b/verilog/dv/cocotb/.gitignore index 907c648c..4fdecb74 100644 --- a/verilog/dv/cocotb/.gitignore +++ b/verilog/dv/cocotb/.gitignore @@ -6,6 +6,6 @@ __pycache__ ./wb_models/housekeepingWB/__pycache__ *.xml *.yml -*.hexe +*.hex* *.elf AN.DB \ No newline at end of file diff --git a/verilog/dv/cocotb/hex_files/IRQ_external.hex b/verilog/dv/cocotb/hex_files/IRQ_external.hex deleted file mode 100755 index b183a3ce..00000000 --- a/verilog/dv/cocotb/hex_files/IRQ_external.hex +++ /dev/null @@ -1,70 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 38 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 80 17 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 -23 26 A4 FE 83 27 C4 FE 63 86 07 00 73 60 04 30 -6F 00 80 00 73 70 04 30 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 81 00 -13 04 01 02 F3 27 00 BC 23 26 F4 FE 83 27 C4 FE -13 85 07 00 03 24 C1 01 13 01 01 02 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00 -23 2C 81 00 13 04 01 02 B7 47 00 F0 93 87 07 80 -13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF -23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 -B7 07 00 26 93 87 07 04 13 07 30 40 23 A0 E7 00 -B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00 -B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE -13 05 00 00 EF F0 DF F6 13 05 10 00 EF F0 9F F0 -EF F0 9F F3 93 07 05 00 93 E7 07 04 13 85 07 00 -EF F0 1F F5 B7 97 00 F0 93 87 47 81 13 07 10 00 -23 A0 E7 00 B7 07 10 30 93 87 C7 FF 13 07 A0 0A -23 A0 E7 00 23 10 00 00 A3 07 04 FE 93 07 80 02 -23 20 F4 FE 23 24 04 FE 6F 00 80 03 03 57 00 00 -93 07 10 00 63 10 F7 02 B7 07 10 30 93 87 87 FF -13 07 B0 01 23 A0 E7 00 93 07 10 00 A3 07 F4 FE -6F 00 C0 01 83 27 84 FE 93 87 17 00 23 24 F4 FE -03 27 84 FE 83 27 04 FE E3 42 F7 FC 83 47 F4 FE -93 C7 17 00 93 F7 F7 0F 63 8A 07 00 B7 07 10 30 -93 87 87 FF 13 07 E0 01 23 A0 E7 00 B7 07 10 30 -93 87 C7 FF 13 07 B0 0B 23 A0 E7 00 23 10 00 00 -A3 07 04 FE 23 22 04 FE 6F 00 80 03 03 57 00 00 -93 07 10 00 63 10 F7 02 B7 07 10 30 93 87 87 FF -13 07 E0 02 23 A0 E7 00 93 07 10 00 A3 07 F4 FE -6F 00 C0 01 83 27 44 FE 93 87 17 00 23 22 F4 FE -03 27 44 FE 83 27 04 FE E3 42 F7 FC 83 47 F4 FE -93 C7 17 00 93 F7 F7 0F 63 8A 07 00 B7 07 10 30 -93 87 87 FF 13 07 B0 02 23 A0 E7 00 B7 07 10 30 -93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/IRQ_timer.hex b/verilog/dv/cocotb/hex_files/IRQ_timer.hex deleted file mode 100755 index 52f883e1..00000000 --- a/verilog/dv/cocotb/hex_files/IRQ_timer.hex +++ /dev/null @@ -1,71 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 38 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 80 17 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 -23 26 A4 FE 83 27 C4 FE 63 86 07 00 73 60 04 30 -6F 00 80 00 73 70 04 30 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 81 00 -13 04 01 02 F3 27 00 BC 23 26 F4 FE 83 27 C4 FE -13 85 07 00 03 24 C1 01 13 01 01 02 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00 -23 2C 81 00 13 04 01 02 B7 47 00 F0 93 87 07 80 -13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF -23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 -13 05 00 00 EF F0 DF F9 13 05 10 00 EF F0 9F F3 -EF F0 9F F6 93 07 05 00 93 E7 17 00 13 85 07 00 -EF F0 1F F8 B7 07 10 30 93 87 C7 FF 13 07 A0 0A -23 A0 E7 00 23 10 00 00 B7 57 00 F0 93 87 87 00 -23 A0 07 00 B7 57 00 F0 13 07 E0 01 23 A0 E7 00 -B7 57 00 F0 93 87 C7 01 13 07 10 00 23 A0 E7 00 -B7 57 00 F0 93 87 87 00 13 07 10 00 23 A0 E7 00 -A3 07 04 FE 93 07 80 02 23 20 F4 FE 23 24 04 FE -6F 00 80 03 03 57 00 00 93 07 10 00 63 10 F7 02 -B7 07 10 30 93 87 87 FF 13 07 B0 01 23 A0 E7 00 -93 07 10 00 A3 07 F4 FE 6F 00 C0 01 83 27 84 FE -93 87 17 00 23 24 F4 FE 03 27 84 FE 83 27 04 FE -E3 42 F7 FC 83 47 F4 FE 93 C7 17 00 93 F7 F7 0F -63 8A 07 00 B7 07 10 30 93 87 87 FF 13 07 E0 01 -23 A0 E7 00 23 10 00 00 B7 07 10 30 93 87 C7 FF -13 07 B0 0B 23 A0 E7 00 B7 57 00 F0 93 87 87 00 -23 A0 07 00 23 10 00 00 A3 07 04 FE 23 22 04 FE -6F 00 80 03 03 57 00 00 93 07 10 00 63 10 F7 02 -B7 07 10 30 93 87 87 FF 13 07 E0 02 23 A0 E7 00 -93 07 10 00 A3 07 F4 FE 6F 00 C0 01 83 27 44 FE -93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE -E3 42 F7 FC 83 47 F4 FE 93 C7 17 00 93 F7 F7 0F -63 8A 07 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 -23 A0 E7 00 B7 07 10 30 93 87 C7 FF 13 07 F0 0F -23 A0 E7 00 13 00 00 00 83 20 C1 01 03 24 81 01 -13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/IRQ_uart.hex b/verilog/dv/cocotb/hex_files/IRQ_uart.hex deleted file mode 100755 index 9792671f..00000000 --- a/verilog/dv/cocotb/hex_files/IRQ_uart.hex +++ /dev/null @@ -1,87 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 47 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 23 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 -23 26 A4 FE 83 27 C4 FE 63 86 07 00 73 60 04 30 -6F 00 80 00 73 70 04 30 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 81 00 -13 04 01 02 F3 27 00 BC 23 26 F4 FE 83 27 C4 FE -13 85 07 00 03 24 C1 01 13 01 01 02 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00 -23 2C 81 00 13 04 01 02 93 07 05 00 A3 07 F4 FE -03 47 F4 FE 93 07 A0 00 63 16 F7 00 13 05 D0 00 -EF F0 9F FD 13 00 00 00 B7 67 00 F0 93 87 47 80 -03 A7 07 00 93 07 10 00 E3 08 F7 FE B7 67 00 F0 -93 87 07 80 03 47 F4 FE 23 A0 E7 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 -23 26 A4 FE 6F 00 C0 01 83 27 C4 FE 13 87 17 00 -23 26 E4 FE 83 C7 07 00 13 85 07 00 EF F0 DF F6 -83 27 C4 FE 83 C7 07 00 E3 90 07 FE 13 00 00 00 -13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 B7 47 00 F0 93 87 07 80 13 07 10 00 -23 A0 E7 00 B7 07 10 30 93 87 87 FF 23 A0 07 00 -B7 07 10 30 93 87 C7 FF 23 A0 07 00 B7 07 00 26 -93 87 C7 03 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 03 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 13 07 10 00 23 A0 E7 00 -13 00 00 00 B7 07 00 26 03 A7 07 00 93 07 10 00 -E3 0A F7 FE B7 67 00 F0 13 07 10 00 23 A0 E7 00 -B7 67 00 F0 93 87 47 81 13 07 10 00 23 A0 E7 00 -13 05 00 00 EF F0 DF E7 13 05 10 00 EF F0 9F E1 -EF F0 9F E4 93 07 05 00 93 E7 27 00 13 85 07 00 -EF F0 1F E6 23 10 00 00 B7 07 10 30 93 87 C7 FF -13 07 A0 0A 23 A0 E7 00 B7 07 00 10 13 85 07 54 -EF F0 1F ED A3 07 04 FE 93 07 40 06 23 20 F4 FE -23 24 04 FE 6F 00 80 03 03 57 00 00 93 07 10 00 -63 10 F7 02 B7 07 10 30 93 87 87 FF 13 07 B0 01 -23 A0 E7 00 93 07 10 00 A3 07 F4 FE 6F 00 C0 01 -83 27 84 FE 93 87 17 00 23 24 F4 FE 03 27 84 FE -83 27 04 FE E3 42 F7 FC 83 47 F4 FE 93 C7 17 00 -93 F7 F7 0F 63 8A 07 00 B7 07 10 30 93 87 87 FF -13 07 E0 01 23 A0 E7 00 B7 07 10 30 93 87 C7 FF -13 07 B0 0B 23 A0 E7 00 23 10 00 00 A3 07 04 FE -23 22 04 FE 6F 00 80 03 03 57 00 00 93 07 10 00 -63 10 F7 02 B7 07 10 30 93 87 87 FF 13 07 E0 02 -23 A0 E7 00 93 07 10 00 A3 07 F4 FE 6F 00 C0 01 -83 27 44 FE 93 87 17 00 23 22 F4 FE 03 27 44 FE -83 27 04 FE E3 42 F7 FC 83 47 F4 FE 93 C7 17 00 -93 F7 F7 0F 63 8A 07 00 B7 07 10 30 93 87 87 FF -13 07 B0 02 23 A0 E7 00 B7 07 10 30 93 87 C7 FF -13 07 F0 0F 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 -@0000053C -00 00 00 00 4D 00 00 00 00 00 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all.hex deleted file mode 100755 index ab7f2105..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_cpu_all.hex +++ /dev/null @@ -1,238 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 -13 06 C6 DF 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 90 07 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 06 -23 A0 E7 00 B7 07 00 26 13 07 60 07 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 60 01 -23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -B7 07 00 26 13 07 60 04 23 A0 E7 00 B7 07 00 26 -13 07 60 05 23 A0 E7 00 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 B7 07 00 26 13 07 60 02 23 A0 E7 00 -B7 07 00 26 13 07 60 03 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 00 -23 A0 E7 00 B7 07 00 26 13 07 E0 00 23 A0 E7 00 -B7 07 00 26 13 07 60 00 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 00 -23 A0 E7 00 B7 07 00 26 13 07 40 00 23 A0 E7 00 -B7 07 00 26 13 07 60 00 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 DF EF EF F0 9F EF -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 5F EE 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 DF E9 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC -EF F0 1F E8 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 5F EB EF F0 1F EB 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF E9 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 1F E2 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 80 00 E3 F6 E7 FC EF F0 5F E0 -13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03 -67 80 00 00 13 01 01 FD 23 26 11 02 23 24 81 02 -13 04 01 03 23 2E A4 FC 83 27 C4 FD 23 24 F4 FE -EF F0 5F E0 EF F0 1F E0 23 26 04 FE 6F 00 00 03 -83 27 84 FE 63 8C 07 00 EF F0 DF DE 83 27 84 FE -93 87 F7 FF 23 24 F4 FE 6F 00 80 00 EF F0 5F DA -83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE -93 07 60 00 E3 F6 E7 FC EF F0 DF DB EF F0 5F D8 -EF F0 1F D8 EF F0 1F DB 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F D1 EF F0 1F D1 -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF CF 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 DF D1 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 60 00 E3 F6 E7 FC -EF F0 DF CC EF F0 DF CF EF F0 9F CF EF F0 1F CC -13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03 -67 80 00 00 13 01 01 FD 23 26 11 02 23 24 81 02 -13 04 01 03 23 2E A4 FC 83 27 C4 FD 23 24 F4 FE -EF F0 DF C8 EF F0 9F C8 23 26 04 FE 6F 00 00 03 -83 27 84 FE 63 8C 07 00 EF F0 5F C7 83 27 84 FE -93 87 F7 FF 23 24 F4 FE 6F 00 80 00 EF F0 5F C9 -83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE -93 07 60 00 E3 F6 E7 FC EF F0 DF CA EF F0 5F C7 -EF F0 9F CD EF F0 9F C3 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F C0 EF F0 1F C0 -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF BE 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 DF C0 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 60 00 E3 F6 E7 FC -EF F0 9F C5 EF F0 DF BE EF F0 DF C1 EF F0 1F BB -13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03 -67 80 00 00 13 01 01 FD 23 26 11 02 23 24 81 02 -13 04 01 03 23 2E A4 FC 83 27 C4 FD 23 24 F4 FE -EF F0 DF B7 EF F0 9F B7 23 26 04 FE 6F 00 00 03 -83 27 84 FE 63 8C 07 00 EF F0 5F B6 83 27 84 FE -93 87 F7 FF 23 24 F4 FE 6F 00 80 00 EF F0 5F B8 -83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE -93 07 60 00 E3 F6 E7 FC EF F0 9F B6 EF F0 5F B6 -EF F0 DF B2 EF F0 9F B2 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F AF EF F0 1F AF -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 9F B7 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 DF AF 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 60 00 E3 F6 E7 FC -EF F0 5F B1 EF F0 DF AD EF F0 1F B4 EF F0 1F AA -13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03 -67 80 00 00 13 01 01 FD 23 26 11 02 23 24 81 02 -13 04 01 03 23 2E A4 FC 83 27 C4 FD 23 24 F4 FE -EF F0 DF A6 EF F0 9F A6 23 26 04 FE 6F 00 00 03 -83 27 84 FE 63 8C 07 00 EF F0 5F A5 83 27 84 FE -93 87 F7 FF 23 24 F4 FE 6F 00 80 00 EF F0 5F A7 -83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE -93 07 60 00 E3 F6 E7 FC EF F0 1F AC EF F0 5F A5 -EF F0 DF A1 EF F0 9F A1 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 EF F0 1F 9F -EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 EF F0 5F A1 -EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 EF F0 5F A0 -EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C EF F0 1F 9C -EF F0 DF A8 13 00 00 00 83 20 C1 00 03 24 81 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 EF F0 5F 99 EF F0 9F 9F -EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B EF F0 5F 9B -EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A EF F0 DF A0 -EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 EF F0 1F A3 -B7 07 00 26 93 87 87 0B 37 27 00 00 13 07 97 80 -23 A0 E7 00 13 00 00 00 83 20 C1 00 03 24 81 00 -13 01 01 01 67 80 00 00 13 01 01 FE 23 2E 11 00 -23 2C 81 00 13 04 01 02 B7 47 00 F0 93 87 07 80 -13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF -23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 -B7 07 00 26 93 87 87 0B 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 0B -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 0A 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 0A 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 0A -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 09 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 09 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 09 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 09 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 08 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 08 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 08 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 08 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 07 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 07 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 07 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 07 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 06 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 06 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 06 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 06 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 05 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 05 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 05 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 05 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 04 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 04 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 04 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 04 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 03 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 03 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 03 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 03 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 02 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 02 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 02 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 -37 27 00 00 13 07 97 80 23 A0 E7 00 13 05 00 00 -EF F0 DF 8B 13 05 00 00 EF F0 5F 8B 13 05 00 00 -EF F0 DF 8A 13 05 00 00 EF F0 5F 8A 13 05 00 00 -EF F0 DF 89 13 05 00 00 EF F0 5F 89 13 05 00 00 -EF F0 DF 88 13 05 00 00 EF F0 5F 88 13 05 00 00 -EF F0 DF 87 13 05 00 00 EF F0 5F 87 13 05 00 00 -EF F0 DF 86 13 05 00 00 EF F0 5F 86 13 05 00 00 -EF F0 DF 85 13 05 00 00 EF F0 5F 85 13 05 00 00 -EF F0 DF 84 13 05 00 00 EF F0 DF 8C 13 05 00 00 -EF F0 DF 83 13 05 00 00 EF F0 5F 83 13 05 00 00 -EF F0 DF 82 EF F0 8F E2 B7 07 10 30 93 87 87 FF -13 07 F0 0F 23 A0 E7 00 B7 07 00 26 93 87 C7 00 -23 A0 07 00 B7 07 00 26 93 87 07 01 23 A0 07 00 -93 07 00 02 23 26 F4 FE 23 24 04 FE 6F 00 80 06 -B7 07 00 26 93 87 07 01 03 27 C4 FE 23 A0 E7 00 -B7 07 10 30 93 87 C7 FF 93 06 50 02 03 27 84 FE -33 87 E6 40 23 A0 E7 00 B7 07 00 26 93 87 07 01 -23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 -83 27 C4 FE 93 D7 17 00 23 26 F4 FE 83 27 C4 FE -93 E7 07 02 23 26 F4 FE 83 27 84 FE 93 87 17 00 -23 24 F4 FE 03 27 84 FE 93 07 40 00 E3 FA E7 F8 -B7 07 00 80 23 26 F4 FE 23 24 04 FE 6F 00 80 08 -B7 07 00 26 93 87 07 01 13 07 F0 03 23 A0 E7 00 -B7 07 00 26 93 87 C7 00 03 27 C4 FE 23 A0 E7 00 -B7 07 10 30 93 87 C7 FF 93 06 00 02 03 27 84 FE -33 87 E6 40 23 A0 E7 00 B7 07 00 26 93 87 07 01 -23 A0 07 00 B7 07 00 26 93 87 C7 00 23 A0 07 00 -B7 07 10 30 93 87 C7 FF 23 A0 07 00 83 27 C4 FE -93 D7 17 00 23 26 F4 FE 03 27 C4 FE B7 07 00 80 -B3 67 F7 00 23 26 F4 FE 83 27 84 FE 93 87 17 00 -23 24 F4 FE 03 27 84 FE 93 07 F0 01 E3 FA E7 F6 -13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 -67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_0011.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_0011.hex deleted file mode 100755 index 6968b98d..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_0011.hex +++ /dev/null @@ -1,212 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 -13 06 C6 C5 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 -23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 -13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 -B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 -23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF -EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 -E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC -EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB -EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 -EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF -EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA -EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 -EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 -EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 -EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF -EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 -EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC -EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 -EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 -EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 -EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C -EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 -EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B -EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A -EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 -EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 B7 47 00 F0 -93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 -93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF -23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0B 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 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00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 04 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 47 02 37 27 00 00 13 07 97 80 23 A0 E7 00 -23 26 04 FE 6F 00 00 02 EF F0 CF E1 EF F0 8F E1 -EF F0 0F DE EF F0 CF DD 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 60 0F E3 DE E7 FC -B7 07 10 30 93 87 87 FF 13 07 F0 0F 23 A0 E7 00 -13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 -67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_01.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_01.hex deleted file mode 100755 index 39ae0dc8..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_01.hex +++ /dev/null @@ -1,211 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 -13 06 46 C5 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 -23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 -13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 -B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 -23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF -EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 -E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC -EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB -EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 -EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF -EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA -EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 -EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 -EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 -EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF -EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 -EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC -EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 -EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 -EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 -EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C -EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 -EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B -EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A -EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 -EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 B7 47 00 F0 -93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 -93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF -23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0B 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 09 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 08 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 08 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 08 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 08 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 07 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 07 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 07 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 06 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 06 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 06 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 06 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 05 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 05 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 05 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 04 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 47 02 37 27 00 00 13 07 97 80 23 A0 E7 00 -23 26 04 FE 6F 00 80 01 EF F0 CF E1 EF F0 4F DE -83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE -93 07 60 0F E3 D2 E7 FE B7 07 10 30 93 87 87 FF -13 07 F0 0F 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_10.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_10.hex deleted file mode 100755 index 8b665aff..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_10.hex +++ /dev/null @@ -1,211 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 -13 06 46 C5 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 -23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 -13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 -B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 -23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF -EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 -E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC -EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB -EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 -EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF -EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA -EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 -EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 -EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 -EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF -EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 -EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC -EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 -EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 -EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 -EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C -EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 -EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B -EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A -EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 -EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 B7 47 00 F0 -93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 -93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF -23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0B 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 09 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 08 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 08 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 08 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 08 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 07 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 07 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 07 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 06 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 06 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 06 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 06 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 05 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 05 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 05 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 04 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 47 02 37 27 00 00 13 07 97 80 23 A0 E7 00 -23 26 04 FE 6F 00 80 01 EF F0 8F DE EF F0 8F E1 -83 27 C4 FE 93 87 17 00 23 26 F4 FE 03 27 C4 FE -93 07 60 0F E3 D2 E7 FE B7 07 10 30 93 87 87 FF -13 07 F0 0F 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_1100.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_1100.hex deleted file mode 100755 index 17ee504b..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_1100.hex +++ /dev/null @@ -1,212 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 -13 06 C6 C5 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 -23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 -13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 -B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 -23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF -EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 -E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC -EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB -EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 -EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF -EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA -EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 -EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 -EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 -EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF -EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 -EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC -EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 -EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 -EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 -EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C -EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 -EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B -EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A -EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 -EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 B7 47 00 F0 -93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 -93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF -23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0B 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 09 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 08 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 08 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 08 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 08 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 07 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 07 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 07 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 06 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 06 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 06 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 06 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 05 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 05 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 05 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 04 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 47 02 37 27 00 00 13 07 97 80 23 A0 E7 00 -23 26 04 FE 6F 00 00 02 EF F0 8F DE EF F0 4F DE -EF F0 4F E1 EF F0 0F E1 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 60 0F E3 DE E7 FC -B7 07 10 30 93 87 87 FF 13 07 F0 0F 23 A0 E7 00 -13 00 00 00 83 20 C1 01 03 24 81 01 13 01 01 02 -67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_i.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_i.hex deleted file mode 100755 index 82d4bc13..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_i.hex +++ /dev/null @@ -1,227 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 -13 06 C6 D4 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 -23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 -13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 -B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 -23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF -EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 -E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC -EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB -EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 -EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF -EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA -EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 -EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 -EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 -EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF -EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 -EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC -EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 -EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 -EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 -EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C -EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 -EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B -EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A -EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 -EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 B7 47 00 F0 -93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 -93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF -23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0B 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0A 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 07 09 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 08 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 87 08 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 08 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 07 08 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 07 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 07 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 07 07 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 06 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 87 06 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 06 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 07 06 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 87 05 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 05 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 07 05 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 07 04 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 47 02 37 27 00 00 13 07 37 80 23 A0 E7 00 -13 05 00 00 EF F0 5F A5 13 05 00 00 EF F0 DF A4 -13 05 00 00 EF F0 5F A4 13 05 00 00 EF F0 DF A3 -13 05 00 00 EF F0 5F A3 13 05 00 00 EF F0 DF A2 -13 05 00 00 EF F0 5F A2 13 05 00 00 EF F0 DF A1 -13 05 00 00 EF F0 5F A1 13 05 00 00 EF F0 DF A0 -13 05 00 00 EF F0 5F A0 13 05 00 00 EF F0 DF 9F -13 05 00 00 EF F0 5F 9F 13 05 00 00 EF F0 DF 9E -13 05 00 00 EF F0 5F 9E 13 05 00 00 EF F0 DF 9D -13 05 00 00 EF F0 5F 9D 13 05 00 00 EF F0 DF 9C -13 05 00 00 EF F0 5F 9C EF F0 8F E2 B7 07 10 30 -93 87 87 FF 13 07 A0 0A 23 A0 E7 00 13 00 00 00 -B7 07 00 26 93 87 C7 00 03 A7 07 00 B7 07 67 8F -93 87 B7 D7 E3 16 F7 FE B7 07 10 30 93 87 87 FF -13 07 B0 0B 23 A0 E7 00 13 00 00 00 B7 07 00 26 -93 87 C7 00 03 A7 07 00 B7 97 A8 FF 93 87 A7 C5 -E3 16 F7 FE B7 07 10 30 93 87 87 FF 13 07 C0 0C -23 A0 E7 00 13 00 00 00 B7 07 00 26 93 87 C7 00 -03 A7 07 00 B7 67 53 C9 93 87 67 34 E3 16 F7 FE -B7 07 10 30 93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 -13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01 -67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_o.hex b/verilog/dv/cocotb/hex_files/bitbang_cpu_all_o.hex deleted file mode 100755 index 317c41ff..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_cpu_all_o.hex +++ /dev/null @@ -1,238 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 -13 06 46 E0 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 -23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 -13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 -B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 -23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF -EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 -E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC -EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB -EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 -EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF -EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA -EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 -EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 -EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 -EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF -EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 -EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC -EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 -EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 -EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 -EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C -EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 -EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B -EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A -EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 -EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 B7 47 00 F0 -93 87 07 80 13 07 10 00 23 A0 E7 00 B7 07 10 30 -93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 C7 FF -23 A0 07 00 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0B -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0B 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 0A 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 0A 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 0A -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 09 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 09 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 09 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 09 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 08 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 08 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 08 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 08 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 07 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 07 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 07 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 07 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 06 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 06 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 06 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 06 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 05 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 05 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 05 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 05 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 04 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 04 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 04 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 04 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 03 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 03 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 03 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 07 03 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 C7 02 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 87 02 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 47 02 37 27 00 00 13 07 97 80 23 A0 E7 00 -13 05 00 00 EF F0 DF 8B 13 05 00 00 EF F0 5F 8B -13 05 00 00 EF F0 DF 8A 13 05 00 00 EF F0 5F 8A -13 05 00 00 EF F0 DF 89 13 05 00 00 EF F0 5F 89 -13 05 00 00 EF F0 DF 88 13 05 00 00 EF F0 5F 88 -13 05 00 00 EF F0 DF 87 13 05 00 00 EF F0 5F 87 -13 05 00 00 EF F0 DF 86 13 05 00 00 EF F0 5F 86 -13 05 00 00 EF F0 DF 85 13 05 00 00 EF F0 5F 85 -13 05 00 00 EF F0 DF 84 13 05 00 00 EF F0 DF 8C -13 05 00 00 EF F0 DF 83 13 05 00 00 EF F0 5F 83 -13 05 00 00 EF F0 DF 82 EF F0 8F E2 B7 07 10 30 -93 87 87 FF 13 07 F0 0F 23 A0 E7 00 B7 07 00 26 -93 87 C7 00 23 A0 07 00 B7 07 00 26 93 87 07 01 -23 A0 07 00 93 07 00 02 23 26 F4 FE 23 24 04 FE -6F 00 80 06 B7 07 00 26 93 87 07 01 03 27 C4 FE -23 A0 E7 00 B7 07 10 30 93 87 C7 FF 93 06 50 02 -03 27 84 FE 33 87 E6 40 23 A0 E7 00 B7 07 00 26 -93 87 07 01 23 A0 07 00 B7 07 10 30 93 87 C7 FF -23 A0 07 00 83 27 C4 FE 93 D7 17 00 23 26 F4 FE -83 27 C4 FE 93 E7 07 02 23 26 F4 FE 83 27 84 FE -93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 40 00 -E3 FA E7 F8 B7 07 00 80 23 26 F4 FE 23 24 04 FE -6F 00 80 08 B7 07 00 26 93 87 07 01 13 07 F0 03 -23 A0 E7 00 B7 07 00 26 93 87 C7 00 03 27 C4 FE -23 A0 E7 00 B7 07 10 30 93 87 C7 FF 93 06 00 02 -03 27 84 FE 33 87 E6 40 23 A0 E7 00 B7 07 00 26 -93 87 07 01 23 A0 07 00 B7 07 00 26 93 87 C7 00 -23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 -83 27 C4 FE 93 D7 17 00 23 26 F4 FE 03 27 C4 FE -B7 07 00 80 B3 67 F7 00 23 26 F4 FE 83 27 84 FE -93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 F0 01 -E3 FA E7 F6 13 00 00 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu.hex deleted file mode 100755 index a9528ab2..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_no_cpu.hex +++ /dev/null @@ -1,47 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 20 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all.hex deleted file mode 100755 index a9528ab2..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all.hex +++ /dev/null @@ -1,47 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 20 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_i.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_i.hex deleted file mode 100755 index 100c12da..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_i.hex +++ /dev/null @@ -1,47 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_o.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_o.hex deleted file mode 100755 index 100c12da..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_all_o.hex +++ /dev/null @@ -1,47 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_i.hex b/verilog/dv/cocotb/hex_files/bitbang_no_cpu_i.hex deleted file mode 100755 index a9528ab2..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_no_cpu_i.hex +++ /dev/null @@ -1,47 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 20 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/bitbang_spi.hex b/verilog/dv/cocotb/hex_files/bitbang_spi.hex deleted file mode 100755 index 100c12da..00000000 --- a/verilog/dv/cocotb/hex_files/bitbang_spi.hex +++ /dev/null @@ -1,47 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/cpu_drive.hex b/verilog/dv/cocotb/hex_files/cpu_drive.hex deleted file mode 100755 index a6ad7e1e..00000000 --- a/verilog/dv/cocotb/hex_files/cpu_drive.hex +++ /dev/null @@ -1,54 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 27 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 C0 1A 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 47 00 F0 93 87 07 80 -13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF -37 07 01 00 13 07 07 FF 23 A0 E7 00 B7 37 00 F0 -93 87 87 01 37 07 19 11 13 07 F7 FF 23 A0 E7 00 -13 00 00 00 B7 07 10 30 93 87 C7 FF 03 A7 07 00 -B7 E7 00 00 93 87 07 FF E3 16 F7 FE B7 07 10 30 -93 87 87 FF 37 E7 00 00 13 07 07 DD 23 A0 E7 00 -93 07 00 00 13 85 07 00 03 24 C1 00 13 01 01 01 -67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/cpu_stress.hex b/verilog/dv/cocotb/hex_files/cpu_stress.hex deleted file mode 100755 index fe38edc5..00000000 --- a/verilog/dv/cocotb/hex_files/cpu_stress.hex +++ /dev/null @@ -1,168 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 03 17 16 00 00 -13 06 C6 95 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 03 -93 05 80 03 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 80 61 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 18 E0 02 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -23 2A 91 00 13 04 01 02 23 26 A4 FE 83 27 C4 FE -63 96 07 00 93 07 00 00 6F 00 40 04 03 27 C4 FE -93 07 10 00 63 16 F7 00 93 07 10 00 6F 00 00 03 -83 27 C4 FE 93 87 F7 FF 13 85 07 00 EF F0 9F FB -93 04 05 00 83 27 C4 FE 93 87 E7 FF 13 85 07 00 -EF F0 5F FA 93 07 05 00 B3 87 F4 00 13 85 07 00 -83 20 C1 01 03 24 81 01 83 24 41 01 13 01 01 02 -67 80 00 00 13 01 01 FD 23 26 11 02 23 24 81 02 -13 04 01 03 23 2E A4 FC 23 2C B4 FC 03 27 84 FD -93 07 10 00 63 D4 E7 0C 83 27 84 FD 93 87 F7 FF -93 85 07 00 03 25 C4 FD EF F0 DF FC 03 27 84 FD -B7 07 00 40 93 87 F7 FF B3 07 F7 00 93 97 27 00 -03 27 C4 FD B3 07 F7 00 83 A7 07 00 23 24 F4 FE -83 27 84 FD 93 87 E7 FF 23 26 F4 FE 6F 00 C0 03 -83 27 C4 FE 93 97 27 00 03 27 C4 FD 33 07 F7 00 -83 27 C4 FE 93 87 17 00 93 97 27 00 83 26 C4 FD -B3 87 F6 00 03 27 07 00 23 A0 E7 00 83 27 C4 FE -93 87 F7 FF 23 26 F4 FE 83 27 C4 FE 63 C0 07 02 -83 27 C4 FE 93 97 27 00 03 27 C4 FD B3 07 F7 00 -83 A7 07 00 03 27 84 FE E3 44 F7 FA 83 27 C4 FE -93 87 17 00 93 97 27 00 03 27 C4 FD B3 07 F7 00 -03 27 84 FE 23 A0 E7 00 6F 00 80 00 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 23 2C B4 FC 23 2A C4 FC 03 27 84 FD -83 27 44 FD 63 5C F7 18 83 27 84 FD 23 22 F4 FE -83 27 84 FD 23 26 F4 FE 83 27 44 FD 23 24 F4 FE -6F 00 80 0E 83 27 C4 FE 93 87 17 00 23 26 F4 FE -83 27 C4 FE 93 97 27 00 03 27 C4 FD B3 07 F7 00 -03 A7 07 00 83 27 44 FE 93 97 27 00 83 26 C4 FD -B3 87 F6 00 83 A7 07 00 63 C0 E7 02 03 27 C4 FE -83 27 44 FD E3 40 F7 FC 6F 00 00 01 83 27 84 FE -93 87 F7 FF 23 24 F4 FE 83 27 84 FE 93 97 27 00 -03 27 C4 FD B3 07 F7 00 03 A7 07 00 83 27 44 FE -93 97 27 00 83 26 C4 FD B3 87 F6 00 83 A7 07 00 -E3 C6 E7 FC 03 27 C4 FE 83 27 84 FE 63 5E F7 04 -83 27 C4 FE 93 97 27 00 03 27 C4 FD B3 07 F7 00 -83 A7 07 00 23 20 F4 FE 83 27 84 FE 93 97 27 00 -03 27 C4 FD 33 07 F7 00 83 27 C4 FE 93 97 27 00 -83 26 C4 FD B3 87 F6 00 03 27 07 00 23 A0 E7 00 -83 27 84 FE 93 97 27 00 03 27 C4 FD B3 07 F7 00 -03 27 04 FE 23 A0 E7 00 03 27 C4 FE 83 27 84 FE -E3 40 F7 F2 83 27 44 FE 93 97 27 00 03 27 C4 FD -B3 07 F7 00 83 A7 07 00 23 20 F4 FE 83 27 84 FE -93 97 27 00 03 27 C4 FD 33 07 F7 00 83 27 44 FE -93 97 27 00 83 26 C4 FD B3 87 F6 00 03 27 07 00 -23 A0 E7 00 83 27 84 FE 93 97 27 00 03 27 C4 FD -B3 07 F7 00 03 27 04 FE 23 A0 E7 00 83 27 84 FE -93 87 F7 FF 13 86 07 00 83 25 84 FD 03 25 C4 FD -EF F0 1F E6 83 27 84 FE 93 87 17 00 03 26 44 FD -93 85 07 00 03 25 C4 FD EF F0 9F E4 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -23 24 B4 FE 23 22 C4 FE 23 20 D4 FE 03 27 C4 FE -83 27 84 FE 33 07 F7 00 83 27 44 FE 33 07 F7 00 -83 27 04 FE B3 07 F7 00 13 85 07 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 26 A4 FE 23 24 B4 FE -23 22 C4 FE 23 20 D4 FE 23 2E E4 FC 83 26 04 FE -03 26 44 FE 83 25 84 FE 03 25 C4 FE EF F0 5F F8 -13 07 05 00 83 27 C4 FD B3 07 F7 00 13 85 07 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 26 A4 FE 23 24 B4 FE 23 22 C4 FE 23 20 D4 FE -23 2E E4 FC 23 2C F4 FC 03 27 C4 FD 83 26 04 FE -03 26 44 FE 83 25 84 FE 03 25 C4 FE EF F0 DF F6 -13 07 05 00 83 27 84 FD B3 07 F7 00 13 85 07 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 26 A4 FE 23 24 B4 FE 23 22 C4 FE 23 20 D4 FE -23 2E E4 FC 23 2C F4 FC 23 2A 04 FD 83 27 84 FD -03 27 C4 FD 83 26 04 FE 03 26 44 FE 83 25 84 FE -03 25 C4 FE EF F0 DF F5 13 07 05 00 83 27 44 FD -B3 07 F7 00 13 85 07 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 26 A4 FE 23 24 B4 FE -23 22 C4 FE 23 20 D4 FE 23 2E E4 FC 23 2C F4 FC -23 2A 04 FD 23 28 14 FD 03 28 44 FD 83 27 84 FD -03 27 C4 FD 83 26 04 FE 03 26 44 FE 83 25 84 FE -03 25 C4 FE EF F0 DF F4 13 07 05 00 83 27 04 FD -B3 07 F7 00 13 85 07 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FA 23 2E 11 04 -23 2C 81 04 13 04 01 06 B7 47 00 F0 93 87 07 80 -13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF -23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 -13 05 A0 00 EF F0 1F AA 23 2A A4 FC 03 27 44 FD -93 07 70 03 63 0C F7 00 B7 07 10 30 93 87 87 FF -13 07 E0 01 23 A0 E7 00 6F 00 40 01 B7 07 10 30 -93 87 87 FF 13 07 B0 01 23 A0 E7 00 23 26 04 FE -23 24 04 FE 6F 00 80 05 13 07 00 00 83 27 84 FE -93 97 27 00 B3 07 F7 00 03 A7 07 00 83 27 84 FE -93 97 27 00 93 87 07 FF B3 87 87 00 23 AC E7 FA -13 07 00 00 83 27 84 FE 93 97 27 00 B3 07 F7 00 -83 A7 07 00 03 27 C4 FE B3 07 F7 00 23 26 F4 FE -83 27 84 FE 93 87 17 00 23 24 F4 FE 03 27 84 FE -93 07 90 00 E3 D2 E7 FA 03 27 C4 FE 93 07 10 19 -63 0C F7 00 B7 07 10 30 93 87 87 FF 13 07 E0 02 -23 A0 E7 00 6F 00 40 01 B7 07 10 30 93 87 87 FF -13 07 B0 02 23 A0 E7 00 93 07 84 FA 93 05 A0 00 -13 85 07 00 EF F0 1F A4 23 22 04 FE 23 20 04 FE -6F 00 00 03 83 27 04 FE 93 97 27 00 93 87 07 FF -B3 87 87 00 83 A7 87 FB 03 27 44 FE B3 07 F7 00 -23 22 F4 FE 83 27 04 FE 93 87 17 00 23 20 F4 FE -03 27 04 FE 93 07 90 00 E3 D6 E7 FC 03 27 C4 FE -83 27 44 FE 63 0C F7 00 B7 07 10 30 93 87 87 FF -13 07 E0 03 23 A0 E7 00 6F 00 40 01 B7 07 10 30 -93 87 87 FF 13 07 B0 03 23 A0 E7 00 23 2E 04 FC -6F 00 80 05 13 07 00 00 83 27 C4 FD 93 97 27 00 -B3 07 F7 00 03 A7 07 00 83 27 C4 FD 93 97 27 00 -93 87 07 FF B3 87 87 00 23 AC E7 FA 13 07 00 00 -83 27 C4 FD 93 97 27 00 B3 07 F7 00 83 A7 07 00 -03 27 C4 FE B3 07 F7 00 23 26 F4 FE 83 27 C4 FD -93 87 17 00 23 2E F4 FC 03 27 C4 FD 93 07 90 00 -E3 D2 E7 FA 93 07 84 FA 13 06 90 00 93 05 00 00 -13 85 07 00 EF F0 DF A4 23 2C 04 FC 6F 00 00 03 -83 27 84 FD 93 97 27 00 93 87 07 FF B3 87 87 00 -83 A7 87 FB 03 27 44 FE B3 07 F7 00 23 22 F4 FE -83 27 84 FD 93 87 17 00 23 2C F4 FC 03 27 84 FD -93 07 90 00 E3 D6 E7 FC 03 27 C4 FE 83 27 44 FE -63 0C F7 00 B7 07 10 30 93 87 87 FF 13 07 E0 04 -23 A0 E7 00 6F 00 40 01 B7 07 10 30 93 87 87 FF -13 07 B0 04 23 A0 E7 00 93 08 00 05 13 08 60 04 -93 07 C0 03 13 07 20 03 93 06 80 02 13 06 E0 01 -93 05 40 01 13 05 A0 00 EF F0 1F CF 23 28 A4 FC -03 27 04 FD 93 07 80 16 63 0C F7 00 B7 07 10 30 -93 87 87 FF 13 07 E0 05 23 A0 E7 00 6F 00 40 01 -B7 07 10 30 93 87 87 FF 13 07 B0 05 23 A0 E7 00 -B7 07 10 30 93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 -13 00 00 00 83 20 C1 05 03 24 81 05 13 01 01 06 -67 80 00 00 -@00000A28 -01 00 00 00 28 00 00 00 02 00 00 00 05 00 00 00 -16 00 00 00 0B 00 00 00 5A 00 00 00 C8 00 00 00 -0A 00 00 00 14 00 00 00 19 00 00 00 00 00 00 00 diff --git a/verilog/dv/cocotb/hex_files/gpio_all_i.hex b/verilog/dv/cocotb/hex_files/gpio_all_i.hex deleted file mode 100755 index b63b1fd4..00000000 --- a/verilog/dv/cocotb/hex_files/gpio_all_i.hex +++ /dev/null @@ -1,218 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 -13 06 46 CC 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 -23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 -13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 -B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 -23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF -EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 -E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC -EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB -EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 -EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF -EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA -EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 -EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 -EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 -EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF -EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 -EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC -EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 -EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 -EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 -EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C -EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 -EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B -EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A -EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 -EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 47 00 F0 93 87 07 80 -13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF -23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 -B7 07 00 26 93 87 87 0B 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 0B 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 0B -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 0A 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 87 0A 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 0A 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 0A -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 09 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 87 09 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 09 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 09 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 08 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 87 08 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 08 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 08 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 07 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 87 07 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 07 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 07 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 06 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 87 06 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 06 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 06 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 05 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 87 05 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 05 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 05 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 04 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 87 04 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 04 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 04 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 03 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 87 03 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 03 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 07 03 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 02 37 27 00 00 13 07 37 80 23 A0 E7 00 -B7 07 00 26 93 87 87 02 37 27 00 00 13 07 37 80 -23 A0 E7 00 B7 07 00 26 93 87 47 02 37 27 00 00 -13 07 37 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -13 07 10 00 23 A0 E7 00 13 00 00 00 B7 07 00 26 -03 A7 07 00 93 07 10 00 E3 0A F7 FE B7 07 10 30 -93 87 87 FF 13 07 A0 0A 23 A0 E7 00 13 00 00 00 -B7 07 00 26 93 87 C7 00 03 A7 07 00 B7 07 67 8F -93 87 B7 D7 E3 16 F7 FE B7 07 10 30 93 87 87 FF -13 07 B0 0B 23 A0 E7 00 13 00 00 00 B7 07 00 26 -93 87 C7 00 03 A7 07 00 B7 97 A8 FF 93 87 A7 C5 -E3 16 F7 FE B7 07 10 30 93 87 87 FF 13 07 C0 0C -23 A0 E7 00 13 00 00 00 B7 07 00 26 93 87 C7 00 -03 A7 07 00 B7 67 53 C9 93 87 67 34 E3 16 F7 FE -B7 07 10 30 93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/gpio_all_o.hex b/verilog/dv/cocotb/hex_files/gpio_all_o.hex deleted file mode 100755 index 66ca4b7f..00000000 --- a/verilog/dv/cocotb/hex_files/gpio_all_o.hex +++ /dev/null @@ -1,230 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 16 00 00 -13 06 C6 D7 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 D0 07 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 06 23 A0 E7 00 B7 07 00 26 13 07 60 07 -23 A0 E7 00 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -B7 07 00 26 13 07 60 00 23 A0 E7 00 B7 07 00 26 -13 07 60 01 23 A0 E7 00 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 B7 07 00 26 13 07 60 04 23 A0 E7 00 -B7 07 00 26 13 07 60 05 23 A0 E7 00 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 B7 07 00 26 13 07 60 02 -23 A0 E7 00 B7 07 00 26 13 07 60 03 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 E0 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 B7 07 00 26 -13 07 60 00 23 A0 E7 00 B7 07 00 26 13 07 40 00 -23 A0 E7 00 B7 07 00 26 13 07 60 00 23 A0 E7 00 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 DF EF -EF F0 9F EF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 5F EE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF E9 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 80 00 -E3 F6 E7 FC EF F0 1F E8 13 00 00 00 83 20 C1 02 -03 24 81 02 13 01 01 03 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -83 27 C4 FD 23 24 F4 FE EF F0 5F EB EF F0 1F EB -23 26 04 FE 6F 00 00 03 83 27 84 FE 63 8C 07 00 -EF F0 DF E9 83 27 84 FE 93 87 F7 FF 23 24 F4 FE -6F 00 80 00 EF F0 1F E2 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 80 00 E3 F6 E7 FC -EF F0 5F E0 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 5F E0 EF F0 1F E0 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 DF DE -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F DA 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF DB -EF F0 5F D8 EF F0 1F D8 EF F0 1F DB 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F D1 -EF F0 1F D1 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF CF 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF D1 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 DF CC EF F0 DF CF EF F0 9F CF -EF F0 1F CC 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF C8 EF F0 9F C8 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F C7 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F C9 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 DF CA -EF F0 5F C7 EF F0 9F CD EF F0 9F C3 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F C0 -EF F0 1F C0 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 DF BE 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF C0 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 9F C5 EF F0 DF BE EF F0 DF C1 -EF F0 1F BB 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF B7 EF F0 9F B7 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F B6 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F B8 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 9F B6 -EF F0 5F B6 EF F0 DF B2 EF F0 9F B2 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FD 23 26 11 02 23 24 81 02 13 04 01 03 -23 2E A4 FC 83 27 C4 FD 23 24 F4 FE EF F0 5F AF -EF F0 1F AF 23 26 04 FE 6F 00 00 03 83 27 84 FE -63 8C 07 00 EF F0 9F B7 83 27 84 FE 93 87 F7 FF -23 24 F4 FE 6F 00 80 00 EF F0 DF AF 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 60 00 -E3 F6 E7 FC EF F0 5F B1 EF F0 DF AD EF F0 1F B4 -EF F0 1F AA 13 00 00 00 83 20 C1 02 03 24 81 02 -13 01 01 03 67 80 00 00 13 01 01 FD 23 26 11 02 -23 24 81 02 13 04 01 03 23 2E A4 FC 83 27 C4 FD -23 24 F4 FE EF F0 DF A6 EF F0 9F A6 23 26 04 FE -6F 00 00 03 83 27 84 FE 63 8C 07 00 EF F0 5F A5 -83 27 84 FE 93 87 F7 FF 23 24 F4 FE 6F 00 80 00 -EF F0 5F A7 83 27 C4 FE 93 87 17 00 23 26 F4 FE -03 27 C4 FE 93 07 60 00 E3 F6 E7 FC EF F0 1F AC -EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 13 00 00 00 -83 20 C1 02 03 24 81 02 13 01 01 03 67 80 00 00 -13 01 01 FF 23 26 11 00 23 24 81 00 13 04 01 01 -EF F0 1F 9F EF F0 5F A5 EF F0 DF A1 EF F0 9F A1 -EF F0 5F A1 EF F0 1F A1 EF F0 DF A0 EF F0 9F A0 -EF F0 5F A0 EF F0 9F A6 EF F0 DF 9F EF F0 5F 9C -EF F0 1F 9C EF F0 DF A8 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 EF F0 5F 99 -EF F0 9F 9F EF F0 1F 9C EF F0 DF 9B EF F0 9F 9B -EF F0 5F 9B EF F0 1F 9B EF F0 DF 9A EF F0 9F 9A -EF F0 DF A0 EF F0 1F 9A EF F0 5F A0 EF F0 5F 96 -EF F0 1F A3 B7 07 00 26 93 87 87 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FE -23 2E 81 00 13 04 01 02 B7 47 00 F0 93 87 07 80 -13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF -23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 -B7 07 00 26 93 87 87 0B 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 0B 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 0B -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 0A 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 0A 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 0A 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 0A -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 09 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 09 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 09 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 09 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 08 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 08 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 08 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 08 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 07 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 07 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 07 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 07 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 06 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 06 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 06 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 06 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 05 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 05 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 05 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 05 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 04 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 04 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 04 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 04 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 03 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 03 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 03 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 07 03 -37 27 00 00 13 07 37 80 23 A0 E7 00 B7 07 00 26 -93 87 C7 02 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 02 37 27 00 00 13 07 97 80 -23 A0 E7 00 B7 07 00 26 93 87 47 02 37 27 00 00 -13 07 97 80 23 A0 E7 00 B7 07 00 26 93 87 47 02 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -13 07 10 00 23 A0 E7 00 13 00 00 00 B7 07 00 26 -03 A7 07 00 93 07 10 00 E3 0A F7 FE B7 07 10 30 -93 87 87 FF 13 07 F0 0F 23 A0 E7 00 B7 07 00 26 -93 87 C7 00 23 A0 07 00 B7 07 00 26 93 87 07 01 -23 A0 07 00 93 07 00 02 23 26 F4 FE 23 24 04 FE -6F 00 80 06 B7 07 00 26 93 87 07 01 03 27 C4 FE -23 A0 E7 00 B7 07 10 30 93 87 C7 FF 93 06 50 02 -03 27 84 FE 33 87 E6 40 23 A0 E7 00 B7 07 00 26 -93 87 07 01 23 A0 07 00 B7 07 10 30 93 87 C7 FF -23 A0 07 00 83 27 C4 FE 93 D7 17 00 23 26 F4 FE -83 27 C4 FE 93 E7 07 02 23 26 F4 FE 83 27 84 FE -93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 40 00 -E3 FA E7 F8 B7 07 00 80 23 26 F4 FE 23 24 04 FE -6F 00 80 08 B7 07 00 26 93 87 07 01 13 07 F0 03 -23 A0 E7 00 B7 07 00 26 93 87 C7 00 03 27 C4 FE -23 A0 E7 00 B7 07 10 30 93 87 C7 FF 93 06 00 02 -03 27 84 FE 33 87 E6 40 23 A0 E7 00 B7 07 00 26 -93 87 07 01 23 A0 07 00 B7 07 00 26 93 87 C7 00 -23 A0 07 00 B7 07 10 30 93 87 C7 FF 23 A0 07 00 -83 27 C4 FE 93 D7 17 00 23 26 F4 FE 03 27 C4 FE -B7 07 00 80 B3 67 F7 00 23 26 F4 FE 83 27 84 FE -93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 F0 01 -E3 FA E7 F6 13 00 00 00 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/helloWorld.hex b/verilog/dv/cocotb/hex_files/helloWorld.hex deleted file mode 100755 index 8816cba9..00000000 --- a/verilog/dv/cocotb/hex_files/helloWorld.hex +++ /dev/null @@ -1,32 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 12 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 C0 0B 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 93 07 00 00 13 85 07 00 -03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/hk_regs_rst_spi.hex b/verilog/dv/cocotb/hex_files/hk_regs_rst_spi.hex deleted file mode 100755 index 100c12da..00000000 --- a/verilog/dv/cocotb/hex_files/hk_regs_rst_spi.hex +++ /dev/null @@ -1,47 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/hk_regs_wr_spi.hex b/verilog/dv/cocotb/hex_files/hk_regs_wr_spi.hex deleted file mode 100755 index 100c12da..00000000 --- a/verilog/dv/cocotb/hex_files/hk_regs_wr_spi.hex +++ /dev/null @@ -1,47 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex b/verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex deleted file mode 100755 index 100c12da..00000000 --- a/verilog/dv/cocotb/hex_files/hk_regs_wr_wb.hex +++ /dev/null @@ -1,47 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 21 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FF 23 26 81 00 13 04 01 01 13 00 00 00 -03 24 C1 00 13 01 01 01 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/mem_stress.hex b/verilog/dv/cocotb/hex_files/mem_stress.hex deleted file mode 100755 index 0e5f942d..00000000 --- a/verilog/dv/cocotb/hex_files/mem_stress.hex +++ /dev/null @@ -1,102 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 57 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 CA 23 2E 81 34 13 04 01 36 -B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 -B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 -93 87 C7 FF 23 A0 07 00 93 07 04 CA 23 2C F4 FC -93 07 04 CA 23 2A F4 FC 93 07 90 07 A3 09 F4 FC -B7 87 79 79 93 87 97 97 23 26 F4 FC B7 87 FF FF -93 C7 97 97 23 15 F4 FC 83 47 34 FD A3 07 F4 FE -23 20 04 FE 6F 00 80 06 83 47 F4 FE 13 87 07 00 -93 07 07 00 93 97 17 00 B3 87 E7 00 93 F7 F7 0F -93 87 57 00 93 F7 F7 0F 13 97 87 01 13 57 87 41 -83 07 34 FD B3 67 F7 00 93 97 87 01 93 D7 87 41 -13 F7 F7 0F 83 27 04 FE 93 87 07 FF B3 87 87 00 -23 88 E7 CA 83 47 F4 FE 93 87 B7 00 A3 07 F4 FE -83 27 04 FE 93 87 17 00 23 20 F4 FE 03 27 04 FE -93 07 F0 31 E3 DA E7 F8 83 47 34 FD A3 07 F4 FE -A3 0F 04 FC 23 20 04 FE 6F 00 C0 08 83 47 F4 FE -13 87 07 00 93 07 07 00 93 97 17 00 B3 87 E7 00 -93 F7 F7 0F 93 87 57 00 93 F7 F7 0F 13 97 87 01 -13 57 87 41 83 07 34 FD B3 67 F7 00 93 97 87 01 -93 D7 87 41 A3 04 F4 FC 83 27 04 FE 93 87 07 FF -B3 87 87 00 83 C7 07 CB 03 47 94 FC 63 00 F7 02 -B7 07 10 30 93 87 87 FF 13 07 E0 01 23 A0 E7 00 -93 07 10 00 A3 0F F4 FC 6F 00 80 02 83 47 F4 FE -93 87 B7 00 A3 07 F4 FE 83 27 04 FE 93 87 17 00 -23 20 F4 FE 03 27 04 FE 93 07 F0 31 E3 D8 E7 F6 -83 47 F4 FD 93 C7 17 00 93 F7 F7 0F 63 8A 07 00 -B7 07 10 30 93 87 87 FF 13 07 B0 01 23 A0 E7 00 -A3 0F 04 FC 83 27 C4 FC 23 24 F4 FE 23 20 04 FE -6F 00 C0 04 03 27 84 FE 93 07 07 00 93 97 17 00 -B3 87 E7 00 93 86 57 00 83 27 04 FE 93 97 27 00 -03 27 44 FD B3 07 F7 00 03 27 C4 FC 33 E7 E6 00 -23 A0 E7 00 83 27 84 FE 93 87 B7 00 23 24 F4 FE -83 27 04 FE 93 87 17 00 23 20 F4 FE 03 27 04 FE -93 07 70 0C E3 D8 E7 FA 83 27 C4 FC 23 24 F4 FE -23 20 04 FE 6F 00 40 07 03 27 84 FE 93 07 07 00 -93 97 17 00 B3 87 E7 00 93 87 57 00 03 27 C4 FC -B3 67 F7 00 23 22 F4 FC 83 27 04 FE 93 97 27 00 -03 27 44 FD B3 07 F7 00 83 A7 07 00 03 27 44 FC -63 00 F7 02 B7 07 10 30 93 87 87 FF 13 07 E0 02 -23 A0 E7 00 93 07 10 00 A3 0F F4 FC 6F 00 80 02 -83 27 84 FE 93 87 B7 00 23 24 F4 FE 83 27 04 FE -93 87 17 00 23 20 F4 FE 03 27 04 FE 93 07 70 0C -E3 D4 E7 F8 83 47 F4 FD 93 C7 17 00 93 F7 F7 0F -63 8A 07 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 -23 A0 E7 00 A3 0F 04 FC 83 57 A4 FC 23 13 F4 FE -23 20 04 FE 6F 00 80 07 83 57 64 FE 13 87 07 00 -93 07 07 00 93 97 17 00 B3 87 E7 00 93 97 07 01 -93 D7 07 01 93 87 57 00 93 97 07 01 93 D7 07 01 -13 97 07 01 13 57 07 41 83 17 A4 FC B3 67 F7 00 -93 96 07 01 93 D6 06 41 83 27 04 FE 93 97 17 00 -03 27 84 FD B3 07 F7 00 13 97 06 01 13 57 07 01 -23 90 E7 00 83 57 64 FE 93 87 B7 00 23 13 F4 FE -83 27 04 FE 93 87 17 00 23 20 F4 FE 03 27 04 FE -93 07 F0 18 E3 D2 E7 F8 83 57 A4 FC 23 13 F4 FE -23 20 04 FE 6F 00 80 09 83 57 64 FE 13 87 07 00 -93 07 07 00 93 97 17 00 B3 87 E7 00 93 97 07 01 -93 D7 07 01 93 87 57 00 93 97 07 01 93 D7 07 01 -13 97 07 01 13 57 07 41 83 17 A4 FC B3 67 F7 00 -93 97 07 01 93 D7 07 41 23 11 F4 FC 83 27 04 FE -93 97 17 00 03 27 84 FD B3 07 F7 00 83 D7 07 00 -03 57 24 FC 63 00 F7 02 B7 07 10 30 93 87 87 FF -13 07 E0 03 23 A0 E7 00 93 07 10 00 A3 0F F4 FC -6F 00 80 02 83 57 64 FE 93 87 B7 00 23 13 F4 FE -83 27 04 FE 93 87 17 00 23 20 F4 FE 03 27 04 FE -93 07 F0 18 E3 D2 E7 F6 83 47 F4 FD 93 C7 17 00 -93 F7 F7 0F 63 8A 07 00 B7 07 10 30 93 87 87 FF -13 07 B0 03 23 A0 E7 00 B7 07 10 30 93 87 C7 FF -13 07 F0 0F 23 A0 E7 00 13 00 00 00 03 24 C1 35 -13 01 01 36 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex b/verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex deleted file mode 100755 index 51a2dfb7..00000000 --- a/verilog/dv/cocotb/hex_files/mgmt_gpio_in.hex +++ /dev/null @@ -1,66 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 34 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 -B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 -B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 -93 87 C7 FF 23 A0 07 00 B7 37 00 F0 93 87 07 80 -13 07 10 00 23 A0 E7 00 B7 37 00 F0 93 87 47 80 -23 A0 07 00 B7 37 00 F0 93 87 87 80 13 07 10 00 -23 A0 E7 00 B7 37 00 F0 93 87 C7 80 13 07 10 00 -23 A0 E7 00 B7 07 10 30 93 87 87 FF 13 07 A0 00 -23 A0 E7 00 23 26 04 FE 6F 00 C0 05 13 00 00 00 -B7 37 00 F0 93 87 07 81 83 A7 07 00 E3 8A 07 FE -B7 07 10 30 93 87 C7 FF 13 07 A0 0A 23 A0 E7 00 -13 00 00 00 B7 37 00 F0 93 87 07 81 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 07 10 30 93 87 C7 FF -13 07 B0 0B 23 A0 E7 00 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 90 00 E3 D0 E7 FA -B7 07 10 30 93 87 C7 FF 13 07 B0 01 23 A0 E7 00 -B7 07 10 30 93 87 87 FF 13 07 40 01 23 A0 E7 00 -23 24 04 FE 6F 00 C0 05 13 00 00 00 B7 37 00 F0 -93 87 07 81 83 A7 07 00 E3 8A 07 FE B7 07 10 30 -93 87 C7 FF 13 07 A0 0A 23 A0 E7 00 13 00 00 00 -B7 37 00 F0 93 87 07 81 03 A7 07 00 93 07 10 00 -E3 08 F7 FE B7 07 10 30 93 87 C7 FF 13 07 B0 0B -23 A0 E7 00 83 27 84 FE 93 87 17 00 23 24 F4 FE -03 27 84 FE 93 07 30 01 E3 D0 E7 FA B7 07 10 30 -93 87 C7 FF 13 07 B0 02 23 A0 E7 00 B7 37 00 F0 -93 87 07 81 83 A7 07 00 23 20 F4 FE B7 07 10 30 -93 87 87 FF 23 A0 07 00 23 22 04 FE 6F 00 40 03 -B7 37 00 F0 93 87 07 81 03 A7 07 00 83 27 04 FE -63 0A F7 00 B7 07 10 30 93 87 C7 FF 13 07 E0 0E -23 A0 E7 00 83 27 44 FE 93 87 17 00 23 22 F4 FE -03 27 44 FE 93 07 10 03 E3 D4 E7 FC B7 07 10 30 -93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 -03 24 C1 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex b/verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex deleted file mode 100755 index 03087382..00000000 --- a/verilog/dv/cocotb/hex_files/mgmt_gpio_out.hex +++ /dev/null @@ -1,54 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 28 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 -B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 -B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 -93 87 C7 FF 23 A0 07 00 B7 37 00 F0 93 87 07 80 -13 07 10 00 23 A0 E7 00 B7 37 00 F0 93 87 47 80 -23 A0 07 00 B7 37 00 F0 93 87 87 80 13 07 10 00 -23 A0 E7 00 B7 37 00 F0 93 87 C7 80 13 07 10 00 -23 A0 E7 00 B7 07 10 30 93 87 87 FF 13 07 A0 00 -23 A0 E7 00 23 26 04 FE 6F 00 C0 02 B7 37 00 F0 -93 87 47 81 13 07 10 00 23 A0 E7 00 B7 37 00 F0 -93 87 47 81 23 A0 07 00 83 27 C4 FE 93 87 17 00 -23 26 F4 FE 03 27 C4 FE 93 07 90 00 E3 D8 E7 FC -B7 07 10 30 93 87 87 FF 13 07 40 01 23 A0 E7 00 -23 24 04 FE 6F 00 C0 02 B7 37 00 F0 93 87 47 81 -13 07 10 00 23 A0 E7 00 B7 37 00 F0 93 87 47 81 -23 A0 07 00 83 27 84 FE 93 87 17 00 23 24 F4 FE -03 27 84 FE 93 07 30 01 E3 D8 E7 FC B7 07 10 30 -93 87 87 FF 23 A0 07 00 B7 07 10 30 93 87 87 FF -23 A0 07 00 B7 07 10 30 93 87 87 FF 23 A0 07 00 -B7 07 10 30 93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 -13 00 00 00 03 24 C1 01 13 01 01 02 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/timer0_oneshot.hex b/verilog/dv/cocotb/hex_files/timer0_oneshot.hex deleted file mode 100755 index 79b4ae69..00000000 --- a/verilog/dv/cocotb/hex_files/timer0_oneshot.hex +++ /dev/null @@ -1,58 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 2B 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 -B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 -B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 -93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00 -23 A0 07 00 B7 57 00 F0 37 37 0F 00 23 A0 E7 00 -B7 57 00 F0 93 87 87 00 13 07 10 00 23 A0 E7 00 -B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 -B7 57 00 F0 93 87 07 01 83 A7 07 00 23 26 F4 FE -B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 -B7 57 00 F0 93 87 07 01 83 A7 07 00 23 22 F4 FE -03 27 44 FE 83 27 C4 FE 63 70 F7 02 83 27 44 FE -63 8C 07 00 B7 07 10 30 93 87 87 FF 13 07 B0 01 -23 A0 E7 00 6F 00 80 03 83 27 44 FE 63 90 07 02 -B7 07 10 30 93 87 87 FF 13 07 B0 02 23 A0 E7 00 -13 00 00 00 23 24 04 FE 6F 00 C0 02 B7 07 10 30 -93 87 87 FF 13 07 F0 01 23 A0 E7 00 83 27 44 FE -23 26 F4 FE 6F F0 DF F7 83 27 84 FE 93 87 17 00 -23 24 F4 FE 03 27 84 FE 93 07 90 00 E3 D6 E7 FE -B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 -B7 57 00 F0 93 87 07 01 83 A7 07 00 63 9C 07 00 -B7 07 10 30 93 87 87 FF 13 07 B0 03 23 A0 E7 00 -6F 00 40 01 B7 07 10 30 93 87 87 FF 13 07 F0 02 -23 A0 E7 00 B7 07 10 30 93 87 C7 FF 13 07 F0 0F -23 A0 E7 00 13 00 00 00 03 24 C1 01 13 01 01 02 -67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/timer0_periodic.hex b/verilog/dv/cocotb/hex_files/timer0_periodic.hex deleted file mode 100755 index 45cfd920..00000000 --- a/verilog/dv/cocotb/hex_files/timer0_periodic.hex +++ /dev/null @@ -1,60 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 0F 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FD 23 26 81 02 13 04 01 03 -B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 -B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 -93 87 C7 FF 23 A0 07 00 B7 57 00 F0 93 87 87 00 -23 A0 07 00 B7 57 00 F0 23 A0 07 00 B7 57 00 F0 -93 87 47 00 13 07 00 30 23 A0 E7 00 B7 57 00 F0 -93 87 87 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 -93 87 C7 00 13 07 10 00 23 A0 E7 00 B7 57 00 F0 -93 87 07 01 83 A7 07 00 23 26 F4 FE 23 24 04 FE -93 07 00 19 23 20 F4 FE 23 22 04 FE 6F 00 C0 0C -B7 57 00 F0 93 87 C7 00 13 07 10 00 23 A0 E7 00 -B7 57 00 F0 93 87 07 01 83 A7 07 00 23 2E F4 FC -03 27 C4 FD 83 27 C4 FE 63 F8 E7 06 83 27 84 FE -93 87 17 00 23 24 F4 FE 03 27 84 FE 93 07 10 00 -63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 01 -23 A0 E7 00 6F 00 40 04 03 27 84 FE 93 07 20 00 -63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 02 -23 A0 E7 00 6F 00 40 02 03 27 84 FE 93 07 30 00 -63 1C F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 03 -23 A0 E7 00 6F 00 00 04 03 27 C4 FD 83 27 C4 FE -63 7A F7 00 B7 07 10 30 93 87 87 FF 13 07 B0 04 -23 A0 E7 00 83 27 C4 FD 23 26 F4 FE 83 27 44 FE -93 87 17 00 23 22 F4 FE 03 27 44 FE 83 27 04 FE -E3 48 F7 F2 83 27 84 FE 63 9A 07 00 B7 07 10 30 -93 87 87 FF 13 07 E0 0E 23 A0 E7 00 B7 07 10 30 -93 87 C7 FF 13 07 F0 0F 23 A0 E7 00 13 00 00 00 -03 24 C1 02 13 01 01 03 67 80 00 00 diff --git a/verilog/dv/cocotb/hex_files/uart_tx.hex b/verilog/dv/cocotb/hex_files/uart_tx.hex deleted file mode 100755 index 25ae4e61..00000000 --- a/verilog/dv/cocotb/hex_files/uart_tx.hex +++ /dev/null @@ -1,62 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 46 2E 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 00 1B 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 11 00 23 2C 81 00 -13 04 01 02 93 07 05 00 A3 07 F4 FE 03 47 F4 FE -93 07 A0 00 63 16 F7 00 13 05 D0 00 EF F0 9F FD -13 00 00 00 B7 67 00 F0 93 87 47 80 03 A7 07 00 -93 07 10 00 E3 08 F7 FE B7 67 00 F0 93 87 07 80 -03 47 F4 FE 23 A0 E7 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FE -23 2E 11 00 23 2C 81 00 13 04 01 02 23 26 A4 FE -6F 00 C0 01 83 27 C4 FE 13 87 17 00 23 26 E4 FE -83 C7 07 00 13 85 07 00 EF F0 DF F6 83 27 C4 FE -83 C7 07 00 E3 90 07 FE 13 00 00 00 13 00 00 00 -83 20 C1 01 03 24 81 01 13 01 01 02 67 80 00 00 -13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 -B7 47 00 F0 93 87 07 80 13 07 10 00 23 A0 E7 00 -B7 07 10 30 93 87 87 FF 23 A0 07 00 B7 07 10 30 -93 87 C7 FF 23 A0 07 00 B7 07 00 26 93 87 C7 03 -37 27 00 00 13 07 97 80 23 A0 E7 00 B7 07 00 26 -13 07 10 00 23 A0 E7 00 13 00 00 00 B7 07 00 26 -03 A7 07 00 93 07 10 00 E3 0A F7 FE B7 67 00 F0 -13 07 10 00 23 A0 E7 00 B7 07 10 30 93 87 87 FF -13 07 A0 0A 23 A0 E7 00 B7 07 00 10 13 85 07 39 -EF F0 DF F1 23 26 04 FE 6F 00 00 01 83 27 C4 FE -93 87 17 00 23 26 F4 FE 03 27 C4 FE 93 07 F0 09 -E3 D6 E7 FE 13 00 00 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 -@0000038C -00 00 00 00 4D 6F 6E 69 74 6F 72 3A 20 54 65 73 -74 20 55 41 52 54 20 28 52 54 4C 29 20 70 61 73 -73 65 64 00 From b5fb97e5f4f854013e95cfa01c1afdfe37549deb Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 04:22:44 -0700 Subject: [PATCH 17/76] rename run.py to cocotb.py --- verilog/dv/cocotb/{run.py => cocotb.py} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename verilog/dv/cocotb/{run.py => cocotb.py} (100%) mode change 100644 => 100755 diff --git a/verilog/dv/cocotb/run.py b/verilog/dv/cocotb/cocotb.py old mode 100644 new mode 100755 similarity index 100% rename from verilog/dv/cocotb/run.py rename to verilog/dv/cocotb/cocotb.py From bd712f64d4a95fb532a73ae7e8c456874b9901ae Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 04:29:48 -0700 Subject: [PATCH 18/76] rename cocotb.py to verify_cocotb.py --- verilog/dv/cocotb/{cocotb.py => verify_cocotb.py} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename verilog/dv/cocotb/{cocotb.py => verify_cocotb.py} (100%) diff --git a/verilog/dv/cocotb/cocotb.py b/verilog/dv/cocotb/verify_cocotb.py similarity index 100% rename from verilog/dv/cocotb/cocotb.py rename to verilog/dv/cocotb/verify_cocotb.py From ad053568e7c6636611e8c572cacb621318636657 Mon Sep 17 00:00:00 2001 From: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Date: Sun, 2 Oct 2022 14:09:49 +0200 Subject: [PATCH 19/76] Create README.md add READme in doc file --- verilog/dv/cocotb/doc/README.md | 1 + 1 file changed, 1 insertion(+) create mode 100644 verilog/dv/cocotb/doc/README.md diff --git a/verilog/dv/cocotb/doc/README.md b/verilog/dv/cocotb/doc/README.md new file mode 100644 index 00000000..8b137891 --- /dev/null +++ b/verilog/dv/cocotb/doc/README.md @@ -0,0 +1 @@ + From a0da0fc90647d2e5bfb37f6aee68cc68922ee7d6 Mon Sep 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zrqv6bsxLKBEgIKGB5~RJVeW!-wfR@F+;NHM!EmkED&19R;msH{YcufHm^GORzV6@I z1mf?uBRR5cyVp-l6bOk;Os3eM!S8{sx)N?jb4ncjrdgnD$+nJEzRB*~UOc@u>P3CW4>@S+CS1&4XrR;o2OY0dHv00@R` zH3PSz+f zpY1VJv=4xcp~Kr#_(qW&un7S4Vx~Gl?mVou z3E&lNy$1TsNSk?1pMZCecfbr85V&0uX+$xoi;HQ=Iemifs%tA$S41ESl@m=w`2Rza z{8IeQ8+RTWJM%O&tB6dYl-K9xHu!^fHUTqnBw^j1W5*Hdb0kN2R{rib1OdM3wd;O)iD=6@76tJcJd(+ZqDOHc!aZWF}{`~KX z)_yyz4*!1Knq%rAYtA(kU@e8kz7@ze2W&imZI^X)w?Yv&GJP>=R$gWvQ0)GDjplwc zV}#Nm+3jNAQ_2=FQ`8R$P4`)0m&fnT9)Hqk_g_z#mNJyo`+0c||GN^ClPMRAl5- Date: Sun, 2 Oct 2022 14:27:42 +0200 Subject: [PATCH 21/76] Update README.md --- verilog/dv/cocotb/README.md | 59 ++++++++++++++++++++++++++++--------- 1 file changed, 45 insertions(+), 14 deletions(-) diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md index 5512fc70..ee57815c 100644 --- a/verilog/dv/cocotb/README.md +++ b/verilog/dv/cocotb/README.md @@ -1,21 +1,52 @@ -# How to run test: +Overview +======== +Cocotb environment (CTN) is a dynamic simulation testing environment. It's purpose is to speed testing simulation time and get coverage data. The environment is developed using cocotb, an open source coroutine-based co simulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. CTN has 2 main layers: tests and whitebox models. Tests layer contain multiple tests and sequences that can communicate with the caravel (dut) through drivers shown in read at fig 1. Whitebox models layer contain multiple models that should mimic the behavior of each main block inside caravel see fig1. Model is supposed to check if the model is working as expected, if its registers contain the expected values all the time and report coverage of features provided by this block if it’s tested or not. -Navigate to the cocotb directory and run the following command -## To run test : - >python3 run.py -t -sim -tag +.. image::docs/CTN.png +fig1. caravel testbench environment (read lines are drivers ) + +Prerequisites +============================= + +- Docker: [Linux](https://hub.docker.com/search?q=&type=edition&offering=community&operating_system=linux&utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Windows](https://desktop.docker.com/win/main/amd64/Docker%20Desktop%20Installer.exe?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with Intel Chip](https://desktop.docker.com/mac/main/amd64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with M1 Chip](https://desktop.docker.com/mac/main/arm64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) +- Python 3.6+ with PIP +- cocotb +- iverilog or vcs + +run a test +============================= + + Use script verify_cocotb.py + +``` - Or + -h, --help show this help message and exit - >python3 run.py --test -sim -tag + -regression REGRESSION, -r REGRESSION + name of regression can found in tests.json + + -test TEST [TEST ...], -t TEST [TEST ...] + name of test if no --sim provided RTL will be run + + + -sim SIM [SIM ...] Simulation type to be run RTL,GL&GL_SDF provided only + when run -test + + -testlist TESTLIST, -tl TESTLIST + path of testlist to be run + + -tag TAG provide tag of the run default would be regression + name and if no regression is provided would be + run___ + + -maxerr MAXERR max number of errors for every test before simulation + breaks default = 3 + +``` -## To run regression - >python3 run.py -r -tag - Or +Tests +=============== - >python3 run.py --regression -tag +Refer to [tests.json](tests.json) for tests list -## Notes -> Tests and regressions can be used in the same command - -> Tests and regressions can be found under cocotb/tests.json From bc9eb2eb3175822e2d004298968f560f8b16e993 Mon Sep 17 00:00:00 2001 From: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Date: Sun, 2 Oct 2022 14:35:49 +0200 Subject: [PATCH 22/76] Update README.md --- verilog/dv/cocotb/README.md | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md index ee57815c..e6365258 100644 --- a/verilog/dv/cocotb/README.md +++ b/verilog/dv/cocotb/README.md @@ -2,7 +2,9 @@ Overview ======== Cocotb environment (CTN) is a dynamic simulation testing environment. It's purpose is to speed testing simulation time and get coverage data. The environment is developed using cocotb, an open source coroutine-based co simulation testbench environment for verifying VHDL and SystemVerilog RTL using Python. CTN has 2 main layers: tests and whitebox models. Tests layer contain multiple tests and sequences that can communicate with the caravel (dut) through drivers shown in read at fig 1. Whitebox models layer contain multiple models that should mimic the behavior of each main block inside caravel see fig1. Model is supposed to check if the model is working as expected, if its registers contain the expected values all the time and report coverage of features provided by this block if it’s tested or not. -.. image::docs/CTN.png + + Alt text + fig1. caravel testbench environment (read lines are drivers ) Prerequisites From cb929cb3292b732f1101f5225fb609f95c1370b3 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 05:37:27 -0700 Subject: [PATCH 23/76] Fix housekeeping spi tests --- verilog/dv/cocotb/caravel.py | 6 +++--- .../housekeeping_regs_tests.py | 19 ++++++++++++++++--- .../wb_models/housekeepingWB/HK_regs.json | 6 +++--- 3 files changed, 22 insertions(+), 9 deletions(-) diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py index 8c4f36a4..1a63847d 100644 --- a/verilog/dv/cocotb/caravel.py +++ b/verilog/dv/cocotb/caravel.py @@ -315,16 +315,16 @@ class Caravel_env: data_bits = [] is_list = isinstance(bits, (list,tuple)) if is_list : - cocotb.log.info(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}') + cocotb.log.debug(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}') data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0] Date: Sun, 2 Oct 2022 05:40:44 -0700 Subject: [PATCH 24/76] delete uart_rx hex --- verilog/dv/cocotb/hex_files/uart_rx.hex | 82 ------------------------- 1 file changed, 82 deletions(-) delete mode 100755 verilog/dv/cocotb/hex_files/uart_rx.hex diff --git a/verilog/dv/cocotb/hex_files/uart_rx.hex b/verilog/dv/cocotb/hex_files/uart_rx.hex deleted file mode 100755 index d688718a..00000000 --- a/verilog/dv/cocotb/hex_files/uart_rx.hex +++ /dev/null @@ -1,82 +0,0 @@ -@00000000 -6F 00 00 0B 13 00 00 00 13 00 00 00 13 00 00 00 -13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 -23 2E 11 FE 23 2C 51 FE 23 2A 61 FE 23 28 71 FE -23 26 A1 FE 23 24 B1 FE 23 22 C1 FE 23 20 D1 FE -23 2E E1 FC 23 2C F1 FC 23 2A 01 FD 23 28 11 FD -23 26 C1 FD 23 24 D1 FD 23 22 E1 FD 23 20 F1 FD -13 01 01 FC EF 00 40 11 83 20 C1 03 83 22 81 03 -03 23 41 03 83 23 01 03 03 25 C1 02 83 25 81 02 -03 26 41 02 83 26 01 02 03 27 C1 01 83 27 81 01 -03 28 41 01 83 28 01 01 03 2E C1 00 83 2E 81 00 -03 2F 41 00 83 2F 01 00 13 01 01 04 73 00 20 30 -17 01 00 F1 13 01 01 75 17 05 00 00 13 05 85 F6 -73 10 55 30 13 05 00 00 93 05 00 00 17 06 00 00 -13 06 C6 41 63 0C B5 00 83 26 06 00 23 20 D5 00 -13 05 45 00 13 06 46 00 6F F0 DF FE 13 05 00 00 -93 05 80 00 63 08 B5 00 23 20 05 00 13 05 45 00 -6F F0 5F FF 37 15 00 00 13 05 05 88 73 10 45 30 -EF 00 40 2D 6F 00 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FF 23 26 81 00 13 04 01 01 -13 00 00 00 03 24 C1 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 81 00 13 04 01 02 23 26 A4 FE -83 27 C4 FE 73 90 07 BC 13 00 00 00 03 24 C1 01 -13 01 01 02 67 80 00 00 13 01 01 FF 23 26 11 00 -23 24 81 00 13 04 01 01 13 05 00 00 EF F0 5F FC -B7 37 00 F0 93 87 87 03 13 07 A0 00 23 A0 E7 00 -B7 37 00 F0 93 87 C7 03 37 07 02 00 23 A0 E7 00 -13 07 10 00 23 10 E0 00 13 00 00 00 83 20 C1 00 -03 24 81 00 13 01 01 01 67 80 00 00 13 01 01 FF -23 26 81 00 13 04 01 01 13 00 00 00 03 24 C1 00 -13 01 01 01 67 80 00 00 13 01 01 FF 23 26 81 00 -13 04 01 01 13 00 00 00 03 24 C1 00 13 01 01 01 -67 80 00 00 13 01 01 FE 23 2E 81 00 13 04 01 02 -23 26 A4 FE 83 27 C4 FE 83 A7 07 00 13 85 07 00 -03 24 C1 01 13 01 01 02 67 80 00 00 13 01 01 FF -23 26 11 00 23 24 81 00 13 04 01 01 B7 67 00 F0 -13 85 87 80 EF F0 1F FC 93 07 05 00 13 85 07 00 -83 20 C1 00 03 24 81 00 13 01 01 01 67 80 00 00 -13 01 01 FE 23 2E 11 00 23 2C 81 00 13 04 01 02 -93 07 05 00 A3 07 F4 FE 03 47 F4 FE 93 07 A0 00 -63 16 F7 00 13 05 D0 00 EF F0 9F FD 13 00 00 00 -B7 67 00 F0 93 87 47 80 03 A7 07 00 93 07 10 00 -E3 08 F7 FE B7 67 00 F0 93 87 07 80 03 47 F4 FE -23 A0 E7 00 13 00 00 00 83 20 C1 01 03 24 81 01 -13 01 01 02 67 80 00 00 13 01 01 FE 23 2E 11 00 -23 2C 81 00 13 04 01 02 23 26 A4 FE 6F 00 C0 01 -83 27 C4 FE 13 87 17 00 23 26 E4 FE 83 C7 07 00 -13 85 07 00 EF F0 DF F6 83 27 C4 FE 83 C7 07 00 -E3 90 07 FE 13 00 00 00 13 00 00 00 83 20 C1 01 -03 24 81 01 13 01 01 02 67 80 00 00 13 01 01 FD -23 26 11 02 23 24 81 02 13 04 01 03 23 2E A4 FC -13 00 00 00 EF F0 9F EF 13 07 05 00 93 07 10 00 -E3 0A F7 FE B7 67 00 F0 93 87 07 80 83 A7 07 00 -03 27 C4 FD 03 47 07 00 63 9C E7 00 B7 07 10 30 -93 87 87 FF 13 07 B0 01 23 A0 E7 00 6F 00 40 01 -B7 07 10 30 93 87 87 FF 13 07 E0 01 23 A0 E7 00 -B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE -B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE -B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE -B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE -B7 67 00 F0 93 87 07 80 83 A7 07 00 23 26 F4 FE -13 00 00 00 83 20 C1 02 03 24 81 02 13 01 01 03 -67 80 00 00 13 01 01 FF 23 26 11 00 23 24 81 00 -13 04 01 01 B7 47 00 F0 93 87 07 80 13 07 10 00 -23 A0 E7 00 B7 07 10 30 93 87 87 FF 23 A0 07 00 -B7 07 10 30 93 87 C7 FF 23 A0 07 00 B7 07 00 26 -93 87 C7 03 37 27 00 00 13 07 97 80 23 A0 E7 00 -B7 07 00 26 93 87 87 03 13 07 30 40 23 A0 E7 00 -B7 07 00 26 13 07 10 00 23 A0 E7 00 13 00 00 00 -B7 07 00 26 03 A7 07 00 93 07 10 00 E3 0A F7 FE -B7 67 00 F0 13 07 10 00 23 A0 E7 00 B7 07 10 30 -93 87 87 FF 13 07 A0 0A 23 A0 E7 00 B7 07 00 10 -13 85 87 4D EF F0 9F E9 B7 07 10 30 93 87 87 FF -13 07 B0 0B 23 A0 E7 00 B7 07 00 10 13 85 C7 4D -EF F0 DF E7 B7 07 10 30 93 87 87 FF 13 07 C0 0C -23 A0 E7 00 B7 07 00 10 13 85 07 4E EF F0 1F E6 -13 00 00 00 83 20 C1 00 03 24 81 00 13 01 01 01 -67 80 00 00 -@000004D4 -00 00 00 00 42 00 00 00 4D 00 00 00 41 00 00 00 -00 00 00 00 From bf9b363f68d7f316e342f82bfa096189dcf680d9 Mon Sep 17 00:00:00 2001 From: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Date: Sun, 2 Oct 2022 15:01:15 +0200 Subject: [PATCH 25/76] Update README.md --- verilog/dv/cocotb/README.md | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md index e6365258..9f94ab04 100644 --- a/verilog/dv/cocotb/README.md +++ b/verilog/dv/cocotb/README.md @@ -52,3 +52,30 @@ Tests Refer to [tests.json](tests.json) for tests list +Directories names fixed for now +=============== +>repo +>>caravel_mgmt_soc_litex/ + +>>caravel +>>>verilog +>>>>dv +>>>>cocotb + +cocotb directory tree +``` +├── caravel.py -> contains driving and mentoring functions for caravel interface +├── caravel_top.sv -> testbench top level +├── cpu.py -> contains driving and mentoring functions for wishbone when disable the cpu +├── hex_files -> folder that contains hex files +├── verify_cocotb.py -> script that run tests and regressions +├── sim -> directory get generate when run a test +│   └── -> tag of the run +│   ├── - -> test result directory contain all logs and wave related to the test +│   ├── command.log -> command use for this run +│   └── runs.log -> contains status of the run fails and passes tests +├── tests -> directory contains all the tests +├── tests.json -> test list have all the tests, regressions and contain small description about every test +└── wb_models -> contains checkers and models for some caravel blocks + +``` From 00a029fec3e5907b80d0986e385d49437faef2cb Mon Sep 17 00:00:00 2001 From: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Date: Sun, 2 Oct 2022 15:17:21 +0200 Subject: [PATCH 26/76] Update README.md --- verilog/dv/cocotb/README.md | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md index 9f94ab04..18e70f0c 100644 --- a/verilog/dv/cocotb/README.md +++ b/verilog/dv/cocotb/README.md @@ -13,6 +13,13 @@ Prerequisites - Docker: [Linux](https://hub.docker.com/search?q=&type=edition&offering=community&operating_system=linux&utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Windows](https://desktop.docker.com/win/main/amd64/Docker%20Desktop%20Installer.exe?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with Intel Chip](https://desktop.docker.com/mac/main/amd64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) || [Mac with M1 Chip](https://desktop.docker.com/mac/main/arm64/Docker.dmg?utm_source=docker&utm_medium=webreferral&utm_campaign=dd-smartbutton&utm_location=header) - Python 3.6+ with PIP - cocotb +``` + apt update && apt install python3 python3-pip + pip3 install cocotb + pip3 install cocotb_coverage + pip3 install coverage + pip3 install cocotb-bus +``` - iverilog or vcs run a test @@ -63,6 +70,7 @@ Directories names fixed for now >>>>cocotb cocotb directory tree +=============== ``` ├── caravel.py -> contains driving and mentoring functions for caravel interface ├── caravel_top.sv -> testbench top level From d8a4b812e88bae78db744a740f377b18146e8112 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 06:37:12 -0700 Subject: [PATCH 27/76] update script to make hex_files directory if not exists and to take argument -vcs if it will work in vcs mode --- verilog/dv/cocotb/verify_cocotb.py | 31 ++++++++++++++++++++++-------- 1 file changed, 23 insertions(+), 8 deletions(-) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index ac6e28b8..cac95b4f 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -11,6 +11,10 @@ from datetime import datetime import random from pathlib import Path + +iverilog = True +vcs = False + def go_up(path, n): for i in range(n): path = os.path.dirname(path) @@ -48,15 +52,19 @@ class RunTest: test_log=f"{self.sim_path}/{self.test_name}.log" self.full_terminal = open(test_log, "w") - # iverilog function - # def runTest(self): - # print(f"Start running test: {self.sim_type}-{self.test_name}") - # os.system(f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} ") - # self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") - # Path(f'{self.sim_path}/{self.passed}').touch() - - # vcs function def runTest(self): + if (iverilog):return self.runTest_iverilog() + elif(vcs): return self.runTest_vcs() + + # iverilog function + def runTest_iverilog(self): + print(f"Start running test: {self.sim_type}-{self.test_name}") + os.system(f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} ") + self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") + Path(f'{self.sim_path}/{self.passed}').touch() + + # vcs function + def runTest_vcs(self): print(f"Start running test: {self.sim_type}-{self.test_name}") dirs = f'+incdir+\\\"{go_up(self.cocotb_path,4)}\\\" ' macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS' @@ -82,6 +90,7 @@ class RunTest: self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() os.system("rm AN.DB/ cm.log results.xml ucli.key -r") + def find(self,name, path): for root, dirs, files in os.walk(path): if name in files: @@ -100,6 +109,8 @@ class RunTest: #open docker test_path =self.test_path() self.cd_make() + if not os.path.exists(f"{self.cocotb_path}/hex_files"): + os.makedirs(f"{self.cocotb_path}/hex_files") # Create a new hex_files directory because it does not exist elf_out = f"{self.cocotb_path}/hex_files/{self.test_name}.elf" c_file = f"{test_path}/{self.test_name}.c" hex_file = f"{self.cocotb_path}/hex_files/{self.test_name}.hex" @@ -293,7 +304,11 @@ parser.add_argument('-sim', nargs='+' ,help='Simulation type to be run RTL,GL&GL parser.add_argument('-testlist','-tl', help='path of testlist to be run ') parser.add_argument('-tag', help='provide tag of the run default would be regression name and if no regression is provided would be run___') parser.add_argument('-maxerr', help='max number of errors for every test before simulation breaks default = 3') +parser.add_argument('-vcs','-v',action='store_true', help='use vcs as compiler if not used iverilog would be used') args = parser.parse_args() +if (args.vcs) : + iverilog = False + vcs = True if args.sim == None: args.sim= ["RTL"] print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}") From 752d12928bda2141b3d08b6f1b376156cff8fff8 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 06:38:22 -0700 Subject: [PATCH 28/76] fix iverlog command for the new structure --- verilog/dv/cocotb/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/Makefile b/verilog/dv/cocotb/Makefile index f1d0b6b3..bc6a73be 100644 --- a/verilog/dv/cocotb/Makefile +++ b/verilog/dv/cocotb/Makefile @@ -46,7 +46,7 @@ cocotb: iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ -DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ - -f$(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv + -o sim_build/sim.vvp caravel_top.sv #GL # iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ # -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \ From f0494ef4b130ddd02681fe6e337332763c21b787 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 06:48:29 -0700 Subject: [PATCH 29/76] update make file to take user_project_wrapper file as input for iverilog --- verilog/dv/cocotb/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/Makefile b/verilog/dv/cocotb/Makefile index bc6a73be..5699749a 100644 --- a/verilog/dv/cocotb/Makefile +++ b/verilog/dv/cocotb/Makefile @@ -46,7 +46,7 @@ cocotb: iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ -DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \ -f$(VERILOG_PATH)/includes/includes.rtl.caravel \ - -o sim_build/sim.vvp caravel_top.sv + -o sim_build/sim.vvp $(CARAVEL_PATH)/rtl/__user_project_wrapper.v $(CARAVEL_PATH)/rtl/debug_regs.v caravel_top.sv #GL # iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ # -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \ From 9812aedaa13b731469eb98037284c11bf37afbd3 Mon Sep 17 00:00:00 2001 From: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com> Date: Sun, 2 Oct 2022 15:50:18 +0200 Subject: [PATCH 30/76] Update README.md --- verilog/dv/cocotb/README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md index 18e70f0c..689e9f2e 100644 --- a/verilog/dv/cocotb/README.md +++ b/verilog/dv/cocotb/README.md @@ -28,7 +28,6 @@ run a test Use script verify_cocotb.py ``` - -h, --help show this help message and exit -regression REGRESSION, -r REGRESSION @@ -51,6 +50,8 @@ run a test -maxerr MAXERR max number of errors for every test before simulation breaks default = 3 + -vcs, -v use vcs as compiler if not used iverilog would be used + ``` From 03527360e317cd10558b1829b82abae91a23488a Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 13:57:05 +0000 Subject: [PATCH 31/76] Apply automatic changes to Manifest and README.rst --- manifest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifest b/manifest index 97300198..dcaa49de 100644 --- a/manifest +++ b/manifest @@ -17,7 +17,7 @@ ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v 60d2384a91301fec5721953d87931193681822c4 verilog/rtl/gpio_control_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v -8dafb824eae7173e43f4e2f31c7470a6a1272c79 verilog/rtl/housekeeping.v +9ef209f70c9e73eac04890458a5c49b39347376e verilog/rtl/housekeeping.v 3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v 0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v 3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v From de2f4a37071668b52944192f9fbf4bff82fe8985 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 2 Oct 2022 08:38:00 -0700 Subject: [PATCH 32/76] Add bitbang_spi_i test --- verilog/dv/cocotb/tests.json | 7 ++ .../dv/cocotb/tests/bitbang/bitbang_spi_i.c | 64 +++++++++++++++++++ .../cocotb/tests/bitbang/bitbang_tests_cpu.py | 56 +++++++++++++++- 3 files changed, 125 insertions(+), 2 deletions(-) create mode 100644 verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index f2cd2ee0..30c81df6 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -71,6 +71,13 @@ "SW":true, "description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"} + ,"bitbang_spi_i" :{"level":0, + "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["push_gl","nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "SW":true, + "description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"} + ,"hk_regs_wr_wb" :{"level":0, "SW":false, "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c new file mode 100644 index 00000000..4c310438 --- /dev/null +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c @@ -0,0 +1,64 @@ +#include +#include + +// Empty C code + +void main() +{ + int i,j; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = 0x1803; + reg_mprj_io_36 = 0x1803; + reg_mprj_io_35 = 0x1803; + reg_mprj_io_34 = 0x1803; + reg_mprj_io_33 = 0x1803; + reg_mprj_io_32 = 0x1803; + reg_mprj_io_31 = 0x1803; + reg_mprj_io_30 = 0x1803; + reg_mprj_io_29 = 0x1803; + reg_mprj_io_28 = 0x1803; + reg_mprj_io_27 = 0x1803; + reg_mprj_io_26 = 0x1803; + reg_mprj_io_25 = 0x1803; + reg_mprj_io_24 = 0x1803; + reg_mprj_io_23 = 0x1803; + reg_mprj_io_22 = 0x1803; + reg_mprj_io_21 = 0x1803; + reg_mprj_io_20 = 0x1803; + reg_mprj_io_19 = 0x1803; + reg_mprj_io_18 = 0x1803; + reg_mprj_io_17 = 0x1803; + reg_mprj_io_16 = 0x1803; + reg_mprj_io_15 = 0x1803; + reg_mprj_io_14 = 0x1803; + reg_mprj_io_13 = 0x1803; + reg_mprj_io_12 = 0x1803; + reg_mprj_io_11 = 0x1803; + reg_mprj_io_10 = 0x1803; + reg_mprj_io_9 = 0x1803; + reg_mprj_io_8 = 0x1803; + reg_mprj_io_7 = 0x1803; + reg_mprj_io_6 = 0x1803; + reg_mprj_io_5 = 0x1803; + reg_mprj_io_4 = 0x1803; + reg_mprj_io_3 = 0x1803; + reg_mprj_io_2 = 0x1803; + reg_mprj_io_1 = 0x1803; + reg_mprj_io_0 = 0x1803; + + reg_debug_1 = 0xFF; // finish configuration + + reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal + while (reg_mprj_datal != 0x8F66FD7B); + reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal + while (reg_mprj_datal != 0xFFA88C5A); + reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal + while (reg_mprj_datal != 0xC9536346); + + reg_debug_2 = 0xFF; + +} + diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py index 4c910271..6d864ffc 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -200,7 +200,7 @@ async def bitbang_cpu_all_i(dut): -"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI.""" +"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as output.""" @cocotb.test() @repot_test async def bitbang_spi_o(dut): @@ -262,4 +262,56 @@ async def bitbang_spi_o(dut): i |= 0x80000000 - await ClockCycles(caravelEnv.clk, 10) \ No newline at end of file + await ClockCycles(caravelEnv.clk, 10) + + +"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI configure all gpio as input.""" +@cocotb.test() +@repot_test +async def bitbang_spi_i(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=56703) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + await wait_reg1(cpu,caravelEnv,0xFF) # wait for housekeeping registers configured + #Configure all as output except reg_mprj_io_3 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 18 and 19 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 17 and 20 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 16 and 21 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 15 and 22 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 14 and 23 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 13 and 24 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 12 and 25 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 11 and 26 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 10 and 27 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 9 and 28 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 8 and 29 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 7 and 30 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 6 and 31 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 5 and 32 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 4 and 33 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 3 and 34 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 2 and 35 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 1 and 36 + await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 0 and 37 + await load_spi(caravelEnv) # load + + await wait_reg1(cpu,caravelEnv,0xAA) + cocotb.log.info("[TEST] finish configuring using bitbang") + data_in = 0x8F66FD7B + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xBB) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + data_in = 0xFFA88C5A + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xCC) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + data_in = 0xC9536346 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + caravelEnv.drive_gpio_in((31,0),data_in) + + await wait_reg2(cpu,caravelEnv,0xFF) + cocotb.log.info(f"[TEST] finish") \ No newline at end of file From 55f6f56921ecd83519b34185f87b1a4367e3fb8c Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 3 Oct 2022 01:56:08 -0700 Subject: [PATCH 33/76] update verify_cocotb script to run iverilog inside a docker --- verilog/dv/cocotb/verify_cocotb.py | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index cac95b4f..25888ce0 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -58,8 +58,21 @@ class RunTest: # iverilog function def runTest_iverilog(self): + CARAVEL_ROOT = os.getenv('CARAVEL_ROOT') + CARAVEL_VERILOG_PATH = os.getenv('CARAVEL_VERILOG_PATH') + MCW_ROOT = os.getenv('MCW_ROOT') + VERILOG_PATH = os.getenv('VERILOG_PATH') + CARAVEL_PATH = os.getenv('CARAVEL_PATH') + USER_PROJECT_VERILOG = os.getenv('USER_PROJECT_VERILOG') + FIRMWARE_PATH = os.getenv('FIRMWARE_PATH') + RUNTAG = os.getenv('RUNTAG') + ERRORMAX = os.getenv('ERRORMAX') + PDK_ROOT = os.getenv('PDK_ROOT') + PDK = os.getenv('PDK') + env_vars = f"-e {CARAVEL_ROOT} -e CARAVEL_VERILOG_PATH={CARAVEL_VERILOG_PATH} -e MCW_ROOT={MCW_ROOT} -e VERILOG_PATH={VERILOG_PATH} -e CARAVEL_PATH={CARAVEL_PATH} -e USER_PROJECT_VERILOG={USER_PROJECT_VERILOG} -e FIRMWARE_PATH={FIRMWARE_PATH} -e RUNTAG={RUNTAG} -e ERRORMAX={ERRORMAX} -e PDK_ROOT={PDK_ROOT} -e PDK={PDK}" print(f"Start running test: {self.sim_type}-{self.test_name}") - os.system(f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} ") + command = f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} " + os.system(f"docker run -it {env_vars} -v /home:/home efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {command}'") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() @@ -89,7 +102,7 @@ class RunTest: os.system(f"vcs -cm line -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() - os.system("rm AN.DB/ cm.log results.xml ucli.key -r") + os.system("rm AN.DB/ cm.log results.xml ucli.key -rf") def find(self,name, path): for root, dirs, files in os.walk(path): @@ -288,7 +301,6 @@ class main(): os.environ["VERILOG_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog" os.environ["CARAVEL_PATH"] = f"{os.getenv('CARAVEL_VERILOG_PATH')}" os.environ["USER_PROJECT_VERILOG"] = f"{repo_path}/verilog/" - os.environ["GCC_PATH"] = "/ciic/tools/rv32/bin" os.environ["FIRMWARE_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog/dv/firmware" os.environ["RUNTAG"] = f"{self.TAG}" print(self.maxerr) From 79f26f6b384f837b86dbe6b0dba2a01b7af54eef Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 3 Oct 2022 05:36:36 -0700 Subject: [PATCH 34/76] add new test spi_master_rd --- verilog/dv/cocotb/caravel_tests.py | 1 + verilog/dv/cocotb/caravel_top.sv | 83 +++++++- verilog/dv/cocotb/tests.json | 7 + verilog/dv/cocotb/tests/spi_master/SPI_VIP.py | 87 +++++++++ .../dv/cocotb/tests/spi_master/spi_master.py | 55 ++++++ .../cocotb/tests/spi_master/spi_master_rd.c | 180 ++++++++++++++++++ verilog/dv/cocotb/tests/spi_master/test_data | 3 + 7 files changed, 415 insertions(+), 1 deletion(-) create mode 100644 verilog/dv/cocotb/tests/spi_master/SPI_VIP.py create mode 100644 verilog/dv/cocotb/tests/spi_master/spi_master.py create mode 100644 verilog/dv/cocotb/tests/spi_master/spi_master_rd.c create mode 100644 verilog/dv/cocotb/tests/spi_master/test_data diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index 8579ed11..80f4bf5c 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -36,6 +36,7 @@ from tests.gpio.gpio import * from tests.mgmt_gpio.mgmt_gpio import * from tests.timer.timer import * from tests.uart.uart import * +from tests.spi_master.spi_master import * diff --git a/verilog/dv/cocotb/caravel_top.sv b/verilog/dv/cocotb/caravel_top.sv index 47138185..581b09c8 100644 --- a/verilog/dv/cocotb/caravel_top.sv +++ b/verilog/dv/cocotb/caravel_top.sv @@ -104,7 +104,7 @@ caravel uut ( // make speical variables for the mprj input to assign the input without writing to the output gpios - // cocotb limitation #2587 + // cocotb limitation #2587: iverilog deal with array as 1 object not multiple of objects so can't write to only 1 element wire bin0; wire bin0_en; wire bin1; @@ -229,6 +229,87 @@ caravel uut ( assign mprj_io_tb[36] = (bin36_en) ? bin36 : 1'bz; assign mprj_io_tb[37] = (bin37_en) ? bin37 : 1'bz; + + + // to read from mprj array with iverilog + wire bin0_monitor; + wire bin1_monitor; + wire bin2_monitor; + wire bin3_monitor; + wire bin4_monitor; + wire bin5_monitor; + wire bin6_monitor; + wire bin7_monitor; + wire bin8_monitor; + wire bin9_monitor; + wire bin10_monitor; + wire bin11_monitor; + wire bin12_monitor; + wire bin13_monitor; + wire bin14_monitor; + wire bin15_monitor; + wire bin16_monitor; + wire bin17_monitor; + wire bin18_monitor; + wire bin19_monitor; + wire bin20_monitor; + wire bin21_monitor; + wire bin22_monitor; + wire bin23_monitor; + wire bin24_monitor; + wire bin25_monitor; + wire bin26_monitor; + wire bin27_monitor; + wire bin28_monitor; + wire bin29_monitor; + wire bin30_monitor; + wire bin31_monitor; + wire bin32_monitor; + wire bin33_monitor; + wire bin34_monitor; + wire bin35_monitor; + wire bin36_monitor; + wire bin37_monitor; + + assign bin0_monitor = mprj_io_tb[0]; + assign bin1_monitor = mprj_io_tb[1]; + assign bin2_monitor = mprj_io_tb[2]; + assign bin3_monitor = mprj_io_tb[3]; + assign bin4_monitor = mprj_io_tb[4]; + assign bin5_monitor = mprj_io_tb[5]; + assign bin6_monitor = mprj_io_tb[6]; + assign bin7_monitor = mprj_io_tb[7]; + assign bin8_monitor = mprj_io_tb[8]; + assign bin9_monitor = mprj_io_tb[9]; + assign bin10_monitor = mprj_io_tb[10]; + assign bin11_monitor = mprj_io_tb[11]; + assign bin12_monitor = mprj_io_tb[12]; + assign bin13_monitor = mprj_io_tb[13]; + assign bin14_monitor = mprj_io_tb[14]; + assign bin15_monitor = mprj_io_tb[15]; + assign bin16_monitor = mprj_io_tb[16]; + assign bin17_monitor = mprj_io_tb[17]; + assign bin18_monitor = mprj_io_tb[18]; + assign bin19_monitor = mprj_io_tb[19]; + assign bin20_monitor = mprj_io_tb[20]; + assign bin21_monitor = mprj_io_tb[21]; + assign bin22_monitor = mprj_io_tb[22]; + assign bin23_monitor = mprj_io_tb[23]; + assign bin24_monitor = mprj_io_tb[24]; + assign bin25_monitor = mprj_io_tb[25]; + assign bin26_monitor = mprj_io_tb[26]; + assign bin27_monitor = mprj_io_tb[27]; + assign bin28_monitor = mprj_io_tb[28]; + assign bin29_monitor = mprj_io_tb[29]; + assign bin30_monitor = mprj_io_tb[30]; + assign bin31_monitor = mprj_io_tb[31]; + assign bin32_monitor = mprj_io_tb[32]; + assign bin33_monitor = mprj_io_tb[33]; + assign bin34_monitor = mprj_io_tb[34]; + assign bin35_monitor = mprj_io_tb[35]; + assign bin36_monitor = mprj_io_tb[36]; + assign bin37_monitor = mprj_io_tb[37]; + endmodule // module that has all needed macros by cocotb diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 30c81df6..3af944fb 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -169,5 +169,12 @@ "GL":["nightly","weekly","tape_out"], "GL_SDF":["weekly","tape_out"], "description":"test uart reception"} + + ,"spi_master_rd" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"using SPI master for reading from external memory"} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/spi_master/SPI_VIP.py b/verilog/dv/cocotb/tests/spi_master/SPI_VIP.py new file mode 100644 index 00000000..e59c61dd --- /dev/null +++ b/verilog/dv/cocotb/tests/spi_master/SPI_VIP.py @@ -0,0 +1,87 @@ + + +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer +import cocotb.log +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * + + +#VIP for SPI +""" + support commands + 00000000 -> No operation + 00000011 -> Read in streaming mode +""" +async def SPI_VIP(csb,clk,SDI,SDO,mem): + while True: + await FallingEdge(csb) + cocotb.log.info (f"[SPI_VIP] CSB is asserted operation has begin ") + op = await cocotb.start(SPI_op(clk,SDI,SDO,mem)) + await csb_watcher(csb,op) + cocotb.log.info (f"[SPI_VIP] CSB is deasserted operation has been killed") + +# cocotb.scheduler.add +# watch the csb and when it's diable kill the SPI_op thread +async def csb_watcher(csb,thread): + cocotb.log.info (f"[csb_watcher] start CSB watching") + await RisingEdge(csb) + thread.kill() + +# detect command and address and apply the command +async def SPI_op(clk,SDI,SDO,mem): + address ='' + command ='' + await RisingEdge(clk) + # command + for i in range(8): + command = command + SDI.value.binstr + await RisingEdge(clk) + cocotb.log.info (f"[SPI_VIP] [SPI_op] command = {command}") + # address + address ='' + for i in range(8*3): # address is 3 parts each part are 8 bits + address = address + SDI.value.binstr + if i != 23: # skip last cycle wait + await RisingEdge(clk) + cocotb.log.info (f"[SPI_VIP] [SPI_op] address = {address}") + address = int(address,2) + #data + if command == "10000000" and False: # not sure about the read command + for i in range(8): + data_in += SDI + await RisingEdge(clk) + elif command == "00000011": + await FallingEdge(clk) + while True: + data = bin(mem[address])[2:].zfill(8) + for i in range(8): + SDO[0].value = 1 # enable + SDO[1].value = int(data[i],2) # bin + cocotb.log.debug (f"[SPI_VIP] [SPI_op] SDO = {data[i]} ") + await FallingEdge(clk) + SDO[0].value = 0 # enable + + cocotb.log.info (f"[SPI_VIP] [SPI_op] finish reading address {hex(address) } data = {hex(int(data,2))} ") + address +=1 + + +def read_mem (file_name): + with open(file_name, 'r') as file: + lines = file.readlines() + mem = dict() + for line in lines: + if line[0] == "@": + address = int(line[1:],16) + cocotb.log.debug (f" found line = {line} address = {hex(address)} ") + else: + line_no_space = line.strip().replace(' ','') + for i in range (0,len(line_no_space),2): + cocotb.log.debug (f" i = {i} ine_no_space[{i}:{i+2}] = {line_no_space[i:i+2]} address = {hex(address)}") + mem[address] = int(line_no_space[i:i+2],16) + address +=1 + cocotb.log.debug (f" found line = {line} line_no_space = {line_no_space} size = {len(line_no_space)}") + cocotb.log.info (f"[read_mem] SPI mem = {mem}") + return mem + diff --git a/verilog/dv/cocotb/tests/spi_master/spi_master.py b/verilog/dv/cocotb/tests/spi_master/spi_master.py new file mode 100644 index 00000000..cc9925c3 --- /dev/null +++ b/verilog/dv/cocotb/tests/spi_master/spi_master.py @@ -0,0 +1,55 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP +from caravel import GPIO_MODE + + +bit_time_ns = 0 +reg = Regs() + + +@cocotb.test() +@repot_test +async def spi_master_rd(dut): + """ the firmware is configured to always send clk to spi so I can't insert alot of logics reading values + + the method of testing used can't work if 2 addresses Consecutive have the same address + """ + + caravelEnv,clock = await test_configure(dut,timeout_cycles=214842) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info (f"[TEST] start spi_master_rd test") + file_name = f"{os.getenv('CARAVEL_VERILOG_PATH')}/dv/cocotb/tests/spi_master/test_data" + mem = read_mem(file_name) + await cocotb.start(SPI_VIP(dut.bin33_monitor,dut.bin32_monitor,dut.bin35_monitor,(dut.bin34_en,dut.bin34),mem)) # fork for SPI + + addresses_to_read = (0x04,0x05,0x06,0x8,0x9,0xa,0xb,0xc,0xd,0xe,0xf) # the addresses that the firmware read from mem file + await wait_reg2(cpu,caravelEnv,0XAA) + cocotb.log.info (f"[TEST] GPIO configuration finished ans start reading from mememory") + val =0 + for address in addresses_to_read: + # await wait_reg2(cpu,caravelEnv,0x55) # value is ready to be read + #wait until value change + while True: + if val != cpu.read_debug_reg1(): + break + await ClockCycles(caravelEnv.clk,100) + + expected_val = mem[address] + val = cpu.read_debug_reg1() + if val == expected_val: + cocotb.log.info(f"[TEST] correct read of value {hex(val)} from address {hex(address)} ") + else: + cocotb.log.error(f"[TEST] wrong read from address {hex(address)} expected value = {hex(expected_val)} value {hex(val)} ") + # cpu.write_debug_reg2_backdoor(0xCC) + + await ClockCycles(caravelEnv.clk,1000) + diff --git a/verilog/dv/cocotb/tests/spi_master/spi_master_rd.c b/verilog/dv/cocotb/tests/spi_master/spi_master_rd.c new file mode 100644 index 00000000..ed857583 --- /dev/null +++ b/verilog/dv/cocotb/tests/spi_master/spi_master_rd.c @@ -0,0 +1,180 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +// -------------------------------------------------------- + +/* + * SPI master Test + * - Enables SPI master + * - Uses SPI master to talk to external SPI module + */ + + void spi_write(char c) +{ + reg_spimaster_wdata = (unsigned long) c; +// reg_spimaster_wdata = c; +// spi_master_control_length_write(8); +// spi_master_control_start_write(1); +// reg_spimaster_control = 0x0800; + reg_spimaster_control = 0x0801; +} + char spi_read() +{ +// reg_spimaster_wdata = c; +// spi_master_control_length_write(8); +// spi_master_control_start_write(1); +// reg_spimaster_control = 0x0800; +// spi_write(0x00); +// reg_spimaster_rdata = 0x00; +// reg_spimaster_control = 0x0801; + spi_write(0x00); + while (reg_spimaster_status != 1); + return reg_spimaster_rdata; +} + +void main() +{ + int i; + uint32_t value; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + // For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4 + // should be outputs. + + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; // SDO + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; // CSB + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; // SCK + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_debug_2 =0xAA; + + reg_spi_enable = 1; + + + // For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4 + // should be outputs. + + // Start test + + // Enable SPI master + // SPI master configuration bits: + // bits 7-0: Clock prescaler value (default 2) + // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first) + // bit 9: CSB sense (0 = inverted, 1 = noninverted) + // bit 10: SCK sense (0 = noninverted, 1 = inverted) + // bit 11: mode (0 = read/write opposite edges, 1 = same edges) + // bit 12: stream (1 = CSB ends transmission) + // bit 13: enable (1 = enabled) + // bit 14: IRQ enable (1 = enabled) + // bit 15: (unused) + + + reg_spimaster_cs = 0x10001; // sel=0, manual CS + + spi_write(0x03); // Write 0x03 (read mode) + spi_write(0x00); // Write 0x00 (start address high byte) + spi_write(0x00); // Write 0x00 (start address middle byte) + spi_write(0x04); // Write 0x04 (start address low byte) + + value = spi_read(); // 0x93 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + + value = spi_read(); // 0x01 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + value = spi_read(); // 0x00 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + reg_spimaster_cs = 0x0000; // release CS + reg_spimaster_cs = 0x10001; // sel=0, manual CS + + spi_write(0x03); // Write 0x03 (read mode) + spi_write(0x00); // Write 0x00 (start address high byte) + spi_write(0x00); // Write 0x00 (start address middle byte) + spi_write(0x08); // Write 0x08 (start address low byte) + + value = spi_read(); // 0x13 + if (value == 0x13) + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + value = spi_read(); // 0x02 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + reg_spimaster_cs = 0x0000; // release CS + reg_spimaster_cs = 0x10001; // sel=0, manual CS + + spi_write(0x03); // Write 0x03 (read mode) + spi_write(0x00); // Write 0x00 (start address high byte) + spi_write(0x00); // Write 0x00 (start address middle byte) + spi_write(0x0a); // Write 0x0a (start address low byte) + + value = spi_read(); // 0x63 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + value = spi_read(); // 0x57 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + value = spi_read(); // 0xb5 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + value = spi_read(); // 0x00 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + value = spi_read();// 0x23 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + + value = spi_read(); // 0x20 + reg_debug_1 = value; + // reg_debug_2 =0x55; // value is ready to be read + // while (reg_debug_2 != 0xCC) // testbench has read the value + + reg_spimaster_cs = 0x0000; // release CS + reg_spimaster_cs = 0x10001; // sel=0, manual CS + +} + diff --git a/verilog/dv/cocotb/tests/spi_master/test_data b/verilog/dv/cocotb/tests/spi_master/test_data new file mode 100644 index 00000000..287a0cf9 --- /dev/null +++ b/verilog/dv/cocotb/tests/spi_master/test_data @@ -0,0 +1,3 @@ +@00000000 +6F 00 00 0B 93 01 00 00 13 02 63 57 b5 00 23 20 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 From e945c3b8825bec3e517634fbfc095808bf1f313d Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 3 Oct 2022 05:45:55 -0700 Subject: [PATCH 35/76] fix bug at mgmt_gpio_out by increasing the number of phases --- verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py index 9f513e67..83ba1478 100644 --- a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py @@ -19,7 +19,7 @@ async def mgmt_gpio_out(dut): cpu.cpu_force_reset() cpu.cpu_release_reset() cocotb.log.info(f"[TEST] Start mgmt_gpio_out test") - phases_fails = 2 + phases_fails = 3 phases_passes = 0 reg1 =0 # buffer reg2 = 0 #buffer @@ -50,6 +50,7 @@ async def mgmt_gpio_out(dut): await ClockCycles(caravelEnv.clk,10) cocotb.log.info("[TEST] passing sending {reg1} blinks ") phases_fails -=1 + phases_passes +=1 await ClockCycles(caravelEnv.clk,10) if phases_fails != 0: From e81416bb511fc500b9706e61797b50cbfa5a9471 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 3 Oct 2022 08:56:46 -0700 Subject: [PATCH 36/76] add new test mgmt_gpio_bidir --- verilog/dv/cocotb/tests.json | 6 ++ .../dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py | 62 ++++++++++++++++++- .../cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c | 61 ++++++++++++++++++ 3 files changed, 128 insertions(+), 1 deletion(-) create mode 100644 verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 3af944fb..7a8022b1 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -145,6 +145,12 @@ "GL":["nightly","weekly","tape_out"], "GL_SDF":["weekly","tape_out"], "description":"tests blinking of mgmt gpio bit as an output"} + ,"mgmt_gpio_bidir" :{"level":0, + "SW":true, + "RTL":["setup","nightly","weekly","tape_out"], + "GL":["nightly","weekly","tape_out"], + "GL_SDF":["weekly","tape_out"], + "description":"send random number of blinks through mgmt_gpio and expect to recieve the same number back "} ,"timer0_oneshot" :{"level":0, "SW":true, "RTL":["setup","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py index 83ba1478..8ddcc7bd 100644 --- a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py @@ -1,4 +1,5 @@ import random +import re import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log @@ -103,4 +104,63 @@ async def mgmt_gpio_in(dut): if phases_fails != 0: cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") else: - cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") \ No newline at end of file + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + + + + +@cocotb.test() +@repot_test +async def mgmt_gpio_bidir(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=243058) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start mgmt_gpio_in test") + phases_fails = 3 + phases_passes = 0 + pass_list = (0x1B,0x2B,0xFF) + fail_list = tuple([0xEE]) + reg2 = 0 #buffer + + await wait_reg1(cpu,caravelEnv,0XAA) + num_blinks = random.randint(1, 20) + cocotb.log.info (f"[TEST] start send {num_blinks} blinks") + for i in range(num_blinks): + if i == num_blinks-1: #last iteration + # await cpu.drive_data2address(reg.get_addr('reg_debug_1'),0xFF) + cpu.write_debug_reg1_backdoor(0xFF) + caravelEnv.drive_mgmt_gpio(1) + await ClockCycles(caravelEnv.clk,4000) + caravelEnv.drive_mgmt_gpio(0) + await ClockCycles(caravelEnv.clk,4000) + cocotb.log.info(f"[TEST] finish sending {num_blinks} blinks ") + + cocotb.log.info(f"[TEST] waiting for {num_blinks} blinks ") + recieved_blinks = 0 + while True: + cocotb.log.info(f"[TEST] here 0 ") + if cpu.read_debug_reg2() == 0xFF: #test finish + break + while (True): + if caravelEnv.monitor_mgmt_gpio() == 0: + break + if cpu.read_debug_reg2() == 0xFF: #test finish + break + cocotb.log.info(f"[TEST] here 1 ") + await ClockCycles(caravelEnv.clk,10) + while (True): + if caravelEnv.monitor_mgmt_gpio() == 1: + recieved_blinks +=1 + break + if cpu.read_debug_reg2() == 0xFF: #test finish + break + cocotb.log.info(f"[TEST] here 2 ") + await ClockCycles(caravelEnv.clk,10) + await ClockCycles(caravelEnv.clk,1) + + + if recieved_blinks == num_blinks: + cocotb.log.info(f"[TEST] recieved the correct number of blinks {num_blinks}") + else: + cocotb.log.error(f"[TEST] recieved the incorrect number of blinks recieved = {recieved_blinks} expected = {num_blinks}") diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c new file mode 100644 index 00000000..001a5625 --- /dev/null +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio_bidir.c @@ -0,0 +1,61 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +// -------------------------------------------------------- + +/* + * Management SoC GPIO Pin Test + * Tests writing to the GPIO pin. + */ + +void main() +{ + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_gpio_mode1 = 1; + reg_gpio_mode0 = 0; // for full swing + + reg_gpio_ien = 1; + reg_gpio_oe = 0; + int num_blinks = 0; + reg_debug_1 = 0xAA; // start of the test + int z = reg_debug_1; + while (true) { + // reg_debug_2 = z; + // z= reg_debug_1; + while(reg_gpio_in == 0); + while(reg_gpio_in == 1); + num_blinks++; + if (reg_debug_1 == 0xFF) + break; + } + reg_gpio_ien = 0; + reg_gpio_oe = 1; + for (int i = 0; i < num_blinks; i++) { + /* Fast blink for simulation */ + reg_gpio_out = 1; + reg_gpio_out = 0; + } + reg_debug_2 = 0xFF; //finish test + + +} + From c4859c878998ef4291f5fbf5bf8da1ad41a42ed0 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 3 Oct 2022 08:57:23 -0700 Subject: [PATCH 37/76] fix bug at reading from debug registers --- verilog/rtl/debug_regs.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/rtl/debug_regs.v b/verilog/rtl/debug_regs.v index df1aaa13..85043928 100644 --- a/verilog/rtl/debug_regs.v +++ b/verilog/rtl/debug_regs.v @@ -34,7 +34,7 @@ module debug_regs ( debug_reg_2[31:24] <= (wbs_adr_i[2] && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_2[31:24]; wbs_ack_o <= 1; end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o) begin // read - wbs_dat_o <= (wbs_adr_i[3]) ? debug_reg_2 : debug_reg_1; + wbs_dat_o <= (wbs_adr_i[2]) ? debug_reg_2 : debug_reg_1; wbs_ack_o <= 1; end else begin wbs_ack_o <= 0; From 37244a2514a97ec7d57e4a6dbe58c1db188a0edf Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 3 Oct 2022 09:01:08 -0700 Subject: [PATCH 38/76] add 3 regressions r_rtl , r_gl,r_sdf --- verilog/dv/cocotb/tests.json | 160 +++++++++++++++++------------------ 1 file changed, 80 insertions(+), 80 deletions(-) diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 7a8022b1..78b0b584 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -5,96 +5,96 @@ ,"bitbang_no_cpu_all_o" :{"level":0, "SW":false, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], "GL":[], "GL_SDF":[], "description":"test disable CPU and control the wishbone to configure gpio[4:37] as mgmt output using bitbang and check them"} ,"bitbang_cpu_all_o" :{"level":0, "SW":true, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt output using bitbang and check them"} ,"gpio_all_o" :{"level":0, "SW":true, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt output using automatic approach firmware and check them"} ,"gpio_all_i" :{"level":0, "SW":true, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt output using automatic approach firmware and check them"} ,"bitbang_cpu_all_10" :{"level":0, "SW":true, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"shift all the register with 10"} ,"bitbang_cpu_all_01" :{"level":0, "SW":true, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"shift all the register with 01"} ,"bitbang_cpu_all_1100" :{"level":0, "SW":true, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"shift all the register with 1100"} ,"bitbang_cpu_all_0011" :{"level":0, "SW":true, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"shift all the register with 0011"} ,"bitbang_no_cpu_all_i" :{"level":0, "SW":false, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], "GL":[], "GL_SDF":[], "description":"test disable CPU and control the wishbone to configure gpio[0:31] as mgmt input using bitbang and check them"} ,"bitbang_cpu_all_i" :{"level":0, "SW":true, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":" configure gpio[0:37] as mgmt input using bitbang and check them"} ,"bitbang_spi_o" :{"level":0, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "SW":true, "description":"Same as bitbang_cpu_all but configure the gpio using the SPI not the firmware"} ,"bitbang_spi_i" :{"level":0, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "SW":true, "description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"} ,"hk_regs_wr_wb" :{"level":0, "SW":false, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"write then read (the written value) from random housekeeping registers through the firmware but without using CPU, the SPI and system regs can't be read using firmware so the test only GPIO regs inside housekeeping "} ,"hk_regs_wr_spi" :{"level":0, "SW":false, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"write then read(the written value) from random housekeeping registers through the SPI housekeeping"} ,"hk_regs_rst_spi" :{"level":0, "SW":false, - "RTL":["setup","push","push_gl","nightly","weekly","tape_out"], - "GL":["push_gl","nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"check reset value of house keeping registers by reading them trough the spi housekeeping"} ,"helloWorld" :{"level":3, "SW":false, @@ -105,82 +105,82 @@ ,"cpu_stress" :{"level":2, "SW":true, - "RTL":["nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"stress the cpu with heavy processing"} ,"mem_stress" :{"level":2, "SW":true, - "RTL":["nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"Memory stress tests write and read from 800 bytes 200 words and 400 half words"} ,"IRQ_external" :{"level":2, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"test external interrupt by mprj 7"} ,"IRQ_timer" :{"level":2, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"test timer0 interrupt"} ,"IRQ_uart" :{"level":2, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"test timer0 interrupt"} ,"mgmt_gpio_out" :{"level":0, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"tests blinking of mgmt gpio bit as an output"} ,"mgmt_gpio_in" :{"level":0, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"tests blinking of mgmt gpio bit as an output"} ,"mgmt_gpio_bidir" :{"level":0, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"send random number of blinks through mgmt_gpio and expect to recieve the same number back "} ,"timer0_oneshot" :{"level":0, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"check timer0 oneshot mode"} ,"timer0_periodic" :{"level":0, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"check timer0 periodic mode"} ,"uart_tx" :{"level":0, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"test uart transmit"} ,"uart_rx" :{"level":0, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"test uart reception"} ,"spi_master_rd" :{"level":0, "SW":true, - "RTL":["setup","nightly","weekly","tape_out"], - "GL":["nightly","weekly","tape_out"], - "GL_SDF":["weekly","tape_out"], + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], "description":"using SPI master for reading from external memory"} } } \ No newline at end of file From 5788214f6dddbe7828984d9aecd55e24ab788d1a Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 3 Oct 2022 16:02:59 +0000 Subject: [PATCH 39/76] Apply automatic changes to Manifest and README.rst --- manifest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifest b/manifest index dcaa49de..c6c17d1e 100644 --- a/manifest +++ b/manifest @@ -11,7 +11,7 @@ cb320bf7e981979c4e823270d823395ea609c77e verilog/rtl/caravel.v d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v 54de41c59139783d39654e1f0a86e2880cb7b076 verilog/rtl/chip_io_alt.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v -f03d9a8496376951855b507cfbcd4afe104e36ac verilog/rtl/debug_regs.v +86cc0b0e4c2ef4ffb239496943cfff2ff7185b4d verilog/rtl/debug_regs.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v 60d2384a91301fec5721953d87931193681822c4 verilog/rtl/gpio_control_block.v From ef9c2e408b220741f358d8481ed3e1a7469c2a78 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 3 Oct 2022 09:49:51 -0700 Subject: [PATCH 40/76] fix bug at IRQ_uart --- verilog/dv/cocotb/tests/irq/IRQ_uart.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/verilog/dv/cocotb/tests/irq/IRQ_uart.c b/verilog/dv/cocotb/tests/irq/IRQ_uart.c index dfd10990..db4136c3 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_uart.c +++ b/verilog/dv/cocotb/tests/irq/IRQ_uart.c @@ -28,7 +28,7 @@ extern uint16_t flag; void main(){ - + flag = 0; reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 reg_debug_1 = 0x0; reg_debug_2 = 0x0; @@ -47,7 +47,6 @@ void main(){ irq_setmask(irq_getmask() | (1 << UART_INTERRUPT)); - flag = 0; reg_debug_2 = 0xAA; //start sending data through the uart print("M"); From 11330823b74e4daf1854f16c123a7dba9855bef6 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 4 Oct 2022 03:24:15 -0700 Subject: [PATCH 41/76] Add hk_regs_wr_wb_cpu test --- verilog/dv/cocotb/tests.json | 7 +- .../housekeeping_regs/hk_regs_wr_wb_cpu.c | 249 ++++++++++++++++++ .../housekeeping_regs_tests.py | 21 ++ verilog/dv/cocotb/tests/spi_master/SPI_VIP.py | 1 - 4 files changed, 276 insertions(+), 2 deletions(-) create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 78b0b584..ed59c687 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -77,7 +77,12 @@ "GL_SDF":["r_sdf","weekly","tape_out"], "SW":true, "description":"Same as bitbang_cpu_all_i but configure the gpio using the SPI not the firmware"} - + ,"hk_regs_wr_wb_cpu" :{"level":0, + "SW":false, + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"bit bash test for housekeeping registers"} ,"hk_regs_wr_wb" :{"level":0, "SW":false, "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c new file mode 100644 index 00000000..a545a74f --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c @@ -0,0 +1,249 @@ +#include +#include + + +// access all housekeeping registers that can be access through firmware and change it's value +void main(){ + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + // write 1 ones to all registers + reg_mprj_io_0 = 0x1FFF; + reg_mprj_io_1 = 0x1FFF; + reg_mprj_io_2 = 0x1FFF; + reg_mprj_io_3 = 0x1FFF; + reg_mprj_io_4 = 0x1FFF; + reg_mprj_io_5 = 0x1FFF; + reg_mprj_io_6 = 0x1FFF; + reg_mprj_io_7 = 0x1FFF; + reg_mprj_io_8 = 0x1FFF; + reg_mprj_io_9 = 0x1FFF; + reg_mprj_io_10 = 0x1FFF; + reg_mprj_io_11 = 0x1FFF; + reg_mprj_io_12 = 0x1FFF; + reg_mprj_io_13 = 0x1FFF; + reg_mprj_io_14 = 0x1FFF; + reg_mprj_io_15 = 0x1FFF; + reg_mprj_io_16 = 0x1FFF; + reg_mprj_io_17 = 0x1FFF; + reg_mprj_io_18 = 0x1FFF; + reg_mprj_io_19 = 0x1FFF; + reg_mprj_io_20 = 0x1FFF; + reg_mprj_io_21 = 0x1FFF; + reg_mprj_io_22 = 0x1FFF; + reg_mprj_io_23 = 0x1FFF; + reg_mprj_io_24 = 0x1FFF; + reg_mprj_io_25 = 0x1FFF; + reg_mprj_io_26 = 0x1FFF; + reg_mprj_io_27 = 0x1FFF; + reg_mprj_io_28 = 0x1FFF; + reg_mprj_io_29 = 0x1FFF; + reg_mprj_io_30 = 0x1FFF; + reg_mprj_io_31 = 0x1FFF; + reg_mprj_io_32 = 0x1FFF; + reg_mprj_io_33 = 0x1FFF; + reg_mprj_io_34 = 0x1FFF; + reg_mprj_io_35 = 0x1FFF; + reg_mprj_io_36 = 0x1FFF; + reg_mprj_io_37 = 0x1FFF; + + // read ones that has been written + if (reg_mprj_io_0 != 0x1FFF) + reg_debug_1 =0x1; + if (reg_mprj_io_1 != 0x1FFF) + reg_debug_1 =0x2; + if (reg_mprj_io_2 != 0x1FFF) + reg_debug_1 =0x3; + if (reg_mprj_io_3 != 0x1FFF) + reg_debug_1 =0x4; + if (reg_mprj_io_4 != 0x1FFF) + reg_debug_1 =0x5; + if (reg_mprj_io_5 != 0x1FFF) + reg_debug_1 =0x6; + if (reg_mprj_io_6 != 0x1FFF) + reg_debug_1 =0x7; + if (reg_mprj_io_7 != 0x1FFF) + reg_debug_1 =0x8; + if (reg_mprj_io_8 != 0x1FFF) + reg_debug_1 =0x9; + if (reg_mprj_io_9 != 0x1FFF) + reg_debug_1 =0xa; + if (reg_mprj_io_10 != 0x1FFF) + reg_debug_1 =0xb; + if (reg_mprj_io_11 != 0x1FFF) + reg_debug_1 =0xc; + if (reg_mprj_io_12 != 0x1FFF) + reg_debug_1 =0xd; + if (reg_mprj_io_13 != 0x1FFF) + reg_debug_1 =0xe; + if (reg_mprj_io_14 != 0x1FFF) + reg_debug_1 =0xf; + if (reg_mprj_io_15 != 0x1FFF) + reg_debug_1 =0x10; + if (reg_mprj_io_16 != 0x1FFF) + reg_debug_1 =0x11; + if (reg_mprj_io_17 != 0x1FFF) + reg_debug_1 =0x12; + if (reg_mprj_io_18 != 0x1FFF) + reg_debug_1 =0x13; + if (reg_mprj_io_19 != 0x1FFF) + reg_debug_1 =0x14; + if (reg_mprj_io_20 != 0x1FFF) + reg_debug_1 =0x15; + if (reg_mprj_io_21 != 0x1FFF) + reg_debug_1 =0x16; + if (reg_mprj_io_22 != 0x1FFF) + reg_debug_1 =0x17; + if (reg_mprj_io_23 != 0x1FFF) + reg_debug_1 =0x18; + if (reg_mprj_io_24 != 0x1FFF) + reg_debug_1 =0x19; + if (reg_mprj_io_25 != 0x1FFF) + reg_debug_1 =0x1a; + if (reg_mprj_io_26 != 0x1FFF) + reg_debug_1 =0x1b; + if (reg_mprj_io_27 != 0x1FFF) + reg_debug_1 =0x1c; + if (reg_mprj_io_28 != 0x1FFF) + reg_debug_1 =0x1d; + if (reg_mprj_io_29 != 0x1FFF) + reg_debug_1 =0x1e; + if (reg_mprj_io_30 != 0x1FFF) + reg_debug_1 =0x1f; + if (reg_mprj_io_31 != 0x1FFF) + reg_debug_1 =0x20; + if (reg_mprj_io_32 != 0x1FFF) + reg_debug_1 =0x21; + if (reg_mprj_io_33 != 0x1FFF) + reg_debug_1 =0x22; + if (reg_mprj_io_34 != 0x1FFF) + reg_debug_1 =0x23; + if (reg_mprj_io_35 != 0x1FFF) + reg_debug_1 =0x24; + if (reg_mprj_io_36 != 0x1FFF) + reg_debug_1 =0x25; + if (reg_mprj_io_37 != 0x1FFF) + reg_debug_1 =0x26; + + + // // write zeros to all registers + reg_mprj_io_0 = 0x0; + reg_mprj_io_1 = 0x0; + reg_mprj_io_2 = 0x0; + reg_mprj_io_3 = 0x0; + reg_mprj_io_4 = 0x0; + reg_mprj_io_5 = 0x0; + reg_mprj_io_6 = 0x0; + reg_mprj_io_7 = 0x0; + reg_mprj_io_8 = 0x0; + reg_mprj_io_9 = 0x0; + reg_mprj_io_10 = 0x0; + reg_mprj_io_11 = 0x0; + reg_mprj_io_12 = 0x0; + reg_mprj_io_13 = 0x0; + reg_mprj_io_14 = 0x0; + reg_mprj_io_15 = 0x0; + reg_mprj_io_16 = 0x0; + reg_mprj_io_17 = 0x0; + reg_mprj_io_18 = 0x0; + reg_mprj_io_19 = 0x0; + reg_mprj_io_20 = 0x0; + reg_mprj_io_21 = 0x0; + reg_mprj_io_22 = 0x0; + reg_mprj_io_23 = 0x0; + reg_mprj_io_24 = 0x0; + reg_mprj_io_25 = 0x0; + reg_mprj_io_26 = 0x0; + reg_mprj_io_27 = 0x0; + reg_mprj_io_28 = 0x0; + reg_mprj_io_29 = 0x0; + reg_mprj_io_30 = 0x0; + reg_mprj_io_31 = 0x0; + reg_mprj_io_32 = 0x0; + reg_mprj_io_33 = 0x0; + reg_mprj_io_34 = 0x0; + reg_mprj_io_35 = 0x0; + reg_mprj_io_36 = 0x0; + reg_mprj_io_37 = 0x0; + + // // read zeros that has been written + if (reg_mprj_io_0 != 0x0) + reg_debug_2 =0x1; + if (reg_mprj_io_1 != 0x0) + reg_debug_2 =0x2; + if (reg_mprj_io_2 != 0x0) + reg_debug_2 =0x3; + if (reg_mprj_io_3 != 0x0) + reg_debug_2 =0x4; + if (reg_mprj_io_4 != 0x0) + reg_debug_2 =0x5; + if (reg_mprj_io_5 != 0x0) + reg_debug_2 =0x6; + if (reg_mprj_io_6 != 0x0) + reg_debug_2 =0x7; + if (reg_mprj_io_7 != 0x0) + reg_debug_2 =0x8; + if (reg_mprj_io_8 != 0x0) + reg_debug_2 =0x9; + if (reg_mprj_io_9 != 0x0) + reg_debug_2 =0xa; + if (reg_mprj_io_10 != 0x0) + reg_debug_2 =0xb; + if (reg_mprj_io_11 != 0x0) + reg_debug_2 =0xc; + if (reg_mprj_io_12 != 0x0) + reg_debug_2 =0xd; + if (reg_mprj_io_13 != 0x0) + reg_debug_2 =0xe; + if (reg_mprj_io_14 != 0x0) + reg_debug_2 =0xf; + if (reg_mprj_io_15 != 0x0) + reg_debug_2 =0x10; + if (reg_mprj_io_16 != 0x0) + reg_debug_2 =0x11; + if (reg_mprj_io_17 != 0x0) + reg_debug_2 =0x12; + if (reg_mprj_io_18 != 0x0) + reg_debug_2 =0x13; + if (reg_mprj_io_19 != 0x0) + reg_debug_2 =0x14; + if (reg_mprj_io_20 != 0x0) + reg_debug_2 =0x15; + if (reg_mprj_io_21 != 0x0) + reg_debug_2 =0x16; + if (reg_mprj_io_22 != 0x0) + reg_debug_2 =0x17; + if (reg_mprj_io_23 != 0x0) + reg_debug_2 =0x18; + if (reg_mprj_io_24 != 0x0) + reg_debug_2 =0x19; + if (reg_mprj_io_25 != 0x0) + reg_debug_2 =0x1a; + if (reg_mprj_io_26 != 0x0) + reg_debug_2 =0x1b; + if (reg_mprj_io_27 != 0x0) + reg_debug_2 =0x1c; + if (reg_mprj_io_28 != 0x0) + reg_debug_2 =0x1d; + if (reg_mprj_io_29 != 0x0) + reg_debug_2 =0x1e; + if (reg_mprj_io_30 != 0x0) + reg_debug_2 =0x1f; + if (reg_mprj_io_31 != 0x0) + reg_debug_2 =0x20; + if (reg_mprj_io_32 != 0x0) + reg_debug_2 =0x21; + if (reg_mprj_io_33 != 0x0) + reg_debug_2 =0x22; + if (reg_mprj_io_34 != 0x0) + reg_debug_2 =0x23; + if (reg_mprj_io_35 != 0x0) + reg_debug_2 =0x24; + if (reg_mprj_io_36 != 0x0) + reg_debug_2 =0x25; + if (reg_mprj_io_37 != 0x0) + reg_debug_2 =0x26; + + reg_debug_2 = 0xFF; +} + diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py index 1c2f80fb..8bbc1c37 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -66,6 +66,27 @@ async def hk_regs_wr_wb(dut): if data_out != int(data_exp,2): cocotb.log.error(f"[TEST] wrong read from {regs[mem][key][0][0]} address {hex(address)} retuned val= {bin(data_out)[2:].zfill(bits_num)} expected = {data_exp}") else: cocotb.log.info(f"[TEST] read the right value {hex(data_out)} from {regs[mem][key][0][0]} address {hex(address)} ") +'''randomly write then read housekeeping regs through wishbone''' +@cocotb.test() +@repot_test +async def hk_regs_wr_wb_cpu(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=157521,num_error=INFINITY) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + reg1 =0 # buffer + reg2 =0 + while True: + if cpu.read_debug_reg2() == 0xFF: # test finish + break + if reg1 != cpu.read_debug_reg1(): + reg1 = cpu.read_debug_reg1() + cocotb.log.error(f"[TEST] error while writing 0x1FFF to reg_mprj_io_{reg1-1}") + if reg2 != cpu.read_debug_reg2(): + reg2 = cpu.read_debug_reg2() + cocotb.log.error(f"[TEST] error while writing 0x0 to reg_mprj_io_{reg2-1}") + await ClockCycles(caravelEnv.clk,10) + '''randomly write then read housekeeping regs through SPI''' @cocotb.test() @repot_test diff --git a/verilog/dv/cocotb/tests/spi_master/SPI_VIP.py b/verilog/dv/cocotb/tests/spi_master/SPI_VIP.py index e59c61dd..2ccd2dac 100644 --- a/verilog/dv/cocotb/tests/spi_master/SPI_VIP.py +++ b/verilog/dv/cocotb/tests/spi_master/SPI_VIP.py @@ -22,7 +22,6 @@ async def SPI_VIP(csb,clk,SDI,SDO,mem): await csb_watcher(csb,op) cocotb.log.info (f"[SPI_VIP] CSB is deasserted operation has been killed") -# cocotb.scheduler.add # watch the csb and when it's diable kill the SPI_op thread async def csb_watcher(csb,thread): cocotb.log.info (f"[csb_watcher] start CSB watching") From 5e523bce5bfc62915c98227a546b8374f504be17 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 4 Oct 2022 10:46:34 -0700 Subject: [PATCH 42/76] Add spi master temp created to simulate the silicon validation test and to be removed after --- verilog/dv/cocotb/tests.json | 14 +++ .../dv/cocotb/tests/spi_master/spi_master.py | 49 ++++++++ .../cocotb/tests/spi_master/spi_master_temp.c | 111 ++++++++++++++++++ 3 files changed, 174 insertions(+) create mode 100644 verilog/dv/cocotb/tests/spi_master/spi_master_temp.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index ed59c687..4ff19c92 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -187,5 +187,19 @@ "GL":["r_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"using SPI master for reading from external memory"} + + ,"spi_master_temp" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"To be deleted"} + + ,"user_pass_thru_rd" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"use the housekeeping spi in user pass thru mode to read from external mem"} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/spi_master/spi_master.py b/verilog/dv/cocotb/tests/spi_master/spi_master.py index cc9925c3..f6b469c5 100644 --- a/verilog/dv/cocotb/tests/spi_master/spi_master.py +++ b/verilog/dv/cocotb/tests/spi_master/spi_master.py @@ -53,3 +53,52 @@ async def spi_master_rd(dut): await ClockCycles(caravelEnv.clk,1000) + + +@cocotb.test() +@repot_test +async def spi_master_temp(dut): + """ the firmware is configured to always send clk to spi so I can't insert alot of logics reading values + + the method of testing used can't work if 2 addresses Consecutive have the same address + """ + caravelEnv,clock = await test_configure(dut,timeout_cycles=214842) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info (f"[TEST] start spi_master_temp test") + await FallingEdge(dut.bin33_monitor) + await RisingEdge(dut.bin32_monitor) + a = '' + b = '' + # first value + for i in range(8): + a = a + dut.bin35_monitor.value.binstr + await RisingEdge(dut.bin32_monitor) + cocotb.log.info (f" [TEST] a = {a} = {int(a,2)}") + + # second val + for i in range(8): + b = b + dut.bin35_monitor.value.binstr + await RisingEdge(dut.bin32_monitor) + cocotb.log.info (f" [TEST] b = {b} = {int(b,2)}") + + s = int(a,2) + int(b,2) + s_bin = bin(s)[2:].zfill(8) + cocotb.log.info (f" [TEST] sending sum of {int(a,2)} + {int(b,2)} = {s} = {s_bin}") + for i in range(8): + dut.bin34_en.value = 1 + dut.bin34.value = int(s_bin[i],2) # bin + cocotb.log.debug (f"[SPI_VIP] [SPI_op] SDO = {s_bin[i]} ") + await FallingEdge(dut.bin32_monitor) + dut.bin34_en.value = 0 # enable + while True: + if cpu.read_debug_reg1() == 0xBB: + cocotb.log.info(f" [TEST] firmware recieve the right value {s}") + break + elif cpu.read_debug_reg1() == 0xBB: + cocotb.log.error(f" [TEST] firmware recieve the incorrect value {cpu.read_debug_reg2()} instead of {s}") + break + + await ClockCycles(caravelEnv.clk,10) + diff --git a/verilog/dv/cocotb/tests/spi_master/spi_master_temp.c b/verilog/dv/cocotb/tests/spi_master/spi_master_temp.c new file mode 100644 index 00000000..27b4bfe4 --- /dev/null +++ b/verilog/dv/cocotb/tests/spi_master/spi_master_temp.c @@ -0,0 +1,111 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +// -------------------------------------------------------- + +/* + * SPI master Test + * - Enables SPI master + * - Uses SPI master to talk to external SPI module + */ + + void spi_write(char c) +{ + reg_spimaster_wdata = (unsigned long) c; +// reg_spimaster_wdata = c; +// spi_master_control_length_write(8); +// spi_master_control_start_write(1); +// reg_spimaster_control = 0x0800; + reg_spimaster_control = 0x0801; +} + char spi_read() +{ +// reg_spimaster_wdata = c; +// spi_master_control_length_write(8); +// spi_master_control_start_write(1); +// reg_spimaster_control = 0x0800; +// spi_write(0x00); +// reg_spimaster_rdata = 0x00; +// reg_spimaster_control = 0x0801; + spi_write(0x00); + while (reg_spimaster_status != 1); + return reg_spimaster_rdata; +} + +void main() +{ + int i; + uint32_t value; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + // For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4 + // should be outputs. + + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; // SDO + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; // CSB + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; // SCK + + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_debug_2 =0xAA; + + reg_spi_enable = 1; + + + // For SPI operation, GPIO 1 should be an input, and GPIOs 2 to 4 + // should be outputs. + + // Start test + + // Enable SPI master + // SPI master configuration bits: + // bits 7-0: Clock prescaler value (default 2) + // bit 8: MSB/LSB first (0 = MSB first, 1 = LSB first) + // bit 9: CSB sense (0 = inverted, 1 = noninverted) + // bit 10: SCK sense (0 = noninverted, 1 = inverted) + // bit 11: mode (0 = read/write opposite edges, 1 = same edges) + // bit 12: stream (1 = CSB ends transmission) + // bit 13: enable (1 = enabled) + // bit 14: IRQ enable (1 = enabled) + // bit 15: (unused) + + + reg_spimaster_cs = 0x10001; // sel=0, manual CS + + spi_write(0x08); // Write 0x03 (read mode) + spi_write(0x05); // Write 0x00 (start address high byte) + value = spi_read(); // 0x93 + if (value == 0xD) + reg_debug_1 = 0xBB; // get correct value + else { + reg_debug_2 = value; + reg_debug_1 = 0xEE; // get wrong value + } + + reg_spimaster_cs = 0x0000; // release CS + reg_spimaster_cs = 0x10001; // sel=0, manual CS + +} + From 0bd6c73b7b839ff3e3442ceeb4d74ab992fc9138 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 4 Oct 2022 10:47:07 -0700 Subject: [PATCH 43/76] update verify_cocotb script to merge coverage --- verilog/dv/cocotb/verify_cocotb.py | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index 25888ce0..1063909f 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -99,10 +99,10 @@ class RunTest: os.environ["SIM"] = self.sim_type os.system(f"vlogan -full64 -sverilog +error+25 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ") - os.system(f"vcs -cm line -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") + os.system(f"vcs -cm line+tgl+cond+fsm+branch+assert -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() - os.system("rm AN.DB/ cm.log results.xml ucli.key -rf") + # os.system("rm AN.DB/ cm.log results.xml ucli.key -rf") def find(self,name, path): for root, dirs, files in os.walk(path): @@ -158,6 +158,7 @@ class RunTest: class RunRegression: def __init__(self,regression,test,type_arg,testlist) -> None: + self.cocotb_path = os.getcwd() self.regression_arg = regression self.test_arg = test self.testlist_arg = testlist @@ -241,8 +242,15 @@ class RunRegression: self.failed_tests +=1 self.unknown_tests -=1 self.update_reg_log() + self.generate_cov() #TODO: add send mail here + def generate_cov(self): + os.chdir(f"{self.cocotb_path}/sim/{os.getenv('RUNTAG')}") + os.system(f"urg -dir RTL*/*.vdb -format both -show tests -report coverageRTL/") + os.system(f"urg -dir GL*/*.vdb -format both -show tests -report coverageGL/") + os.system(f"urg -dir SDF*/*.vdb -format both -show tests -report coverageSDF/") + os.chdir(self.cocotb_path) def update_reg_log(self): file_name=f"sim/{os.getenv('RUNTAG')}/runs.log" From e2b345dcbbffc47baf3a8349e1e81f4a7df27ec7 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 4 Oct 2022 10:55:53 -0700 Subject: [PATCH 44/76] Add new test user_pass_thru_rd --- verilog/dv/cocotb/caravel_tests.py | 1 + verilog/dv/cocotb/tests.json | 2 +- .../housekeeping_regs_tests.py | 19 +----- .../housekeeping_spi/spi_access_functions.py | 38 ++++++++++++ .../housekeeping/housekeeping_spi/test_data | 3 + .../housekeeping_spi/user_pass_thru.py | 51 +++++++++++++++ .../housekeeping_spi/user_pass_thru_rd.c | 62 +++++++++++++++++++ 7 files changed, 157 insertions(+), 19 deletions(-) create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py create mode 100644 verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru_rd.c diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index 80f4bf5c..4df2b34a 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -25,6 +25,7 @@ import os from tests.bitbang.bitbang_tests import * from tests.bitbang.bitbang_tests_cpu import * from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import * +from tests.housekeeping.housekeeping_spi.user_pass_thru import * from tests.temp_partial_test.partial import * from tests.hello_world.helloWorld import * from tests.cpu.cpu_stress import * diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 4ff19c92..3fe26c9b 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -194,7 +194,7 @@ "GL":["r_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"To be deleted"} - + ,"user_pass_thru_rd" :{"level":0, "SW":true, "RTL":["r_rtl","setup","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py index 8bbc1c37..c1ebcf81 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -9,8 +9,8 @@ from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * from caravel import GPIO_MODE +from tests.housekeeping.housekeeping_spi.spi_access_functions import * import json - reg = Regs() @@ -193,23 +193,6 @@ async def hk_regs_rst_spi(dut): -async def write_reg_spi(caravelEnv,address,data): - await caravelEnv.enable_csb() - await caravelEnv.hk_write_byte(0x80) # Write stream command - await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control) - await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode) - await caravelEnv.disable_csb() - - -async def read_reg_spi(caravelEnv,address): - await caravelEnv.enable_csb() - await caravelEnv.hk_write_byte(0x40) # read stream command - await caravelEnv.hk_write_byte(address) # Address - data = await caravelEnv.hk_read_byte() # Data = 0x01 (enable bit-bang mode) - await caravelEnv.disable_csb() - return data - - def generate_key_from_num(num): hex_string = hex(num) hex_list = [i for i in hex_string] diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py new file mode 100644 index 00000000..96e2e9e1 --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/spi_access_functions.py @@ -0,0 +1,38 @@ + + +async def write_reg_spi(caravelEnv,address,data): + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x80) # Write stream command + await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control) + await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + + +async def read_reg_spi(caravelEnv,address): + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0x40) # read stream command + await caravelEnv.hk_write_byte(address) # Address + data = await caravelEnv.hk_read_byte() # Data = 0x01 (enable bit-bang mode) + await caravelEnv.disable_csb() + return data + + +async def reg_spi_user_pass_thru(caravelEnv,command,address): + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(0xc2) # Apply user pass-thru command to housekeeping SPI + await caravelEnv.hk_write_byte(command) # read command + address = address.to_bytes(3,'big') + await caravelEnv.hk_write_byte(address[0]) # high byte + await caravelEnv.hk_write_byte(address[1]) # middle byte + await caravelEnv.hk_write_byte(address[2]) # low byte + +async def reg_spi_user_pass_thru_read(caravelEnv): + data = await caravelEnv.hk_read_byte() + return data + +# use for configure in mgmt pass thru or user pass thru +async def reg_spi_op(caravelEnv,command,address): + await caravelEnv.enable_csb() + await caravelEnv.hk_write_byte(command) # command + await caravelEnv.hk_write_byte(address) # Address + await caravelEnv.disable_csb() diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data new file mode 100644 index 00000000..287a0cf9 --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data @@ -0,0 +1,3 @@ +@00000000 +6F 00 00 0B 93 01 00 00 13 02 63 57 b5 00 23 20 +13 00 00 00 13 00 00 00 13 00 00 00 13 00 00 00 diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py new file mode 100644 index 00000000..d970f2a3 --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py @@ -0,0 +1,51 @@ +from email.headerregistry import Address +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP +from tests.housekeeping.housekeeping_spi.spi_access_functions import * + + +bit_time_ns = 0 +reg = Regs() + + +@cocotb.test() +@repot_test +async def user_pass_thru_rd(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=14833) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info (f"[TEST] start spi_master_rd test") + file_name = f"{os.getenv('CARAVEL_VERILOG_PATH')}/dv/cocotb/tests/housekeeping/housekeeping_spi/test_data" + mem = read_mem(file_name) + await cocotb.start(SPI_VIP(dut.bin8_monitor,dut.bin9_monitor,dut.bin10_monitor,(dut.bin11_en,dut.bin11),mem)) # fork for SPI + await wait_reg1(cpu,caravelEnv,0XAA) + cocotb.log.info (f"[TEST] Configuration finished") + #The SPI flash may need to be reset + # 0xff and 0xAB commands are suppose to have functionality in the future but for now they would do nothing + await write_reg_spi(caravelEnv,0xc2,0xff) # 0xc2 is for appling user pass-thru command to housekeeping SPI + await write_reg_spi(caravelEnv,0xc2,0xab) # 0xc2 is for appling user pass-thru command to housekeeping SPI + + # start reading from memory + address = 0x0 + await reg_spi_user_pass_thru(caravelEnv,command = 0x3,address=address) # read command + for i in range(8): + val = await reg_spi_user_pass_thru_read(caravelEnv) + if val != mem[address]: + cocotb.log.error(f"[TEST] reading incorrect value from address {hex(address)} expected = {hex(mem[address])} returened = {val}") + else: + cocotb.log.info(f"[TEST] reading correct value {hex(val)} from address {hex(address)} ") + address +=1 + + await caravelEnv.disable_csb() + + # Wait for processor to restart + await wait_reg1(cpu,caravelEnv,0xBB) + cocotb.log.info(f"[TEST] processor has restarted successfully") diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru_rd.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru_rd.c new file mode 100644 index 00000000..7e2d18dd --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru_rd.c @@ -0,0 +1,62 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + + + +void main() +{ + // This program is just to keep the processor busy while the + // housekeeping SPI is being accessed. to show that the + // processor is halted while the SPI is accessing the + // flash SPI in pass-through mode. + + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + // Management needs to apply output on these pads to access the user area SPI flash + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; // SDI + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; // SDO + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; // clk + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; // csb + + + // Apply configuration + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // Start test + reg_debug_1 = 0xAA; + reg_debug_1 = 0xBB; + reg_uart_enable = 1; + + // Test in progress + reg_mprj_datal = 0xa5000000; + + // Test message +// print("Test message\n"); + print("ABC\n"); + + for (int i=0; i<1200; i++); + + // End test + reg_debug_1 = 0xFF; +} + From 7de6bdf75e44bb7614129686453c263fd8cee2a7 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 4 Oct 2022 17:58:52 +0000 Subject: [PATCH 45/76] Apply automatic changes to Manifest and README.rst --- manifest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifest b/manifest index 3f7913e8..e1333331 100644 --- a/manifest +++ b/manifest @@ -1,7 +1,7 @@ 535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v -b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v +d1c5814b58ece3ee2cccdf95dd332529f653fc2e verilog/rtl/__user_project_wrapper.v 0e2cda74281c33da2f4e23d0ff5af91adcbcf32a verilog/rtl/caravan.v a855d65d6fc59352e4f8a994e451418d113586fc verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v From 4610f6b00434b243db417ebd7c6f28b384204183 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 5 Oct 2022 08:22:51 -0700 Subject: [PATCH 46/76] Add trial of test gpio_all_i_pu still not work --- verilog/dv/cocotb/caravel.py | 26 +++++-- verilog/dv/cocotb/tests.json | 10 ++- verilog/dv/cocotb/tests/gpio/gpio.py | 44 +++++++++++ verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c | 81 ++++++++++++++++++++ 4 files changed, 153 insertions(+), 8 deletions(-) create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py index 1a63847d..107ce9f4 100644 --- a/verilog/dv/cocotb/caravel.py +++ b/verilog/dv/cocotb/caravel.py @@ -297,12 +297,12 @@ class Caravel_env: gpio_dm =sum(d * 2**i for i, d in enumerate(gpio_dm)) # convert list to binary int path.gpio_dm.value = gpio_dm - """drive the value of mprj bits with spicific data from input pad at the top""" - def release_gpio(self): - io = self.caravel_hdl.padframe.mprj_pads.io - mprj , n_bits = common.signal_valueZ_size(io) - io.value = mprj - cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}') + # """drive the value of mprj bits with spicific data from input pad at the top""" + # def release_gpio(self): + # io = self.caravel_hdl.padframe.mprj_pads.io + # mprj , n_bits = common.signal_valueZ_size(io) + # io.value = mprj + # cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}') """drive the value of mprj bits with spicific data from input pad at the top""" def drive_gpio_in(self,bits,data): @@ -326,6 +326,20 @@ class Caravel_env: self.dut._id(f'bin{bits}_en',False).value = 1 cocotb.log.debug(f'[caravel] [drive_gpio_in] drive bin{bits} with {data} and bin{bits}_en with 1') + """ release driving the value of mprj bits """ + def release_gpio(self,bits): + data_bits = [] + is_list = isinstance(bits, (list,tuple)) + if is_list : + cocotb.log.debug(f'[caravel] [drive_gpio_disable] start bits[1] = {bits[1]} bits[0]= {bits[0]}') + for i,bits2 in enumerate(range(bits[1],bits[0]+1)): + self.dut._id(f"bin{bits2}_en",False).value = 0 + cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits2}') + else: + self.dut._id(f'bin{bits}_en',False).value = 1 + cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits}') + + """drive the value of gpio management""" def drive_mgmt_gpio(self,data): mgmt_io = self.dut.gpio_tb diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 3fe26c9b..20412fd3 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -26,7 +26,13 @@ "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], "GL":["r_gl","push_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], - "description":"configure all gpios as mgmt output using automatic approach firmware and check them"} + "description":"configure all gpios as mgmt input using automatic approach firmware and check them"} + ,"gpio_all_i_pu" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them"} ,"bitbang_cpu_all_10" :{"level":0, "SW":true, "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], @@ -194,7 +200,7 @@ "GL":["r_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"To be deleted"} - + ,"user_pass_thru_rd" :{"level":0, "SW":true, "RTL":["r_rtl","setup","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index 9ebcd824..58feb9af 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -8,6 +8,7 @@ from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * from caravel import GPIO_MODE +from cocotb.binary import BinaryValue reg = Regs() @@ -80,4 +81,47 @@ async def gpio_all_i(dut): cocotb.log.info(f"[TEST] finish") +@cocotb.test() +@repot_test +async def gpio_all_i_pu(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=1245464) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + uut = dut.uut + + # for i in range(200): + # caravelEnv.drive_gpio_in((31,0),0x0) + # await ClockCycles(caravelEnv.clk,10000) + # caravelEnv.drive_gpio_in((31,0),0xFFFFFFFF) + # await ClockCycles(caravelEnv.clk,10000) + + # return + await wait_reg1(cpu,caravelEnv,0xAA) + + cocotb.log.info(f"[TEST] configuration finished") + await wait_reg1(cpu,caravelEnv,0xB1) + data_in = 0x0 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:31]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xB2) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:31]") + size = 32 + data_in = int(size) * 'z' + data_in = 0xFFFFFFFF + cocotb.log.info(f"[TEST] send {data_in} to gpio[0:32]") + caravelEnv.release_gpio((31,0)) + await wait_reg1(cpu,caravelEnv,0xB3) + cocotb.log.info(f"[TEST] data {data_in} sent successfully to gpio[0:31]") + data_in = 0x0 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:16]") + caravelEnv.drive_gpio_in((15,0),data_in) + + # await wait_reg2(cpu,caravelEnv,0xFF) + cocotb.log.info(f"[TEST] finish") + + + await wait_reg1(cpu,caravelEnv,0xFF) + + diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c new file mode 100644 index 00000000..23b9a276 --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c @@ -0,0 +1,81 @@ +#include +#include +#include "../bitbang/bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; + + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_debug_1 = 0XAA; // configuration done + + // while (true){ + // reg_debug_2 = reg_mprj_datal; + + // } + reg_debug_1 = 0XB1; // wait environment to send 0x0 to reg_mprj_datal + while (reg_mprj_datal != 0x0); + reg_debug_2 = reg_mprj_datal; + reg_debug_1 = 0XB2; // wait environment to send 0xzzzzzzzz to reg_mprj_datal + while (reg_mprj_datal != 0xFFFFFFFF); + reg_debug_2 = reg_mprj_datal; + reg_debug_1 = 0XB3; // wait environment to send 0xzzzz0000 to reg_mprj_datal + while (reg_mprj_datal != 0xFFFF0000); + reg_debug_2 = reg_mprj_datal; + + reg_debug_1 = 0XB5; // wait environment to send 0x0 to reg_mprj_datah + while (reg_mprj_datah != 0x0); + reg_debug_2 = reg_mprj_datah; + reg_debug_1 = 0XB6; // wait environment to send 0xzz to reg_mprj_datah + while (reg_mprj_datah != 0x3F); + reg_debug_2 = reg_mprj_datah; + reg_debug_1 = 0XB7; // wait environment to send 0xz0 to reg_mprj_datah + while (reg_mprj_datah != 0x30); + reg_debug_2 = reg_mprj_datah; + + reg_debug_1 = 0xFF; +} From fca511f306139535c45a603e0e25fc818e7a5c06 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 5 Oct 2022 11:10:24 -0700 Subject: [PATCH 47/76] change docker mount from the home to repo directory and pdk root --- verilog/dv/cocotb/verify_cocotb.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index 1063909f..99142a87 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -72,7 +72,7 @@ class RunTest: env_vars = f"-e {CARAVEL_ROOT} -e CARAVEL_VERILOG_PATH={CARAVEL_VERILOG_PATH} -e MCW_ROOT={MCW_ROOT} -e VERILOG_PATH={VERILOG_PATH} -e CARAVEL_PATH={CARAVEL_PATH} -e USER_PROJECT_VERILOG={USER_PROJECT_VERILOG} -e FIRMWARE_PATH={FIRMWARE_PATH} -e RUNTAG={RUNTAG} -e ERRORMAX={ERRORMAX} -e PDK_ROOT={PDK_ROOT} -e PDK={PDK}" print(f"Start running test: {self.sim_type}-{self.test_name}") command = f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} " - os.system(f"docker run -it {env_vars} -v /home:/home efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {command}'") + os.system(f"docker run -it {env_vars} -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)} -v {os.getenv('PDK_ROOT')}:{os.getenv('PDK_ROOT')} efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {command}'") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() @@ -140,7 +140,7 @@ class RunTest: f"--strip-debug -ffreestanding -nostdlib -o {elf_out} {SOURCE_FILES} {c_file}") hex_command = f"{GCC_PATH}/{GCC_PREFIX}-objcopy -O verilog {elf_out} {hex_file} " sed_command = f"sed -ie 's/@10/@00/g' {hex_file}" - hex_gen_state = os.system(f"docker run -it -v /home:/home efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '") + hex_gen_state = os.system(f"docker run -it -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)} efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '") self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n") self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n") self.full_terminal.write(os.path.expandvars(sed_command)+"\n"+"\n") From b31efbdeeab875c3bb0c5b56b977a96b9c9d616d Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 5 Oct 2022 13:47:23 -0700 Subject: [PATCH 48/76] IO[0] affects the uart selecting btw system and debug --- verilog/dv/cocotb/tests/uart/uart.py | 1 + 1 file changed, 1 insertion(+) diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 1e86e100..0cf6eb79 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -66,6 +66,7 @@ async def uart_rx(dut): cpu.cpu_force_reset() cpu.cpu_release_reset() cocotb.log.info(f"[TEST] Start uart test") + caravelEnv.drive_gpio_in((0,0),0) # IO[0] affects the uart selecting btw system and debug caravelEnv.drive_gpio_in((5,5),1) # calculate bit time clk = clock.period/1000 From 8e21a2f722e89f945a69f2357b34a9d71879bd4e Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 5 Oct 2022 13:58:36 -0700 Subject: [PATCH 49/76] Add test pll --- verilog/dv/cocotb/caravel_tests.py | 1 + verilog/dv/cocotb/tests.json | 8 + .../cocotb/tests/housekeeping/general/pll.c | 152 ++++++++++++++++++ .../cocotb/tests/housekeeping/general/pll.py | 86 ++++++++++ 4 files changed, 247 insertions(+) create mode 100644 verilog/dv/cocotb/tests/housekeeping/general/pll.c create mode 100644 verilog/dv/cocotb/tests/housekeeping/general/pll.py diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index 4df2b34a..05d2dea7 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -26,6 +26,7 @@ from tests.bitbang.bitbang_tests import * from tests.bitbang.bitbang_tests_cpu import * from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import * from tests.housekeeping.housekeeping_spi.user_pass_thru import * +from tests.housekeeping.general.pll import * from tests.temp_partial_test.partial import * from tests.hello_world.helloWorld import * from tests.cpu.cpu_stress import * diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 20412fd3..93baf8a3 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -207,5 +207,13 @@ "GL":["r_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"use the housekeeping spi in user pass thru mode to read from external mem"} + + + ,"pll" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"Check pll diffrent configuration"} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/general/pll.c b/verilog/dv/cocotb/tests/housekeeping/general/pll.c new file mode 100644 index 00000000..a30629f6 --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/general/pll.c @@ -0,0 +1,152 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +// -------------------------------------------------------- + +/* + * PLL Test (self-switching) + * - Switches PLL bypass in housekeeping + * - Changes PLL divider in housekeeping + * + */ +void main() +{ + int i; + + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + /* Monitor pins must be set to output */ + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + // Start test + + /* + *------------------------------------------------------------- + * Register 2610_000c reg_hkspi_pll_ena + * SPI address 0x08 = PLL enables + * bit 0 = PLL enable, bit 1 = DCO enable + * + * Register 2610_0010 reg_hkspi_pll_bypass + * SPI address 0x09 = PLL bypass + * bit 0 = PLL bypass + * + * Register 2610_0020 reg_hkspi_pll_source + * SPI address 0x11 = PLL source + * bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider + * + * Register 2610_0024 reg_hkspi_pll_divider + * SPI address 0x12 = PLL divider + * bits 0-4 = feedback divider + * + * Register 2620_0004 reg_clk_out_dest + * SPI address 0x1b = Output redirect + * bit 0 = trap to mprj_io[13] + * bit 1 = clk to mprj_io[14] + * bit 2 = clk2 to mprj_io[15] + *------------------------------------------------------------- + */ + + // Monitor the core clock and user clock on mprj_io[14] and mprj_io[15] + // reg_clk_out_dest = 0x6 to turn on, 0x0 to turn off + + // Write checkpoint for clock counting (PLL bypassed) + reg_debug_1 = 0xA1; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; + reg_debug_1 = 0xA2; + + // Set PLL enable, no DCO mode + reg_hkspi_pll_ena = 0x1; + + // Set PLL output divider to 0x03 + reg_hkspi_pll_source = 0x3; + + // Write checkpoint for clock counting (PLL bypassed) + reg_debug_1 = 0xA3; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; + reg_debug_1 = 0xA4; + + // Disable PLL bypass + reg_hkspi_pll_bypass = 0x0; + + // Write checkpoint for clock counting + reg_debug_1 = 0xA5; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; + reg_debug_1 = 0xA6; + + // Write 0x03 to feedback divider (was 0x04) + reg_hkspi_pll_divider = 0x3; + + // Write checkpoint + reg_debug_1 = 0xA7; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; + reg_debug_1 = 0xA8; + + // Write 0x04 to PLL output divider + reg_hkspi_pll_source = 0x4; + + // Write checkpoint + reg_debug_1 = 0xA9; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x6; + reg_clk_out_dest = 0x0; + reg_debug_1 = 0xAa; + + // End test + reg_mprj_datal = 0xA0900000; +} + diff --git a/verilog/dv/cocotb/tests/housekeeping/general/pll.py b/verilog/dv/cocotb/tests/housekeeping/general/pll.py new file mode 100644 index 00000000..e7dbc1be --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/general/pll.py @@ -0,0 +1,86 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE +from cocotb.binary import BinaryValue + +reg = Regs() +caravel_clock = 0 +user_clock = 0 +@cocotb.test() +@repot_test +async def pll(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=264012) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + error_margin = 0.1 + + await wait_reg1(cpu,caravelEnv,0xA1) + + await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock")) + await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock")) + await wait_reg1(cpu,caravelEnv,0xA3) + if abs(caravel_clock - user_clock) > error_margin*caravel_clock: + cocotb.log.error(f"[TEST] Error: clocks should be equal in phase 1 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + else: + cocotb.log.info(f"[TEST] pass phase 1 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock")) + await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock")) + await wait_reg1(cpu,caravelEnv,0xA5) + if abs(caravel_clock - user_clock) > error_margin*caravel_clock: + cocotb.log.error(f"[TEST] Error: clocks should be equal in phase 2 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + else: + cocotb.log.info(f"[TEST] pass phase 2 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock")) + await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock")) + await wait_reg1(cpu,caravelEnv,0xA7) + if abs(caravel_clock - user_clock*3) > error_margin*caravel_clock: + cocotb.log.error(f"[TEST] Error: user clock shoud be 3 times caravel clock in phase 3 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + else: + cocotb.log.info(f"[TEST] pass phase 3 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock")) + await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock ")) + await wait_reg1(cpu,caravelEnv,0xA9) + if abs(caravel_clock - user_clock*3) > error_margin*caravel_clock: + cocotb.log.error(f"[TEST] Error: user clock shoud be 3 times caravel clock in phase 4 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + else: + cocotb.log.info(f"[TEST] pass phase 4 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + await cocotb.start(calculate_clk_period(dut.bin14_monitor,"caravel clock")) + await cocotb.start(calculate_clk_period(dut.bin15_monitor,"user clock")) + await wait_reg1(cpu,caravelEnv,0xAa) + if abs(caravel_clock - user_clock*4) > error_margin*caravel_clock: + cocotb.log.error(f"[TEST] Error: user clock shoud be 4 times caravel clock in phase 5 but caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + else: + cocotb.log.info(f"[TEST] pass phase 5 caravel clock = {round(1000000/caravel_clock,2)} MHz user clock = {round(1000000/user_clock,2)} MHz") + await ClockCycles(caravelEnv.clk,10000) + + # for i in range(1000): + # await ClockCycles(caravelEnv.clk,10000) + # cocotb.log.info(f"time = {cocotb.simulator.get_sim_time()}") + +async def calculate_clk_period(clk,name): + await RisingEdge(clk) + initial_time = cocotb.simulator.get_sim_time() + initial_time = (initial_time[0] <<32) | (initial_time[1]) + for i in range(100): + await RisingEdge(clk) + end_time = cocotb.simulator.get_sim_time() + end_time = (end_time[0] <<32) | (end_time[1]) + val = (end_time - initial_time) / 100 + cocotb.log.debug(f"[TEST] clock of {name} is {val}") + if name == "caravel clock": + global caravel_clock + caravel_clock = val + elif name == "user clock": + global user_clock + user_clock = val + + val = str(val) + return val \ No newline at end of file From 78613c95cc44ce7bf3b886b6cba1015e90496a55 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 5 Oct 2022 15:02:07 -0700 Subject: [PATCH 50/76] increase timeout for uart_rx and add uart_ev_pending_write --- verilog/dv/cocotb/tests/uart/uart.py | 4 ++-- verilog/dv/cocotb/tests/uart/uart_rx.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 0cf6eb79..3d499938 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -61,7 +61,7 @@ async def start_of_tx(caravelEnv): @cocotb.test() @repot_test async def uart_rx(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=95844) + caravelEnv,clock = await test_configure(dut,timeout_cycles=11195844) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -120,7 +120,7 @@ async def uart_check_char_recieved(caravelEnv,cpu): cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}") return if reg1 == 0x1E: - cocotb.log.error(f"[TEST] Failed Pass cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") + cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") return await ClockCycles(caravelEnv.clk,1) \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/uart/uart_rx.c b/verilog/dv/cocotb/tests/uart/uart_rx.c index 8a0ec37d..bb50c117 100644 --- a/verilog/dv/cocotb/tests/uart/uart_rx.c +++ b/verilog/dv/cocotb/tests/uart/uart_rx.c @@ -17,14 +17,14 @@ #include #include - +#include // -------------------------------------------------------- void wait_for_char(char *c){ - while (uart_rxempty_read() == 1); if (reg_uart_data == *c){ reg_debug_1 = 0x1B; // recieved the correct character + uart_ev_pending_write(UART_EV_RX); }else{ reg_debug_1 = 0x1E; // timeout didn't recieve the character } From a6e7b461283b5546d7e24f3b6bf557c60b010064 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 5 Oct 2022 15:07:38 -0700 Subject: [PATCH 51/76] delete reading from uart register in uart_rx test --- verilog/dv/cocotb/tests/uart/uart.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 3d499938..9446fb4c 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -113,14 +113,14 @@ async def uart_send_char(caravelEnv,char): async def uart_check_char_recieved(caravelEnv,cpu): # check cpu recieved the correct character while True: - reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr + # reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr reg1 = cpu.read_debug_reg1() cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}") if reg1 == 0x1B: - cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}") + cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character ") return if reg1 == 0x1E: - cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") + cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character ") return await ClockCycles(caravelEnv.clk,1) \ No newline at end of file From 6830c79ae8deb0e3ffec8523cc54339e29a196ee Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 02:14:59 -0700 Subject: [PATCH 52/76] fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX); --- verilog/dv/cocotb/tests/uart/uart.py | 10 +++++----- verilog/dv/cocotb/tests/uart/uart_rx.c | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 9446fb4c..af965acc 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -61,7 +61,7 @@ async def start_of_tx(caravelEnv): @cocotb.test() @repot_test async def uart_rx(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=11195844) + caravelEnv,clock = await test_configure(dut,timeout_cycles=104029) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -95,7 +95,7 @@ async def uart_send_char(caravelEnv,char): caravelEnv.drive_gpio_in((5,5),0) await Timer(bit_time_ns, units='ns') #send bits - for i in range(8): + for i in reversed(range(8)): caravelEnv.drive_gpio_in((5,5),char_bits[i]) await Timer(bit_time_ns, units='ns') @@ -113,14 +113,14 @@ async def uart_send_char(caravelEnv,char): async def uart_check_char_recieved(caravelEnv,cpu): # check cpu recieved the correct character while True: - # reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr + reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr reg1 = cpu.read_debug_reg1() cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}") if reg1 == 0x1B: - cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character ") + cocotb.log.info(f"[TEST] Pass cpu has recieved the correct character {chr(int(reg_uart_data,2))}") return if reg1 == 0x1E: - cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character ") + cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") return await ClockCycles(caravelEnv.clk,1) \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/uart/uart_rx.c b/verilog/dv/cocotb/tests/uart/uart_rx.c index bb50c117..ce23de00 100644 --- a/verilog/dv/cocotb/tests/uart/uart_rx.c +++ b/verilog/dv/cocotb/tests/uart/uart_rx.c @@ -24,10 +24,10 @@ void wait_for_char(char *c){ while (uart_rxempty_read() == 1); if (reg_uart_data == *c){ reg_debug_1 = 0x1B; // recieved the correct character - uart_ev_pending_write(UART_EV_RX); }else{ reg_debug_1 = 0x1E; // timeout didn't recieve the character } + uart_ev_pending_write(UART_EV_RX); } From 8e72d5e13e5a244538c24f18613456095c2fef76 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 03:12:44 -0700 Subject: [PATCH 53/76] Add test uart_loopback --- verilog/dv/cocotb/tests.json | 7 ++- verilog/dv/cocotb/tests/uart/uart.py | 42 ++++++++++++- verilog/dv/cocotb/tests/uart/uart_loopback.c | 64 ++++++++++++++++++++ 3 files changed, 110 insertions(+), 3 deletions(-) create mode 100644 verilog/dv/cocotb/tests/uart/uart_loopback.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 93baf8a3..80533529 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -186,7 +186,12 @@ "GL":["r_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"test uart reception"} - + ,"uart_loopback" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"test uart in loopback mode input and output is shorted"} ,"spi_master_rd" :{"level":0, "SW":true, "RTL":["r_rtl","setup","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index af965acc..f640e8b7 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -1,7 +1,7 @@ from curses import baudrate import random import cocotb -from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer,Edge import cocotb.log from cpu import RiskV from defsParser import Regs @@ -72,7 +72,6 @@ async def uart_rx(dut): clk = clock.period/1000 global bit_time_ns bit_time_ns = round(10**5 * clk / (96)) - print (clk) # send first char await wait_reg1(cpu,caravelEnv,0XAA) await uart_send_char(caravelEnv,"B") @@ -123,4 +122,43 @@ async def uart_check_char_recieved(caravelEnv,cpu): cocotb.log.error(f"[TEST] Failed cpu has recieved the wrong character {chr(int(reg_uart_data,2))}") return + await ClockCycles(caravelEnv.clk,1) + +@cocotb.test() +@repot_test +async def uart_loopback(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=216756) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + cocotb.log.info(f"[TEST] Start uart test") + await cocotb.start( connect_5_6(dut,caravelEnv)) # short gpio 6 and 5 + caravelEnv.drive_gpio_in((0,0),0) # IO[0] affects the uart selecting btw system and debug + + # setup watcher loopback results + await cocotb.start(uart_check_char_recieved_loopback(caravelEnv,cpu)) + + await ClockCycles(caravelEnv.clk,197000) + +async def connect_5_6(dut,caravelEnv): + while True: + caravelEnv.drive_gpio_in(5,dut.bin6_monitor.value) + await Edge(dut.bin6_monitor) + + +async def uart_check_char_recieved_loopback(caravelEnv,cpu): + # check cpu recieved the correct character + while True: + reg_uart_data = caravelEnv.caravel_hdl.soc.core.uart_rxtx_w.value.binstr + reg1 = cpu.read_debug_reg1() + cocotb.log.debug(f"[TEST] reg1 = {hex(reg1)}") + if reg1 == 0x1B: + cocotb.log.info(f"[TEST] Pass cpu has sent and recieved the correct character {chr(int(reg_uart_data,2))}") + await wait_reg1(cpu,caravelEnv,0) + + if reg1 == 0x1E: + cocotb.log.error(f"[TEST] Failed cpu has sent and recieved the wrong character {chr(int(reg_uart_data,2))}") + await wait_reg1(cpu,caravelEnv,0) + + await ClockCycles(caravelEnv.clk,1) \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/uart/uart_loopback.c b/verilog/dv/cocotb/tests/uart/uart_loopback.c new file mode 100644 index 00000000..5cedf381 --- /dev/null +++ b/verilog/dv/cocotb/tests/uart/uart_loopback.c @@ -0,0 +1,64 @@ +/* + * SPDX-FileCopyrightText: 2020 Efabless Corporation + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +// -------------------------------------------------------- + +void wait_for_char(char *c){ + while (uart_rxempty_read() == 1); + if (reg_uart_data == *c){ + reg_debug_1 = 0x1B; // recieved the correct character + }else{ + reg_debug_1 = 0x1E; // timeout didn't recieve the character + } + reg_debug_1 =0; + uart_ev_pending_write(UART_EV_RX); +} + +void main(){ + int j; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + + // Now, apply the configuration + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_uart_enable = 1; + + print("M"); + wait_for_char("M"); + + print("B"); + wait_for_char("B"); + + print("A"); + wait_for_char("A"); + + print("5"); + wait_for_char("5"); + + print("o"); + wait_for_char("o"); + +} From 1bc78c4eea155c16f51f76c372fac85672b2a941 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 04:43:02 -0700 Subject: [PATCH 54/76] update verify_cocotb.py script to collect coverage only when -cov is passed --- verilog/dv/cocotb/verify_cocotb.py | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index 99142a87..a1e11668 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -14,7 +14,7 @@ from pathlib import Path iverilog = True vcs = False - +coverage = False def go_up(path, n): for i in range(n): path = os.path.dirname(path) @@ -93,13 +93,15 @@ class RunTest: macros = f'{macros} +define+SIM=\\\"RTL\\\"' else: print(f"Fatal: incorrect simulation type {self.sim_type}") - + coverage_command = "" + if coverage: + coverage_command = "-cm line+tgl+cond+fsm+branch+assert" os.environ["TESTCASE"] = f"{self.test_name}" os.environ["MODULE"] = f"caravel_tests" os.environ["SIM"] = self.sim_type os.system(f"vlogan -full64 -sverilog +error+25 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ") - os.system(f"vcs -cm line+tgl+cond+fsm+branch+assert -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") + os.system(f"vcs {coverage_command} -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() # os.system("rm AN.DB/ cm.log results.xml ucli.key -rf") @@ -242,7 +244,8 @@ class RunRegression: self.failed_tests +=1 self.unknown_tests -=1 self.update_reg_log() - self.generate_cov() + if coverage: + self.generate_cov() #TODO: add send mail here def generate_cov(self): @@ -325,10 +328,13 @@ parser.add_argument('-testlist','-tl', help='path of testlist to be run ') parser.add_argument('-tag', help='provide tag of the run default would be regression name and if no regression is provided would be run___') parser.add_argument('-maxerr', help='max number of errors for every test before simulation breaks default = 3') parser.add_argument('-vcs','-v',action='store_true', help='use vcs as compiler if not used iverilog would be used') +parser.add_argument('-cov','-c',action='store_true', help='enale code coverage') args = parser.parse_args() if (args.vcs) : iverilog = False vcs = True +if args.cov: + coverage = True if args.sim == None: args.sim= ["RTL"] print(f"regression:{args.regression}, test:{args.test}, testlist:{args.testlist} sim: {args.sim}") From a69185dfca31ca2bf46f8ea3571669e225adaaf2 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 04:44:55 -0700 Subject: [PATCH 55/76] update verify_cocotb.py script to collect coverage only when -cov is passed --- verilog/dv/cocotb/README.md | 2 ++ verilog/dv/cocotb/verify_cocotb.py | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/README.md b/verilog/dv/cocotb/README.md index 689e9f2e..e276434a 100644 --- a/verilog/dv/cocotb/README.md +++ b/verilog/dv/cocotb/README.md @@ -51,6 +51,8 @@ run a test breaks default = 3 -vcs, -v use vcs as compiler if not used iverilog would be used + + -cov, -c enable code coverage ``` diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index a1e11668..45be69cd 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -328,7 +328,7 @@ parser.add_argument('-testlist','-tl', help='path of testlist to be run ') parser.add_argument('-tag', help='provide tag of the run default would be regression name and if no regression is provided would be run___') parser.add_argument('-maxerr', help='max number of errors for every test before simulation breaks default = 3') parser.add_argument('-vcs','-v',action='store_true', help='use vcs as compiler if not used iverilog would be used') -parser.add_argument('-cov','-c',action='store_true', help='enale code coverage') +parser.add_argument('-cov','-c',action='store_true', help='enable code coverage') args = parser.parse_args() if (args.vcs) : iverilog = False From fb34d9a54150c1b50f176f3995a9d14af64c2901 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 05:32:46 -0700 Subject: [PATCH 56/76] update input tests to cover the gpio from 32 to 37 --- .../cocotb/tests/bitbang/bitbang_cpu_all_i.c | 8 ++ .../dv/cocotb/tests/bitbang/bitbang_spi_i.c | 86 ++++++++++--------- .../cocotb/tests/bitbang/bitbang_tests_cpu.py | 63 +++++++++++--- verilog/dv/cocotb/tests/gpio/gpio.py | 41 ++++++--- verilog/dv/cocotb/tests/gpio/gpio_all_i.c | 86 ++++++++++--------- 5 files changed, 183 insertions(+), 101 deletions(-) diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_i.c b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_i.c index e3f49723..7164b5f3 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_i.c +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_cpu_all_i.c @@ -76,6 +76,14 @@ void main(){ while (reg_mprj_datal != 0xFFA88C5A); reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal while (reg_mprj_datal != 0xC9536346); + reg_debug_1 = 0XD1; + while (reg_mprj_datah != 0x3F); + reg_debug_1 = 0XD2; + while (reg_mprj_datah != 0x0); + reg_debug_1 = 0XD3; + while (reg_mprj_datah != 0x15); + reg_debug_1 = 0XD4; + while (reg_mprj_datah != 0x2A); reg_debug_2 = 0xFF; diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c index 4c310438..d3dc61c6 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c @@ -10,44 +10,44 @@ void main() reg_debug_1 = 0x0; reg_debug_2 = 0x0; - reg_mprj_io_37 = 0x1803; - reg_mprj_io_36 = 0x1803; - reg_mprj_io_35 = 0x1803; - reg_mprj_io_34 = 0x1803; - reg_mprj_io_33 = 0x1803; - reg_mprj_io_32 = 0x1803; - reg_mprj_io_31 = 0x1803; - reg_mprj_io_30 = 0x1803; - reg_mprj_io_29 = 0x1803; - reg_mprj_io_28 = 0x1803; - reg_mprj_io_27 = 0x1803; - reg_mprj_io_26 = 0x1803; - reg_mprj_io_25 = 0x1803; - reg_mprj_io_24 = 0x1803; - reg_mprj_io_23 = 0x1803; - reg_mprj_io_22 = 0x1803; - reg_mprj_io_21 = 0x1803; - reg_mprj_io_20 = 0x1803; - reg_mprj_io_19 = 0x1803; - reg_mprj_io_18 = 0x1803; - reg_mprj_io_17 = 0x1803; - reg_mprj_io_16 = 0x1803; - reg_mprj_io_15 = 0x1803; - reg_mprj_io_14 = 0x1803; - reg_mprj_io_13 = 0x1803; - reg_mprj_io_12 = 0x1803; - reg_mprj_io_11 = 0x1803; - reg_mprj_io_10 = 0x1803; - reg_mprj_io_9 = 0x1803; - reg_mprj_io_8 = 0x1803; - reg_mprj_io_7 = 0x1803; - reg_mprj_io_6 = 0x1803; - reg_mprj_io_5 = 0x1803; - reg_mprj_io_4 = 0x1803; - reg_mprj_io_3 = 0x1803; - reg_mprj_io_2 = 0x1803; - reg_mprj_io_1 = 0x1803; - reg_mprj_io_0 = 0x1803; + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; reg_debug_1 = 0xFF; // finish configuration @@ -57,7 +57,15 @@ void main() while (reg_mprj_datal != 0xFFA88C5A); reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal while (reg_mprj_datal != 0xC9536346); - + reg_debug_1 = 0XD1; + while (reg_mprj_datah != 0x3F); + reg_debug_1 = 0XD2; + while (reg_mprj_datah != 0x0); + reg_debug_1 = 0XD3; + while (reg_mprj_datah != 0x15); + reg_debug_1 = 0XD4; + while (reg_mprj_datah != 0x2A); + reg_debug_2 = 0xFF; } diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py index 6d864ffc..cd4f1abf 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -182,18 +182,38 @@ async def bitbang_cpu_all_i(dut): await wait_reg1(cpu,caravelEnv,0xAA) cocotb.log.info(f"[TEST] configuration finished") data_in = 0x8F66FD7B - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) await wait_reg1(cpu,caravelEnv,0xBB) - cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") data_in = 0xFFA88C5A - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) await wait_reg1(cpu,caravelEnv,0xCC) - cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") data_in = 0xC9536346 - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xD1) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + data_in = 0x3F + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD2) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]") + data_in = 0x0 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD3) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]") + data_in = 0x15 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD4) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]") + data_in = 0x2A + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) await wait_reg2(cpu,caravelEnv,0xFF) cocotb.log.info(f"[TEST] finish") @@ -298,20 +318,39 @@ async def bitbang_spi_i(dut): await load_spi(caravelEnv) # load await wait_reg1(cpu,caravelEnv,0xAA) - cocotb.log.info("[TEST] finish configuring using bitbang") + cocotb.log.info(f"[TEST] configuration finished") data_in = 0x8F66FD7B - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) await wait_reg1(cpu,caravelEnv,0xBB) - cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") data_in = 0xFFA88C5A - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) await wait_reg1(cpu,caravelEnv,0xCC) - cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") data_in = 0xC9536346 - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) - + await wait_reg1(cpu,caravelEnv,0xD1) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + data_in = 0x3F + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD2) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]") + data_in = 0x0 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD3) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]") + data_in = 0x15 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD4) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]") + data_in = 0x2A + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) await wait_reg2(cpu,caravelEnv,0xFF) cocotb.log.info(f"[TEST] finish") \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index 58feb9af..f5f9c9b5 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -56,7 +56,7 @@ async def gpio_all_o(dut): @cocotb.test() @repot_test async def gpio_all_i(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=45464) + caravelEnv,clock = await test_configure(dut,timeout_cycles=44980) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -64,19 +64,38 @@ async def gpio_all_i(dut): await wait_reg1(cpu,caravelEnv,0xAA) cocotb.log.info(f"[TEST] configuration finished") data_in = 0x8F66FD7B - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) await wait_reg1(cpu,caravelEnv,0xBB) - cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") data_in = 0xFFA88C5A - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) await wait_reg1(cpu,caravelEnv,0xCC) - cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:32]") + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") data_in = 0xC9536346 - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) - + await wait_reg1(cpu,caravelEnv,0xD1) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + data_in = 0x3F + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD2) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]") + data_in = 0x0 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD3) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]") + data_in = 0x15 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD4) + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[37:32]") + data_in = 0x2A + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) await wait_reg2(cpu,caravelEnv,0xFF) cocotb.log.info(f"[TEST] finish") @@ -102,17 +121,17 @@ async def gpio_all_i_pu(dut): cocotb.log.info(f"[TEST] configuration finished") await wait_reg1(cpu,caravelEnv,0xB1) data_in = 0x0 - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:31]") + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") caravelEnv.drive_gpio_in((31,0),data_in) await wait_reg1(cpu,caravelEnv,0xB2) - cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[0:31]") + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") size = 32 data_in = int(size) * 'z' data_in = 0xFFFFFFFF - cocotb.log.info(f"[TEST] send {data_in} to gpio[0:32]") + cocotb.log.info(f"[TEST] send {data_in} to gpio[31:0]") caravelEnv.release_gpio((31,0)) await wait_reg1(cpu,caravelEnv,0xB3) - cocotb.log.info(f"[TEST] data {data_in} sent successfully to gpio[0:31]") + cocotb.log.info(f"[TEST] data {data_in} sent successfully to gpio[31:0]") data_in = 0x0 cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:16]") caravelEnv.drive_gpio_in((15,0),data_in) diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i.c index dd6c9c22..4882b056 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_i.c +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i.c @@ -8,45 +8,45 @@ void main(){ reg_debug_1 = 0x0; reg_debug_2 = 0x0; - reg_mprj_io_37 = 0x1803; - reg_mprj_io_36 = 0x1803; - reg_mprj_io_35 = 0x1803; - reg_mprj_io_34 = 0x1803; - reg_mprj_io_33 = 0x1803; - reg_mprj_io_32 = 0x1803; - reg_mprj_io_31 = 0x1803; - reg_mprj_io_30 = 0x1803; - reg_mprj_io_29 = 0x1803; - reg_mprj_io_28 = 0x1803; - reg_mprj_io_27 = 0x1803; - reg_mprj_io_26 = 0x1803; - reg_mprj_io_25 = 0x1803; - reg_mprj_io_24 = 0x1803; - reg_mprj_io_23 = 0x1803; - reg_mprj_io_22 = 0x1803; - reg_mprj_io_21 = 0x1803; - reg_mprj_io_20 = 0x1803; - reg_mprj_io_19 = 0x1803; - reg_mprj_io_18 = 0x1803; - reg_mprj_io_17 = 0x1803; - reg_mprj_io_16 = 0x1803; - reg_mprj_io_15 = 0x1803; - reg_mprj_io_14 = 0x1803; - reg_mprj_io_13 = 0x1803; - reg_mprj_io_12 = 0x1803; - reg_mprj_io_11 = 0x1803; - reg_mprj_io_10 = 0x1803; - reg_mprj_io_9 = 0x1803; - reg_mprj_io_8 = 0x1803; - reg_mprj_io_7 = 0x1803; - reg_mprj_io_6 = 0x1803; - reg_mprj_io_5 = 0x1803; - reg_mprj_io_4 = 0x1803; - reg_mprj_io_3 = 0x1803; - reg_mprj_io_2 = 0x1803; - reg_mprj_io_1 = 0x1803; - reg_mprj_io_0 = 0x1803; - reg_mprj_io_0 = 0x1803; + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL; reg_mprj_xfer = 1; while (reg_mprj_xfer == 1); @@ -57,6 +57,14 @@ void main(){ while (reg_mprj_datal != 0xFFA88C5A); reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal while (reg_mprj_datal != 0xC9536346); + reg_debug_1 = 0XD1; + while (reg_mprj_datah != 0x3F); + reg_debug_1 = 0XD2; + while (reg_mprj_datah != 0x0); + reg_debug_1 = 0XD3; + while (reg_mprj_datah != 0x15); + reg_debug_1 = 0XD4; + while (reg_mprj_datah != 0x2A); reg_debug_2 = 0xFF; } From 28b453783f514b6e970099256118607c63a43ff1 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 09:20:06 -0700 Subject: [PATCH 57/76] Add clock redirect test --- verilog/dv/cocotb/caravel_tests.py | 1 + verilog/dv/cocotb/tests.json | 7 ++ .../housekeeping/general/clock_redirect.c | 18 ++++ .../tests/housekeeping/general/sys_ctrl.py | 88 +++++++++++++++++++ 4 files changed, 114 insertions(+) create mode 100644 verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c create mode 100644 verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index 05d2dea7..d0cb4087 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -27,6 +27,7 @@ from tests.bitbang.bitbang_tests_cpu import * from tests.housekeeping.housekeeping_regs.housekeeping_regs_tests import * from tests.housekeeping.housekeeping_spi.user_pass_thru import * from tests.housekeeping.general.pll import * +from tests.housekeeping.general.sys_ctrl import * from tests.temp_partial_test.partial import * from tests.hello_world.helloWorld import * from tests.cpu.cpu_stress import * diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 80533529..22f5f9e5 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -220,5 +220,12 @@ "GL":["r_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"Check pll diffrent configuration"} + + ,"clock_redirect" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"check clock redirect is working as expected"} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c b/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c new file mode 100644 index 00000000..19ec69e9 --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c @@ -0,0 +1,18 @@ +#include +#include +// -------------------------------------------------------- + +void main(){ + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + + /* Monitor pins must be set to output */ + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + /* Apply configuration */ + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + reg_debug_1 =0xAA; + return; + } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py b/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py new file mode 100644 index 00000000..bccc0f53 --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py @@ -0,0 +1,88 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE +from cocotb.binary import BinaryValue +from tests.housekeeping.housekeeping_spi.spi_access_functions import * + +reg = Regs() +caravel_clock = 0 +user_clock = 0 +core_clock = 0 +@cocotb.test() +@repot_test +async def clock_redirect(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=264012) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + # calculate core clock + await cocotb.start(calculate_clk_period(dut.uut.clock,"core clock")) + await ClockCycles(caravelEnv.clk,110) + cocotb.log.info(f"[TEST] core clock requency = {round(1000000/core_clock,2)} MHz period = {core_clock}ps") + await wait_reg1(cpu,caravelEnv,0xAa) + # check clk redirect working + #user clock + clock_name = "user clock" + await write_reg_spi(caravelEnv,0x1b,0x0) # disable user clock output redirect + await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name)) + await ClockCycles(caravelEnv.clk,110) + if user_clock != 0: + cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled") + else: + cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled") + + await write_reg_spi(caravelEnv,0x1b,0x4) # enable user clock output redirect + await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name)) + await ClockCycles(caravelEnv.clk,110) + if user_clock != core_clock: + cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {user_clock} and core clock = {core_clock}") + else: + cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully") + + #caravel clock + clock_name = "caravel clock" + await write_reg_spi(caravelEnv,0x1b,0x0) # disable caravel clock output redirect + await cocotb.start(calculate_clk_period(dut.bin14_monitor,clock_name)) + await ClockCycles(caravelEnv.clk,110) + if caravel_clock != 0: + cocotb.log.error(f"[TEST] Error: {clock_name} is directed while clk2_output_dest is disabled") + else: + cocotb.log.info(f"[TEST] Pass: {clock_name} has not directed when reg clk2_output_dest is disabled") + + await write_reg_spi(caravelEnv,0x1b,0x4) # enable caravel clock output redirect + await cocotb.start(calculate_clk_period(dut.bin15_monitor,clock_name)) + await ClockCycles(caravelEnv.clk,110) + if caravel_clock != core_clock: + cocotb.log.error(f"[TEST] Error: {clock_name} is directed with wrong value {clock_name} period = {caravel_clock} and core clock = {core_clock}") + else: + cocotb.log.info(f"[TEST] Pass: {clock_name} has directed successfully") + + +async def calculate_clk_period(clk,name): + await RisingEdge(clk) + initial_time = cocotb.simulator.get_sim_time() + initial_time = (initial_time[0] <<32) | (initial_time[1]) + for i in range(100): + await RisingEdge(clk) + end_time = cocotb.simulator.get_sim_time() + end_time = (end_time[0] <<32) | (end_time[1]) + val = (end_time - initial_time) / 100 + cocotb.log.debug(f"[TEST] clock of {name} is {val}") + if name == "caravel clock": + global caravel_clock + caravel_clock = val + elif name == "user clock": + global user_clock + user_clock = val + elif name == "core clock": + global core_clock + core_clock = val + return val + From 7e407e115591a81f5e70c306f4f10d75f3624283 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 10:12:12 -0700 Subject: [PATCH 58/76] Add test hk_disable --- verilog/dv/cocotb/tests.json | 7 +++ .../housekeeping/general/clock_redirect.c | 2 +- .../tests/housekeeping/general/hk_disable.c | 14 +++++ .../tests/housekeeping/general/sys_ctrl.py | 61 ++++++++++++++++++- 4 files changed, 82 insertions(+), 2 deletions(-) create mode 100644 verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 22f5f9e5..116828ca 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -227,5 +227,12 @@ "GL":["r_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"check clock redirect is working as expected"} + + ,"hk_disable" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"check Housekeeping SPI disable register is working"} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c b/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c index 19ec69e9..7dbba8d2 100644 --- a/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c +++ b/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c @@ -15,4 +15,4 @@ void main(){ while (reg_mprj_xfer == 1); reg_debug_1 =0xAA; return; - } \ No newline at end of file +} \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c b/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c new file mode 100644 index 00000000..fb9e808a --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c @@ -0,0 +1,14 @@ +#include +#include +// -------------------------------------------------------- + +void main(){ + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0xBB; + + while (reg_debug_1 != 0xAA); + reg_hkspi_disable = 0; + // reg_hkspi_pll_ena =0; + reg_debug_1 =0xBB; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py b/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py index bccc0f53..b6c5a42f 100644 --- a/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py +++ b/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py @@ -1,3 +1,4 @@ +from faulthandler import disable import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles @@ -18,7 +19,7 @@ core_clock = 0 @cocotb.test() @repot_test async def clock_redirect(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=264012) + caravelEnv,clock = await test_configure(dut,timeout_cycles=13060) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -86,3 +87,61 @@ async def calculate_clk_period(clk,name): core_clock = val return val + +@cocotb.test() +@repot_test +async def hk_disable(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=11243) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + # check spi working by writing to PLL enables + old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}") + await write_reg_spi(caravelEnv,0x8,1-old_pll_enable) + pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}") + if pll_enable == 1-old_pll_enable: + cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}") + else: + cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}") + old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}") + await write_reg_spi(caravelEnv,0x8,1-old_pll_enable) + pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}") + if pll_enable == 1-old_pll_enable: + cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}") + else: + cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}") + + # disable Housekeeping SPIca + await write_reg_spi(caravelEnv,0x6f,0x1) + + # try to change pll_en + old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}") + await write_reg_spi(caravelEnv,0x8,1-old_pll_enable) + pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}") + if pll_enable == 1-old_pll_enable: + cocotb.log.error(f"[TEST] Error: SPI swap pll_enable value from {old_pll_enable} to {pll_enable} while housekeeping spi is disabled") + else: + cocotb.log.info(f"[TEST] pass: SPI isn't working when SPI housekeeping is disabled") + + # enable SPI housekeeping through firmware + await wait_reg2(cpu,caravelEnv,0xBB) # start waiting on reg1 AA + cpu.write_debug_reg1_backdoor(0xAA) + await wait_reg1(cpu,caravelEnv,0xBB) # enabled the housekeeping + + old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}") + await write_reg_spi(caravelEnv,0x8,1-old_pll_enable) + pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}") + if pll_enable == 1-old_pll_enable: + cocotb.log.info(f"[TEST] Pass: Housekeeping SPI has been enabled correctly through firmware") + else: + cocotb.log.error(f"[TEST] Error: Housekeeping SPI failed to be enabled through firmware") + \ No newline at end of file From 4f483adb36eec31c9e12472a57122c079c70df2b Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 11:16:07 -0700 Subject: [PATCH 59/76] update hk_regs_wr_wb_cpu test to include all house keeping regs --- .../housekeeping_regs/hk_regs_wr_wb_cpu.c | 166 +++++++++++++----- .../housekeeping_regs_tests.py | 17 +- 2 files changed, 137 insertions(+), 46 deletions(-) diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c index a545a74f..0295812c 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/hk_regs_wr_wb_cpu.c @@ -7,45 +7,66 @@ void main(){ reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 reg_debug_1 = 0x0; reg_debug_2 = 0x0; + // store RO value regs + int old_reg_hkspi_status = reg_hkspi_status; + int old_reg_hkspi_chip_id = reg_hkspi_chip_id; + int old_reg_hkspi_user_id = reg_hkspi_user_id; + int old_reg_hkspi_trap = reg_hkspi_trap; + int old_reg_hkspi_irq = reg_hkspi_irq; // write 1 ones to all registers - reg_mprj_io_0 = 0x1FFF; - reg_mprj_io_1 = 0x1FFF; - reg_mprj_io_2 = 0x1FFF; - reg_mprj_io_3 = 0x1FFF; - reg_mprj_io_4 = 0x1FFF; - reg_mprj_io_5 = 0x1FFF; - reg_mprj_io_6 = 0x1FFF; - reg_mprj_io_7 = 0x1FFF; - reg_mprj_io_8 = 0x1FFF; - reg_mprj_io_9 = 0x1FFF; - reg_mprj_io_10 = 0x1FFF; - reg_mprj_io_11 = 0x1FFF; - reg_mprj_io_12 = 0x1FFF; - reg_mprj_io_13 = 0x1FFF; - reg_mprj_io_14 = 0x1FFF; - reg_mprj_io_15 = 0x1FFF; - reg_mprj_io_16 = 0x1FFF; - reg_mprj_io_17 = 0x1FFF; - reg_mprj_io_18 = 0x1FFF; - reg_mprj_io_19 = 0x1FFF; - reg_mprj_io_20 = 0x1FFF; - reg_mprj_io_21 = 0x1FFF; - reg_mprj_io_22 = 0x1FFF; - reg_mprj_io_23 = 0x1FFF; - reg_mprj_io_24 = 0x1FFF; - reg_mprj_io_25 = 0x1FFF; - reg_mprj_io_26 = 0x1FFF; - reg_mprj_io_27 = 0x1FFF; - reg_mprj_io_28 = 0x1FFF; - reg_mprj_io_29 = 0x1FFF; - reg_mprj_io_30 = 0x1FFF; - reg_mprj_io_31 = 0x1FFF; - reg_mprj_io_32 = 0x1FFF; - reg_mprj_io_33 = 0x1FFF; - reg_mprj_io_34 = 0x1FFF; - reg_mprj_io_35 = 0x1FFF; - reg_mprj_io_36 = 0x1FFF; - reg_mprj_io_37 = 0x1FFF; + reg_mprj_io_0 = 0xFFFFFFFF; + reg_mprj_io_1 = 0xFFFFFFFF; + reg_mprj_io_2 = 0xFFFFFFFF; + reg_mprj_io_3 = 0xFFFFFFFF; + reg_mprj_io_4 = 0xFFFFFFFF; + reg_mprj_io_5 = 0xFFFFFFFF; + reg_mprj_io_6 = 0xFFFFFFFF; + reg_mprj_io_7 = 0xFFFFFFFF; + reg_mprj_io_8 = 0xFFFFFFFF; + reg_mprj_io_9 = 0xFFFFFFFF; + reg_mprj_io_10 = 0xFFFFFFFF; + reg_mprj_io_11 = 0xFFFFFFFF; + reg_mprj_io_12 = 0xFFFFFFFF; + reg_mprj_io_13 = 0xFFFFFFFF; + reg_mprj_io_14 = 0xFFFFFFFF; + reg_mprj_io_15 = 0xFFFFFFFF; + reg_mprj_io_16 = 0xFFFFFFFF; + reg_mprj_io_17 = 0xFFFFFFFF; + reg_mprj_io_18 = 0xFFFFFFFF; + reg_mprj_io_19 = 0xFFFFFFFF; + reg_mprj_io_20 = 0xFFFFFFFF; + reg_mprj_io_21 = 0xFFFFFFFF; + reg_mprj_io_22 = 0xFFFFFFFF; + reg_mprj_io_23 = 0xFFFFFFFF; + reg_mprj_io_24 = 0xFFFFFFFF; + reg_mprj_io_25 = 0xFFFFFFFF; + reg_mprj_io_26 = 0xFFFFFFFF; + reg_mprj_io_27 = 0xFFFFFFFF; + reg_mprj_io_28 = 0xFFFFFFFF; + reg_mprj_io_29 = 0xFFFFFFFF; + reg_mprj_io_30 = 0xFFFFFFFF; + reg_mprj_io_31 = 0xFFFFFFFF; + reg_mprj_io_32 = 0xFFFFFFFF; + reg_mprj_io_33 = 0xFFFFFFFF; + reg_mprj_io_34 = 0xFFFFFFFF; + reg_mprj_io_35 = 0xFFFFFFFF; + reg_mprj_io_36 = 0xFFFFFFFF; + reg_mprj_io_37 = 0xFFFFFFFF; + // house keeping + reg_hkspi_status = 0xFFFFFFFF; + reg_hkspi_chip_id = 0xFFFFFFFF; + reg_hkspi_user_id = 0xFFFFFFFF; + reg_hkspi_pll_ena = 0xFFFFFFFF; + reg_hkspi_pll_bypass = 0xFFFFFFFF; + reg_hkspi_irq = 0xFFFFFFFF; + // reg_hkspi_reset = 0xFFFFFFFF; can't write 1 to it cpu would be reset + reg_hkspi_trap = 0xFFFFFFFF; + reg_hkspi_pll_trim = 0xFFFFFFFF; + reg_hkspi_pll_source = 0xFFFFFFFF; + reg_hkspi_pll_divider = 0xFFFFFFFF; + // sys + reg_clk_out_dest = 0xFFFFFFFF; + reg_hkspi_disable = 0xFFFFFFFF; // read ones that has been written if (reg_mprj_io_0 != 0x1FFF) @@ -124,8 +145,31 @@ void main(){ reg_debug_1 =0x25; if (reg_mprj_io_37 != 0x1FFF) reg_debug_1 =0x26; - - + // housekeeping + if (reg_hkspi_status != old_reg_hkspi_status) // RO + reg_debug_1 =0x27; + if (reg_hkspi_chip_id != old_reg_hkspi_chip_id) // RO + reg_debug_1 =0x28; + if (reg_hkspi_user_id != old_reg_hkspi_user_id) // RO + reg_debug_1 =0x29; + if (reg_hkspi_pll_ena != 0x3) // size =2 + reg_debug_1 =0x2a; + if (reg_hkspi_pll_bypass != 0x1) // size = 1 + reg_debug_1 = 0x2b; + if (reg_hkspi_irq != old_reg_hkspi_irq) // RO + reg_debug_1 = 0x2c; + if (reg_hkspi_trap != old_reg_hkspi_trap) // RO + reg_debug_1 =0x2d; + if (reg_hkspi_pll_trim != 0x3FFFFFF) // size 26 + reg_debug_1 = 0x2f; + if (reg_hkspi_pll_source != 0x3F) // size 6 bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider + reg_debug_1 =0x2f; + if (reg_hkspi_pll_divider != 0x1F) // size 7 -> PLL output divider, PLL output divider2 , PLL feedback divider + reg_debug_1 =0x30; + if (reg_hkspi_disable != 0x1) // size 1 + reg_debug_1 =0x31; + if (reg_clk_out_dest != 0x7) // trap and clocks redirect + reg_debug_1 =0x32; // // write zeros to all registers reg_mprj_io_0 = 0x0; reg_mprj_io_1 = 0x0; @@ -165,6 +209,21 @@ void main(){ reg_mprj_io_35 = 0x0; reg_mprj_io_36 = 0x0; reg_mprj_io_37 = 0x0; + // house keeping + reg_hkspi_status = 0x0; + reg_hkspi_chip_id = 0x0; + reg_hkspi_user_id = 0x0; + reg_hkspi_pll_ena = 0x0; + reg_hkspi_pll_bypass = 0x0; + reg_hkspi_irq = 0x0; + reg_hkspi_reset = 0x0; + reg_hkspi_trap = 0x0; + reg_hkspi_pll_trim = 0x0; + reg_hkspi_pll_source = 0x0; + reg_hkspi_pll_divider = 0x0; + // sys + reg_clk_out_dest = 0x0; + reg_hkspi_disable = 0x0; // // read zeros that has been written if (reg_mprj_io_0 != 0x0) @@ -243,7 +302,32 @@ void main(){ reg_debug_2 =0x25; if (reg_mprj_io_37 != 0x0) reg_debug_2 =0x26; - + // housekeeping + if (reg_hkspi_status != old_reg_hkspi_status) // RO + reg_debug_2 =0x27; + if (reg_hkspi_chip_id != old_reg_hkspi_chip_id) // RO + reg_debug_2 =0x28; + if (reg_hkspi_user_id != old_reg_hkspi_user_id) // RO + reg_debug_2 =0x29; + if (reg_hkspi_pll_ena != 0x0) // size =2 + reg_debug_2 =0x2a; + if (reg_hkspi_pll_bypass != 0x0) // size = 1 + reg_debug_2 = 0x2b; + if (reg_hkspi_irq != old_reg_hkspi_irq) // RO + reg_debug_2 = 0x2c; + if (reg_hkspi_trap != old_reg_hkspi_trap) // RO + reg_debug_2 =0x2d; + if (reg_hkspi_pll_trim != 0x0) // size 26 + reg_debug_2 = 0x2f; + if (reg_hkspi_pll_source != 0x0) // size 6 bits 0-2 = phase 0 divider, bits 3-5 = phase 90 divider + reg_debug_2 =0x2f; + if (reg_hkspi_pll_divider != 0x0) // size 7 -> PLL output divider, PLL output divider2 , PLL feedback divider + reg_debug_2 =0x30; + if (reg_hkspi_disable != 0x0) // size 1 + reg_debug_2 =0x31; + if (reg_clk_out_dest != 0x0) // trap and clocks redirect + reg_debug_2 =0x32; + reg_debug_2 = 0xFF; } diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py index c1ebcf81..29465bd5 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -70,22 +70,29 @@ async def hk_regs_wr_wb(dut): @cocotb.test() @repot_test async def hk_regs_wr_wb_cpu(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=157521,num_error=INFINITY) + caravelEnv,clock = await test_configure(dut,timeout_cycles=198243,num_error=INFINITY) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() reg1 =0 # buffer reg2 =0 + regs_list = ("reg_hkspi_status","reg_hkspi_chip_id","reg_hkspi_user_id", "reg_hkspi_pll_ena","reg_hkspi_pll_bypass","reg_hkspi_irq","reg_hkspi_trap","reg_hkspi_pll_trim","reg_hkspi_pll_source","reg_hkspi_pll_divide","reg_clk_out_des","reg_hkspi_disable") while True: if cpu.read_debug_reg2() == 0xFF: # test finish break if reg1 != cpu.read_debug_reg1(): - reg1 = cpu.read_debug_reg1() - cocotb.log.error(f"[TEST] error while writing 0x1FFF to reg_mprj_io_{reg1-1}") + reg1 = cpu.read_debug_reg1() + if reg1 < 38: + cocotb.log.error(f"[TEST] error while writing 0xFFFFFFFF to reg_mprj_io_{reg1-1}") + else: + cocotb.log.error(f"[TEST] error while writing 0xFFFFFFFF to {regs_list[reg1-39]}") if reg2 != cpu.read_debug_reg2(): reg2 = cpu.read_debug_reg2() - cocotb.log.error(f"[TEST] error while writing 0x0 to reg_mprj_io_{reg2-1}") - await ClockCycles(caravelEnv.clk,10) + if reg1 < 38: + cocotb.log.error(f"[TEST] error while writing 0x0 to reg_mprj_io_{reg2-1}") + else: + cocotb.log.error(f"[TEST] error while writing 0x0 to {regs_list[reg1-39]}") + await ClockCycles(caravelEnv.clk,1) '''randomly write then read housekeeping regs through SPI''' @cocotb.test() From 3eb0b113804564712893400462659e9c7b8a0104 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 11:18:48 -0700 Subject: [PATCH 60/76] update verify_cocotb.py to remove vcs generate files --- verilog/dv/cocotb/verify_cocotb.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index 45be69cd..88dcbd1b 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -104,7 +104,7 @@ class RunTest: os.system(f"vcs {coverage_command} -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() - # os.system("rm AN.DB/ cm.log results.xml ucli.key -rf") + os.system("rm AN.DB/ cm.log results.xml ucli.key -rf") def find(self,name, path): for root, dirs, files in os.walk(path): From e1eba1d5343dddf1caad1920749a4ae2a3e1afca Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 7 Oct 2022 06:04:18 -0700 Subject: [PATCH 61/76] update gpio_all_i_pu test --- verilog/dv/cocotb/caravel.py | 7 +- verilog/dv/cocotb/tests/gpio/gpio.py | 122 +++++++++++++++---- verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c | 38 +++--- 3 files changed, 123 insertions(+), 44 deletions(-) diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py index 107ce9f4..9713806c 100644 --- a/verilog/dv/cocotb/caravel.py +++ b/verilog/dv/cocotb/caravel.py @@ -122,8 +122,9 @@ class Caravel_env: """set the spi vsb signal high impedance """ async def release_csb(self ): cocotb.log.info(f' [caravel] release housekeeping spi transmission') - await self.drive_csb('z') - + self.drive_gpio_in((3,3),'z') + self.drive_gpio_in((2,2),'z') + await ClockCycles(self.clk, 1) """set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]""" async def enable_csb(self ): @@ -336,7 +337,7 @@ class Caravel_env: self.dut._id(f"bin{bits2}_en",False).value = 0 cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits2}') else: - self.dut._id(f'bin{bits}_en',False).value = 1 + self.dut._id(f'bin{bits}_en',False).value = 0 cocotb.log.debug(f'[caravel] [drive_gpio_disable] release driving bin{bits}') diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index f5f9c9b5..4016d452 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -103,12 +103,13 @@ async def gpio_all_i(dut): @cocotb.test() @repot_test async def gpio_all_i_pu(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=1245464) + caravelEnv,clock = await test_configure(dut,timeout_cycles=1245464,num_error=2000) + await caravelEnv.release_csb() cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() uut = dut.uut - + # await ClockCycles(caravelEnv.clk,1000000000) # for i in range(200): # caravelEnv.drive_gpio_in((31,0),0x0) # await ClockCycles(caravelEnv.clk,10000) @@ -117,30 +118,107 @@ async def gpio_all_i_pu(dut): # return await wait_reg1(cpu,caravelEnv,0xAA) + # monitor the output of padframe module it suppose to be all ones when no input is applied + await ClockCycles(caravelEnv.clk,100) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i] != "1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and float") + await ClockCycles(caravelEnv.clk,1000) + # drive gpios with zero + data_in = 0x0 + caravelEnv.drive_gpio_in((37,0),data_in) + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i] != "0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as pullup and drived with 0") + await ClockCycles(caravelEnv.clk,1000) + # drive gpios with ones + data_in = 0x3FFFFFFFFF + caravelEnv.drive_gpio_in((37,0),data_in) + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i] != "1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with 1") + await ClockCycles(caravelEnv.clk,1000) + # drive odd half gpios with zeros and float other half + data_in = 0x0 + caravelEnv.drive_gpio_in((37,0),data_in) + for i in range(0,38,2): + caravelEnv.release_gpio(i) # release even gpios + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if i%2 ==1: #odd + if gpio[i]!="1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with odd half with 0") + else: + if gpio[i] != "0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as pullup and drived with odd half with 0") + await ClockCycles(caravelEnv.clk,1000) + # drive even half gpios with zeros and float other half + caravelEnv.drive_gpio_in((37,0),data_in) + for i in range(1,38,2): + caravelEnv.release_gpio(i) # release odd gpios + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if i%2 ==1: #odd + if gpio[i] != "0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as pullup and drived with even half with 0") + else: + if gpio[i]!="1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with even half with 0") + await ClockCycles(caravelEnv.clk,1000) + # drive odd half gpios with ones and float other half + data_in = 0x3FFFFFFFFF + caravelEnv.drive_gpio_in((37,0),data_in) + for i in range(0,38,2): + caravelEnv.release_gpio(i) # release even gpios + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i]!="1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with odd half with 1") + + await ClockCycles(caravelEnv.clk,1000) + # drive even half gpios with zeros and float other half + caravelEnv.drive_gpio_in((37,0),data_in) + for i in range(1,38,2): + caravelEnv.release_gpio(i) # release odd gpios + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i] != "1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with even half with 1") + + await ClockCycles(caravelEnv.clk,1000) - cocotb.log.info(f"[TEST] configuration finished") - await wait_reg1(cpu,caravelEnv,0xB1) - data_in = 0x0 - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") - caravelEnv.drive_gpio_in((31,0),data_in) - await wait_reg1(cpu,caravelEnv,0xB2) - cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") - size = 32 - data_in = int(size) * 'z' - data_in = 0xFFFFFFFF - cocotb.log.info(f"[TEST] send {data_in} to gpio[31:0]") - caravelEnv.release_gpio((31,0)) - await wait_reg1(cpu,caravelEnv,0xB3) - cocotb.log.info(f"[TEST] data {data_in} sent successfully to gpio[31:0]") - data_in = 0x0 - cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:16]") - caravelEnv.drive_gpio_in((15,0),data_in) + # cocotb.log.info(f"[TEST] configuration finished") + # await wait_reg1(cpu,caravelEnv,0xB1) + # data_in = 0x0 + # cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") + # caravelEnv.drive_gpio_in((31,0),data_in) + # await wait_reg1(cpu,caravelEnv,0xB2) + # cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + # size = 32 + # data_in = int(size) * 'z' + # data_in = 0xFFFFFFFF + # cocotb.log.info(f"[TEST] send {data_in} to gpio[31:0]") + # caravelEnv.release_gpio((31,0)) + # await wait_reg1(cpu,caravelEnv,0xB3) + # cocotb.log.info(f"[TEST] data {data_in} sent successfully to gpio[31:0]") + # data_in = 0x0 + # cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:16]") + # caravelEnv.drive_gpio_in((15,0),data_in) - # await wait_reg2(cpu,caravelEnv,0xFF) - cocotb.log.info(f"[TEST] finish") + # # await wait_reg2(cpu,caravelEnv,0xFF) + # cocotb.log.info(f"[TEST] finish") - await wait_reg1(cpu,caravelEnv,0xFF) + # await wait_reg1(cpu,caravelEnv,0xFF) diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c index 23b9a276..22a7a0db 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c @@ -7,7 +7,7 @@ void main(){ reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 reg_debug_1 = 0x0; reg_debug_2 = 0x0; - + reg_hkspi_disable = 1; reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_PULLUP; @@ -57,25 +57,25 @@ void main(){ // reg_debug_2 = reg_mprj_datal; // } - reg_debug_1 = 0XB1; // wait environment to send 0x0 to reg_mprj_datal - while (reg_mprj_datal != 0x0); - reg_debug_2 = reg_mprj_datal; - reg_debug_1 = 0XB2; // wait environment to send 0xzzzzzzzz to reg_mprj_datal - while (reg_mprj_datal != 0xFFFFFFFF); - reg_debug_2 = reg_mprj_datal; - reg_debug_1 = 0XB3; // wait environment to send 0xzzzz0000 to reg_mprj_datal - while (reg_mprj_datal != 0xFFFF0000); - reg_debug_2 = reg_mprj_datal; + // reg_debug_1 = 0XB1; // wait environment to send 0x0 to reg_mprj_datal + // while (reg_mprj_datal != 0x0); + // reg_debug_2 = reg_mprj_datal; + // reg_debug_1 = 0XB2; // wait environment to send 0xzzzzzzzz to reg_mprj_datal + // while (reg_mprj_datal != 0xFFFFFFFF); + // reg_debug_2 = reg_mprj_datal; + // reg_debug_1 = 0XB3; // wait environment to send 0xzzzz0000 to reg_mprj_datal + // while (reg_mprj_datal != 0xFFFF0000); + // reg_debug_2 = reg_mprj_datal; - reg_debug_1 = 0XB5; // wait environment to send 0x0 to reg_mprj_datah - while (reg_mprj_datah != 0x0); - reg_debug_2 = reg_mprj_datah; - reg_debug_1 = 0XB6; // wait environment to send 0xzz to reg_mprj_datah - while (reg_mprj_datah != 0x3F); - reg_debug_2 = reg_mprj_datah; - reg_debug_1 = 0XB7; // wait environment to send 0xz0 to reg_mprj_datah - while (reg_mprj_datah != 0x30); - reg_debug_2 = reg_mprj_datah; + // reg_debug_1 = 0XB5; // wait environment to send 0x0 to reg_mprj_datah + // while (reg_mprj_datah != 0x0); + // reg_debug_2 = reg_mprj_datah; + // reg_debug_1 = 0XB6; // wait environment to send 0xzz to reg_mprj_datah + // while (reg_mprj_datah != 0x3F); + // reg_debug_2 = reg_mprj_datah; + // reg_debug_1 = 0XB7; // wait environment to send 0xz0 to reg_mprj_datah + // while (reg_mprj_datah != 0x30); + // reg_debug_2 = reg_mprj_datah; reg_debug_1 = 0xFF; } From 0aa649265e80a4f8fe5952030395b97f518b8a09 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 7 Oct 2022 13:07:22 +0000 Subject: [PATCH 62/76] Apply automatic changes to Manifest and README.rst --- manifest | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/manifest b/manifest index 6aa88057..51ff59c6 100644 --- a/manifest +++ b/manifest @@ -1,7 +1,7 @@ 535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v -b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v +d1c5814b58ece3ee2cccdf95dd332529f653fc2e verilog/rtl/__user_project_wrapper.v 220d7b7f62f07b3fbe88ea87699bf7cb24336ce5 verilog/rtl/caravan.v 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v @@ -12,12 +12,13 @@ fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v 8a4f1bd4eb40367c3ca8df76df6e1423a8271461 verilog/rtl/chip_io_alt.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v 941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v +86cc0b0e4c2ef4ffb239496943cfff2ff7185b4d verilog/rtl/debug_regs.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v 1f894f1c43d42017c157d8dd7d2e4674c1a43303 verilog/rtl/gpio_control_block.v 9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v 32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v -9b602cb0e7f0e6b7e21d87d3a2bd30cb631302c4 verilog/rtl/housekeeping.v +4290fcaf6bbcff701c2c47c7a23ce4fd4698e888 verilog/rtl/housekeeping.v 3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v ee3fbd794fcc6d221562147b09891e315873ac4c verilog/rtl/mgmt_protect.v 3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v From f072e9cb2df274a3100594c2a63df34e12725a8d Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 7 Oct 2022 06:41:21 -0700 Subject: [PATCH 63/76] Add gpio_all_i_pd --- verilog/dv/cocotb/caravel.py | 4 +- verilog/dv/cocotb/tests.json | 6 + verilog/dv/cocotb/tests/gpio/gpio.py | 159 ++++++++++++++----- verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c | 57 +++++++ verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c | 26 +-- 5 files changed, 186 insertions(+), 66 deletions(-) create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py index 9713806c..94caaff2 100644 --- a/verilog/dv/cocotb/caravel.py +++ b/verilog/dv/cocotb/caravel.py @@ -122,8 +122,8 @@ class Caravel_env: """set the spi vsb signal high impedance """ async def release_csb(self ): cocotb.log.info(f' [caravel] release housekeeping spi transmission') - self.drive_gpio_in((3,3),'z') - self.drive_gpio_in((2,2),'z') + self.release_gpio(3) + self.release_gpio(2) await ClockCycles(self.clk, 1) """set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]""" diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 116828ca..1d515125 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -33,6 +33,12 @@ "GL":["r_gl","push_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt input pull up using automatic approach firmware and check them"} + ,"gpio_all_i_pd" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them"} ,"bitbang_cpu_all_10" :{"level":0, "SW":true, "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index 4016d452..7b8ca34f 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -109,21 +109,14 @@ async def gpio_all_i_pu(dut): cpu.cpu_force_reset() cpu.cpu_release_reset() uut = dut.uut - # await ClockCycles(caravelEnv.clk,1000000000) - # for i in range(200): - # caravelEnv.drive_gpio_in((31,0),0x0) - # await ClockCycles(caravelEnv.clk,10000) - # caravelEnv.drive_gpio_in((31,0),0xFFFFFFFF) - # await ClockCycles(caravelEnv.clk,10000) - - # return + await wait_reg1(cpu,caravelEnv,0xAA) # monitor the output of padframe module it suppose to be all ones when no input is applied await ClockCycles(caravelEnv.clk,100) gpio = dut.uut.padframe.mprj_io_in.value.binstr for i in range(38): if gpio[i] != "1": - cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and float") + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and float") await ClockCycles(caravelEnv.clk,1000) # drive gpios with zero data_in = 0x0 @@ -132,7 +125,7 @@ async def gpio_all_i_pu(dut): gpio = dut.uut.padframe.mprj_io_in.value.binstr for i in range(38): if gpio[i] != "0": - cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as pullup and drived with 0") + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with 0") await ClockCycles(caravelEnv.clk,1000) # drive gpios with ones data_in = 0x3FFFFFFFFF @@ -141,7 +134,7 @@ async def gpio_all_i_pu(dut): gpio = dut.uut.padframe.mprj_io_in.value.binstr for i in range(38): if gpio[i] != "1": - cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with 1") + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with 1") await ClockCycles(caravelEnv.clk,1000) # drive odd half gpios with zeros and float other half data_in = 0x0 @@ -153,10 +146,10 @@ async def gpio_all_i_pu(dut): for i in range(38): if i%2 ==1: #odd if gpio[i]!="1": - cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with odd half with 0") + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 0") else: if gpio[i] != "0": - cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as pullup and drived with odd half with 0") + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with odd half with 0") await ClockCycles(caravelEnv.clk,1000) # drive even half gpios with zeros and float other half caravelEnv.drive_gpio_in((37,0),data_in) @@ -167,10 +160,10 @@ async def gpio_all_i_pu(dut): for i in range(38): if i%2 ==1: #odd if gpio[i] != "0": - cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as pullup and drived with even half with 0") + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pullup and drived with even half with 0") else: if gpio[i]!="1": - cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with even half with 0") + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with even half with 0") await ClockCycles(caravelEnv.clk,1000) # drive odd half gpios with ones and float other half data_in = 0x3FFFFFFFFF @@ -181,7 +174,7 @@ async def gpio_all_i_pu(dut): gpio = dut.uut.padframe.mprj_io_in.value.binstr for i in range(38): if gpio[i]!="1": - cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with odd half with 1") + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with odd half with 1") await ClockCycles(caravelEnv.clk,1000) # drive even half gpios with zeros and float other half @@ -192,33 +185,121 @@ async def gpio_all_i_pu(dut): gpio = dut.uut.padframe.mprj_io_in.value.binstr for i in range(38): if gpio[i] != "1": - cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as pullup and drived with even half with 1") + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and drived with even half with 1") await ClockCycles(caravelEnv.clk,1000) - # cocotb.log.info(f"[TEST] configuration finished") - # await wait_reg1(cpu,caravelEnv,0xB1) - # data_in = 0x0 - # cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") - # caravelEnv.drive_gpio_in((31,0),data_in) - # await wait_reg1(cpu,caravelEnv,0xB2) - # cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") - # size = 32 - # data_in = int(size) * 'z' - # data_in = 0xFFFFFFFF - # cocotb.log.info(f"[TEST] send {data_in} to gpio[31:0]") - # caravelEnv.release_gpio((31,0)) - # await wait_reg1(cpu,caravelEnv,0xB3) - # cocotb.log.info(f"[TEST] data {data_in} sent successfully to gpio[31:0]") - # data_in = 0x0 - # cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[0:16]") - # caravelEnv.drive_gpio_in((15,0),data_in) - - # # await wait_reg2(cpu,caravelEnv,0xFF) - # cocotb.log.info(f"[TEST] finish") + # drive with zeros then release all gpio + data_in = 0x0 + caravelEnv.drive_gpio_in((37,0),data_in) + await ClockCycles(caravelEnv.clk,1000) + caravelEnv.release_gpio((37,0)) + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i] != "1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pullup and all released") + await ClockCycles(caravelEnv.clk,1000) - # await wait_reg1(cpu,caravelEnv,0xFF) - +@cocotb.test() +@repot_test +async def gpio_all_i_pd(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=1245464,num_error=2000) + await caravelEnv.release_csb() + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + uut = dut.uut + + await wait_reg1(cpu,caravelEnv,0xAA) + # monitor the output of padframe module it suppose to be all ones when no input is applied + await ClockCycles(caravelEnv.clk,100) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i] != "0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and float") + await ClockCycles(caravelEnv.clk,1000) + # drive gpios with zero + data_in = 0x0 + caravelEnv.drive_gpio_in((37,0),data_in) + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i] != "0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with 0") + await ClockCycles(caravelEnv.clk,1000) + # drive gpios with ones + data_in = 0x3FFFFFFFFF + caravelEnv.drive_gpio_in((37,0),data_in) + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i] != "1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with 1") + await ClockCycles(caravelEnv.clk,1000) + # drive odd half gpios with zeros and float other half + data_in = 0x0 + caravelEnv.drive_gpio_in((37,0),data_in) + for i in range(0,38,2): + caravelEnv.release_gpio(i) # release even gpios + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i]!="0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 0") + + await ClockCycles(caravelEnv.clk,1000) + # drive even half gpios with zeros and float other half + caravelEnv.drive_gpio_in((37,0),data_in) + for i in range(1,38,2): + caravelEnv.release_gpio(i) # release odd gpios + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i]!="0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with even half with 0") + await ClockCycles(caravelEnv.clk,1000) + # drive odd half gpios with ones and float other half + data_in = 0x3FFFFFFFFF + caravelEnv.drive_gpio_in((37,0),data_in) + for i in range(0,38,2): + caravelEnv.release_gpio(i) # release even gpios + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if i%2 ==0: #even + if gpio[i]!="1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with odd half with 1") + else: + if gpio[i] != "0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 1") + + await ClockCycles(caravelEnv.clk,1000) + # drive even half gpios with zeros and float other half + caravelEnv.drive_gpio_in((37,0),data_in) + for i in range(1,38,2): + caravelEnv.release_gpio(i) # release odd gpios + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if i%2 ==1: #odd + if gpio[i]!="1": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 1 while configured as input pulldown and drived with odd half with 1") + else: + if gpio[i] != "0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and drived with odd half with 1") + await ClockCycles(caravelEnv.clk,1000) + # drive with ones then release all gpio + data_in = 0x3FFFFFFFFF + caravelEnv.drive_gpio_in((37,0),data_in) + await ClockCycles(caravelEnv.clk,1000) + caravelEnv.release_gpio((37,0)) + await ClockCycles(caravelEnv.clk,1000) + gpio = dut.uut.padframe.mprj_io_in.value.binstr + for i in range(38): + if gpio[i] != "0": + cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and all released") + await ClockCycles(caravelEnv.clk,1000) \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c new file mode 100644 index 00000000..bda2e652 --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pd.c @@ -0,0 +1,57 @@ +#include +#include +#include "../bitbang/bitbang_functions.c" + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + reg_hkspi_disable = 1; + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_3 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_PULLDOWN; + + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_debug_1 = 0XAA; // configuration done + + while (true); +} diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c index 22a7a0db..805af50f 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_i_pu.c @@ -53,29 +53,5 @@ void main(){ reg_debug_1 = 0XAA; // configuration done - // while (true){ - // reg_debug_2 = reg_mprj_datal; - - // } - // reg_debug_1 = 0XB1; // wait environment to send 0x0 to reg_mprj_datal - // while (reg_mprj_datal != 0x0); - // reg_debug_2 = reg_mprj_datal; - // reg_debug_1 = 0XB2; // wait environment to send 0xzzzzzzzz to reg_mprj_datal - // while (reg_mprj_datal != 0xFFFFFFFF); - // reg_debug_2 = reg_mprj_datal; - // reg_debug_1 = 0XB3; // wait environment to send 0xzzzz0000 to reg_mprj_datal - // while (reg_mprj_datal != 0xFFFF0000); - // reg_debug_2 = reg_mprj_datal; - - // reg_debug_1 = 0XB5; // wait environment to send 0x0 to reg_mprj_datah - // while (reg_mprj_datah != 0x0); - // reg_debug_2 = reg_mprj_datah; - // reg_debug_1 = 0XB6; // wait environment to send 0xzz to reg_mprj_datah - // while (reg_mprj_datah != 0x3F); - // reg_debug_2 = reg_mprj_datah; - // reg_debug_1 = 0XB7; // wait environment to send 0xz0 to reg_mprj_datah - // while (reg_mprj_datah != 0x30); - // reg_debug_2 = reg_mprj_datah; - - reg_debug_1 = 0xFF; + while (true); } From 0f167fc041e312baf21aee3c6316a720c9d56a12 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 7 Oct 2022 07:02:09 -0700 Subject: [PATCH 64/76] update timeout for gpio_all_i_pd and gpio_all_i_pu --- verilog/dv/cocotb/tests/gpio/gpio.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index 7b8ca34f..44855a2d 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -103,7 +103,7 @@ async def gpio_all_i(dut): @cocotb.test() @repot_test async def gpio_all_i_pu(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=1245464,num_error=2000) + caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000) await caravelEnv.release_csb() cpu = RiskV(dut) cpu.cpu_force_reset() @@ -205,7 +205,7 @@ async def gpio_all_i_pu(dut): @cocotb.test() @repot_test async def gpio_all_i_pd(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=1245464,num_error=2000) + caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000) await caravelEnv.release_csb() cpu = RiskV(dut) cpu.cpu_force_reset() From 2dc29bb2072765fbd9bc8d178290b492660238ef Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Fri, 7 Oct 2022 07:02:58 -0700 Subject: [PATCH 65/76] comment disabling the housekeeping at the begining of each test as it's not needed anymore --- verilog/dv/cocotb/caravel.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py index 94caaff2..43bbed27 100644 --- a/verilog/dv/cocotb/caravel.py +++ b/verilog/dv/cocotb/caravel.py @@ -51,7 +51,7 @@ class Caravel_env: """start carvel by insert power then reset""" async def start_up(self): await self.power_up() - await self.disable_csb() + # await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup await self.reset() await self.disable_bins() common.fill_macros(self.dut.macros) # get macros value From d90001eac281ce912ed7d64366aeec2f31f3ed26 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 8 Oct 2022 01:56:41 -0700 Subject: [PATCH 66/76] update caravel.py to disable bin 3 also --- verilog/dv/cocotb/caravel.py | 2 -- verilog/dv/cocotb/tests/irq/IRQ_external.py | 10 +++------- 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py index 43bbed27..f793d19a 100644 --- a/verilog/dv/cocotb/caravel.py +++ b/verilog/dv/cocotb/caravel.py @@ -58,8 +58,6 @@ class Caravel_env: async def disable_bins(self): for i in range(38): - if i == 3: - continue common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) """setup the vdd and vcc power bins""" diff --git a/verilog/dv/cocotb/tests/irq/IRQ_external.py b/verilog/dv/cocotb/tests/irq/IRQ_external.py index 8db198f9..b996b831 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_external.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_external.py @@ -8,13 +8,9 @@ from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * from caravel import GPIO_MODE +from tests.housekeeping.housekeeping_spi.spi_access_functions import * + -async def write_reg_spi(caravelEnv,address,data): - await caravelEnv.enable_csb() - await caravelEnv.hk_write_byte(0x80) # Write stream command - await caravelEnv.hk_write_byte(address) # Address (register 19 = GPIO bit-bang control) - await caravelEnv.hk_write_byte(data) # Data = 0x01 (enable bit-bang mode) - await caravelEnv.disable_csb() reg = Regs() """Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" @@ -62,7 +58,7 @@ async def IRQ_external(dut): cocotb.log.info(f"[TEST] Pass interrupt isn't detected when mprj 7 deasserted") elif reg1 in fail_list: # pass phase if reg1 == 0x1E: - cocotb.log.info(f"[TEST] Failed interrupt isn't detected when mprj 7 asserted") + cocotb.log.error(f"[TEST] Failed interrupt isn't detected when mprj 7 asserted") elif reg1 == 0x2E: cocotb.log.error(f"[TEST] Failed interrupt is detected when mprj 7 deasserted") else: From e94a8e0477d8f4b84b2a485146784b2b498fdee8 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 8 Oct 2022 06:25:26 -0700 Subject: [PATCH 67/76] add test la test --- verilog/dv/cocotb/caravel_tests.py | 2 +- verilog/dv/cocotb/tests.json | 7 ++ .../.vscode/c_cpp_properties.json | 16 +++ verilog/dv/cocotb/tests/logicAnalyzer/la.c | 111 ++++++++++++++++++ verilog/dv/cocotb/tests/logicAnalyzer/la.py | 48 ++++++++ verilog/dv/cocotb/verify_cocotb.py | 4 +- verilog/rtl/__user_project_la_example.v | 47 ++++++++ verilog/rtl/__user_project_wrapper.v | 4 + 8 files changed, 237 insertions(+), 2 deletions(-) create mode 100644 verilog/dv/cocotb/tests/logicAnalyzer/.vscode/c_cpp_properties.json create mode 100644 verilog/dv/cocotb/tests/logicAnalyzer/la.c create mode 100644 verilog/dv/cocotb/tests/logicAnalyzer/la.py create mode 100644 verilog/rtl/__user_project_la_example.v diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index d0cb4087..b2034fe7 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -40,7 +40,7 @@ from tests.mgmt_gpio.mgmt_gpio import * from tests.timer.timer import * from tests.uart.uart import * from tests.spi_master.spi_master import * - +from tests.logicAnalyzer.la import * diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 1d515125..48e08259 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -240,5 +240,12 @@ "GL":["r_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"check Housekeeping SPI disable register is working"} + + ,"la" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"check logic analyzer input and output enable"} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/logicAnalyzer/.vscode/c_cpp_properties.json b/verilog/dv/cocotb/tests/logicAnalyzer/.vscode/c_cpp_properties.json new file mode 100644 index 00000000..862aed87 --- /dev/null +++ b/verilog/dv/cocotb/tests/logicAnalyzer/.vscode/c_cpp_properties.json @@ -0,0 +1,16 @@ +{ + "configurations": [ + { + "name": "Linux", + "includePath": [ + "${workspaceFolder}/**" + ], + "defines": [], + "compilerPath": "/usr/bin/gcc", + "cStandard": "gnu17", + "cppStandard": "gnu++14", + "intelliSenseMode": "linux-gcc-x64" + } + ], + "version": 4 +} \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/logicAnalyzer/la.c b/verilog/dv/cocotb/tests/logicAnalyzer/la.c new file mode 100644 index 00000000..7986a817 --- /dev/null +++ b/verilog/dv/cocotb/tests/logicAnalyzer/la.c @@ -0,0 +1,111 @@ + +#include +#include + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + reg_hkspi_disable = 1; + + // Configure LA probes [63:32] and [127:96] as inputs to the cpu + // Configure LA probes [31:0] and [63:32] as outputs from the cpu + reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF; // [31:0] + reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32] + reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF; // [95:64] + reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96] + + reg_la0_data = 0xAAAAAAAA; + reg_la2_data = 0xAAAAAAAA; + + reg_debug_2 = reg_la1_data_in; + if (reg_la1_data_in != 0xAAAAAAAA) + reg_debug_1 = 0x1E; + else + reg_debug_1 = 0x1B; + reg_debug_2 = reg_la3_data_in; + if (reg_la3_data_in != 0xAAAAAAAA) + reg_debug_1 = 0x2E; + else + reg_debug_1 = 0x2B; + + reg_la0_data = 0x55555555; + reg_la2_data = 0x55555555; + + reg_debug_2 = reg_la1_data_in; + if (reg_la1_data_in != 0x55555555) + reg_debug_1 = 0x3E; + else + reg_debug_1 = 0x3B; + + reg_debug_2 = reg_la3_data_in; + if (reg_la3_data_in != 0x55555555) + reg_debug_1 = 0x4E; + else + reg_debug_1 = 0x4B; + + // Configure LA probes [31:0] and [63:32] as inputs to the cpu + // Configure LA probes [63:32] and [127:96] as outputs from the cpu + reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0] + reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32] + reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64] + reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96] + + reg_la1_data = 0xAAAAAAAA; + reg_la3_data = 0xAAAAAAAA; + + reg_debug_2 = reg_la0_data_in; + if (reg_la0_data_in != 0xAAAAAAAA) + reg_debug_1 = 0x5E; + else + reg_debug_1 = 0x5B; + + reg_debug_2 = reg_la2_data_in; + if (reg_la2_data_in != 0xAAAAAAAA) + reg_debug_1 = 0x6E; + else + reg_debug_1 = 0x6B; + + reg_la1_data = 0x55555555; + reg_la3_data = 0x55555555; + + reg_debug_2 = reg_la0_data_in; + if (reg_la0_data_in != 0x55555555) + reg_debug_1 = 0x7E; + else + reg_debug_1 = 0x7B; + + reg_debug_2 = reg_la2_data_in; + if (reg_la2_data_in != 0x55555555) + reg_debug_1 = 0x8E; + else + reg_debug_1 = 0x8B; + + // Configure LA probes [31:0] and [63:32] as inputs to the cpu + // Configure LA probes [63:32] and [127:96] as disabled input and output + reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0] + reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32] + reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64] + reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF; // [127:96] + + reg_la1_iena = reg_la3_iena = 0x00000000; // disable input for la1 and la3 + + reg_la1_data = 0xAAAAAAAA; + reg_la3_data = 0xAAAAAAAA; + + reg_debug_2 = reg_la0_data_in; + if (reg_la0_data == 0xAAAAAAAA) + reg_debug_1 = 0x9E; + else + reg_debug_1 = 0x9B; + + reg_debug_2 = reg_la2_data_in; + if (reg_la2_data == 0xAAAAAAAA) + reg_debug_1 = 0xaE; + else + reg_debug_1 = 0xaB; + + reg_debug_2 = 0xFF; + +} diff --git a/verilog/dv/cocotb/tests/logicAnalyzer/la.py b/verilog/dv/cocotb/tests/logicAnalyzer/la.py new file mode 100644 index 00000000..b845e4a3 --- /dev/null +++ b/verilog/dv/cocotb/tests/logicAnalyzer/la.py @@ -0,0 +1,48 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE +from cocotb.binary import BinaryValue + +reg = Regs() + +@cocotb.test() +@repot_test +async def la(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=264012) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + pass_list = (0x1B,0x2B,0x3B,0x4B,0x5B,0x6B,0x7B,0x8B,0x9B,0xaB) + fail_list = (0x1E,0x2E,0x3E,0x4E,0x5E,0x6E,0x7E,0x8E,0x9E,0xaE) + phases_fails = 10 + phases_passes = 0 + reg1 =0 # buffer + while True: + if cpu.read_debug_reg2() == 0xFF: # test finish + break + if reg1 != cpu.read_debug_reg1(): + reg1 = cpu.read_debug_reg1() + if reg1 in pass_list: # pass phase + phases_passes +=1 + phases_fails -=1 + cocotb.log.info(f"[TEST] test passes phase {hex(reg1)[2]}") + elif reg1 in fail_list: # fail phase + cocotb.log.error(f"[TEST] test fails phase {hex(reg1)[2]} incorrect value recieved {hex(cpu.read_debug_reg2())}") + + await ClockCycles(caravelEnv.clk,1) + + if phases_fails != 0: + cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + else: + cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") + + await ClockCycles(caravelEnv.clk, 10000) + + \ No newline at end of file diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index 88dcbd1b..bb02e722 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -80,7 +80,9 @@ class RunTest: def runTest_vcs(self): print(f"Start running test: {self.sim_type}-{self.test_name}") dirs = f'+incdir+\\\"{go_up(self.cocotb_path,4)}\\\" ' - macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS' + macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS ' + if self.test_name == "la": + macros = f'{macros} +define+LA_TESTING' # shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex') # if os.path.exists(f'{self.test_full_dir}/test_data'): # shutil.copyfile(f'{self.test_full_dir}/test_data',f'{self.sim_path}/test_data') diff --git a/verilog/rtl/__user_project_la_example.v b/verilog/rtl/__user_project_la_example.v new file mode 100644 index 00000000..5a1de5f0 --- /dev/null +++ b/verilog/rtl/__user_project_la_example.v @@ -0,0 +1,47 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_project_la_example + * + * This is a user project for testing the la only + * + *------------------------------------------------------------- + */ + +module user_project_la_example ( + // Logic Analyzer Signals + input [127:0] la_data_in, + output [127:0] la_data_out, + input [127:0] la_oenb +); + // LA + assign la_data_out[63:32] = la_oenb[31:0] ? 32'hz: la_data_in[31:0] ; // assign la0 to la1 if la0 output enable + assign la_data_out[31:0] = la_oenb[63:32] ? 32'hz: la_data_in[63:32] ; // assign la1 to la0 if la1 output enable + assign la_data_out[127:96] = la_oenb[95:64] ? 32'hz: la_data_in[95:64] ; // assign la2 to la3 if la2 output enable + assign la_data_out[95:64] = la_oenb[127:96] ? 32'hz: la_data_in[127:96] ; // assign la3 to la2 if la3 output enable + // // LA + // assign la_data_out[63:32] = la_oenb[31:0] ? la_data_in[31:0] : 32'hz ; // assign la0 to la1 if la0 output enable + // assign la_data_out[31:0] = la_oenb[63:32] ? la_data_in[63:32] : 32'hz ; // assign la1 to la0 if la1 output enable + // assign la_data_out[127:96] = la_oenb[95:64] ? la_data_in[95:64] : 32'hz ; // assign la2 to la3 if la2 output enable + // assign la_data_out[95:64] = la_oenb[127:96] ? la_data_in[127:96] : 32'hz ; // assign la3 to la2 if la3 output enable + + +endmodule + +`default_nettype wire diff --git a/verilog/rtl/__user_project_wrapper.v b/verilog/rtl/__user_project_wrapper.v index 9395fb07..ebcf54cc 100644 --- a/verilog/rtl/__user_project_wrapper.v +++ b/verilog/rtl/__user_project_wrapper.v @@ -87,6 +87,10 @@ assign io_oeb = 0; assign io_out = io_in; `endif +`ifdef LA_TESTING +user_project_la_example la_testing(la_data_in,la_data_out,la_oenb); +`endif + // splitting the address space to user address space and debug address space // debug address space are the last 2 registers of user_project_wrapper address space wire wbs_cyc_i_user; From 7b2994e70eae104704bc705926d846abc269ea99 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sat, 8 Oct 2022 13:26:20 +0000 Subject: [PATCH 68/76] Apply automatic changes to Manifest and README.rst --- manifest | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/manifest b/manifest index 51ff59c6..9ae7c139 100644 --- a/manifest +++ b/manifest @@ -1,7 +1,8 @@ 535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v -d1c5814b58ece3ee2cccdf95dd332529f653fc2e verilog/rtl/__user_project_wrapper.v +5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v +c7519ecb9852030028d7dc6377f66aff54c2f534 verilog/rtl/__user_project_wrapper.v 220d7b7f62f07b3fbe88ea87699bf7cb24336ce5 verilog/rtl/caravan.v 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v From 08229d6a9b659ebc35a85aac6cc50d1e96eec543 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 9 Oct 2022 05:08:12 -0700 Subject: [PATCH 69/76] Add gpio_all_bidir test but it still not working yet --- verilog/dv/cocotb/tests.json | 6 ++ verilog/dv/cocotb/tests/gpio/gpio.py | 101 +++++++++++++++++- verilog/dv/cocotb/tests/gpio/gpio_all_bidir.c | 98 +++++++++++++++++ 3 files changed, 204 insertions(+), 1 deletion(-) create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_all_bidir.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 48e08259..0c3f0ed7 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -39,6 +39,12 @@ "GL":["r_gl","push_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt input pull down using automatic approach firmware and check them"} + ,"gpio_all_bidir" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"configure all gpios as mgmt bidir using automatic approach firmware and check them"} ,"bitbang_cpu_all_10" :{"level":0, "SW":true, "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index 44855a2d..6383f917 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -302,4 +302,103 @@ async def gpio_all_i_pd(dut): for i in range(38): if gpio[i] != "0": cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and all released") - await ClockCycles(caravelEnv.clk,1000) \ No newline at end of file + await ClockCycles(caravelEnv.clk,1000) + +@cocotb.test() +@repot_test +async def gpio_all_bidir(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=1144980) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + uut = dut.uut + await wait_reg1(cpu,caravelEnv,0x1A) + cocotb.log.info("[TEST] finish configuring using bitbang") + i= 0x20 + for j in range(5): + await wait_reg2(cpu,caravelEnv,37-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') + if caravelEnv.monitor_gpio((37,0)).integer != i << 32: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i << 32)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') + i = i >> 1 + i |= 0x20 + + i= 0x80000000 + for j in range(32): + await wait_reg2(cpu,caravelEnv,32-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') + if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ') + if caravelEnv.monitor_gpio((31,0)).integer != i : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x80000000 + + await wait_reg1(cpu,caravelEnv,0x2A) + cocotb.log.info(f"[TEST] configuration finished") + data_in = 0x8F66FD7B + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xBB) + if cpu.read_debug_reg2() == data_in: + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + else: + cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}") + data_in = 0xFFA88C5A + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xCC) + if cpu.read_debug_reg2() == data_in: + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + else: + cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}") + data_in = 0xC9536346 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[31:0]") + caravelEnv.drive_gpio_in((31,0),data_in) + await wait_reg1(cpu,caravelEnv,0xD1) + if cpu.read_debug_reg2() == data_in: + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + else: + cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}") + data_in = 0xC9536346 + data_in = 0x3F + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD2) + if cpu.read_debug_reg2() == data_in: + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + else: + cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}") + data_in = 0xC9536346 + data_in = 0x0 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD3) + if cpu.read_debug_reg2() == data_in: + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + else: + cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}") + data_in = 0xC9536346 + data_in = 0x15 + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg1(cpu,caravelEnv,0xD4) + if cpu.read_debug_reg2() == data_in: + cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully to gpio[31:0]") + else: + cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}") + data_in = 0xC9536346 + data_in = 0x2A + cocotb.log.info(f"[TEST] send {hex(data_in)} to gpio[37:32]") + caravelEnv.drive_gpio_in((37,32),data_in) + await wait_reg2(cpu,caravelEnv,0xFF) + cocotb.log.info(f"[TEST] finish") + + await ClockCycles(caravelEnv.clk, 10) diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_bidir.c b/verilog/dv/cocotb/tests/gpio/gpio_all_bidir.c new file mode 100644 index 00000000..a6280785 --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_bidir.c @@ -0,0 +1,98 @@ +#include +#include + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + reg_hkspi_disable = 1; + + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_3 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_BIDIRECTIONAL; + + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + reg_debug_1 = 0x1A; // try the gpios as output + reg_mprj_datal = 0x0; + reg_mprj_datah = 0x0; + i = 0x20; + for (j = 0; j < 5; j++) { + reg_mprj_datah = i; + reg_debug_2 = 37-j; + reg_mprj_datah = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x20; + } + i = 0x80000000; + for (j = 0; j < 32; j++) { + reg_mprj_datah = 0x3f; + reg_mprj_datal = i; + reg_debug_2 = 32-j; + reg_mprj_datah = 0x00; + reg_mprj_datal = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x80000000; + } + // test input + reg_debug_1 = 0X2A; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal + while (reg_mprj_datal != 0x8F66FD7B); + reg_debug_2 = reg_mprj_datal; + reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal + while (reg_mprj_datal != 0xFFA88C5A); + reg_debug_2 = reg_mprj_datal; + reg_debug_1 = 0XCC; // configuration done wait environment to send 0xC9536346 to reg_mprj_datal + while (reg_mprj_datal != 0xC9536346); + reg_debug_2 = reg_mprj_datal; + reg_debug_1 = 0XD1; + while (reg_mprj_datah != 0x3F); + reg_debug_2 = reg_mprj_datal; + reg_debug_1 = 0XD2; + while (reg_mprj_datah != 0x0); + reg_debug_2 = reg_mprj_datal; + reg_debug_1 = 0XD3; + while (reg_mprj_datah != 0x15); + reg_debug_2 = reg_mprj_datal; + reg_debug_1 = 0XD4; + while (reg_mprj_datah != 0x2A); + + reg_debug_2=0xFF; +} \ No newline at end of file From 1690c8e068cc7e60bdd5788631bdf6e6dfc35970 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 9 Oct 2022 06:07:19 -0700 Subject: [PATCH 70/76] enhance gpio_all_o test --- verilog/dv/cocotb/tests/gpio/gpio.py | 43 ++++-- verilog/dv/cocotb/tests/gpio/gpio_all_o.c | 151 ++++++++++++---------- 2 files changed, 111 insertions(+), 83 deletions(-) diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index 6383f917..3dcb60f0 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -15,44 +15,61 @@ reg = Regs() @cocotb.test() @repot_test async def gpio_all_o(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=264012) + caravelEnv,clock = await test_configure(dut,timeout_cycles=376123) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() - await wait_reg1(cpu,caravelEnv,0xFF) + await wait_reg1(cpu,caravelEnv,0xAA) cocotb.log.info("[TEST] finish configuring using bitbang") i= 0x20 for j in range(5): await wait_reg2(cpu,caravelEnv,37-j) - cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}') - if caravelEnv.monitor_gpio((37,4)).integer != i << 28: - cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,4))} instead of {bin(i << 28)}') + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') + if caravelEnv.monitor_gpio((37,0)).integer != i<<32: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}') await wait_reg2(cpu,caravelEnv,0) - if caravelEnv.monitor_gpio((37,4)).integer != 0: - cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') i = i >> 1 i |= 0x20 i= 0x80000000 for j in range(32): await wait_reg2(cpu,caravelEnv,32-j) - cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,4))} j = {j}') + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ') - if caravelEnv.monitor_gpio((31,4)).integer != i>>4 : - cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,4))} instead of {bin(i>>4)}') + if caravelEnv.monitor_gpio((31,0)).integer != i : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}') await wait_reg2(cpu,caravelEnv,0) - if caravelEnv.monitor_gpio((37,4)).integer != 0: - cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,4))} instead of {bin(0x00000)}') + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') i = i >> 1 i |= 0x80000000 - + await wait_reg1(cpu,caravelEnv,0XBB) + data_in = 0x8F66FD7B + cocotb.log.info(f"[TEST] try send {hex(data_in)} to gpio[31:0]") + caravelEnv.drive_gpio_in((31,0),data_in) + reg2 =0 + await wait_reg1(cpu,caravelEnv,0XFF) + try: + reg2 =cpu.read_debug_reg2() + if reg2 == data_in: + cocotb.log.error(f"[TEST] Error: data {hex(data_in)} driven on gpio[31:0] is seen by firmware while gpios are configured as output") + else: + cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output it can see {reg2}") + except Exception as e: + cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output") + return + + await ClockCycles(caravelEnv.clk, 10) + @cocotb.test() @repot_test async def gpio_all_i(dut): diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_o.c b/verilog/dv/cocotb/tests/gpio/gpio_all_o.c index 14014a89..be8748bf 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_all_o.c +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_o.c @@ -3,77 +3,88 @@ #include "../bitbang/bitbang_functions.c" void main(){ - unsigned int i, j, k; - reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 - reg_debug_1 = 0x0; - reg_debug_2 = 0x0; + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + reg_hkspi_disable = 1; + reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_3 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_15 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_14 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_13 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_12 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_11 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_10 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_9 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_8 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_7 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_5 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_4 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_3 = 0x1803 ; - reg_mprj_io_2 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_1 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; - reg_mprj_io_0 = GPIO_MODE_MGMT_STD_OUTPUT; - - reg_mprj_xfer = 1; - while (reg_mprj_xfer == 1); - - reg_debug_1 = 0xFF; // finish configuration - reg_mprj_datal = 0x0; - reg_mprj_datah = 0x0; - i = 0x20; - for (j = 0; j < 5; j++) { - reg_mprj_datah = i; - reg_debug_2 = 37-j; - reg_mprj_datah = 0x00000000; - reg_debug_2 = 0; - i >>=1; - i |= 0x20; - } - i = 0x80000000; - for (j = 0; j < 32; j++) { - reg_mprj_datah = 0x3f; - reg_mprj_datal = i; - reg_debug_2 = 32-j; - reg_mprj_datah = 0x00; - reg_mprj_datal = 0x00000000; - reg_debug_2 = 0; - i >>=1; - i |= 0x80000000; - } + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + reg_debug_1 = 0xAA; // finish configuration + reg_mprj_datal = 0x0; + reg_mprj_datah = 0x0; + i = 0x20; + for (j = 0; j < 5; j++) { + reg_mprj_datah = i; + reg_debug_2 = 37-j; + reg_mprj_datah = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x20; + } + i = 0x80000000; + for (j = 0; j < 32; j++) { + reg_mprj_datah = 0x3f; + reg_mprj_datal = i; + reg_debug_2 = 32-j; + reg_mprj_datah = 0x00; + reg_mprj_datal = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x80000000; + } + + // try to give input + reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal + int timeout = 1000; + while (reg_mprj_datal != 0x8F66FD7B){ + timeout--; + if (timeout==0){ + break; + } + } + reg_debug_2 = reg_mprj_datal; + reg_debug_1 = 0XFF; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal } From 00364eb09250a250b5f6651edd1b84f7af94ddb8 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 9 Oct 2022 07:53:25 -0700 Subject: [PATCH 71/76] Add gpio_all_o_user test --- verilog/dv/cocotb/caravel_tests.py | 1 + verilog/dv/cocotb/tests.json | 6 ++ verilog/dv/cocotb/tests/gpio/gpio.py | 4 +- .../dv/cocotb/tests/gpio/gpio_all_o_user.c | 93 +++++++++++++++++++ verilog/dv/cocotb/tests/gpio/gpio_user.py | 69 ++++++++++++++ verilog/dv/cocotb/verify_cocotb.py | 2 + verilog/rtl/__user_project_gpio_example.v | 80 ++++++++++++++++ verilog/rtl/__user_project_wrapper.v | 48 +++++++++- verilog/rtl/debug_regs.v | 22 ++--- 9 files changed, 308 insertions(+), 17 deletions(-) create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c create mode 100644 verilog/dv/cocotb/tests/gpio/gpio_user.py create mode 100644 verilog/rtl/__user_project_gpio_example.v diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index b2034fe7..10922a96 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -36,6 +36,7 @@ from tests.irq.IRQ_external import * from tests.irq.IRQ_timer import * from tests.irq.IRQ_uart import * from tests.gpio.gpio import * +from tests.gpio.gpio_user import * from tests.mgmt_gpio.mgmt_gpio import * from tests.timer.timer import * from tests.uart.uart import * diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 0c3f0ed7..308efdf4 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -21,6 +21,12 @@ "GL":["r_gl","push_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"configure all gpios as mgmt output using automatic approach firmware and check them"} + ,"gpio_all_o_user" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], + "GL":["r_gl","push_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"configure all gpios as user output using automatic approach firmware and check them"} ,"gpio_all_i" :{"level":0, "SW":true, "RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"], diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index 3dcb60f0..cb1aed80 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -21,7 +21,7 @@ async def gpio_all_o(dut): cpu.cpu_release_reset() await wait_reg1(cpu,caravelEnv,0xAA) - cocotb.log.info("[TEST] finish configuring using bitbang") + cocotb.log.info("[TEST] finish configuring ") i= 0x20 for j in range(5): await wait_reg2(cpu,caravelEnv,37-j) @@ -330,7 +330,7 @@ async def gpio_all_bidir(dut): cpu.cpu_release_reset() uut = dut.uut await wait_reg1(cpu,caravelEnv,0x1A) - cocotb.log.info("[TEST] finish configuring using bitbang") + cocotb.log.info("[TEST] finish configuring ") i= 0x20 for j in range(5): await wait_reg2(cpu,caravelEnv,37-j) diff --git a/verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c b/verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c new file mode 100644 index 00000000..851b25ea --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_all_o_user.c @@ -0,0 +1,93 @@ +#include +#include +#include "../bitbang/bitbang_functions.c" +// Debug reg DEBUG_ON +#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0) +#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4) + +void main(){ + unsigned int i, j, k; + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0x0; + reg_hkspi_disable = 1; + reg_mprj_io_37 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_36 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_34 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_33 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_32 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_31 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_30 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_29 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_28 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_27 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_26 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_25 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_24 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_23 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_22 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_21 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_20 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_19 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_18 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_17 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_16 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; + reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT; + + reg_mprj_xfer = 1; + while (reg_mprj_xfer == 1); + + reg_debug_1 = 0xAA; // finish configuration + reg_mprj_userl = 0x0; + reg_mprj_userh = 0x0; + i = 0x20; + for (j = 0; j < 5; j++) { + reg_mprj_userh = i; + reg_debug_2 = 37-j; + reg_mprj_userh = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x20; + } + i = 0x80000000; + for (j = 0; j < 32; j++) { + reg_mprj_userh = 0x3f; + reg_mprj_userl = i; + reg_debug_2 = 32-j; + reg_mprj_userh = 0x00; + reg_mprj_userl = 0x00000000; + reg_debug_2 = 0; + i >>=1; + i |= 0x80000000; + } + + // try to give input + reg_debug_1 = 0XBB; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_userl + int timeout = 1000; + while (reg_mprj_userl != 0x8F66FD7B){ + timeout--; + if (timeout==0){ + break; + } + } + reg_debug_2 = reg_mprj_userl; + reg_debug_1 = 0XFF; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_userl +} + diff --git a/verilog/dv/cocotb/tests/gpio/gpio_user.py b/verilog/dv/cocotb/tests/gpio/gpio_user.py new file mode 100644 index 00000000..3266ae4d --- /dev/null +++ b/verilog/dv/cocotb/tests/gpio/gpio_user.py @@ -0,0 +1,69 @@ +import random +import cocotb +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +from cpu import RiskV +from defsParser import Regs +from cocotb.result import TestSuccess +from tests.common_functions.test_functions import * +from tests.bitbang.bitbang_functions import * +from caravel import GPIO_MODE +from cocotb.binary import BinaryValue + +reg = Regs() + +@cocotb.test() +@repot_test +async def gpio_all_o_user(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=376123) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + await wait_reg1(cpu,caravelEnv,0xAA) + cocotb.log.info("[TEST] finish configuring as user output") + i= 0x20 + for j in range(5): + await wait_reg2(cpu,caravelEnv,37-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') + if caravelEnv.monitor_gpio((37,0)).integer != i<<32: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i<<32)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') + i = i >> 1 + i |= 0x20 + + i= 0x80000000 + for j in range(32): + await wait_reg2(cpu,caravelEnv,32-j) + cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}') + if caravelEnv.monitor_gpio((37,32)).integer != 0x3f: + cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ') + if caravelEnv.monitor_gpio((31,0)).integer != i : + cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}') + await wait_reg2(cpu,caravelEnv,0) + if caravelEnv.monitor_gpio((37,0)).integer != 0: + cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}') + + i = i >> 1 + i |= 0x80000000 + + await wait_reg1(cpu,caravelEnv,0XBB) + data_in = 0x8F66FD7B + cocotb.log.info(f"[TEST] try send {hex(data_in)} to gpio[31:0]") + caravelEnv.drive_gpio_in((31,0),data_in) + reg2 =0 + await wait_reg1(cpu,caravelEnv,0XFF) + try: + reg2 =cpu.read_debug_reg2() + if reg2 == data_in: + cocotb.log.error(f"[TEST] Error: data {hex(data_in)} driven on gpio[31:0] is seen by firmware while gpios are configured as output") + else: + cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output it can see {reg2}") + except Exception as e: + cocotb.log.info(f"[TEST] driven data {hex(data_in)} sent can't be sent to gpio[31:0] when it configure as output") + return + + + await ClockCycles(caravelEnv.clk, 10) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index bb02e722..e8837d38 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -83,6 +83,8 @@ class RunTest: macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS ' if self.test_name == "la": macros = f'{macros} +define+LA_TESTING' + if self.test_name == "gpio_all_o_user": + macros = f'{macros} +define+GPIO_TESTING' # shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex') # if os.path.exists(f'{self.test_full_dir}/test_data'): # shutil.copyfile(f'{self.test_full_dir}/test_data',f'{self.sim_path}/test_data') diff --git a/verilog/rtl/__user_project_gpio_example.v b/verilog/rtl/__user_project_gpio_example.v new file mode 100644 index 00000000..4bcdfc39 --- /dev/null +++ b/verilog/rtl/__user_project_gpio_example.v @@ -0,0 +1,80 @@ +// SPDX-FileCopyrightText: 2020 Efabless Corporation +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// SPDX-License-Identifier: Apache-2.0 + +`default_nettype none +/* + *------------------------------------------------------------- + * + * user_project_la_example + * + * This is a user project for testing the gpio testing only + * + *------------------------------------------------------------- + */ + +module user_project_gpio_example ( + // Wishbone Slave ports (WB MI A) + input wb_clk_i, + input wb_rst_i, + input wbs_stb_i, + input wbs_cyc_i, + input wbs_we_i, + input [3:0] wbs_sel_i, + input [31:0] wbs_dat_i, + input [31:0] wbs_adr_i, + output reg wbs_ack_o, + output reg[31:0] wbs_dat_o, + + // IOs + input [`MPRJ_IO_PADS-1:0] io_in, + output [`MPRJ_IO_PADS-1:0] io_out, + output [`MPRJ_IO_PADS-1:0] io_oeb + +); + reg [31:0] io_l; + reg [5:0] io_h; + + + always @(posedge wb_clk_i or posedge wb_rst_i) begin + if (wb_rst_i) begin + io_l <=0; + io_h <=0; + wbs_dat_o <=0; + wbs_ack_o <=0; + end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0))begin // write + // write to io_l + io_l[7:0] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[0])? wbs_dat_i[7:0] :io_l[7:0]; + io_l[15:8] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[1])? wbs_dat_i[15:8] :io_l[15:8]; + io_l[23:16] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[2])? wbs_dat_i[23:16] :io_l[23:16]; + io_l[31:24] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[3])? wbs_dat_i[31:24] :io_l[31:24]; + // io_h + io_h[5:0] <= ((wbs_adr_i[3:0]==4'h4) && wbs_sel_i[0])? wbs_dat_i[5:0] :io_h[5:0]; + + wbs_ack_o <= 1; + end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0)) begin // read + wbs_dat_o <= (wbs_adr_i[3:0]==4'h0)? io_in[31:0] : io_in[`MPRJ_IO_PADS-1:32]; + wbs_ack_o <= 1; + end else begin + wbs_ack_o <= 0; + wbs_dat_o <= 0; + end + end + + assign io_out = {io_h,io_l}; + assign io_oeb = 38'h0; + +endmodule + +`default_nettype wire diff --git a/verilog/rtl/__user_project_wrapper.v b/verilog/rtl/__user_project_wrapper.v index ebcf54cc..bda6291a 100644 --- a/verilog/rtl/__user_project_wrapper.v +++ b/verilog/rtl/__user_project_wrapper.v @@ -79,6 +79,7 @@ module user_project_wrapper #( ); // Dummy assignments so that we can take it through the openlane flow +`ifndef GPIO_TESTING `ifdef SIM // Needed for running GL simulation assign io_out = 0; @@ -86,6 +87,7 @@ assign io_oeb = 0; `else assign io_out = io_in; `endif +`endif // GPIO_TESTING `ifdef LA_TESTING user_project_la_example la_testing(la_data_in,la_data_out,la_oenb); @@ -99,15 +101,53 @@ wire [31:0] wbs_dat_o_user; wire wbs_cyc_i_debug; wire wbs_ack_o_debug; +`ifdef GPIO_TESTING +wire wbs_ack_o_gpio; +wire [31:0] wbs_dat_o_gpio; +`endif wire [31:0] wbs_dat_o_debug; // reserve the last 2 regs for debugging registers -assign wbs_cyc_i_user = (wbs_adr_i[19:3] != 17'h1ffff) ? wbs_cyc_i : 0; -assign wbs_cyc_i_debug = (wbs_adr_i[19:3] == 17'h1ffff) ? wbs_cyc_i : 0; +`ifndef GPIO_TESTING +assign wbs_cyc_i_user = (wbs_adr_i[31:3] != 29'h601FFFF) ? wbs_cyc_i : 0; +assign wbs_cyc_i_debug = (wbs_adr_i[31:3] == 29'h601FFFF) ? wbs_cyc_i : 0; +`endif -assign wbs_ack_o = (wbs_adr_i[19:3] == 17'h1ffff) ? wbs_ack_o_debug : wbs_ack_o_debug; -assign wbs_dat_o = (wbs_adr_i[19:3] == 17'h1ffff) ? wbs_dat_o_debug : wbs_dat_o_user; +`ifndef GPIO_TESTING +assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_o_debug; +assign wbs_dat_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_dat_o_debug : wbs_dat_o_user; +`endif + + +// reserve the last 4 regs for debugging registers in case of user gpio testing +`ifdef GPIO_TESTING +assign wbs_cyc_i_user = (wbs_adr_i[31:4] != 28'h300FFFF) ? wbs_cyc_i : 0; +assign wbs_cyc_i_debug = (wbs_adr_i[31:4] == 28'h300FFFF) ? wbs_cyc_i : 0; +`endif + +`ifdef GPIO_TESTING +assign wbs_ack_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_ack_o_debug : wbs_ack_o_gpio : wbs_ack_o_debug; +assign wbs_dat_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_dat_o_debug : wbs_dat_o_gpio : wbs_dat_o_user; +`endif + + +`ifdef GPIO_TESTING +user_project_gpio_example gpio_testing( + .wb_clk_i(wb_clk_i), + .wb_rst_i(wb_rst_i), + .wbs_cyc_i(wbs_cyc_i_debug), + .wbs_stb_i(wbs_stb_i), + .wbs_we_i(wbs_we_i), + .wbs_sel_i(wbs_sel_i), + .wbs_adr_i(wbs_adr_i), + .wbs_dat_i(wbs_dat_i), + .wbs_ack_o(wbs_ack_o_gpio), + .wbs_dat_o(wbs_dat_o_gpio), + .io_in(io_in), + .io_out(io_out), + .io_oeb(io_oeb)); +`endif debug_regs debug( .wb_clk_i(wb_clk_i), diff --git a/verilog/rtl/debug_regs.v b/verilog/rtl/debug_regs.v index 85043928..2551a3c4 100644 --- a/verilog/rtl/debug_regs.v +++ b/verilog/rtl/debug_regs.v @@ -21,20 +21,20 @@ module debug_regs ( debug_reg_2 <=0; wbs_dat_o <=0; wbs_ack_o <=0; - end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o)begin // write + end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8))begin // write // write to reg1 - debug_reg_1[7:0] <= (!wbs_adr_i[2] && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_1[7:0]; - debug_reg_1[15:8] <= (!wbs_adr_i[2] && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_1[15:8]; - debug_reg_1[23:16] <= (!wbs_adr_i[2] && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_1[23:16]; - debug_reg_1[31:24] <= (!wbs_adr_i[2] && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_1[31:24]; + debug_reg_1[7:0] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_1[7:0]; + debug_reg_1[15:8] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_1[15:8]; + debug_reg_1[23:16] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_1[23:16]; + debug_reg_1[31:24] <= ((wbs_adr_i[3:0]==4'h8) && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_1[31:24]; // write to reg2 - debug_reg_2[7:0] <= (wbs_adr_i[2] && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_2[7:0]; - debug_reg_2[15:8] <= (wbs_adr_i[2] && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_2[15:8]; - debug_reg_2[23:16] <= (wbs_adr_i[2] && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_2[23:16]; - debug_reg_2[31:24] <= (wbs_adr_i[2] && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_2[31:24]; + debug_reg_2[7:0] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[0])? wbs_dat_i[7:0] :debug_reg_2[7:0]; + debug_reg_2[15:8] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[1])? wbs_dat_i[15:8] :debug_reg_2[15:8]; + debug_reg_2[23:16] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[2])? wbs_dat_i[23:16] :debug_reg_2[23:16]; + debug_reg_2[31:24] <= ((wbs_adr_i[3:0]==4'hC) && wbs_sel_i[3])? wbs_dat_i[31:24] :debug_reg_2[31:24]; wbs_ack_o <= 1; - end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o) begin // read - wbs_dat_o <= (wbs_adr_i[2]) ? debug_reg_2 : debug_reg_1; + end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'hC||wbs_adr_i[3:0]==4'h8)) begin // read + wbs_dat_o <= ((wbs_adr_i[3:0]==4'hC)) ? debug_reg_2 : debug_reg_1; wbs_ack_o <= 1; end else begin wbs_ack_o <= 0; From f0037c35fdbb53bae222e97918c6ce028bfec55c Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Sun, 9 Oct 2022 14:54:31 +0000 Subject: [PATCH 72/76] Apply automatic changes to Manifest and README.rst --- manifest | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/manifest b/manifest index 9ae7c139..5eddda7f 100644 --- a/manifest +++ b/manifest @@ -1,8 +1,9 @@ 535d0592c0b1349489b6b86fd5449f9d1d81482e verilog/rtl/__uprj_analog_netlists.v 87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v +1315c3df4decc1a015ec78dfb7df174eb3a74e9a verilog/rtl/__user_project_gpio_example.v 5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v -c7519ecb9852030028d7dc6377f66aff54c2f534 verilog/rtl/__user_project_wrapper.v +ef356bbc8938fef0c1866a709a3bf846d8c7e1e4 verilog/rtl/__user_project_wrapper.v 220d7b7f62f07b3fbe88ea87699bf7cb24336ce5 verilog/rtl/caravan.v 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v @@ -13,7 +14,7 @@ fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v 8a4f1bd4eb40367c3ca8df76df6e1423a8271461 verilog/rtl/chip_io_alt.v 126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v 941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v -86cc0b0e4c2ef4ffb239496943cfff2ff7185b4d verilog/rtl/debug_regs.v +653b230c7cbf092a6210ba7820bc942f312e53f3 verilog/rtl/debug_regs.v 36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v 1f894f1c43d42017c157d8dd7d2e4674c1a43303 verilog/rtl/gpio_control_block.v From 45a885caaa278cc17a8208dcb20dcfbd095970a6 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 10 Oct 2022 04:34:26 -0700 Subject: [PATCH 73/76] update verify_cocotb script to be dependent on CARAVEL_ROOT and MCW_ROOT --- verilog/dv/cocotb/caravel_top.sv | 14 +++++++------ verilog/dv/cocotb/verify_cocotb.py | 32 ++++++++++++++++++------------ 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/verilog/dv/cocotb/caravel_top.sv b/verilog/dv/cocotb/caravel_top.sv index 581b09c8..297fe3b4 100644 --- a/verilog/dv/cocotb/caravel_top.sv +++ b/verilog/dv/cocotb/caravel_top.sv @@ -1,11 +1,13 @@ `ifdef VCS - `ifndef GL - `include "caravel_mgmt_soc_litex/verilog/includes/rtl_caravel_vcs.v" - `else - `include "caravel_mgmt_soc_litex/verilog/includes/gl_caravel_vcs.v" - `endif - //`include "verilog/includes/user_project_vcs.v" + `include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v" + `include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v" + `include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v" + `include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v" + `include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v" + `include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v" `endif +`timescale 1 ns / 1 ps + module caravel_top ; // parameter FILENAME = {"hex_files/",`TESTNAME,".hex"}; diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index e8837d38..a5f56a18 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -33,7 +33,7 @@ def search_str(file_path, word): class RunTest: def __init__(self,test_name,sim) -> None: - self.cocotb_path = os.getcwd() + self.cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb" self.test_name = test_name self.sim_type = sim self.create_log_file() @@ -72,14 +72,22 @@ class RunTest: env_vars = f"-e {CARAVEL_ROOT} -e CARAVEL_VERILOG_PATH={CARAVEL_VERILOG_PATH} -e MCW_ROOT={MCW_ROOT} -e VERILOG_PATH={VERILOG_PATH} -e CARAVEL_PATH={CARAVEL_PATH} -e USER_PROJECT_VERILOG={USER_PROJECT_VERILOG} -e FIRMWARE_PATH={FIRMWARE_PATH} -e RUNTAG={RUNTAG} -e ERRORMAX={ERRORMAX} -e PDK_ROOT={PDK_ROOT} -e PDK={PDK}" print(f"Start running test: {self.sim_type}-{self.test_name}") command = f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} " - os.system(f"docker run -it {env_vars} -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)} -v {os.getenv('PDK_ROOT')}:{os.getenv('PDK_ROOT')} efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {command}'") + os.system(f"docker run -it {env_vars} -v {os.getenv('CARAVEL_ROOT')}:{os.getenv('CARAVEL_ROOT')} -v {os.getenv('MCW_ROOT')}:{os.getenv('MCW_ROOT')} -v {os.getenv('PDK_ROOT')}:{os.getenv('PDK_ROOT')} efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {command}'") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() # vcs function def runTest_vcs(self): print(f"Start running test: {self.sim_type}-{self.test_name}") - dirs = f'+incdir+\\\"{go_up(self.cocotb_path,4)}\\\" ' + PDK_ROOT = os.getenv('PDK_ROOT') + PDK = os.getenv('PDK') + VERILOG_PATH = os.getenv('VERILOG_PATH') + dirs = f'+incdir+\\\"{PDK_ROOT}/{PDK}\\\" ' + if self.sim_type == "RTL": + dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/rtl_caravel_vcs.lst\\\" ' + else: + dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/gl_caravel_vcs.lst\\\" ' + macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS ' if self.test_name == "la": macros = f'{macros} +define+LA_TESTING' @@ -104,8 +112,8 @@ class RunTest: os.environ["MODULE"] = f"caravel_tests" os.environ["SIM"] = self.sim_type - os.system(f"vlogan -full64 -sverilog +error+25 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ") - os.system(f"vcs {coverage_command} -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") + os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.sim_type}-{self.test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ") + os.system(f"vcs {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)") self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors") Path(f'{self.sim_path}/{self.passed}').touch() os.system("rm AN.DB/ cm.log results.xml ucli.key -rf") @@ -164,7 +172,7 @@ class RunTest: class RunRegression: def __init__(self,regression,test,type_arg,testlist) -> None: - self.cocotb_path = os.getcwd() + self.cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb" self.regression_arg = regression self.test_arg = test self.testlist_arg = testlist @@ -308,17 +316,15 @@ class main(): print(f"Run tag: {self.TAG}") def def_env_vars(self): - cocotb_path = os.getcwd() - repo_path = go_up(cocotb_path,4) - os.environ["CARAVEL_ROOT"] = f"{repo_path}/caravel" - os.environ["CARAVEL_VERILOG_PATH"] = f"{repo_path}/caravel/verilog" - os.environ["MCW_ROOT"] = f"{repo_path}/caravel_mgmt_soc_litex/" + if os.getenv('CARAVEL_ROOT') is None or os.getenv('MCW_ROOT') is None: + print(f"Fatal: CARAVEL_ROOT or MCW_ROOT are not defined") + sys.exit() + cocotb_path = f"{os.getenv('CARAVEL_ROOT')}/verilog/dv/cocotb" + os.environ["CARAVEL_VERILOG_PATH"] = f"{os.getenv('CARAVEL_ROOT')}/verilog" os.environ["VERILOG_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog" os.environ["CARAVEL_PATH"] = f"{os.getenv('CARAVEL_VERILOG_PATH')}" - os.environ["USER_PROJECT_VERILOG"] = f"{repo_path}/verilog/" os.environ["FIRMWARE_PATH"] = f"{os.getenv('MCW_ROOT')}/verilog/dv/firmware" os.environ["RUNTAG"] = f"{self.TAG}" - print(self.maxerr) os.environ["ERRORMAX"] = f"{self.maxerr}" From 688429eedacbd595ee39aa438be8f7ccbe474eed Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 10 Oct 2022 04:50:45 -0700 Subject: [PATCH 74/76] move caravel.py, cpu.py ... to interfaces directory --- verilog/dv/cocotb/caravel.py | 2 +- verilog/dv/cocotb/caravel_tests.py | 12 +- verilog/dv/cocotb/cpu.py | 2 +- verilog/dv/cocotb/interfaces/caravel.py | 432 ++++++++++++++++++ verilog/dv/cocotb/{ => interfaces}/common.py | 0 verilog/dv/cocotb/interfaces/cpu.py | 232 ++++++++++ .../dv/cocotb/{ => interfaces}/defsParser.py | 0 .../cocotb/{ => interfaces}/logic_analyzer.py | 8 +- .../cocotb/tests/bitbang/bitbang_functions.py | 2 +- .../dv/cocotb/tests/bitbang/bitbang_tests.py | 6 +- .../cocotb/tests/bitbang/bitbang_tests_cpu.py | 8 +- .../tests/common_functions/test_functions.py | 8 +- verilog/dv/cocotb/tests/cpu/cpu_stress.py | 6 +- verilog/dv/cocotb/tests/gpio/gpio.py | 6 +- verilog/dv/cocotb/tests/gpio/gpio_user.py | 6 +- .../cocotb/tests/housekeeping/general/pll.py | 6 +- .../tests/housekeeping/general/sys_ctrl.py | 6 +- .../housekeeping_regs_tests.py | 8 +- .../housekeeping_spi/user_pass_thru.py | 4 +- verilog/dv/cocotb/tests/irq/IRQ_external.py | 6 +- verilog/dv/cocotb/tests/irq/IRQ_timer.py | 6 +- verilog/dv/cocotb/tests/irq/IRQ_uart.py | 6 +- verilog/dv/cocotb/tests/logicAnalyzer/la.py | 6 +- verilog/dv/cocotb/tests/mem/mem_stress.py | 6 +- .../dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py | 6 +- .../dv/cocotb/tests/spi_master/spi_master.py | 6 +- .../cocotb/tests/temp_partial_test/partial.py | 6 +- verilog/dv/cocotb/tests/timer/timer.py | 6 +- verilog/dv/cocotb/tests/uart/uart.py | 6 +- .../wb_models/housekeepingWB/HKSPImonitor.py | 2 +- .../housekeepingWB/housekeepingWB.py | 2 +- 31 files changed, 741 insertions(+), 77 deletions(-) create mode 100644 verilog/dv/cocotb/interfaces/caravel.py rename verilog/dv/cocotb/{ => interfaces}/common.py (100%) create mode 100644 verilog/dv/cocotb/interfaces/cpu.py rename verilog/dv/cocotb/{ => interfaces}/defsParser.py (100%) rename verilog/dv/cocotb/{ => interfaces}/logic_analyzer.py (95%) diff --git a/verilog/dv/cocotb/caravel.py b/verilog/dv/cocotb/caravel.py index f793d19a..c759ccc1 100644 --- a/verilog/dv/cocotb/caravel.py +++ b/verilog/dv/cocotb/caravel.py @@ -20,7 +20,7 @@ from cocotb.handle import ( from itertools import groupby, product -import common +import interfaces.common as common from common import GPIO_MODE from common import MASK_GPIO_CTRL from common import Macros diff --git a/verilog/dv/cocotb/caravel_tests.py b/verilog/dv/cocotb/caravel_tests.py index 10922a96..2dfe83e6 100644 --- a/verilog/dv/cocotb/caravel_tests.py +++ b/verilog/dv/cocotb/caravel_tests.py @@ -7,16 +7,16 @@ import cocotb.log import cocotb.simulator from cocotb_coverage.coverage import * from cocotb.binary import BinaryValue -import caravel -from logic_analyzer import LA -from caravel import GPIO_MODE, Caravel_env +import interfaces.caravel +from interfaces.logic_analyzer import LA +from interfaces.caravel import GPIO_MODE, Caravel_env from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox -import common +import interfaces.common as common import logging -from cpu import RiskV +from interfaces.cpu import RiskV from cocotb.log import SimTimeContextFilter from cocotb.log import SimLogFormatter -from defsParser import Regs +from interfaces.defsParser import Regs from tests.common_functions.Timeout import Timeout from cocotb.result import TestSuccess import inspect diff --git a/verilog/dv/cocotb/cpu.py b/verilog/dv/cocotb/cpu.py index b9da137b..0cb121cd 100644 --- a/verilog/dv/cocotb/cpu.py +++ b/verilog/dv/cocotb/cpu.py @@ -21,7 +21,7 @@ from cocotb.handle import ( from itertools import groupby, product -import common +import interfaces.common as common from common import GPIO_MODE from common import MASK_GPIO_CTRL from common import Macros diff --git a/verilog/dv/cocotb/interfaces/caravel.py b/verilog/dv/cocotb/interfaces/caravel.py new file mode 100644 index 00000000..74f4d2ac --- /dev/null +++ b/verilog/dv/cocotb/interfaces/caravel.py @@ -0,0 +1,432 @@ +import random +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +import cocotb.simulator +from cocotb.handle import SimHandleBase +from cocotb.handle import Force +from cocotb_coverage.coverage import * +from cocotb.binary import BinaryValue +import enum +from cocotb.handle import ( + ConstantObject, + HierarchyArrayObject, + HierarchyObject, + ModifiableObject, + NonHierarchyIndexableObject, + SimHandle, +) + +from itertools import groupby, product + +import interfaces.common as common +from interfaces.common import GPIO_MODE +from interfaces.common import MASK_GPIO_CTRL +from interfaces.common import Macros + +def gpio_mode(gpios_values:list): + gpios=[] + for array in gpios_values: + gpio_value = GPIO_MODE(array[1]).name + for gpio in array[0]: + gpios.append((gpio,gpio_value)) + cocotb.log.info(f'[caravel][gpio_mode] gpios {gpios}') + return gpios + +Carvel_Coverage = coverage_section ( + + CoverPoint("top.caravel.gpio", vname="gpios mode", xf = lambda gpio ,gpio_mode: (gpio,gpio_mode) , + bins = list(product(range(38),[e.name for e in GPIO_MODE]))) + +) + +class Caravel_env: + def __init__(self,dut:SimHandleBase): + self.dut = dut + self.clk = dut.clock_tb + self.caravel_hdl = dut.uut + self.hk_hdl = dut.uut.housekeeping + + """start carvel by insert power then reset""" + async def start_up(self): + await self.power_up() + # await self.disable_csb() # no need for this anymore as default for gpio3 is now pullup + await self.reset() + await self.disable_bins() + common.fill_macros(self.dut.macros) # get macros value + + async def disable_bins(self): + for i in range(38): + common.drive_hdl(self.dut._id(f"bin{i}_en",False),(0,0),0) + + """setup the vdd and vcc power bins""" + async def power_up(self): + cocotb.log.info(f' [caravel] start powering up') + self.set_vdd(0) + self.set_vcc(0) + await ClockCycles(self.clk, 10) + cocotb.log.info(f' [caravel] power up -> connect vdd' ) + self.set_vdd(1) + # await ClockCycles(self.clk, 10) + cocotb.log.info(f' [caravel] power up -> connect vcc' ) + self.set_vcc(1) + await ClockCycles(self.clk, 10) + + """"reset caravel""" + async def reset(self): + cocotb.log.info(f' [caravel] start resetting') + self.dut.resetb_tb.value = 0 + await ClockCycles(self.clk, 20) + self.dut.resetb_tb.value = 1 + await ClockCycles(self.clk, 1) + cocotb.log.info(f' [caravel] finish resetting') + + + def set_vdd(self,value:bool): + self.dut.vddio_tb.value = value + self.dut.vssio_tb.value = 0 + self.dut.vddio_2_tb.value = value + self.dut.vssio_2_tb.value = 0 + self.dut.vdda_tb.value = value + self.dut.vssa_tb.value = 0 + self.dut.vdda1_tb.value = value + self.dut.vssa1_tb.value = 0 + self.dut.vdda1_2_tb.value = value + self.dut.vssa1_2_tb.value = 0 + self.dut.vdda2_tb.value = value + self.dut.vssa2_tb.value = 0 + + def set_vcc(self , value:bool): + self.dut.vccd_tb.value = value + self.dut.vssd_tb.value = 0 + self.dut.vccd1_tb.value = value + self.dut.vssd1_tb.value = 0 + self.dut.vccd2_tb.value = value + self.dut.vssd2_tb.value = 0 + + """drive csb signal bin E8 mprj[3]""" + async def drive_csb(self,bit): + self.drive_gpio_in((3,3),bit) + self.drive_gpio_in((2,2),0) + await ClockCycles(self.clk, 1) + + + """set the spi vsb signal high to disable housekeeping spi transmission bin E8 mprj[3]""" + async def disable_csb(self ): + cocotb.log.info(f' [caravel] disable housekeeping spi transmission') + await self.drive_csb(1) + + """set the spi vsb signal high impedance """ + async def release_csb(self ): + cocotb.log.info(f' [caravel] release housekeeping spi transmission') + self.release_gpio(3) + self.release_gpio(2) + await ClockCycles(self.clk, 1) + + """set the spi vsb signal low to enable housekeeping spi transmission bin E8 mprj[3]""" + async def enable_csb(self ): + cocotb.log.info(f' [caravel] enable housekeeping spi transmission') + await self.drive_csb(0) + + + """return the value of mprj in bits used tp monitor the output gpios value""" + def monitor_gpio(self,bits:tuple): + mprj = self.dut.mprj_io_tb.value + size =mprj.n_bits -1 #size of bins array + mprj_out= self.dut.mprj_io_tb.value[size - bits[0]:size - bits[1]] + if(mprj_out.is_resolvable): + cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {hex(mprj_out)}') + else: + cocotb.log.debug(f' [caravel] Monitor : mprj[{bits[0]}:{bits[1]}] = {mprj_out}') + return mprj_out + + """return the value of management gpio""" + def monitor_mgmt_gpio(self): + data = self.dut.gpio_tb.value + cocotb.log.debug(f' [caravel] Monitor mgmt gpio = {data}') + return data + + """change the configration of the gpios by overwrite their defaults value then reset + need to take at least 1 cycle for reset """ + ### dont use back door accessing + async def configure_gpio_defaults(self,gpios_values: list): + gpio_defaults = self.caravel_hdl.gpio_defaults.value + cocotb.log.info(f' [caravel] start cofigure gpio gpios ') + size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults + # list example [[(gpios),value],[(gpios),value],[(gpios),value]] + for array in gpios_values: + gpio_value = array[1] + for gpio in array[0]: + self.cov_configure_gpios(gpio,gpio_value.name) + gpio_defaults[size - (gpio*13 + 12): size -gpio*13] = gpio_value.value + #cocotb.log.info(f' [caravel] gpio_defaults[{size - (gpio*13 + 12)}:{size -gpio*13}] = {gpio_value.value} ') + self.caravel_hdl.gpio_defaults.value = gpio_defaults + #reset + self.caravel_hdl.gpio_resetn_1_shifted.value = 0 + self.caravel_hdl.gpio_resetn_2_shifted.value = 0 + await ClockCycles(self.clk, 1) + self.caravel_hdl.gpio_resetn_1_shifted.value = 1 + self.caravel_hdl.gpio_resetn_2_shifted.value = 1 + cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ') + self.print_gpios_ctrl_val() + + """change the configration of the gpios by overwrite the register value + in control registers and housekeeping regs, don't consume simulation cycles""" + ### dont use back door accessing + def configure_gpios_regs(self,gpios_values: list): + cocotb.log.info(f' [caravel] start cofigure gpio gpios ') + control_modules = self.control_blocks_paths() + # list example [[(gpios),value],[(gpios),value],[(gpios),value]] + for array in gpios_values: + gpio_value = array[1] + for gpio in array[0]: + self.cov_configure_gpios(gpio,gpio_value.name) + self.gpio_control_reg_write(control_modules[gpio],gpio_value.value) # for control blocks regs + self.caravel_hdl.housekeeping.gpio_configure[gpio].value = gpio_value.value # for house keeping regs + cocotb.log.info(f' [caravel] finish configuring gpios, the curret gpios value: ') + self.print_gpios_ctrl_val() + self.print_gpios_HW_val() + + """dummy function for coverage sampling""" + @Carvel_Coverage + def cov_configure_gpios(self,gpio,gpio_mode): + cocotb.log.debug(f' [caravel] gpio [{gpio}] = {gpio_mode} ') + pass + + def print_gpios_default_val(self,print=1): + gpio_defaults = self.caravel_hdl.gpio_defaults.value + size = gpio_defaults.n_bits -1 #number of bins in gpio_defaults + gpios = [] + for gpio in range(Macros['MPRJ_IO_PADS']): + gpio_value = gpio_defaults[size - (gpio*13 + 12): size -gpio*13] + gpio_enum = GPIO_MODE(gpio_value.integer) + gpios.append((gpio,gpio_enum)) + group_bins = groupby(gpios,key=lambda x: x[1]) + for key,value in group_bins: + gpios=[] + for gpio in list(value): + gpios.append(gpio[0]) + if (print): + cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ') + return gpios + + """print the values return in the gpio of control block mode in GPIO Mode format""" + def print_gpios_ctrl_val(self, print=1): + control_modules = self.control_blocks_paths() + gpios = [] + for i , gpio in enumerate(control_modules): + gpios.append((i,self.gpio_control_reg_read(gpio))) + group_bins = groupby(gpios,key=lambda x: x[1]) + for key,value in group_bins: + gpios=[] + for gpio in list(value): + gpios.append(gpio[0]) + if (print): + cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ') + return gpios + + def _check_gpio_ctrl_eq_HW(self): + assert self.print_gpios_ctrl_val(1) == self.print_gpios_HW_val(1), f'there is an issue while configuration the control block register value isn\'t the same as the house keeping gpio register' + + """print the values return in the gpio of housekeeping block mode in GPIO Mode format""" + def print_gpios_HW_val(self,print=1): + gpios = [] + for pin in range(Macros['MPRJ_IO_PADS']): + gpios.append((pin,GPIO_MODE(self.caravel_hdl.housekeeping.gpio_configure[pin].value))) + group_bins = groupby(gpios,key=lambda x: x[1]) + for key,value in group_bins: + gpios=[] + for gpio in list(value): + gpios.append(gpio[0]) + if (print): + cocotb.log.info(f' [caravel] gpios[{gpios}] are {key} ') + return gpios + + + """return the paths of the control blocks""" + def control_blocks_paths(self)-> list: + car = self.caravel_hdl + control_modules =[car._id("gpio_control_bidir_1[0]",False),car._id("gpio_control_bidir_1[1]",False)] + #add gpio_control_in_1a (GPIO 2 to 7) + for i in range(6): + control_modules.append(car._id(f'gpio_control_in_1a[{i}]',False)) + #add gpio_control_in_1 (GPIO 8 to 18) + for i in range(Macros['MPRJ_IO_PADS_1']-9+1): + control_modules.append(car._id(f'gpio_control_in_1[{i}]',False)) + #add gpio_control_in_2 (GPIO 19 to 34) + for i in range(Macros['MPRJ_IO_PADS_2']-4+1): + control_modules.append(car._id(f'gpio_control_in_2[{i}]',False)) + # Last three GPIOs (spi_sdo, flash_io2, and flash_io3) gpio_control_bidir_2 + for i in range(3): + control_modules.append(car._id(f'gpio_control_bidir_2[{i}]',False)) + return control_modules + + """read the control register and return a GPIO Mode it takes the path to the control reg""" + def gpio_control_reg_read(self,path:SimHandleBase) -> GPIO_MODE: + gpio_mgmt_en = path.mgmt_ena.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value + gpio_out_dis = path.gpio_outenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value + gpio_holdover = path.gpio_holdover.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value + gpio_in_dis = path.gpio_inenb.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value + gpio_mode_sel = path.gpio_ib_mode_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value + gpio_anlg_en = path.gpio_ana_en.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value + gpio_anlg_sel = path.gpio_ana_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value + gpio_anlg_pol = path.gpio_ana_pol.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value + gpio_slow_sel = path.gpio_slow_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value + gpio_vtrip_sel = path.gpio_vtrip_sel.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value + gpio_dgtl_mode = path.gpio_dm.value << MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value + control_reg = (gpio_mgmt_en | gpio_out_dis | gpio_holdover| gpio_in_dis | gpio_mode_sel | gpio_anlg_en + |gpio_anlg_sel|gpio_anlg_pol|gpio_slow_sel|gpio_vtrip_sel|gpio_dgtl_mode) + return(GPIO_MODE(control_reg)) + + """read the control register and return a GPIO Mode it takes the path to the control reg""" + def gpio_control_reg_write(self,path:SimHandleBase,data) : + bits =common.int_to_bin_list(data,14) + path.mgmt_ena.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MGMT_EN.value] + path.gpio_outenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OUT_DIS.value] + path.gpio_holdover.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_OVERRIDE.value] + path.gpio_inenb.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_INP_DIS.value] + path.gpio_ib_mode_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_MOD_SEL.value] + path.gpio_ana_en.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_EN.value] + path.gpio_ana_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_SEL.value] + path.gpio_ana_pol.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_ANLG_POL.value] + path.gpio_slow_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_SLOW.value] + path.gpio_vtrip_sel.value = bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_TRIP.value] + gpio_dm =bits[MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value:MASK_GPIO_CTRL.MASK_GPIO_CTRL_DGTL_MODE.value+3] + gpio_dm =sum(d * 2**i for i, d in enumerate(gpio_dm)) # convert list to binary int + path.gpio_dm.value = gpio_dm + + # """drive the value of mprj bits with spicific data from input pad at the top""" + # def release_gpio(self): + # io = self.caravel_hdl.padframe.mprj_pads.io + # mprj , n_bits = common.signal_valueZ_size(io) + # io.value = mprj + # cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}') + + """drive the value of mprj bits with spicific data from input pad at the top""" + def drive_gpio_in(self,bits,data): + # io = self.caravel_hdl.padframe.mprj_pads.io + # mprj , n_bits = common.signal_value_size(io) + # cocotb.log.debug(f' [caravel] before mprj with {mprj} and data = {data} bit [{n_bits-1-bits[0]}]:[{n_bits-1-bits[1]}]') + # mprj[n_bits-1-bits[0]:n_bits-1-bits[1]] = data + # io.value = mprj + # cocotb.log.info(f' [caravel] drive_gpio_in pad mprj with {mprj}') + data_bits = [] + is_list = isinstance(bits, (list,tuple)) + if is_list : + cocotb.log.debug(f'[caravel] [drive_gpio_in] start bits[1] = {bits[1]} bits[0]= {bits[0]}') + data_bits = BinaryValue(value = data, n_bits =bits[0]-bits[1]+1 ,bigEndian=(bits[0] {data}') + await FallingEdge(self.dut.wb_ack_o) # wait for acknowledge + self.hk_hdl.wb_stb_i.value = 0 + self.hk_hdl.wb_cyc_i.value = 0 + cocotb.log.info(f'Monitor: End writing {hex(addr)} -> {data}') + + + """read from the house keeping registers by back door no need for commands and waiting for the data to show on mprj""" + async def hk_read_backdoor(self,addr): + await RisingEdge(self.clk) + self.hk_hdl.wb_stb_i.value = 1 + self.hk_hdl.wb_cyc_i.value = 1 + self.hk_hdl.wb_sel_i.value = 0 + self.hk_hdl.wb_we_i.value = 0 + self.hk_hdl.wb_adr_i.value = addr + cocotb.log.info(f' [housekeeping] Monitor: Start reading from {hex(addr)}') + await FallingEdge(self.hk_hdl.wb_ack_o) + self.hk_hdl.wb_stb_i.value = 0 + self.hk_hdl.wb_cyc_i.value = 0 + cocotb.log.info(f' [housekeeping] Monitor: read from {hex(addr)} value {(self.hk_hdl.wb_dat_o.value)}') + return self.hk_hdl.wb_dat_o.value + + + diff --git a/verilog/dv/cocotb/common.py b/verilog/dv/cocotb/interfaces/common.py similarity index 100% rename from verilog/dv/cocotb/common.py rename to verilog/dv/cocotb/interfaces/common.py diff --git a/verilog/dv/cocotb/interfaces/cpu.py b/verilog/dv/cocotb/interfaces/cpu.py new file mode 100644 index 00000000..115c0f67 --- /dev/null +++ b/verilog/dv/cocotb/interfaces/cpu.py @@ -0,0 +1,232 @@ +from operator import add +import random +import cocotb +from cocotb.clock import Clock +from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles +import cocotb.log +import cocotb.simulator +from cocotb.handle import SimHandleBase +from cocotb.handle import Force +from cocotb_coverage.coverage import * +from cocotb.binary import BinaryValue +import enum +from cocotb.handle import ( + ConstantObject, + HierarchyArrayObject, + HierarchyObject, + ModifiableObject, + NonHierarchyIndexableObject, + SimHandle, +) + +from itertools import groupby, product + +import interfaces.common as common +from interfaces.common import GPIO_MODE +from interfaces.common import MASK_GPIO_CTRL +from interfaces.common import Macros + +class RiskV: + def __init__(self,dut:SimHandleBase): + self.dut = dut + self.clk = dut.clock_tb + if not Macros['GL']: + self.cpu_hdl = dut.uut.soc.core.VexRiscv + else: + self.cpu_hdl = dut.uut.soc.core + self.debug_hdl = dut.uut.mprj.debug + self.force_reset = 0 + cocotb.scheduler.add(self.force_reset_fun()) + + + """ """ + async def drive_data_with_address(self,address,data,SEL=0xF): + self.cpu_hdl.dBusWishbone_CYC.value = 1 + self.cpu_hdl.iBusWishbone_CYC.value = 0 + self.cpu_hdl.dBusWishbone_STB.value = 1 + self.cpu_hdl.dBusWishbone_WE.value = 1 + self.cpu_hdl.dBusWishbone_SEL.value = SEL + self.cpu_hdl.dBusWishbone_ADR.value = address >> 2 + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data + await RisingEdge(self.cpu_hdl.dBusWishbone_ACK) + await ClockCycles(self.clk, 1) + self.cpu_hdl.dBusWishbone_CYC.value = BinaryValue(value = 'z') + self.cpu_hdl.iBusWishbone_CYC.value = BinaryValue(value = 'z') + self.cpu_hdl.dBusWishbone_STB.value = BinaryValue(value = 'z') + self.cpu_hdl.dBusWishbone_WE.value = BinaryValue(value = 'z') + self.cpu_hdl.dBusWishbone_SEL.value = BinaryValue(value = 'zzzz') + self.cpu_hdl.dBusWishbone_ADR.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_ADR)[0] + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = common.signal_valueZ_size(self.cpu_hdl.dBusWishbone_DAT_MOSI)[0] + + """ """ + async def drive_data2address(self,address,data,SEL=0xF): + cocotb.log.info(f"[RiskV][drive_data2address] start driving address {hex(address)} with {hex(data)}") + # print(dir(self.cpu_hdl)) + dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value + if not Macros['GL']: + iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value + dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value + dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value + if not Macros['GL']: + dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value + else: + dBusWishbone_SEL0 = self.cpu_hdl.net2121.value + dBusWishbone_SEL1 = self.cpu_hdl.net1979.value + dBusWishbone_SEL2 = self.cpu_hdl.net848.value + dBusWishbone_SEL3 = self.cpu_hdl.net1956.value + if not Macros['GL']: + dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value + dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value + self.cpu_hdl.dBusWishbone_CYC.value = 1 + + if not Macros['GL']: + self.cpu_hdl.iBusWishbone_CYC.value = 0 + self.cpu_hdl.dBusWishbone_STB.value = 1 + self.cpu_hdl.dBusWishbone_WE.value = 1 + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_SEL.value = SEL + else: + self.cpu_hdl.net2121.value = (SEL >>0 ) &1 + self.cpu_hdl.net1979.value = (SEL >>1 ) &1 + self.cpu_hdl.net848.value = (SEL >>2 ) &1 + self.cpu_hdl.net1956.value = (SEL >>3 ) &1 + + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_ADR.value = address >> 2 + else: + address_temp = address >> 2 + for i in range(30): + self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1 + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = data + else: + for i in range(32): + self.cpu_hdl._id(f'dBusWishbone_DAT_MOSI[{i}]',False).value = (data >> i) & 1 + + if not Macros['GL']: + await RisingEdge(self.cpu_hdl.dBusWishbone_ACK) + else: + # await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False))) + await RisingEdge(self.cpu_hdl._id("_07019_",False) ) + + await ClockCycles(self.clk, 1) + self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI + self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC + self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB + self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE + self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL + + await ClockCycles(self.clk, 1) + cocotb.log.info(f"[RiskV][drive_data2address] finish driving address {hex(address)} with {hex(data)}") + + """ """ + async def read_address(self,address,SEL=0xF): + cocotb.log.info(f"[RiskV][read_address] start reading address {hex(address)}") + # print(dir(self.cpu_hdl)) + dBusWishbone_CYC = self.cpu_hdl.dBusWishbone_CYC.value + if not Macros['GL']: + iBusWishbone_CYC = self.cpu_hdl.iBusWishbone_CYC.value + dBusWishbone_STB = self.cpu_hdl.dBusWishbone_STB.value + dBusWishbone_WE = self.cpu_hdl.dBusWishbone_WE.value + if not Macros['GL']: + dBusWishbone_SEL = self.cpu_hdl.dBusWishbone_SEL.value + else: + dBusWishbone_SEL0 = self.cpu_hdl.net2121.value + dBusWishbone_SEL1 = self.cpu_hdl.net1979.value + dBusWishbone_SEL2 = self.cpu_hdl.net848.value + dBusWishbone_SEL3 = self.cpu_hdl.net1956.value + if not Macros['GL']: + dBusWishbone_ADR = self.cpu_hdl.dBusWishbone_ADR.value + dBusWishbone_DAT_MOSI = self.cpu_hdl.dBusWishbone_DAT_MOSI.value + self.cpu_hdl.dBusWishbone_CYC.value = 1 + + if not Macros['GL']: + self.cpu_hdl.iBusWishbone_CYC.value = 0 + self.cpu_hdl.dBusWishbone_STB.value = 1 + self.cpu_hdl.dBusWishbone_WE.value = 0 + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_SEL.value = SEL + else: + self.cpu_hdl.net2121.value = (SEL >>0 ) &1 + self.cpu_hdl.net1979.value = (SEL >>1 ) &1 + self.cpu_hdl.net848.value = (SEL >>2 ) &1 + self.cpu_hdl.net1956.value = (SEL >>3 ) &1 + + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_ADR.value = address >> 2 + else: + address_temp = address >> 2 + for i in range(30): + self.cpu_hdl._id(f'dBusWishbone_ADR[{i}]',False).value = (address_temp >> i) & 1 + + + if not Macros['GL']: + await RisingEdge(self.cpu_hdl.dBusWishbone_ACK) + else: + # await RisingEdge(self.cpu_hdl._id("_07019_",False) & (self.cpu_hdl._id("grant[0]",False))) + await RisingEdge(self.cpu_hdl._id("_07019_",False) ) + + await ClockCycles(self.clk, 1) + self.cpu_hdl.dBusWishbone_CYC.value = dBusWishbone_CYC + if not Macros['GL']: + self.cpu_hdl.dBusWishbone_ADR.value = dBusWishbone_ADR + self.cpu_hdl.dBusWishbone_DAT_MOSI.value = dBusWishbone_DAT_MOSI + self.cpu_hdl.iBusWishbone_CYC.value = iBusWishbone_CYC + self.cpu_hdl.dBusWishbone_STB.value = dBusWishbone_STB + self.cpu_hdl.dBusWishbone_WE.value = dBusWishbone_WE + self.cpu_hdl.dBusWishbone_SEL.value = dBusWishbone_SEL + data = self.cpu_hdl.dBusWishbone_DAT_MISO.value + await ClockCycles(self.clk, 1) + cocotb.log.info(f"[RiskV][read_address] finish reading address {hex(address)} data = {data}") + + # return data + return int(str(bin(data.integer)[2:]).zfill(32),2) + # return int(str(bin(data.integer)[2:]).zfill(32)[::-1],2) + + + def read_debug_reg1(self): + return self.debug_hdl.debug_reg_1.value.integer + def read_debug_reg2(self): + return self.debug_hdl.debug_reg_2.value.integer + + # writing debug registers using backdoor because in GL cpu can't be disabled for now because of different netlist names + def write_debug_reg1_backdoor(self,data): + self.debug_hdl.debug_reg_1.value = data + def write_debug_reg2_backdoor(self,data): + self.debug_hdl.debug_reg_2.value = data + + async def force_reset_fun(self): + first_time_force = True + first_time_release = True + while True: + if self.force_reset: + if first_time_force: + cocotb.log.info(f"[RiskV][force_reset_fun] Force CPU reset") + first_time_force = False + first_time_release = True + self.cpu_hdl.reset.value =1 + if not Macros['GL']: + common.drive_hdl(self.cpu_hdl.reset,(0,0),1) + else: + common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),1) + else: + if first_time_release: + first_time_force = True + first_time_release = False + + if not Macros['GL']: + common.drive_hdl(self.cpu_hdl.reset,(0,0),0) + else: + common.drive_hdl(self.cpu_hdl.mgmtsoc_vexriscv_debug_reset,(0,0),0) + cocotb.log.info(f"[RiskV][force_reset_fun] release CPU reset") + + await ClockCycles(self.clk, 1) + def cpu_force_reset(self): + self.force_reset = True + + def cpu_release_reset(self): + self.force_reset = False + \ No newline at end of file diff --git a/verilog/dv/cocotb/defsParser.py b/verilog/dv/cocotb/interfaces/defsParser.py similarity index 100% rename from verilog/dv/cocotb/defsParser.py rename to verilog/dv/cocotb/interfaces/defsParser.py diff --git a/verilog/dv/cocotb/logic_analyzer.py b/verilog/dv/cocotb/interfaces/logic_analyzer.py similarity index 95% rename from verilog/dv/cocotb/logic_analyzer.py rename to verilog/dv/cocotb/interfaces/logic_analyzer.py index 61e9298c..04b3dc23 100644 --- a/verilog/dv/cocotb/logic_analyzer.py +++ b/verilog/dv/cocotb/interfaces/logic_analyzer.py @@ -20,10 +20,10 @@ from cocotb.handle import ( from itertools import groupby, product -import common -from common import GPIO_MODE -from common import MASK_GPIO_CTRL -from common import Macros +import interfaces.common as common +from interfaces.common import GPIO_MODE +from interfaces.common import MASK_GPIO_CTRL +from interfaces.common import Macros class LA: def __init__(self,dut:SimHandleBase): diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_functions.py b/verilog/dv/cocotb/tests/bitbang/bitbang_functions.py index 225f8b43..bc2ced7b 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_functions.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_functions.py @@ -1,4 +1,4 @@ -from defsParser import Regs +from interfaces.defsParser import Regs reg = Regs() diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py index 3a9b3b13..cc2d24de 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE reg = Regs() diff --git a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py index cd4f1abf..5c6ec045 100644 --- a/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py +++ b/verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py @@ -2,13 +2,13 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE -from common import Macros +from interfaces.caravel import GPIO_MODE +from interfaces.common import Macros reg = Regs() diff --git a/verilog/dv/cocotb/tests/common_functions/test_functions.py b/verilog/dv/cocotb/tests/common_functions/test_functions.py index de619163..8cd08f9f 100644 --- a/verilog/dv/cocotb/tests/common_functions/test_functions.py +++ b/verilog/dv/cocotb/tests/common_functions/test_functions.py @@ -3,12 +3,12 @@ import random import cocotb from cocotb.clock import Clock import cocotb.log -import caravel -from logic_analyzer import LA +import interfaces.caravel as caravel +from interfaces.logic_analyzer import LA from wb_models.housekeepingWB.housekeepingWB import HK_whiteBox -import common +import interfaces.common as common import logging -from cpu import RiskV +from interfaces.cpu import RiskV from cocotb.log import SimTimeContextFilter from cocotb.log import SimLogFormatter from tests.common_functions.Timeout import Timeout diff --git a/verilog/dv/cocotb/tests/cpu/cpu_stress.py b/verilog/dv/cocotb/tests/cpu/cpu_stress.py index 29a45080..451b37ad 100644 --- a/verilog/dv/cocotb/tests/cpu/cpu_stress.py +++ b/verilog/dv/cocotb/tests/cpu/cpu_stress.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE reg = Regs() """stress the cpu with heavy processing""" diff --git a/verilog/dv/cocotb/tests/gpio/gpio.py b/verilog/dv/cocotb/tests/gpio/gpio.py index cb1aed80..388034d2 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio.py +++ b/verilog/dv/cocotb/tests/gpio/gpio.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE from cocotb.binary import BinaryValue reg = Regs() diff --git a/verilog/dv/cocotb/tests/gpio/gpio_user.py b/verilog/dv/cocotb/tests/gpio/gpio_user.py index 3266ae4d..d68dad6a 100644 --- a/verilog/dv/cocotb/tests/gpio/gpio_user.py +++ b/verilog/dv/cocotb/tests/gpio/gpio_user.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE from cocotb.binary import BinaryValue reg = Regs() diff --git a/verilog/dv/cocotb/tests/housekeeping/general/pll.py b/verilog/dv/cocotb/tests/housekeeping/general/pll.py index e7dbc1be..b0445da0 100644 --- a/verilog/dv/cocotb/tests/housekeeping/general/pll.py +++ b/verilog/dv/cocotb/tests/housekeeping/general/pll.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE from cocotb.binary import BinaryValue reg = Regs() diff --git a/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py b/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py index b6c5a42f..592aa635 100644 --- a/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py +++ b/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py @@ -3,12 +3,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE from cocotb.binary import BinaryValue from tests.housekeeping.housekeeping_spi.spi_access_functions import * diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py index 29465bd5..635c1271 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -3,12 +3,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE from tests.housekeeping.housekeeping_spi.spi_access_functions import * import json reg = Regs() @@ -27,7 +27,7 @@ async def hk_regs_wr_wb(dut): # write then read for i in range(random.randint(7, 20)): bits_num = 32 - mem = random.choice(['GPIO']) # can't access 'SPI' and 'sys' register from cpu / read or write + mem = random.choice(['GPIO']) # can't access 'SPI' and 'sys' register from interfaces.cpu / read or write key = random.choice(list(regs[mem].keys())) if key == 'base_addr': continue diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py index d970f2a3..34534770 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py @@ -3,8 +3,8 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP diff --git a/verilog/dv/cocotb/tests/irq/IRQ_external.py b/verilog/dv/cocotb/tests/irq/IRQ_external.py index b996b831..ba50c582 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_external.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_external.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE from tests.housekeeping.housekeeping_spi.spi_access_functions import * diff --git a/verilog/dv/cocotb/tests/irq/IRQ_timer.py b/verilog/dv/cocotb/tests/irq/IRQ_timer.py index 348b3994..f71d120b 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_timer.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_timer.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE reg = Regs() """Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" diff --git a/verilog/dv/cocotb/tests/irq/IRQ_uart.py b/verilog/dv/cocotb/tests/irq/IRQ_uart.py index 20863626..f8611627 100644 --- a/verilog/dv/cocotb/tests/irq/IRQ_uart.py +++ b/verilog/dv/cocotb/tests/irq/IRQ_uart.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE async def write_reg_spi(caravelEnv,address,data): await caravelEnv.enable_csb() diff --git a/verilog/dv/cocotb/tests/logicAnalyzer/la.py b/verilog/dv/cocotb/tests/logicAnalyzer/la.py index b845e4a3..72ca532e 100644 --- a/verilog/dv/cocotb/tests/logicAnalyzer/la.py +++ b/verilog/dv/cocotb/tests/logicAnalyzer/la.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE from cocotb.binary import BinaryValue reg = Regs() diff --git a/verilog/dv/cocotb/tests/mem/mem_stress.py b/verilog/dv/cocotb/tests/mem/mem_stress.py index a668591c..c2afd6c2 100644 --- a/verilog/dv/cocotb/tests/mem/mem_stress.py +++ b/verilog/dv/cocotb/tests/mem/mem_stress.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE reg = Regs() """Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" diff --git a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py index 8ddcc7bd..8002ed62 100644 --- a/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py +++ b/verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py @@ -3,12 +3,12 @@ import re import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE reg = Regs() """Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" diff --git a/verilog/dv/cocotb/tests/spi_master/spi_master.py b/verilog/dv/cocotb/tests/spi_master/spi_master.py index f6b469c5..fb565613 100644 --- a/verilog/dv/cocotb/tests/spi_master/spi_master.py +++ b/verilog/dv/cocotb/tests/spi_master/spi_master.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.spi_master.SPI_VIP import read_mem ,SPI_VIP -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE bit_time_ns = 0 diff --git a/verilog/dv/cocotb/tests/temp_partial_test/partial.py b/verilog/dv/cocotb/tests/temp_partial_test/partial.py index bb5a0469..6ee3dfa4 100644 --- a/verilog/dv/cocotb/tests/temp_partial_test/partial.py +++ b/verilog/dv/cocotb/tests/temp_partial_test/partial.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE reg = Regs() """Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" diff --git a/verilog/dv/cocotb/tests/timer/timer.py b/verilog/dv/cocotb/tests/timer/timer.py index 75f99981..5ddaf917 100644 --- a/verilog/dv/cocotb/tests/timer/timer.py +++ b/verilog/dv/cocotb/tests/timer/timer.py @@ -2,12 +2,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE reg = Regs() """Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI.""" diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index f640e8b7..69d9f793 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -3,12 +3,12 @@ import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles,Timer,Edge import cocotb.log -from cpu import RiskV -from defsParser import Regs +from interfaces.cpu import RiskV +from interfaces.defsParser import Regs from cocotb.result import TestSuccess from tests.common_functions.test_functions import * from tests.bitbang.bitbang_functions import * -from caravel import GPIO_MODE +from interfaces.caravel import GPIO_MODE bit_time_ns = 0 diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/HKSPImonitor.py b/verilog/dv/cocotb/wb_models/housekeepingWB/HKSPImonitor.py index baa2003e..bcaddfa5 100644 --- a/verilog/dv/cocotb/wb_models/housekeepingWB/HKSPImonitor.py +++ b/verilog/dv/cocotb/wb_models/housekeepingWB/HKSPImonitor.py @@ -10,7 +10,7 @@ from math import ceil import copy import logging from wb_models.housekeepingWB.HKmonitor import HKmonitor -from common import Macros +from interfaces.common import Macros class HKSPImonitor(Monitor): diff --git a/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingWB.py b/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingWB.py index 7d717ce0..d69c2bb3 100644 --- a/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingWB.py +++ b/verilog/dv/cocotb/wb_models/housekeepingWB/housekeepingWB.py @@ -14,7 +14,7 @@ import logging import fnmatch import copy from cocotb.result import TestFailure -from common import Macros +from interfaces.common import Macros class HK_whiteBox: From 0006ae4f25f48ebb6b977b1312e20d69f9741d11 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 10 Oct 2022 12:06:07 +0000 Subject: [PATCH 75/76] Apply automatic changes to Manifest and README.rst --- manifest | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/manifest b/manifest index 4d44544a..474b884c 100644 --- a/manifest +++ b/manifest @@ -3,7 +3,7 @@ 684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v 1315c3df4decc1a015ec78dfb7df174eb3a74e9a verilog/rtl/__user_project_gpio_example.v 5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v -b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v +ef356bbc8938fef0c1866a709a3bf846d8c7e1e4 verilog/rtl/__user_project_wrapper.v f93c57988b0044d2bff4470a84b5eddc158f2094 verilog/rtl/caravan.v 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v From 71d53b9958a6baffe467e6673df3c91d5600a812 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 10 Oct 2022 06:23:47 -0700 Subject: [PATCH 76/76] added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list --- verilog/dv/cocotb/verify_cocotb.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/verilog/dv/cocotb/verify_cocotb.py b/verilog/dv/cocotb/verify_cocotb.py index a5f56a18..71c5958b 100755 --- a/verilog/dv/cocotb/verify_cocotb.py +++ b/verilog/dv/cocotb/verify_cocotb.py @@ -84,9 +84,9 @@ class RunTest: VERILOG_PATH = os.getenv('VERILOG_PATH') dirs = f'+incdir+\\\"{PDK_ROOT}/{PDK}\\\" ' if self.sim_type == "RTL": - dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/rtl_caravel_vcs.lst\\\" ' + dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/rtl_caravel_vcs.list\\\" ' else: - dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/gl_caravel_vcs.lst\\\" ' + dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/gl_caravel_vcs.list\\\" ' macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS ' if self.test_name == "la":