mirror of https://github.com/efabless/caravel.git
Merge branch 'caravel_redesign' into make_CSB_a_pullup
This commit is contained in:
R. Timothy Edwards
GitHub
commit
cda2c87ae8
File diff suppressed because it is too large
Load Diff
Binary file not shown.
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@ -344,91 +344,95 @@ MACRO gpio_control_block
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|||
END
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||||
END user_gpio_out
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||||
PIN vccd
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||||
DIRECTION INPUT ;
|
||||
DIRECTION INOUT ;
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||||
USE POWER ;
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||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 5.900 49.220 7.500 ;
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||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 22.800 49.220 24.400 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 39.700 49.220 41.300 ;
|
||||
LAYER met4 ;
|
||||
RECT 12.800 2.480 14.400 60.080 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 12.800 5.440 14.400 57.360 ;
|
||||
RECT 37.800 2.480 39.400 60.080 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 37.800 5.200 39.400 57.360 ;
|
||||
LAYER met5 ;
|
||||
RECT 4.360 5.900 51.760 7.500 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 22.800 51.760 24.400 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 39.700 51.760 41.300 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 56.600 51.760 58.200 ;
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||||
END
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||||
END vccd
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||||
PIN vccd1
|
||||
DIRECTION INPUT ;
|
||||
DIRECTION INOUT ;
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||||
USE POWER ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 11.140 49.220 12.740 ;
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||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 28.040 49.220 29.640 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 44.940 49.220 46.540 ;
|
||||
LAYER met4 ;
|
||||
RECT 17.800 2.480 19.400 60.080 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 17.800 5.440 19.400 57.120 ;
|
||||
RECT 42.800 2.480 44.400 60.080 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 42.800 5.440 44.400 57.120 ;
|
||||
LAYER met5 ;
|
||||
RECT 4.360 11.140 51.760 12.740 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 28.040 51.760 29.640 ;
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||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 44.940 51.760 46.540 ;
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||||
END
|
||||
END vccd1
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||||
PIN vssd
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||||
DIRECTION INPUT ;
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||||
DIRECTION INOUT ;
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USE GROUND ;
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PORT
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||||
LAYER met5 ;
|
||||
RECT 4.600 14.350 49.220 15.950 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 31.250 49.220 32.850 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 48.150 49.220 49.750 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 25.300 5.200 26.900 57.360 ;
|
||||
RECT 25.300 2.480 26.900 60.080 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 14.350 51.760 15.950 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 31.250 51.760 32.850 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 48.150 51.760 49.750 ;
|
||||
END
|
||||
END vssd
|
||||
PIN vssd1
|
||||
DIRECTION INPUT ;
|
||||
DIRECTION INOUT ;
|
||||
USE GROUND ;
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 19.590 49.220 21.190 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 36.490 49.220 38.090 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.600 53.390 49.220 54.990 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met4 ;
|
||||
RECT 30.300 5.440 31.900 57.120 ;
|
||||
RECT 30.300 2.480 31.900 60.080 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 19.590 51.760 21.190 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 36.490 51.760 38.090 ;
|
||||
END
|
||||
PORT
|
||||
LAYER met5 ;
|
||||
RECT 4.360 53.390 51.760 54.990 ;
|
||||
END
|
||||
END vssd1
|
||||
PIN zero
|
||||
|
|
@ -440,32 +444,281 @@ MACRO gpio_control_block
|
|||
END
|
||||
END zero
|
||||
OBS
|
||||
LAYER nwell ;
|
||||
RECT 4.410 55.705 49.410 57.310 ;
|
||||
RECT 4.410 50.265 49.410 53.095 ;
|
||||
RECT 4.410 44.825 49.410 47.655 ;
|
||||
RECT 4.410 39.385 49.410 42.215 ;
|
||||
RECT 4.410 33.945 49.410 36.775 ;
|
||||
RECT 4.410 28.505 49.410 31.335 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.600 5.355 49.220 57.205 ;
|
||||
RECT 0.000 64.930 4.265 65.070 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.265 64.930 169.810 65.000 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 64.845 49.815 64.930 ;
|
||||
LAYER li1 ;
|
||||
RECT 49.815 64.845 169.810 64.930 ;
|
||||
LAYER li1 ;
|
||||
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|
||||
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|
||||
LAYER li1 ;
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
LAYER li1 ;
|
||||
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|
||||
LAYER li1 ;
|
||||
RECT 17.450 26.015 169.810 26.185 ;
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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||||
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|
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
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||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
RECT 6.280 60.840 69.600 61.705 ;
|
||||
RECT 6.280 60.200 70.000 60.840 ;
|
||||
|
|
@ -525,9 +778,20 @@ MACRO gpio_control_block
|
|||
RECT 6.280 5.120 70.000 5.760 ;
|
||||
RECT 6.280 3.720 69.600 5.120 ;
|
||||
RECT 6.280 3.080 70.000 3.720 ;
|
||||
RECT 6.280 2.215 69.600 3.080 ;
|
||||
RECT 6.280 1.680 69.600 3.080 ;
|
||||
RECT 6.280 0.175 70.000 1.680 ;
|
||||
LAYER met4 ;
|
||||
RECT 6.280 8.160 11.380 22.240 ;
|
||||
RECT 6.280 60.480 170.000 65.000 ;
|
||||
RECT 6.280 2.080 12.400 60.480 ;
|
||||
RECT 14.800 2.080 17.400 60.480 ;
|
||||
RECT 19.800 2.080 24.900 60.480 ;
|
||||
RECT 27.300 2.080 29.900 60.480 ;
|
||||
RECT 32.300 2.080 37.400 60.480 ;
|
||||
RECT 39.800 2.080 42.400 60.480 ;
|
||||
RECT 44.800 2.080 170.000 60.480 ;
|
||||
RECT 6.280 0.000 170.000 2.080 ;
|
||||
LAYER met5 ;
|
||||
RECT 67.000 0.000 170.000 65.000 ;
|
||||
END
|
||||
END gpio_control_block
|
||||
END LIBRARY
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,18 +1,12 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1649688057
|
||||
<< nwell >>
|
||||
rect 882 11141 9882 11462
|
||||
rect 882 10053 9882 10619
|
||||
rect 882 8965 9882 9531
|
||||
rect 882 7877 9882 8443
|
||||
rect 882 6789 9882 7355
|
||||
rect 882 5701 9882 6267
|
||||
timestamp 1664286915
|
||||
<< obsli1 >>
|
||||
rect 920 1071 9844 11441
|
||||
rect 0 13000 853 13014
|
||||
rect 0 0 33962 13000
|
||||
<< obsm1 >>
|
||||
rect 920 960 16638 11472
|
||||
rect 860 0 34000 13000
|
||||
<< metal2 >>
|
||||
rect 938 12200 994 13000
|
||||
rect 1398 12200 1454 13000
|
||||
|
|
@ -28,20 +22,20 @@ rect 5538 12200 5594 13000
|
|||
rect 5998 12200 6054 13000
|
||||
rect 6458 12200 6514 13000
|
||||
<< obsm2 >>
|
||||
rect 1050 12144 1342 12345
|
||||
rect 1510 12144 1802 12345
|
||||
rect 1970 12144 2262 12345
|
||||
rect 2430 12144 2722 12345
|
||||
rect 2890 12144 3182 12345
|
||||
rect 3350 12144 3642 12345
|
||||
rect 3810 12144 4102 12345
|
||||
rect 4270 12144 4562 12345
|
||||
rect 4730 12144 5022 12345
|
||||
rect 5190 12144 5482 12345
|
||||
rect 5650 12144 5942 12345
|
||||
rect 6110 12144 6402 12345
|
||||
rect 6570 12144 16634 12345
|
||||
rect 994 439 16634 12144
|
||||
rect 1050 12144 1342 13000
|
||||
rect 1510 12144 1802 13000
|
||||
rect 1970 12144 2262 13000
|
||||
rect 2430 12144 2722 13000
|
||||
rect 2890 12144 3182 13000
|
||||
rect 3350 12144 3642 13000
|
||||
rect 3810 12144 4102 13000
|
||||
rect 4270 12144 4562 13000
|
||||
rect 4730 12144 5022 13000
|
||||
rect 5190 12144 5482 13000
|
||||
rect 5650 12144 5942 13000
|
||||
rect 6110 12144 6402 13000
|
||||
rect 6570 12144 34000 13000
|
||||
rect 940 0 34000 12144
|
||||
<< metal3 >>
|
||||
rect 14000 12248 34000 12368
|
||||
rect 14000 11840 34000 11960
|
||||
|
|
@ -132,29 +126,41 @@ rect 1256 1152 13920 1432
|
|||
rect 1256 1024 14000 1152
|
||||
rect 1256 744 13920 1024
|
||||
rect 1256 616 14000 744
|
||||
rect 1256 443 13920 616
|
||||
rect 1256 336 13920 616
|
||||
rect 1256 35 14000 336
|
||||
<< metal4 >>
|
||||
rect 2560 1088 2880 11472
|
||||
rect 3560 1088 3880 11424
|
||||
rect 5060 1040 5380 11472
|
||||
rect 6060 1088 6380 11424
|
||||
rect 7560 1040 7880 11472
|
||||
rect 8560 1088 8880 11424
|
||||
rect 2560 496 2880 12016
|
||||
rect 3560 496 3880 12016
|
||||
rect 5060 496 5380 12016
|
||||
rect 6060 496 6380 12016
|
||||
rect 7560 496 7880 12016
|
||||
rect 8560 496 8880 12016
|
||||
<< obsm4 >>
|
||||
rect 1256 1632 2276 4448
|
||||
rect 1256 12096 34000 13000
|
||||
rect 1256 416 2480 12096
|
||||
rect 2960 416 3480 12096
|
||||
rect 3960 416 4980 12096
|
||||
rect 5460 416 5980 12096
|
||||
rect 6460 416 7480 12096
|
||||
rect 7960 416 8480 12096
|
||||
rect 8960 416 34000 12096
|
||||
rect 1256 0 34000 416
|
||||
<< metal5 >>
|
||||
rect 920 10678 9844 10998
|
||||
rect 920 9630 9844 9950
|
||||
rect 920 8988 9844 9308
|
||||
rect 920 7940 9844 8260
|
||||
rect 920 7298 9844 7618
|
||||
rect 920 6250 9844 6570
|
||||
rect 920 5608 9844 5928
|
||||
rect 920 4560 9844 4880
|
||||
rect 920 3918 9844 4238
|
||||
rect 920 2870 9844 3190
|
||||
rect 920 2228 9844 2548
|
||||
rect 920 1180 9844 1500
|
||||
rect 872 11320 10352 11640
|
||||
rect 872 10678 10352 10998
|
||||
rect 872 9630 10352 9950
|
||||
rect 872 8988 10352 9308
|
||||
rect 872 7940 10352 8260
|
||||
rect 872 7298 10352 7618
|
||||
rect 872 6250 10352 6570
|
||||
rect 872 5608 10352 5928
|
||||
rect 872 4560 10352 4880
|
||||
rect 872 3918 10352 4238
|
||||
rect 872 2870 10352 3190
|
||||
rect 872 2228 10352 2548
|
||||
rect 872 1180 10352 1500
|
||||
<< obsm5 >>
|
||||
rect 13400 0 34000 13000
|
||||
<< labels >>
|
||||
rlabel metal2 s 938 12200 994 13000 6 gpio_defaults[0]
|
||||
port 1 nsew signal input
|
||||
|
|
@ -240,50 +246,52 @@ rlabel metal3 s 14000 11840 34000 11960 6 user_gpio_oeb
|
|||
port 41 nsew signal input
|
||||
rlabel metal3 s 14000 12248 34000 12368 6 user_gpio_out
|
||||
port 42 nsew signal input
|
||||
rlabel metal5 s 920 1180 9844 1500 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s 920 4560 9844 4880 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s 920 7940 9844 8260 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal4 s 2560 1088 2880 11472 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal4 s 7560 1040 7880 11472 6 vccd
|
||||
port 43 nsew power input
|
||||
rlabel metal5 s 920 2228 9844 2548 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal5 s 920 5608 9844 5928 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal5 s 920 8988 9844 9308 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal4 s 3560 1088 3880 11424 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal4 s 8560 1088 8880 11424 6 vccd1
|
||||
port 44 nsew power input
|
||||
rlabel metal5 s 920 2870 9844 3190 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal5 s 920 6250 9844 6570 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal5 s 920 9630 9844 9950 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal4 s 5060 1040 5380 11472 6 vssd
|
||||
port 45 nsew ground input
|
||||
rlabel metal5 s 920 3918 9844 4238 6 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal5 s 920 7298 9844 7618 6 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal5 s 920 10678 9844 10998 6 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal4 s 6060 1088 6380 11424 6 vssd1
|
||||
port 46 nsew ground input
|
||||
rlabel metal4 s 2560 496 2880 12016 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal4 s 7560 496 7880 12016 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 1180 10352 1500 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 4560 10352 4880 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 7940 10352 8260 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal5 s 872 11320 10352 11640 6 vccd
|
||||
port 43 nsew power bidirectional
|
||||
rlabel metal4 s 3560 496 3880 12016 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal4 s 8560 496 8880 12016 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal5 s 872 2228 10352 2548 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal5 s 872 5608 10352 5928 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal5 s 872 8988 10352 9308 6 vccd1
|
||||
port 44 nsew power bidirectional
|
||||
rlabel metal4 s 5060 496 5380 12016 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal5 s 872 2870 10352 3190 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal5 s 872 6250 10352 6570 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal5 s 872 9630 10352 9950 6 vssd
|
||||
port 45 nsew ground bidirectional
|
||||
rlabel metal4 s 6060 496 6380 12016 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal5 s 872 3918 10352 4238 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal5 s 872 7298 10352 7618 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal5 s 872 10678 10352 10998 6 vssd1
|
||||
port 46 nsew ground bidirectional
|
||||
rlabel metal3 s 14000 416 34000 536 6 zero
|
||||
port 47 nsew signal output
|
||||
<< properties >>
|
||||
string FIXED_BBOX 0 0 34000 13000
|
||||
string LEFclass BLOCK
|
||||
string LEFview TRUE
|
||||
string GDS_END 563480
|
||||
string GDS_FILE /home/marwan/work/caravel_user_project/caravel/openlane/gpio_control_block/runs/gpio_control_block/results/finishing/gpio_control_block.magic.gds
|
||||
string GDS_START 197174
|
||||
string GDS_END 572784
|
||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_09_27_06_53/results/signoff/gpio_control_block.magic.gds
|
||||
string GDS_START 204218
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
4
manifest
4
manifest
|
|
@ -13,10 +13,10 @@ d0c5cf9260783b1a88c0b772c2e3cee3dcd0cf76 verilog/rtl/chip_io.v
|
|||
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
|
||||
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
|
||||
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
||||
41f899d8a8510f933e08e41d1b4ac13d84191f38 verilog/rtl/gpio_control_block.v
|
||||
60d2384a91301fec5721953d87931193681822c4 verilog/rtl/gpio_control_block.v
|
||||
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
|
||||
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
||||
1659246cc676cbf1469464178d82d8d94f363af5 verilog/rtl/housekeeping.v
|
||||
8dafb824eae7173e43f4e2f31c7470a6a1272c79 verilog/rtl/housekeeping.v
|
||||
3030f955d5f110d24012bd1562c0e18c1a0d04e2 verilog/rtl/housekeeping_spi.v
|
||||
0f3db7cf4d68971ba4e286c8706b20c9252d1f98 verilog/rtl/mgmt_protect.v
|
||||
3b1ff20593bc386d13f5e2cf1571f08121889957 verilog/rtl/mgmt_protect_hv.v
|
||||
|
|
|
|||
|
|
@ -13,74 +13,77 @@
|
|||
#
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
BLOCKS = $(shell find * -maxdepth 0 -type d)
|
||||
CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
|
||||
CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
|
||||
MAKEFLAGS+=--warn-undefined-variables
|
||||
|
||||
export OPENLANE_RUN_TAG = $(shell date '+%y_%m_%d_%H_%M')
|
||||
OPENLANE_TAG ?= 2021.11.23_01.42.34
|
||||
OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
|
||||
OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
|
||||
OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -it -file ./$*/interactive.tcl"
|
||||
designs = $(shell find * -maxdepth 0 -type d)
|
||||
current_design = null
|
||||
|
||||
all: $(BLOCKS)
|
||||
openlane_cmd = \
|
||||
"flow.tcl \
|
||||
-design $$(realpath ./$*) \
|
||||
-save_path $$(realpath ..) \
|
||||
-save \
|
||||
-tag $(OPENLANE_RUN_TAG) \
|
||||
-overwrite"
|
||||
openlane_cmd_interactive = "flow.tcl -it -file $$(realpath ./$*/interactive.tcl)"
|
||||
|
||||
$(CONFIG) :
|
||||
@echo "Missing $@. Please create a configuration for that design"
|
||||
@exit 1
|
||||
docker_mounts = \
|
||||
-v $$(realpath $(PWD)/..):$$(realpath $(PWD)/..) \
|
||||
-v $(PDK_ROOT):$(PDK_ROOT) \
|
||||
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
|
||||
-v $(PWD):$(PWD) \
|
||||
-v $(HOME):$(HOME)
|
||||
|
||||
.PHONY: $(BLOCKS)
|
||||
$(BLOCKS) : % : ./%/config.tcl
|
||||
ifeq ($(OPENLANE_ROOT),)
|
||||
@echo "Please export OPENLANE_ROOT"
|
||||
@exit 1
|
||||
docker_env = \
|
||||
-e PDK_ROOT=$(PDK_ROOT) \
|
||||
-e PDK=$(PDK) \
|
||||
-e MISMATCHES_OK=1 \
|
||||
-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
|
||||
-e OPENLANE_RUN_TAG=$(OPENLANE_RUN_TAG) \
|
||||
-w $(PWD)
|
||||
|
||||
ifneq ($(MCW_ROOT),)
|
||||
docker_env += -e MCW_ROOT=$(MCW_ROOT)
|
||||
docker_mounts += -v $(MCW_ROOT):$(MCW_ROOT)
|
||||
endif
|
||||
ifeq ($(PDK_ROOT),)
|
||||
@echo "Please export PDK_ROOT"
|
||||
@exit 1
|
||||
endif
|
||||
@echo "###############################################"
|
||||
@sleep 1
|
||||
|
||||
@if [ -f ./$*/interactive.tcl ]; then\
|
||||
docker run --rm -v $(OPENLANE_ROOT):/openlane \
|
||||
-v $(PDK_ROOT):$(PDK_ROOT) \
|
||||
-v $(PWD)/..:$(PWD)/.. \
|
||||
-v $(MCW_ROOT):$(MCW_ROOT) \
|
||||
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
|
||||
-e MCW_ROOT=$(MCW_ROOT) \
|
||||
-e PDK_ROOT=$(PDK_ROOT) \
|
||||
-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
|
||||
-e PDK=$(PDK) \
|
||||
-e TEST_MISMATCHES=tools \
|
||||
-e MISMATCHES_OK=1 \
|
||||
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
|
||||
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
|
||||
else\
|
||||
docker run --rm -v $(OPENLANE_ROOT):/openlane \
|
||||
-v $(PDK_ROOT):$(PDK_ROOT) \
|
||||
-v $(PWD)/..:$(PWD)/.. \
|
||||
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
|
||||
-v $(MCW_ROOT):$(MCW_ROOT) \
|
||||
-e MCW_ROOT=$(MCW_ROOT) \
|
||||
-e PDK=$(PDK) \
|
||||
-e PDK_ROOT=$(PDK_ROOT) \
|
||||
-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
|
||||
-e TEST_MISMATCHES=tools \
|
||||
-e MISMATCHES_OK=1 \
|
||||
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
|
||||
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
|
||||
fi
|
||||
mkdir -p ../signoff/$*/
|
||||
cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
|
||||
cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
|
||||
cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
|
||||
docker_startup_mode = $(shell test -t 0 && echo "-it" || echo "--rm" )
|
||||
docker_run = \
|
||||
docker run $(docker_startup_mode) \
|
||||
$(docker_mounts) \
|
||||
$(docker_env) \
|
||||
-u $(shell id -u $(USER)):$(shell id -g $(USER))
|
||||
|
||||
list:
|
||||
@echo $(designs)
|
||||
|
||||
.PHONY: $(designs)
|
||||
$(designs) : % : ./%/config.tcl
|
||||
ifneq (,$(wildcard ./$(MAKECMDGOALS)/interactive.tcl)))
|
||||
$(docker_run) \
|
||||
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_interactive)
|
||||
else
|
||||
# $(MAKECMDGOALS)
|
||||
mkdir -p ./$*/runs/$(OPENLANE_RUN_TAG)
|
||||
rm -rf ./$*/runs/$*
|
||||
ln -s $$(realpath ./$*/runs/$(OPENLANE_RUN_TAG)) ./$*/runs/$*
|
||||
$(docker_run) \
|
||||
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd)
|
||||
endif
|
||||
@mkdir -p ../signoff/$*/
|
||||
@cp ./$*/runs/$(OPENLANE_RUN_TAG)/OPENLANE_VERSION ../signoff/$*/
|
||||
@cp ./$*/runs/$(OPENLANE_RUN_TAG)/PDK_SOURCES ../signoff/$*/
|
||||
@cp ./$*/runs/$(OPENLANE_RUN_TAG)/reports/*.csv ../signoff/$*/
|
||||
|
||||
.PHONY: openlane
|
||||
openlane: check-openlane-env
|
||||
if [ -d "$(OPENLANE_ROOT)" ]; then\
|
||||
echo "Deleting exisiting $(OPENLANE_ROOT)" && \
|
||||
rm -rf $(OPENLANE_ROOT) && sleep 2; \
|
||||
fi
|
||||
fi
|
||||
git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
|
||||
cd $(OPENLANE_ROOT) && \
|
||||
export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
|
||||
|
|
@ -93,16 +96,3 @@ ifeq ($(OPENLANE_ROOT),)
|
|||
@echo "Please export OPENLANE_ROOT"
|
||||
@exit 1
|
||||
endif
|
||||
|
||||
FORCE:
|
||||
|
||||
clean:
|
||||
@echo "Use clean_all to clean everything :)"
|
||||
|
||||
clean_all: $(CLEAN)
|
||||
|
||||
$(CLEAN): clean-% :
|
||||
rm -rf runs/$*
|
||||
rm -rf ../gds/$**
|
||||
rm -rf ../mag/$**
|
||||
rm -rf ../lef/$**
|
||||
|
|
|
|||
|
|
@ -14,6 +14,22 @@ create_clock -name serial_load -period 50.0000 [get_ports {serial_load}]
|
|||
set_clock_transition 0.1500 [get_clocks {serial_load}]
|
||||
set_clock_uncertainty 0.4000 serial_load
|
||||
set_propagated_clock [get_clocks {serial_load}]
|
||||
|
||||
set_max_transition 1.25 [current_design]
|
||||
set clk_input [get_port serial_clock)]
|
||||
set clk_indx [lsearch [all_inputs] $clk_input]
|
||||
set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx ""]
|
||||
|
||||
set_input_transition 5.0 $all_inputs_wo_clk
|
||||
#set_driving_cell -lib_cell sky130_fd_sc_hd__buf_1 -pin {X} -input_transition_rise 1.0000 -input_transition_fall 1.0000 [all_inputs]
|
||||
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
set_max_fanout 7.0000 [current_design]
|
||||
#
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [all_outputs]
|
||||
set_load -pin_load 0.25 [all_outputs]
|
||||
#
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[0]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[10]}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {gpio_defaults[11]}]
|
||||
|
|
@ -35,76 +51,3 @@ set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports
|
|||
#set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_oeb}]
|
||||
set_input_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {mgmt_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {one}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_en}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_pol}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ana_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[0]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[1]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_dm[2]}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_holdover}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_inenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_outenb}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_slow_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {resetn_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_clock_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_data_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {serial_load_out}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {user_gpio_in}]
|
||||
set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_ports {zero}]
|
||||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_in}]
|
||||
set_load -pin_load 0.0334 [get_ports {one}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_en}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_pol}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_holdover}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_inenb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_outenb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_slow_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {resetn_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_clock_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_data_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_load_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {user_gpio_in}]
|
||||
set_load -pin_load 0.0334 [get_ports {zero}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_gpio_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetn}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_clock}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_data_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_load}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
# Copyright 2020 Efabless Corporation
|
||||
#
|
||||
# Licensed under the Apache License, Version 2.0 (the "License");
|
||||
# you may not use this file except in compliance with the License.
|
||||
# You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS,
|
||||
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
# See the License for the specific language governing permissions and
|
||||
# limitations under the License.
|
||||
|
||||
foreach lib $::env(LIB_RESIZER_OPT) {
|
||||
read_liberty $lib
|
||||
}
|
||||
|
||||
if { [info exists ::env(EXTRA_LIBS) ] } {
|
||||
foreach lib $::env(EXTRA_LIBS) {
|
||||
read_liberty $lib
|
||||
}
|
||||
}
|
||||
|
||||
if {[catch {read_lef $::env(MERGED_LEF)} errmsg]} {
|
||||
puts stderr $errmsg
|
||||
exit 1
|
||||
}
|
||||
|
||||
if {[catch {read_def $::env(CURRENT_DEF)} errmsg]} {
|
||||
puts stderr $errmsg
|
||||
exit 1
|
||||
}
|
||||
source $::env(SCRIPTS_DIR)/openroad/insert_buffer.tcl
|
||||
puts "inserting buffer on serial_clock_out"
|
||||
set serial_clock_out_instance [get_property [get_cells -of_objects serial_clock_out] name]
|
||||
insert_buffer ${serial_clock_out_instance}/X ITerm sky130_fd_sc_hd__clkbuf_16 serial_clock_out_buffered serial_clock_out_buffer
|
||||
|
||||
puts "inserting buffer on serial_load_out"
|
||||
set serial_load_out_instance [get_property [get_cells -of_objects serial_load_out] name]
|
||||
insert_buffer ${serial_load_out_instance}/X ITerm sky130_fd_sc_hd__clkbuf_16 serial_load_out_buffered serial_load_out_buffer
|
||||
|
||||
# .HI(one),
|
||||
# .LO(zero));
|
||||
puts "inserting buffer on one"
|
||||
set const_instance [get_property [get_cells -of_objects one] name]
|
||||
insert_buffer ${const_instance}/HI ITerm sky130_fd_sc_hd__buf_16 one_buffered one_buffer
|
||||
|
||||
puts "inserting buffer on zero"
|
||||
set const_instance [get_property [get_cells -of_objects zero] name]
|
||||
insert_buffer ${const_instance}/LO ITerm sky130_fd_sc_hd__buf_16 zero_buffered zero_buffer
|
||||
|
||||
write_def $::env(SAVE_DEF)
|
||||
|
|
@ -13,67 +13,72 @@
|
|||
# limitations under the License.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
|
||||
set ::env(DESIGN_NAME) gpio_control_block
|
||||
|
||||
set ::env(VERILOG_FILES) "\
|
||||
$script_dir/../../verilog/rtl/defines.v\
|
||||
$script_dir/../../verilog/rtl/gpio_control_block.v"
|
||||
$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
|
||||
$::env(DESIGN_DIR)/../../verilog/rtl/gpio_control_block.v"
|
||||
|
||||
|
||||
set ::env(PL_TARGET_DENSITY) 0.8
|
||||
set ::env(CLOCK_PORT) "serial_clock"
|
||||
|
||||
set ::env(FP_DEF_TEMPLATE) "$::env(DESIGN_DIR)/template/gpio_control_block.def"
|
||||
|
||||
# This needs to be half the mgmt_core clock frequency
|
||||
set ::env(CLOCK_PERIOD) "50"
|
||||
|
||||
set ::env(VDD_NETS) "vccd vccd1"
|
||||
set ::env(GND_NETS) "vssd vssd1"
|
||||
|
||||
set ::env(BASE_SDC_FILE) $script_dir/base.sdc
|
||||
set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
|
||||
|
||||
## Synthesis
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
|
||||
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
|
||||
set ::env(SYNTH_STRATEGY) "DELAY 0"
|
||||
set ::env(SYNTH_STRATEGY) "AREA 0"
|
||||
|
||||
## Floorplan
|
||||
set ::env(FP_SIZING) absolute
|
||||
set ::env(DIE_AREA) "0 0 170 65"
|
||||
|
||||
set ::env(FP_IO_VEXTEND) 0
|
||||
set ::env(FP_IO_HEXTEND) 0
|
||||
set ::env(FP_IO_HLENGTH) 100
|
||||
set ::env(FP_IO_VLENGTH) 4
|
||||
|
||||
set ::env(RIGHT_MARGIN_MULT) 262
|
||||
set ::env(RIGHT_MARGIN_MULT) 257
|
||||
set ::env(LEFT_MARGIN_MULT) 10
|
||||
set ::env(TOP_MARGIN_MULT) 2
|
||||
set ::env(BOTTOM_MARGIN_MULT) 2
|
||||
set ::env(TOP_MARGIN_MULT) 1
|
||||
set ::env(BOTTOM_MARGIN_MULT) 1
|
||||
|
||||
set ::env(CELL_PAD) 0
|
||||
set ::env(DPL_CELL_PADDING) 0
|
||||
set ::env(GPL_CELL_PADDING) 0
|
||||
|
||||
## PDN
|
||||
set ::env(PDN_CFG) $script_dir/pdn.tcl
|
||||
set ::env(FP_PDN_MACRO_HOOKS) "\
|
||||
gpio_logic_high vccd1 vssd1 vccd1 vssd1"
|
||||
|
||||
set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
|
||||
set ::env(FP_PDN_AUTO_ADJUST) 0
|
||||
|
||||
set ::env(FP_PDN_VWIDTH) 1.6
|
||||
set ::env(FP_PDN_HWIDTH) 1.6
|
||||
|
||||
set ::env(FP_PDN_HORIZONTAL_HALO) 2
|
||||
set ::env(FP_PDN_VERTICAL_HALO) 2
|
||||
set ::env(FP_PDN_HORIZONTAL_HALO) 0
|
||||
set ::env(FP_PDN_VERTICAL_HALO) 0
|
||||
|
||||
set ::env(FP_PDN_CHECK_NODES) 0
|
||||
|
||||
# these PDN vars are mostly hard coded in the custom ./pdn.tcl file
|
||||
# keeping them in case openlane depends on the variable definition
|
||||
set ::env(FP_PDN_HOFFSET) 1.5
|
||||
set ::env(FP_PDN_VOFFSET) 9.0
|
||||
|
||||
set ::env(FP_PDN_HPITCH) 16.9
|
||||
set ::env(FP_PDN_HPITCH) 20
|
||||
set ::env(FP_PDN_VPITCH) 25
|
||||
|
||||
set ::env(FP_PDN_VSPACING) 3.4
|
||||
set ::env(FP_PDN_HSPACING) 3.4
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.7
|
||||
set ::env(PL_TARGET_DENSITY) 0.9
|
||||
# for some reason resizer is leaving a floating net after running repair_tie_fanout command
|
||||
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 0
|
||||
|
||||
|
|
@ -81,19 +86,19 @@ set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 0
|
|||
# set ::env(DONT_BUFFER_PORTS) "mgmt_gpio_in"
|
||||
|
||||
## Routing
|
||||
set ::env(GLB_RT_MINLAYER) 2
|
||||
set ::env(GLB_RT_MAXLAYER) 4
|
||||
set ::env(GLB_RT_ADJUSTMENT) 0.05
|
||||
set ::env(GRT_MINLAYER) 2
|
||||
set ::env(GRT_MAXLAYER) 4
|
||||
set ::env(GRT_ADJUSTMENT) 0.05
|
||||
|
||||
# Add obstructions on the areas that will lie underneath the padframe
|
||||
set ::env(GLB_RT_OBS) "\
|
||||
set ::env(GRT_OBS) "\
|
||||
li1 0 0 16.79500 30.02500,
|
||||
li1 0 29.96500 4.26500 65.07000,
|
||||
li1 4.21500 57.40500 49.81500 64.93000,
|
||||
li1 16.83000 0 49.41000 5.24000,
|
||||
li1 49.000 0 169.81000 64.84500,
|
||||
met5 67 0 170 65,
|
||||
met4 67 0 170 65,
|
||||
met4 49 0 170 65,
|
||||
met2 120 0 170 65,
|
||||
met1 120 0 170 65"
|
||||
|
||||
|
|
@ -104,28 +109,48 @@ set ::env(FP_TAP_HORIZONTAL_HALO) {2}
|
|||
set ::env(FP_TAP_VERTICAL_HALO) {2}
|
||||
|
||||
## Internal macros
|
||||
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
|
||||
set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
|
||||
|
||||
set ::env(VERILOG_FILES_BLACKBOX) "\
|
||||
$script_dir/../../verilog/rtl/gpio_logic_high.v"
|
||||
$::env(DESIGN_DIR)/../../verilog/rtl/gpio_logic_high.v"
|
||||
|
||||
set ::env(EXTRA_LEFS) "\
|
||||
$script_dir/../../lef/gpio_logic_high.lef"
|
||||
$::env(DESIGN_DIR)/../../lef/gpio_logic_high.lef"
|
||||
|
||||
set ::env(EXTRA_GDS_FILES) "\
|
||||
$script_dir/../../gds/gpio_logic_high.gds"
|
||||
$::env(DESIGN_DIR)/../../gds/gpio_logic_high.gds"
|
||||
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
|
||||
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
|
||||
#Placement
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
|
||||
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
|
||||
#Post cts
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
|
||||
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 1
|
||||
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 1
|
||||
|
||||
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 1
|
||||
set ::env(PL_RESIZER_MAX_CAP_MARGIN) 1
|
||||
|
||||
set ::env(CLOCK_TREE_SYNTH) 1
|
||||
set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/template/gpio_control_block.def
|
||||
set ::env(SYNTH_BUFFERING) 0
|
||||
set ::env(SYNTH_SIZING) 0
|
||||
# 0.07 ns 70 ps
|
||||
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.05
|
||||
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
|
||||
#set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 2
|
||||
|
||||
set ::env(QUIT_ON_MAGIC_DRC) 0
|
||||
set ::env(QUIT_ON_LVS_ERROR) 0
|
||||
# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.07
|
||||
# set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
|
||||
# set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 2
|
||||
|
||||
set ::env(SYNTH_EXTRA_MAPPING_FILE) $script_dir/yosys_mapping.v
|
||||
set ::env(QUIT_ON_MAGIC_DRC) 1
|
||||
set ::env(QUIT_ON_LVS_ERROR) 1
|
||||
|
||||
set ::env(SYNTH_EXTRA_MAPPING_FILE) $::env(DESIGN_DIR)/yosys_mapping.v
|
||||
|
||||
set ::env(DECAP_CELL) {sky130_fd_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST) $::env(DESIGN_DIR)/drc_exclude_list.txt
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) $::env(DESIGN_DIR)/drc_exclude_list.txt
|
||||
set ::env(RSZ_DONT_TOUCH) "user_gpio_out user_gpio_oeb serial_clock_out serial_load_out gpio_defaults*"
|
||||
set ::env(FP_PDN_SKIPTRIM) 1
|
||||
|
|
|
|||
|
|
@ -0,0 +1,37 @@
|
|||
|
||||
sky130_fd_sc_hd__clkdlybuf4s15_1
|
||||
sky130_fd_sc_hd__clkdlybuf4s18_1
|
||||
sky130_fd_sc_hd__lpflow_bleeder_1
|
||||
sky130_fd_sc_hd__lpflow_clkbufkapwr_1
|
||||
sky130_fd_sc_hd__lpflow_clkbufkapwr_16
|
||||
sky130_fd_sc_hd__lpflow_clkbufkapwr_2
|
||||
sky130_fd_sc_hd__lpflow_clkbufkapwr_4
|
||||
sky130_fd_sc_hd__lpflow_clkbufkapwr_8
|
||||
sky130_fd_sc_hd__lpflow_clkinvkapwr_1
|
||||
sky130_fd_sc_hd__lpflow_clkinvkapwr_16
|
||||
sky130_fd_sc_hd__lpflow_clkinvkapwr_2
|
||||
sky130_fd_sc_hd__lpflow_clkinvkapwr_4
|
||||
sky130_fd_sc_hd__lpflow_clkinvkapwr_8
|
||||
sky130_fd_sc_hd__lpflow_decapkapwr_12
|
||||
sky130_fd_sc_hd__lpflow_decapkapwr_3
|
||||
sky130_fd_sc_hd__lpflow_decapkapwr_4
|
||||
sky130_fd_sc_hd__lpflow_decapkapwr_6
|
||||
sky130_fd_sc_hd__lpflow_decapkapwr_8
|
||||
sky130_fd_sc_hd__lpflow_inputiso0n_1
|
||||
sky130_fd_sc_hd__lpflow_inputiso0p_1
|
||||
sky130_fd_sc_hd__lpflow_inputiso1n_1
|
||||
sky130_fd_sc_hd__lpflow_inputiso1p_1
|
||||
sky130_fd_sc_hd__lpflow_inputisolatch_1
|
||||
sky130_fd_sc_hd__lpflow_isobufsrc_1
|
||||
sky130_fd_sc_hd__lpflow_isobufsrc_16
|
||||
sky130_fd_sc_hd__lpflow_isobufsrc_2
|
||||
sky130_fd_sc_hd__lpflow_isobufsrc_4
|
||||
sky130_fd_sc_hd__lpflow_isobufsrc_8
|
||||
sky130_fd_sc_hd__lpflow_isobufsrckapwr_16
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2
|
||||
sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4
|
||||
|
|
@ -14,74 +14,101 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
package require openlane
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
set save_path $script_dir/../..
|
||||
|
||||
prep -design $script_dir -tag gpio_control_block -overwrite
|
||||
proc custom_run_placement {args} {
|
||||
global SCRIPT_DIR
|
||||
global_placement_or
|
||||
|
||||
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
|
||||
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
|
||||
set log [index_file $::env(placement_logs)/resizer-1.log]
|
||||
set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/resizer-1.def]
|
||||
set ::env(SAVE_SDC) [index_file $::env(placement_tmpfiles)/resizer-1.sdc]
|
||||
run_openroad_script $::env(SCRIPTS_DIR)/openroad/resizer.tcl -indexed_log $log
|
||||
set_def $::env(SAVE_DEF)
|
||||
set ::env(CURRENT_SDC) $::env(SAVE_SDC)
|
||||
|
||||
set dont_use_buffers "sky130_fd_sc_hd__probe* sky130_fd_sc_hd__bufbuf* sky130_fd_sc_hd__buf_1 sky130_fd_sc_hd__buf_2 sky130_fd_sc_hd__buf_4 sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_8 sky130_fd_sc_hd__buf_12 sky130_fd_sc_hd__clkbuf* "
|
||||
set dont_use_old ""
|
||||
if { [info exists ::env(DONT_USE_CELLS)] } {
|
||||
set ::env(DONT_USE_CELLS) "$::env(DONT_USE_CELLS) $dont_use_buffers"
|
||||
} else {
|
||||
set ::env(DONT_USE_CELLS) "$dont_use_buffers"
|
||||
set dont_use_old ::env(DONT_USE_CELLS)
|
||||
}
|
||||
set dont_touch_old "$::env(RSZ_DONT_TOUCH)"
|
||||
set ::env(RSZ_DONT_TOUCH) "$::env(RSZ_DONT_TOUCH) mgmt_gpio_out mgmt_gpio_oeb pad_gpio_in user_gpio_oeb user_gpio_out"
|
||||
set log [index_file $::env(placement_logs)/resizer-2.log]
|
||||
set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/resizer-2.def]
|
||||
set ::env(SAVE_SDC) [index_file $::env(placement_tmpfiles)/resizer-2.sdc]
|
||||
run_openroad_script $SCRIPT_DIR/buffer.tcl -indexed_log $log
|
||||
set_def $::env(SAVE_DEF)
|
||||
set ::env(CURRENT_SDC) $::env(SAVE_SDC)
|
||||
write_verilog $::env(placement_results)/$::env(DESIGN_NAME).resized.v -log $::env(placement_logs)/write_verilog.log
|
||||
|
||||
set ::env(RSZ_DONT_TOUCH) "$dont_touch_old"
|
||||
set ::env(DONT_USE_CELLS) $dont_use_old
|
||||
|
||||
exit 1
|
||||
|
||||
detailed_placement_or -def $::env(placement_results)/$::env(DESIGN_NAME).def -log $::env(placement_logs)/detailed.log
|
||||
}
|
||||
|
||||
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
|
||||
prep -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 0
|
||||
exec rm -rf $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
run_synthesis
|
||||
|
||||
init_floorplan
|
||||
|
||||
set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/gpio_control_block.io.def]
|
||||
try_catch openroad -exit $script_dir/io_place.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(floorplan_logs)/io.log 0]
|
||||
set_def $::env(SAVE_DEF)
|
||||
|
||||
file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/placement/macro_placement.cfg
|
||||
manual_macro_placement f
|
||||
|
||||
place_io
|
||||
apply_def_template
|
||||
file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(placement_tmpfiles)/macro_placement.cfg
|
||||
manual_macro_placement -f
|
||||
tap_decap_or
|
||||
|
||||
add_route_obs
|
||||
run_power_grid_generation
|
||||
|
||||
run_placement
|
||||
set dont_use_old ::env(DONT_USE_CELLS)
|
||||
global_placement_or
|
||||
set ::env(DONT_USE_CELLS) "$::env(DONT_USE_CELLS) sky130_fd_sc_hd__buf_1"
|
||||
run_resizer_design
|
||||
set ::env(DONT_USE_CELLS) "$dont_use_old"
|
||||
|
||||
set ::env(SAVE_DEF) [index_file $::env(placement_tmpfiles)/buffer_insert.def]
|
||||
run_openroad_script $SCRIPT_DIR/buffer.tcl -indexed_log [index_file $::env(placement_logs)/buffer_insert.log]
|
||||
set_def $::env(SAVE_DEF)
|
||||
write_verilog [index_file $::env(placement_tmpfiles)/buffer_insert.v] -log $::env(placement_logs)/write_verilog_buffer.log
|
||||
set ::env(UNBUFFER_NETS) "serial_clock_out_buffered|serial_load_out_buffered"
|
||||
write_verilog [index_file $::env(placement_tmpfiles)/buffer_remove.v] -log $::env(placement_logs)/write_verilog_buffer_remove.log
|
||||
|
||||
detailed_placement_or -def $::env(CURRENT_DEF) -log $::env(placement_logs)/detailed.log
|
||||
run_cts
|
||||
run_resizer_timing
|
||||
|
||||
run_routing
|
||||
|
||||
if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
|
||||
run_antenna_check
|
||||
heal_antenna_violators; # modifies the routed DEF
|
||||
}
|
||||
|
||||
remove_buffers_from_nets
|
||||
run_resizer_timing_routing
|
||||
ins_diode_cells_4
|
||||
ins_fill_cells
|
||||
global_routing
|
||||
set global_routed_netlist [index_file $::env(routing_tmpfiles)/global.v]
|
||||
write_verilog $global_routed_netlist -log $::env(routing_logs)/write_verilog_global.log
|
||||
# detailed routing
|
||||
detailed_routing
|
||||
set detailed_routed_netlist [index_file $::env(routing_tmpfiles)/detailed.v]
|
||||
write_verilog $detailed_routed_netlist -log $::env(routing_logs)/write_verilog_detailed.log
|
||||
# for lvs
|
||||
set_netlist $detailed_routed_netlist
|
||||
run_parasitics_sta
|
||||
run_irdrop_report
|
||||
run_magic
|
||||
|
||||
run_magic_spice_export
|
||||
|
||||
set powered_netlist_name [index_file $::env(finishing_tmpfiles)/powered_netlist.v]
|
||||
set powered_def_name [index_file $::env(finishing_tmpfiles)/powered_def.def]
|
||||
write_powered_verilog\
|
||||
-output_verilog $powered_netlist_name\
|
||||
-output_def $powered_def_name\
|
||||
-log $::env(finishing_logs)/write_verilog.log\
|
||||
-def_log $::env(finishing_logs)/write_powered_def.log
|
||||
|
||||
set_netlist $powered_netlist_name
|
||||
|
||||
run_magic_spice_export;
|
||||
run_lvs; # requires run_magic_spice_export
|
||||
run_magic_drc
|
||||
|
||||
run_lvs
|
||||
|
||||
run_antenna_check
|
||||
|
||||
run_lef_cvc
|
||||
|
||||
save_views -save_path $save_path \
|
||||
-def_path $::env(CURRENT_DEF) \
|
||||
-lef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef \
|
||||
-gds_path $::env(finishing_results)/$::env(DESIGN_NAME).gds \
|
||||
-mag_path $::env(finishing_results)/$::env(DESIGN_NAME).mag \
|
||||
-maglef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef.mag \
|
||||
-spice_path $::env(finishing_results)/$::env(DESIGN_NAME).spice \
|
||||
-verilog_path $::env(CURRENT_NETLIST) \
|
||||
-spef_path $::env(SPEF_TYPICAL) \
|
||||
-sdf_path $::env(CURRENT_SDF) \
|
||||
-sdc_path $::env(CURRENT_SDC)
|
||||
|
||||
calc_total_runtime
|
||||
save_final_views
|
||||
save_final_views -save_path .. -tag $::env(RUN_TAG)
|
||||
save_state
|
||||
generate_final_summary_report
|
||||
|
||||
check_timing_violations
|
||||
|
||||
|
|
|
|||
|
|
@ -1,104 +1,154 @@
|
|||
# Power nets
|
||||
|
||||
if { ! [info exists ::env(VDD_NET)] } {
|
||||
set ::env(VDD_NET) $::env(VDD_PIN)
|
||||
}
|
||||
if { ! [info exists ::env(GND_NET)] } {
|
||||
set ::env(GND_NET) $::env(GND_PIN)
|
||||
}
|
||||
|
||||
set ::power_nets $::env(VDD_NET)
|
||||
set ::ground_nets $::env(GND_NET)
|
||||
|
||||
if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
|
||||
if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
|
||||
foreach power_pin $::env(STD_CELL_POWER_PINS) {
|
||||
add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power
|
||||
add_global_connection \
|
||||
-net $::env(VDD_NET) \
|
||||
-inst_pattern .* \
|
||||
-pin_pattern $power_pin \
|
||||
-power
|
||||
}
|
||||
foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
|
||||
add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground
|
||||
add_global_connection \
|
||||
-net $::env(GND_NET) \
|
||||
-inst_pattern .* \
|
||||
-pin_pattern $ground_pin \
|
||||
-ground
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
|
||||
if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 &&
|
||||
[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
|
||||
set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
|
||||
foreach pdn_hook $pdn_hooks {
|
||||
set instance_name [lindex $pdn_hook 0]
|
||||
set power_net [lindex $pdn_hook 1]
|
||||
set ground_net [lindex $pdn_hook 2]
|
||||
set power_pin [lindex $pdn_hook 3]
|
||||
set ground_pin [lindex $pdn_hook 4]
|
||||
|
||||
# Assesses whether the deisgn is the core of the chip or not based on the
|
||||
if { $power_pin == "" || $ground_pin == "" } {
|
||||
puts "FP_PDN_MACRO_HOOKS missing power and ground pin names"
|
||||
exit -1
|
||||
}
|
||||
|
||||
add_global_connection \
|
||||
-net $power_net \
|
||||
-inst_pattern $instance_name \
|
||||
-pin_pattern $power_pin \
|
||||
-power
|
||||
|
||||
add_global_connection \
|
||||
-net $ground_net \
|
||||
-inst_pattern $instance_name \
|
||||
-pin_pattern $ground_pin \
|
||||
-ground
|
||||
}
|
||||
}
|
||||
|
||||
set secondary []
|
||||
|
||||
foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
|
||||
if { $vdd != $::env(VDD_NET)} {
|
||||
lappend secondary $vdd
|
||||
|
||||
set db_net [[ord::get_db_block] findNet $vdd]
|
||||
if {$db_net == "NULL"} {
|
||||
set net [odb::dbNet_create [ord::get_db_block] $vdd]
|
||||
$net setSpecial
|
||||
$net setSigType "POWER"
|
||||
}
|
||||
}
|
||||
|
||||
if { $gnd != $::env(GND_NET)} {
|
||||
lappend secondary $gnd
|
||||
|
||||
set db_net [[ord::get_db_block] findNet $gnd]
|
||||
if {$db_net == "NULL"} {
|
||||
set net [odb::dbNet_create [ord::get_db_block] $gnd]
|
||||
$net setSpecial
|
||||
$net setSigType "GROUND"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
puts "set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
|
||||
-secondary_power $secondary"
|
||||
set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
|
||||
-secondary_power $secondary
|
||||
|
||||
# Assesses whether the design is the core of the chip or not based on the
|
||||
# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
|
||||
define_pdn_grid \
|
||||
-name stdcell_grid \
|
||||
-starts_with POWER \
|
||||
-voltage_domain CORE \
|
||||
-pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
-pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
|
||||
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_LOWER_LAYER) \
|
||||
-width $::env(FP_PDN_VWIDTH) \
|
||||
-pitch $::env(FP_PDN_VPITCH) \
|
||||
-offset $::env(FP_PDN_VOFFSET) \
|
||||
-starts_with POWER
|
||||
-pitch 25 \
|
||||
-offset 9.0 \
|
||||
-spacing 10.9 \
|
||||
-nets "vccd vssd" \
|
||||
-starts_with POWER -extend_to_core_ring
|
||||
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_LOWER_LAYER) \
|
||||
-width $::env(FP_PDN_VWIDTH) \
|
||||
-pitch 25 \
|
||||
-offset 14.0 \
|
||||
-spacing 10.9 \
|
||||
-nets "vccd1 vssd1" \
|
||||
-starts_with POWER -extend_to_core_ring
|
||||
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_UPPER_LAYER) \
|
||||
-width $::env(FP_PDN_HWIDTH) \
|
||||
-pitch $::env(FP_PDN_HPITCH) \
|
||||
-offset $::env(FP_PDN_HOFFSET) \
|
||||
-starts_with POWER
|
||||
-pitch 16.9 \
|
||||
-offset 9.22 \
|
||||
-spacing 6.85 \
|
||||
-nets "vccd1 vssd1"\
|
||||
-starts_with POWER -extend_to_core_ring
|
||||
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_UPPER_LAYER) \
|
||||
-width $::env(FP_PDN_HWIDTH) \
|
||||
-pitch 16.9 \
|
||||
-offset 3.98 \
|
||||
-spacing 6.85 \
|
||||
-nets "vccd vssd"\
|
||||
-starts_with POWER -extend_to_core_ring
|
||||
|
||||
add_pdn_connect \
|
||||
-grid stdcell_grid \
|
||||
-layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
|
||||
|
||||
# Adds the standard cell rails if enabled.
|
||||
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
|
||||
add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
|
||||
}
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_RAILS_LAYER) \
|
||||
-width $::env(FP_PDN_RAIL_WIDTH) \
|
||||
-followpins \
|
||||
-starts_with POWER
|
||||
|
||||
# Adds the core ring if enabled.
|
||||
if { $::env(FP_PDN_CORE_RING) == 1 } {
|
||||
add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
|
||||
-widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
|
||||
-spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
|
||||
-core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
|
||||
}
|
||||
add_pdn_connect \
|
||||
-grid stdcell_grid \
|
||||
-layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
|
||||
|
||||
if { $::env(VDD_NET) == "vccd1" } {
|
||||
add_global_connection -net vccd1 -inst_pattern gpio_logic_high -pin_pattern vccd1
|
||||
add_global_connection -net vssd1 -inst_pattern gpio_logic_high -pin_pattern vssd1
|
||||
define_pdn_grid \
|
||||
-macro \
|
||||
-orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
add_pdn_connect \
|
||||
-layers { met4_PIN_ver met5 }
|
||||
# set macro {
|
||||
# orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
# power_pins "vccd1"
|
||||
# ground_pins "vssd1"
|
||||
# blockages "met1 met2 met3 met4 met5"
|
||||
# straps {
|
||||
# }
|
||||
# connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
|
||||
# }
|
||||
# pdngen::specify_grid macro [subst $macro]
|
||||
set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
|
||||
} else {
|
||||
# set macro {
|
||||
# orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
# power_pins "vccd1"
|
||||
# ground_pins "vssd1"
|
||||
# blockages "met1 met2 met3 met4 met5"
|
||||
# straps {
|
||||
# }
|
||||
# }
|
||||
# pdngen::specify_grid macro [subst $macro]
|
||||
define_pdn_grid \
|
||||
-macro \
|
||||
-orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
|
||||
}
|
||||
|
||||
# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
|
||||
set ::rails_start_with "POWER" ;
|
||||
define_pdn_grid \
|
||||
-macro \
|
||||
-default \
|
||||
-name macro \
|
||||
-starts_with POWER \
|
||||
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
|
||||
|
||||
# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
|
||||
set ::stripes_start_with "POWER" ;
|
||||
add_pdn_connect \
|
||||
-grid macro \
|
||||
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -13,14 +13,13 @@
|
|||
# limitations under the License.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
|
||||
set ::env(DESIGN_NAME) gpio_logic_high
|
||||
set ::env(DESIGN_IS_CORE) 0
|
||||
|
||||
set ::env(VERILOG_FILES) "\
|
||||
$script_dir/../../verilog/rtl/defines.v\
|
||||
$script_dir/../../verilog/rtl/gpio_logic_high.v"
|
||||
$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
|
||||
$::env(DESIGN_DIR)/../../verilog/rtl/gpio_logic_high.v"
|
||||
|
||||
set ::env(CLOCK_PORT) ""
|
||||
set ::env(CLOCK_TREE_SYNTH) 0
|
||||
|
|
@ -30,20 +29,23 @@ set ::env(SYNTH_READ_BLACKBOX_LIB) 1
|
|||
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
|
||||
|
||||
## Floorplan
|
||||
set ::env(DIE_AREA) "0 0 7 16"
|
||||
set ::env(DIE_AREA) "0 0 7 10"
|
||||
set ::env(FP_SIZING) absolute
|
||||
|
||||
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
|
||||
set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
|
||||
|
||||
set ::env(FP_HORIZONTAL_HALO) 0
|
||||
set ::env(FP_VERTICAL_HALO) 0
|
||||
set ::env(FP_PDN_HORIZONTAL_HALO) 0
|
||||
set ::env(FP_PDN_VERTICAL_HALO) 0
|
||||
|
||||
set ::env(FP_TOP_HORIZONTAL_HALO) 0
|
||||
set ::env(FP_TOP_VERTICAL_HALO) 0
|
||||
|
||||
set ::env(FP_TAPCELL_DIST) 4
|
||||
|
||||
set ::env(TOP_MARGIN_MULT) 0
|
||||
set ::env(BOTTOM_MARGIN_MULT) 0
|
||||
set ::env(LEFT_MARGIN_MULT) 0
|
||||
set ::env(RIGHT_MARGIN_MULT) 0
|
||||
set ::env(TOP_MARGIN_MULT) 1
|
||||
set ::env(BOTTOM_MARGIN_MULT) 1
|
||||
set ::env(LEFT_MARGIN_MULT) 1
|
||||
set ::env(RIGHT_MARGIN_MULT) 1
|
||||
|
||||
set ::env(CELL_PAD) 0
|
||||
|
||||
|
|
@ -53,13 +55,14 @@ set ::env(GND_NETS) "vssd1"
|
|||
|
||||
## PDN Configuration
|
||||
set ::env(FP_PDN_AUTO_ADJUST) 0
|
||||
set ::env(FP_PDN_VWIDTH) 1.4
|
||||
set ::env(FP_PDN_VWIDTH) 1.0
|
||||
set ::env(FP_PDN_VOFFSET) 1
|
||||
set ::env(FP_PDN_VPITCH) 7.4
|
||||
set ::env(FP_PDN_VPITCH) 6
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.8
|
||||
set ::env(PL_RANDOM_INITIAL_PLACEMENT) 1
|
||||
set ::env(PL_RANDOM_INITIAL_PLACEMENT) 0
|
||||
set ::env(PL_RANDOM_GLB_PLACEMENT) 1
|
||||
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
|
|
|
|||
|
|
@ -1,137 +1,144 @@
|
|||
### Housekeeping SDC Update
|
||||
### Mod Rev 2
|
||||
### Date: 28/9/2022
|
||||
|
||||
set ::env(WB_CLK_PERIOD) 25
|
||||
set ::env(SCK_CLK_PERIOD) 100
|
||||
set ::env(RESET_PORT) "wb_rstn_i"
|
||||
set ::env(STD_CELL_LIBRARY) "sky130_fd_sc_hd"
|
||||
|
||||
## MASTER CLOCKS
|
||||
create_clock [get_ports {"wb_clk_i"} ] -name "wb_clk_i" -period $::env(WB_CLK_PERIOD)
|
||||
create_clock [get_ports {"user_clock"} ] -name "user_clock" -period $::env(WB_CLK_PERIOD)
|
||||
create_clock [get_ports {"mgmt_gpio_in[4]"} ] -name "mgmt_gpio_in" -period $::env(SCK_CLK_PERIOD)
|
||||
create_clock [get_ports {"mgmt_gpio_in[4]"} ] -name "sck" -period $::env(SCK_CLK_PERIOD)
|
||||
|
||||
## GENERATED CLOCKS
|
||||
# NOTE: change the clock pins whenever the synthesis receipe changes
|
||||
create_generated_clock -name "wbbd_sck" -source [get_ports {"wb_clk_i"} ] -divide_by 1 [get_pins {"_9640_/Q"} ]
|
||||
create_generated_clock -name "csclk_fast" -source [get_pins {"_9640_/Q"}] -divide_by 1 [get_pins {"_8847_/X"} ]
|
||||
create_generated_clock -name "csclk_slow" -source [get_ports {"mgmt_gpio_in[4]"} ] -divide_by 1 [get_pins {"_8847_/X"} ]
|
||||
set wbbd_sck_pin [get_pins -of_objects wbbd_sck -filter lib_pin_name==Q]
|
||||
|
||||
# serial_clock (twice the wb_clk_i frequency)
|
||||
create_generated_clock -name "serial_clock_pre" -source [get_ports {"wb_clk_i"} ] -multiply_by 2 [get_pins {"_9239_/Q"} ]
|
||||
create_generated_clock -name "serial_bb_clock" -source [get_pins {"_8847_/X"} ] -multiply_by 2 [get_pins {"_9772_/Q"} ]
|
||||
create_generated_clock -name "wbbd_sck" -source [get_ports {"wb_clk_i"} ] -divide_by 2 $wbbd_sck_pin
|
||||
|
||||
create_generated_clock -name "serial_clock_wb" -source [get_pins {"_9239_/Q"} ] -multiply_by 2 [get_pins {"_8819_/X"} ]
|
||||
create_generated_clock -name "serial_clock_bb" -source [get_pins {"_9772_/Q"} ] -multiply_by 2 [get_pins {"_8819_/X"} ]
|
||||
# paths between wb_clk_i and sck shouldn't be timed
|
||||
set_clock_groups -logically_exclusive -group wb_clk_i -group sck
|
||||
|
||||
# paths between wb_clk_i and mgmt_gpio_in shouldn't be timed
|
||||
set_clock_groups -logically_exclusive -group wb_clk_i -group mgmt_gpio_in
|
||||
# mux output is logically exclusive
|
||||
set_clock_groups -logically_exclusive -group csclk_fast -group csclk_slow
|
||||
|
||||
set_clock_groups -logically_exclusive -group serial_clock_wb -group serial_clock_bb
|
||||
set_propagated_clock [all_clocks]
|
||||
|
||||
## FALSE PATHS
|
||||
set_false_path -from [get_ports $::env(RESET_PORT)]
|
||||
set_false_path -from [get_ports "porb"]
|
||||
|
||||
## INPUT/OUTPUT DELAYS
|
||||
set input_delay_value [expr $::env(WB_CLK_PERIOD) * $::env(IO_PCT)]
|
||||
set output_delay_value [expr $::env(WB_CLK_PERIOD) * $::env(IO_PCT)]
|
||||
set input_delay_value 10
|
||||
set output_delay_value 5
|
||||
puts "\[INFO\]: Setting output delay to: $output_delay_value"
|
||||
puts "\[INFO\]: Setting input delay to: $input_delay_value"
|
||||
|
||||
## Filter clocks from the all inputs
|
||||
set sck_clk_indx [lsearch [all_inputs] [get_port "mgmt_gpio_in[4]"]]
|
||||
#set rst_indx [lsearch [all_inputs] [get_port resetn]]
|
||||
set all_inputs_wo_clk [lreplace [all_inputs] $sck_clk_indx $sck_clk_indx]
|
||||
#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx]
|
||||
set all_inputs_wo_clk_rst $all_inputs_wo_clk
|
||||
set all_inputs_wo_sckclk [lreplace [all_inputs] $sck_clk_indx $sck_clk_indx]
|
||||
set wb_clk_indx [lsearch $all_inputs_wo_sckclk [get_port "wb_clk_i"]]
|
||||
set all_inputs_wo_2clks [lreplace $all_inputs_wo_sckclk $wb_clk_indx $wb_clk_indx]
|
||||
set usr_clk_indx [lsearch $all_inputs_wo_2clks [get_port "user_clock"]]
|
||||
set all_inputs_wo_clk [lreplace $all_inputs_wo_2clks $usr_clk_indx $usr_clk_indx]
|
||||
|
||||
set_input_delay $input_delay_value -clock [get_clocks $::env(CLOCK_PORT)] $all_inputs_wo_clk
|
||||
set_input_delay $input_delay_value -clock [get_clocks wb_clk_i] $all_inputs_wo_clk
|
||||
|
||||
## OUTPUT DELAYS
|
||||
|
||||
# WISHBONE DELAY
|
||||
|
||||
set wb_output_delay 5
|
||||
set_output_delay $wb_output_delay -clock [get_clocks $::env(CLOCK_PORT)] [get_ports wb_ack_o]
|
||||
set_output_delay $wb_output_delay -clock [get_clocks $::env(CLOCK_PORT)] [get_ports wb_dat_o[*]]
|
||||
set_output_delay $wb_output_delay -clock [get_clocks wb_clk_i] [get_ports wb_ack_o]
|
||||
set_output_delay $wb_output_delay -clock [get_clocks wb_clk_i] [get_ports wb_dat_o[*]]
|
||||
|
||||
# PLL DELAYS
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_ena]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_dco_ena]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_div[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_sel[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll90_sel[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_trim[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pll_bypass[*]]
|
||||
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_ena]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_dco_ena]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_div[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_sel[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll90_sel[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_trim[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pll_bypass]
|
||||
|
||||
# SOC DELAYS
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports ser_tx]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports ser_rx]
|
||||
|
||||
# SPI DELAYS
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spi_sdi]
|
||||
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spi_sdi]
|
||||
|
||||
# IRQ
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports irq[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports reset]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports irq[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports reset]
|
||||
|
||||
# GPIO
|
||||
# Specify serial_clock as a generated clock signal
|
||||
#set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_clock]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_load]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_resetn]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_data_1]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports serial_data_2]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports mgmt_gpio_out[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports mgmt_gpio_oeb[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pwr_ctrl_out[*]]
|
||||
#set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_clock]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_load]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_resetn]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_data_1]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports serial_data_2]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports mgmt_gpio_out[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports mgmt_gpio_oeb[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pwr_ctrl_out[*]]
|
||||
|
||||
# FLASH
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spimemio_flash_io0_di]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spimemio_flash_io1_di]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spimemio_flash_io2_di]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports spimemio_flash_io3_di]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spimemio_flash_io0_di]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spimemio_flash_io1_di]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spimemio_flash_io2_di]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports spimemio_flash_io3_di]
|
||||
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports debug_in]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports debug_in]
|
||||
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_csb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_csb_oeb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_clk]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_clk_oeb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io0_oeb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io1_oeb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io0_ieb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io1_ieb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io0_do]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io1_do]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports pad_flash_io0_ieb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_csb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_csb_oeb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_clk]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_clk_oeb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io0_oeb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io1_oeb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io0_ieb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io1_ieb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io0_do]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io1_do]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports pad_flash_io0_ieb]
|
||||
|
||||
# SRAM
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports sram_ro_clk]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports sram_ro_csb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks $::env(CLOCK_PORT)] [get_ports sram_ro_addr[*]]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports sram_ro_clk]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports sram_ro_csb]
|
||||
set_output_delay $output_delay_value -clock [get_clocks wb_clk_i] [get_ports sram_ro_addr[*]]
|
||||
|
||||
# TODO set this as parameter
|
||||
set_driving_cell -lib_cell $::env(SYNTH_DRIVING_CELL) -pin $::env(SYNTH_DRIVING_CELL_PIN) [all_inputs]
|
||||
set cap_load [expr $::env(SYNTH_CAP_LOAD) / 1000.0]
|
||||
puts "\[INFO\]: Setting load to: $cap_load"
|
||||
set_load $cap_load [all_outputs]
|
||||
## OUTPUT LOADS
|
||||
set PT_cap_load 0.21
|
||||
puts "\[INFO\]: Setting load to: $PT_cap_load"
|
||||
set_load $PT_cap_load [all_outputs]
|
||||
|
||||
## TIMING DERATE
|
||||
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 10}] %"
|
||||
set ::env(SYNTH_TIMING_DERATE) 0.05
|
||||
puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
|
||||
set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
|
||||
set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
|
||||
|
||||
## CLOCK UNCERTAINITY
|
||||
puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINITY)"
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {wb_clk_i}]
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {user_clock}]
|
||||
set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINITY) [get_clocks {mgmt_gpio_in}]
|
||||
set wb_clk_uncer [expr $::env(WB_CLK_PERIOD)*0.05]
|
||||
set sck_clk_uncer [expr $::env(SCK_CLK_PERIOD)*0.05]
|
||||
|
||||
puts "\[INFO\]: Setting WB clock uncertainity to: $wb_clk_uncer"
|
||||
puts "\[INFO\]: Setting SCK clock uncertainity to: $sck_clk_uncer"
|
||||
set_clock_uncertainty $wb_clk_uncer [get_clocks {wb_clk_i}]
|
||||
set_clock_uncertainty $wb_clk_uncer [get_clocks {user_clock}]
|
||||
set_clock_uncertainty $sck_clk_uncer [get_clocks {sck}]
|
||||
|
||||
## CLOCK TRANSITION
|
||||
puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {wb_clk_i}]
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {user_clock}]
|
||||
set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {mgmt_gpio_in}]
|
||||
set wb_clk_tran [expr $::env(WB_CLK_PERIOD)*0.01]
|
||||
set sck_clk_tran [expr $::env(SCK_CLK_PERIOD)*0.01]
|
||||
|
||||
puts "\[INFO\]: Setting clock transition to: $wb_clk_tran"
|
||||
puts "\[INFO\]: Setting clock transition to: $sck_clk_tran"
|
||||
|
||||
set_clock_transition $wb_clk_tran [get_clocks {wb_clk_i}]
|
||||
set_clock_transition $wb_clk_tran [get_clocks {user_clock}]
|
||||
set_clock_transition $sck_clk_tran [get_clocks {sck}]
|
||||
|
||||
## FANOUT
|
||||
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
|
||||
set ::env(SYNTH_MAX_FANOUT) 7
|
||||
puts "\[INFO\]: Setting maximum fanout to: $::env(SYNTH_MAX_FANOUT)"
|
||||
set_max_fanout $::env(SYNTH_MAX_FANOUT) [current_design]
|
||||
|
|
|
|||
|
|
@ -14,57 +14,56 @@
|
|||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# OR COMMIT: 182e733faa149c80f36cfd2198a83dcdeb7853ea
|
||||
set script_dir [file dirname [file normalize [info script]]]
|
||||
|
||||
set ::env(DESIGN_NAME) "housekeeping"
|
||||
set ::env(ROUTING_CORES) 6
|
||||
set ::env(ROUTING_CORES) 36
|
||||
set ::env(RUN_KLAYOUT) 0
|
||||
|
||||
set ::env(VERILOG_FILES) "\
|
||||
$script_dir/../../verilog/rtl/defines.v\
|
||||
$script_dir/../../verilog/rtl/housekeeping_spi.v\
|
||||
$script_dir/../../verilog/rtl/housekeeping.v"
|
||||
$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
|
||||
$::env(DESIGN_DIR)/../../verilog/rtl/housekeeping_spi.v\
|
||||
$::env(DESIGN_DIR)/../../verilog/rtl/housekeeping.v"
|
||||
|
||||
set ::env(CLOCK_PORT) "wb_clk_i"
|
||||
set ::env(CLOCK_NET) "$::env(CLOCK_PORT) csclk mgmt_gpio_in\[4\]"
|
||||
|
||||
set ::env(BASE_SDC_FILE) $script_dir/base.sdc
|
||||
set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/template/housekeeping.def
|
||||
|
||||
set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
|
||||
|
||||
## Synthesis
|
||||
set ::env(NO_SYNTH_CELL_LIST) $script_dir/no_synth.list
|
||||
set ::env(NO_SYNTH_CELL_LIST) $::env(DESIGN_DIR)/no_synth.list
|
||||
set ::env(SYNTH_STRATEGY) "AREA 0"
|
||||
|
||||
set ::env(SYNTH_MAX_FANOUT) 20
|
||||
set ::env(SYNTH_MAX_FANOUT) 7
|
||||
|
||||
## Floorplan
|
||||
set ::env(FP_SIZING) absolute
|
||||
set ::env(DIE_AREA) "0 0 300.230 550.950"
|
||||
|
||||
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
|
||||
|
||||
set ::env(FP_IO_MIN_DISTANCE) 2
|
||||
|
||||
set ::env(CELL_PAD) 0
|
||||
set ::env(DPL_CELL_PADDING) 2
|
||||
set ::env(GPL_CELL_PADDING) 2
|
||||
|
||||
## Routing
|
||||
set ::env(GLB_RT_ADJUSTMENT) 0.06
|
||||
set ::env(GLB_RT_OVERFLOW_ITERS) 100
|
||||
set ::env(GRT_ADJUSTMENT) 0.06
|
||||
set ::env(GRT_LAYER_ADJUSTMENTS) "0.99,0.2,0,0,0,0"
|
||||
set ::env(GRT_OVERFLOW_ITERS) 100
|
||||
|
||||
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) 0.17
|
||||
|
||||
# prevent signal routing on li1
|
||||
set ::env(GLB_RT_OBS) "\
|
||||
li1 0 0 5.94500 550.950,\
|
||||
li1 0 0 300.23000 10.97000,\
|
||||
li1 294.23500 0 300.22000 550.95000,\
|
||||
li1 0 538.84500 300.2300 550.95000"
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.378
|
||||
set ::env(PL_TARGET_DENSITY) 0.5
|
||||
|
||||
set ::env(GRT_ALLOW_CONGESTION) 0
|
||||
|
||||
set ::env(CLOCK_TREE_SYNTH) 1
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
|
||||
|
||||
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) .17
|
||||
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) "30"
|
||||
|
||||
## Diode Insertion
|
||||
set ::env(DIODE_INSERTION_STRATEGY) "3"
|
||||
set ::env(GLB_RT_ANT_ITERS) "7"
|
||||
set ::env(GRT_ANT_ITERS) "7"
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Mon Apr 11 14:40:34 2022
|
||||
# Tue Sep 27 13:54:44 2022
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
###############################################################################
|
||||
|
|
@ -57,52 +57,53 @@ set_output_delay 10.0000 -clock [get_clocks {serial_clock}] -add_delay [get_port
|
|||
###############################################################################
|
||||
# Environment
|
||||
###############################################################################
|
||||
set_load -pin_load 0.0334 [get_ports {mgmt_gpio_in}]
|
||||
set_load -pin_load 0.0334 [get_ports {one}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_en}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_pol}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ana_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_holdover}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_inenb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_outenb}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_slow_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_load -pin_load 0.0334 [get_ports {resetn_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_clock_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_data_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {serial_load_out}]
|
||||
set_load -pin_load 0.0334 [get_ports {user_gpio_in}]
|
||||
set_load -pin_load 0.0334 [get_ports {zero}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[2]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[1]}]
|
||||
set_load -pin_load 0.0334 [get_ports {pad_gpio_dm[0]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {mgmt_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {pad_gpio_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {resetn}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_clock}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_data_in}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {serial_load}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_oeb}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {user_gpio_out}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[12]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[11]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[10]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[9]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[8]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[7]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[6]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[5]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[4]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[3]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[2]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[1]}]
|
||||
set_driving_cell -lib_cell sky130_fd_sc_hd__inv_2 -pin {Y} -input_transition_rise 0.0000 -input_transition_fall 0.0000 [get_ports {gpio_defaults[0]}]
|
||||
set_load -pin_load 0.2500 [get_ports {mgmt_gpio_in}]
|
||||
set_load -pin_load 0.2500 [get_ports {one}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_en}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_pol}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ana_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_holdover}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_ib_mode_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_inenb}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_outenb}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_slow_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_vtrip_sel}]
|
||||
set_load -pin_load 0.2500 [get_ports {resetn_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {serial_clock_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {serial_data_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {serial_load_out}]
|
||||
set_load -pin_load 0.2500 [get_ports {user_gpio_in}]
|
||||
set_load -pin_load 0.2500 [get_ports {zero}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[2]}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[1]}]
|
||||
set_load -pin_load 0.2500 [get_ports {pad_gpio_dm[0]}]
|
||||
set_input_transition 5.0000 [get_ports {mgmt_gpio_oeb}]
|
||||
set_input_transition 5.0000 [get_ports {mgmt_gpio_out}]
|
||||
set_input_transition 5.0000 [get_ports {pad_gpio_in}]
|
||||
set_input_transition 5.0000 [get_ports {resetn}]
|
||||
set_input_transition 5.0000 [get_ports {serial_clock}]
|
||||
set_input_transition 5.0000 [get_ports {serial_data_in}]
|
||||
set_input_transition 5.0000 [get_ports {serial_load}]
|
||||
set_input_transition 5.0000 [get_ports {user_gpio_oeb}]
|
||||
set_input_transition 5.0000 [get_ports {user_gpio_out}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[12]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[11]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[10]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[9]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[8]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[7]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[6]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[5]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[4]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[3]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[2]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[1]}]
|
||||
set_input_transition 5.0000 [get_ports {gpio_defaults[0]}]
|
||||
set_timing_derate -early 0.9500
|
||||
set_timing_derate -late 1.0500
|
||||
###############################################################################
|
||||
# Design Rules
|
||||
###############################################################################
|
||||
set_max_fanout 5.0000 [current_design]
|
||||
set_max_transition 1.2500 [current_design]
|
||||
set_max_fanout 7.0000 [current_design]
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1 +1 @@
|
|||
openlane 302609248b0947f2497a4684c503deca03ad0259
|
||||
openlane 37faafee20ec76a349fb817d7a75ed26d94be904
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
open_pdks 7519dfb04400f224f140749cda44ee7de6f5e095
|
||||
open_pdks fa87f8f4bbcc7255b6f0c0fb506960f531ae2392
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,127 +1,103 @@
|
|||
* NGSPICE file created from gpio_control_block.ext - technology: sky130A
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_2 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_4 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkdlybuf4s50_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkdlybuf4s50_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfbbn_2 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkbuf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkdlybuf4s25_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkdlybuf4s25_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd3_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dlygate4sd3_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2_2 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__a31o_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__a31o_2 A1 A2 A3 B1 VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2b_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2b_2 A_N B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2b_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2b_2 A B_N VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_16 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_16 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_16 abstract view
|
||||
.subckt sky130_fd_sc_hd__clkbuf_16 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__einvp_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__einvp_8 A TE VGND VNB VPB VPWR Z
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd3_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dlygate4sd3_1 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__ebufn_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__ebufn_2 A TE_B VGND VNB VPB VPWR Z
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__nand2b_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__nand2b_2 A_N B VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_0 abstract view
|
||||
.subckt sky130_fd_sc_hd__or2_0 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2_2 A B VGND VNB VPB VPWR X
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__einvp_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__einvp_8 A TE VGND VNB VPB VPWR Z
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__o22ai_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__o22ai_2 A1 A2 B1 B2 VGND VNB VPB VPWR Y
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__o31ai_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__o31ai_2 A1 A2 A3 B1 VGND VNB VPB VPWR Y
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__o21ai_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__o21ai_4 A1 A2 B1 VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__o21a_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__o21a_2 A1 A2 B1 VGND VNB VPB VPWR X
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for gpio_logic_high abstract view
|
||||
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__nand2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__nand2_2 A B VGND VNB VPB VPWR Y
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__ebufn_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__ebufn_8 A TE_B VGND VNB VPB VPWR Z
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd2_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__dlygate4sd2_1 A VGND VNB VPB VPWR X
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__o21ai_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__o21ai_2 A1 A2 B1 VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2b_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2b_2 A_N B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and3b_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__and3b_2 A_N B C VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_2 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__mux2_4 A0 A1 S VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_0 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2_0 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
||||
.subckt gpio_control_block gpio_defaults[0] gpio_defaults[10] gpio_defaults[11] gpio_defaults[12]
|
||||
|
|
@ -132,331 +108,277 @@
|
|||
+ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
|
||||
+ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
|
||||
+ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
|
||||
X_200_ _207_/CLK hold2/X resetn vssd vssd vccd vccd _200_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
XANTENNA__127__B_N gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_18_31 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_114_ resetn vssd vssd vccd vccd _177_/A sky130_fd_sc_hd__buf_1
|
||||
XFILLER_13_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_3_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_130_ _130_/A vssd vssd vccd vccd _130_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__124__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__160__B_N gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_0_47 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold20 _201_/Q vssd vssd vccd vccd _202_/D sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
X_179__3 _179__3/A vssd vssd vccd vccd _179__3/Y sky130_fd_sc_hd__inv_2
|
||||
X_189_ _154__11/Y hold6/X _153_/X _156_/X vssd vssd vccd vccd pad_gpio_dm[0] _104_/A2
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA__200__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xclkbuf_1_1_0__077_ clkbuf_0__077_/X vssd vssd vccd vccd _131__7/A sky130_fd_sc_hd__clkbuf_2
|
||||
X_112_ _210_/A vssd vssd vccd vccd _112_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold10 hold9/X vssd vssd vccd vccd _198_/D sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
Xhold21 _200_/Q vssd vssd vccd vccd _201_/D sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
XFILLER_3_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_111_ _111_/A vssd vssd vccd vccd _111_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__146__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_188_ _148__10/Y hold8/X _147_/X _150_/X vssd vssd vccd vccd _188_/Q _188_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold22 _205_/D vssd vssd vccd vccd _185_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
Xhold11 _195_/Q vssd vssd vccd vccd hold12/A sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_15_24 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_187_ _142__9/Y hold2/X _140_/X _145_/X vssd vssd vccd vccd pad_gpio_ib_mode_sel
|
||||
+ _187_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_110_ _180_/A gpio_defaults[0] vssd vssd vccd vccd _111_/A sky130_fd_sc_hd__or2_2
|
||||
Xhold12 hold12/A vssd vssd vccd vccd _196_/D sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
Xhold23 _207_/D vssd vssd vccd vccd _190_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XANTENNA__162__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__157__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_186_ _136__8/Y _199_/D _135_/X _138_/X vssd vssd vccd vccd pad_gpio_inenb _186_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold13 _198_/Q vssd vssd vccd vccd hold14/A sky130_fd_sc_hd__dlygate4sd3_1
|
||||
X_131_ _134_/CLK _131_/D _085_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_4
|
||||
XFILLER_0_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_20_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_114_ _101__6/Y _127_/D _081_/X _082_/Y vssd vssd vccd vccd _114_/Q _114_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xoutput20 _135_/Q vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_16
|
||||
Xoutput7 _121_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_16
|
||||
X_130_ _130_/CLK hold8/X _095_/A vssd vssd vccd vccd _130_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
X_113_ _100__5/Y hold6/X _079_/X _080_/Y vssd vssd vccd vccd _113_/Q _113_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xclkbuf_1_0__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _103__8/A sky130_fd_sc_hd__clkbuf_16
|
||||
X_097__2 _104__9/A vssd vssd vccd vccd _097__2/Y sky130_fd_sc_hd__inv_2
|
||||
Xoutput8 _120_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_16
|
||||
Xoutput10 _117_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_16
|
||||
X_060_ _139_/A vssd vssd vccd vccd _060_/Y sky130_fd_sc_hd__inv_2
|
||||
X_112_ _099__4/Y hold1/X _077_/X _078_/Y vssd vssd vccd vccd _112_/Q _112_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA__065__A0 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold10 _132_/Q vssd vssd vccd vccd _133_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xoutput9 _116_/Q vssd vssd vccd vccd pad_gpio_dm[0] sky130_fd_sc_hd__buf_16
|
||||
Xoutput11 _118_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_16
|
||||
XANTENNA__084__A_N _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_3_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_111_ _098__3/Y _131_/D _075_/X _076_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold11 _127_/Q vssd vssd vccd vccd _128_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
X_107__12 _103__8/A vssd vssd vccd vccd _107__12/Y sky130_fd_sc_hd__inv_2
|
||||
Xoutput12 _110_/Q vssd vssd vccd vccd pad_gpio_holdover sky130_fd_sc_hd__buf_16
|
||||
X_110_ _097__2/Y hold4/X _073_/X _074_/Y vssd vssd vccd vccd _110_/Q _110_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold12 _130_/Q vssd vssd vccd vccd _131_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA__072__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__074__A_N _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput13 _114_/Q vssd vssd vccd vccd pad_gpio_ib_mode_sel sky130_fd_sc_hd__buf_16
|
||||
XANTENNA__083__A _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__080__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__075__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold13 _126_/Q vssd vssd vccd vccd _127_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA__083__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__203__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_185_ _131__7/Y _185_/D _130_/X _133_/X vssd vssd vccd vccd pad_gpio_vtrip_sel _185_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA__196__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_099_ _188_/Q mgmt_gpio_oeb _182_/Q _098_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__a31o_2
|
||||
Xhold14 hold14/A vssd vssd vccd vccd _199_/D sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
X_168_ _168_/A vssd vssd vccd vccd _168_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_6_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__078__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput14 _113_/Q vssd vssd vccd vccd pad_gpio_inenb sky130_fd_sc_hd__buf_16
|
||||
XANTENNA__125__RESET_B _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__091__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__086__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput15 _070_/Y vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__buf_16
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_164__13 _164__13/A vssd vssd vccd vccd _164__13/Y sky130_fd_sc_hd__inv_2
|
||||
X_184_ _126__6/Y _204_/D _125_/X _128_/X vssd vssd vccd vccd pad_gpio_slow_sel _184_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XFILLER_18_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xconst_source vssd vssd vccd vccd one zero sky130_fd_sc_hd__conb_1
|
||||
X_098_ _182_/Q user_gpio_oeb vssd vssd vccd vccd _098_/X sky130_fd_sc_hd__and2b_2
|
||||
X_167_ _172_/A gpio_defaults[5] vssd vssd vccd vccd _168_/A sky130_fd_sc_hd__or2_2
|
||||
Xhold15 _203_/Q vssd vssd vccd vccd hold16/A sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_16_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__094__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__089__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_100__5 _104__9/A vssd vssd vccd vccd _100__5/Y sky130_fd_sc_hd__inv_2
|
||||
Xconst_source vssd vssd vccd vccd one_buffer/A zero_buffer/A sky130_fd_sc_hd__conb_1
|
||||
XFILLER_19_70 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xoutput16 _065_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__buf_16
|
||||
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_183_ _120__5/Y _198_/D _119_/X _122_/X vssd vssd vccd vccd pad_gpio_holdover _183_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
X_166_ _166_/A vssd vssd vccd vccd _166_/X sky130_fd_sc_hd__buf_1
|
||||
X_097_ _097_/A vssd vssd vccd vccd _097_/X sky130_fd_sc_hd__buf_1
|
||||
X_149_ _165_/A gpio_defaults[1] vssd vssd vccd vccd _150_/A sky130_fd_sc_hd__or2b_2
|
||||
Xhold16 hold16/A vssd vssd vccd vccd _204_/D sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
Xoutput17 _111_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_16
|
||||
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__100__A user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_182_ _113__4/Y _196_/D _111_/X _117_/X vssd vssd vccd vccd _182_/Q _182_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold17 _204_/Q vssd vssd vccd vccd _205_/D sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
X_096_ pad_gpio_inenb _188_/Q vssd vssd vccd vccd _097_/A sky130_fd_sc_hd__or2b_2
|
||||
X_165_ _165_/A gpio_defaults[12] vssd vssd vccd vccd _166_/A sky130_fd_sc_hd__or2b_2
|
||||
XANTENNA__206__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_10_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_096_ _095_/A gpio_defaults[7] vssd vssd vccd vccd _096_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XFILLER_1_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_1_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_079_ _083_/A gpio_defaults[3] vssd vssd vccd vccd _079_/X sky130_fd_sc_hd__or2_0
|
||||
Xoutput18 _112_/Q vssd vssd vccd vccd pad_gpio_vtrip_sel sky130_fd_sc_hd__buf_16
|
||||
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__199__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__195__D serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xclkbuf_1_1_0_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _210_/A sky130_fd_sc_hd__clkbuf_2
|
||||
X_181_ _181_/A vssd vssd vccd vccd _181_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_18_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
X_147_ _147_/A vssd vssd vccd vccd _147_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__106__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold18 _206_/Q vssd vssd vccd vccd _207_/D sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
X_095_ _095_/A gpio_defaults[7] vssd vssd vccd vccd _095_/X sky130_fd_sc_hd__or2_0
|
||||
XANTENNA_input4_A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_078_ _085_/A gpio_defaults[9] vssd vssd vccd vccd _078_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xoutput19 _136_/X vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_16
|
||||
XFILLER_7_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_103__8 _103__8/A vssd vssd vccd vccd _103__8/Y sky130_fd_sc_hd__inv_2
|
||||
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__114__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_180_ _180_/A gpio_defaults[7] vssd vssd vccd vccd _181_/A sky130_fd_sc_hd__or2b_2
|
||||
X_169__1 _179__3/A vssd vssd vccd vccd _169__1/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__109__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__149__B_N gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold19 _202_/Q vssd vssd vccd vccd _203_/D sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
XFILLER_1_78 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_163_ _163_/A vssd vssd vccd vccd _163_/X sky130_fd_sc_hd__buf_1
|
||||
X_129_ _146_/A gpio_defaults[9] vssd vssd vccd vccd _130_/A sky130_fd_sc_hd__or2_2
|
||||
Xclkbuf_0__077_ _112_/X vssd vssd vccd vccd clkbuf_0__077_/X sky130_fd_sc_hd__clkbuf_16
|
||||
Xclkbuf_1_0_0__077_ clkbuf_0__077_/X vssd vssd vccd vccd _136__8/A sky130_fd_sc_hd__clkbuf_2
|
||||
X_146_ _146_/A gpio_defaults[1] vssd vssd vccd vccd _147_/A sky130_fd_sc_hd__or2_2
|
||||
Xfanout21 _095_/A vssd vssd vccd vccd _091_/A sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__080__A_N _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_094_ _091_/A gpio_defaults[6] vssd vssd vccd vccd _094_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_077_ _089_/A gpio_defaults[9] vssd vssd vccd vccd _077_/X sky130_fd_sc_hd__or2_0
|
||||
X_129_ _130_/CLK hold9/X _095_/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_174__2 _179__3/A vssd vssd vccd vccd _174__2/Y sky130_fd_sc_hd__inv_2
|
||||
X_162_ _172_/A gpio_defaults[12] vssd vssd vccd vccd _163_/A sky130_fd_sc_hd__or2_2
|
||||
X_145_ _145_/A vssd vssd vccd vccd _145_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__116__B_N gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_128_ _128_/A vssd vssd vccd vccd _128_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_7_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xfanout22 fanout28/X vssd vssd vccd vccd _095_/A sky130_fd_sc_hd__buf_2
|
||||
X_093_ _095_/A gpio_defaults[6] vssd vssd vccd vccd _093_/X sky130_fd_sc_hd__or2_0
|
||||
X_076_ _085_/A gpio_defaults[8] vssd vssd vccd vccd _076_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xinput1 mgmt_gpio_oeb vssd vssd vccd vccd _067_/C sky130_fd_sc_hd__buf_2
|
||||
X_128_ _130_/CLK _128_/D _095_/A vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_161_ _161_/A vssd vssd vccd vccd _161_/X sky130_fd_sc_hd__buf_1
|
||||
Xgpio_in_buf _106_/Y gpio_in_buf/TE vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__einvp_8
|
||||
Xfanout23 _072_/A_N vssd vssd vccd vccd _083_/A sky130_fd_sc_hd__buf_2
|
||||
X_092_ _091_/A gpio_defaults[5] vssd vssd vccd vccd _092_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xgpio_in_buf _060_/Y gpio_in_buf/TE vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__einvp_8
|
||||
XANTENNA_input2_A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xinput2 mgmt_gpio_out vssd vssd vccd vccd input2/X sky130_fd_sc_hd__buf_2
|
||||
X_075_ _085_/A gpio_defaults[8] vssd vssd vccd vccd _075_/X sky130_fd_sc_hd__or2_0
|
||||
X_127_ _130_/CLK _127_/D _091_/A vssd vssd vccd vccd _127_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA_clkbuf_0_serial_load_A serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_127_ _137_/A gpio_defaults[8] vssd vssd vccd vccd _128_/A sky130_fd_sc_hd__or2b_2
|
||||
XFILLER_16_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_144_ _165_/A gpio_defaults[4] vssd vssd vccd vccd _145_/A sky130_fd_sc_hd__or2b_2
|
||||
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_143_ _177_/A vssd vssd vccd vccd _165_/A sky130_fd_sc_hd__buf_1
|
||||
X_136__8 _136__8/A vssd vssd vccd vccd _136__8/Y sky130_fd_sc_hd__inv_2
|
||||
X_160_ _165_/A gpio_defaults[11] vssd vssd vccd vccd _161_/A sky130_fd_sc_hd__or2b_2
|
||||
XFILLER_1_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
X_106__11 _103__8/A vssd vssd vccd vccd _106__11/Y sky130_fd_sc_hd__inv_2
|
||||
Xfanout24 fanout28/X vssd vssd vccd vccd _072_/A_N sky130_fd_sc_hd__buf_2
|
||||
XFILLER_19_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_70 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput3 pad_gpio_in vssd vssd vccd vccd _139_/A sky130_fd_sc_hd__buf_2
|
||||
X_091_ _091_/A gpio_defaults[5] vssd vssd vccd vccd _091_/X sky130_fd_sc_hd__or2_0
|
||||
X_074_ _083_/A gpio_defaults[2] vssd vssd vccd vccd _074_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_126_ _130_/CLK hold6/X _091_/A vssd vssd vccd vccd _126_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
X_098__3 _103__8/A vssd vssd vccd vccd _098__3/Y sky130_fd_sc_hd__inv_2
|
||||
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__139__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_109_ resetn vssd vssd vccd vccd _180_/A sky130_fd_sc_hd__buf_1
|
||||
X_109_ _061__1/Y hold3/X _071_/X _072_/Y vssd vssd vccd vccd _109_/Q _109_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xfanout25 fanout28/X vssd vssd vccd vccd _089_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_71 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_60 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA__152__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_125_ _125_/A vssd vssd vccd vccd _125_/X sky130_fd_sc_hd__buf_1
|
||||
X_211_ pad_gpio_in _097_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_2
|
||||
X_108_ _108_/A vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_1
|
||||
X_154__11 _142__9/A vssd vssd vccd vccd _154__11/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_13_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__175__B_N gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_210_ _210_/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__buf_2
|
||||
Xinput4 resetn vssd vssd vccd vccd input4/X sky130_fd_sc_hd__buf_2
|
||||
X_090_ _136_/A gpio_defaults[12] vssd vssd vccd vccd _090_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_073_ _083_/A gpio_defaults[2] vssd vssd vccd vccd _073_/X sky130_fd_sc_hd__or2_0
|
||||
X_125_ _130_/CLK hold4/X _083_/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__073__A _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xfanout26 fanout28/X vssd vssd vccd vccd _136_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_72 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_61 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_072_ _072_/A_N gpio_defaults[0] vssd vssd vccd vccd _072_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_141_ _210_/A vssd vssd vccd vccd _141_/X sky130_fd_sc_hd__buf_1
|
||||
Xclkbuf_1_1_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _209_/A sky130_fd_sc_hd__clkbuf_2
|
||||
X_124_ _146_/A gpio_defaults[8] vssd vssd vccd vccd _125_/A sky130_fd_sc_hd__or2_2
|
||||
XANTENNA__202__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__195__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_14_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_107_ one _107_/B vssd vssd vccd vccd _108_/A sky130_fd_sc_hd__and2_2
|
||||
XANTENNA__165__B_N gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xinput5 serial_data_in vssd vssd vccd vccd _122_/D sky130_fd_sc_hd__buf_2
|
||||
X_124_ _130_/CLK hold5/X _072_/A_N vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__073__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xfanout27 fanout28/X vssd vssd vccd vccd _085_/A sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__079__A _083_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__076__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__081__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_73 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_071_ _089_/A gpio_defaults[0] vssd vssd vccd vccd _071_/X sky130_fd_sc_hd__or2_0
|
||||
XTAP_62 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_140_ _140_/A vssd vssd vccd vccd _140_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_10_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_40 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_123_ _177_/A vssd vssd vccd vccd _146_/A sky130_fd_sc_hd__buf_1
|
||||
X_106_ pad_gpio_in vssd vssd vccd vccd _106_/Y sky130_fd_sc_hd__inv_2
|
||||
X_148__10 _142__9/A vssd vssd vccd vccd _148__10/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__132__B_N gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_123_ _130_/CLK hold3/X _072_/A_N vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__084__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xfanout28 input4/X vssd vssd vccd vccd fanout28/X sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__079__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_63 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA__177__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_070_ _068_/X _069_/Y _066_/Y vssd vssd vccd vccd _070_/Y sky130_fd_sc_hd__o21ai_4
|
||||
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_41 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA__155__B_N gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_16_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_11_60 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_122_ _122_/A vssd vssd vccd vccd _122_/X sky130_fd_sc_hd__buf_1
|
||||
X_199_ _207_/CLK _199_/D resetn vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_2
|
||||
X_105_ _182_/Q _100_/Y _103_/X _104_/Y vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__o22ai_2
|
||||
XANTENNA__092__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__087__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_122_ _134_/CLK _122_/D _072_/A_N vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__095__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xserial_clock_out_buffer _134_/CLK vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_16
|
||||
XTAP_64 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_14_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_198_ _209_/A _198_/D resetn vssd vssd vccd vccd _198_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA__098__B user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_121_ _137_/A gpio_defaults[2] vssd vssd vccd vccd _122_/A sky130_fd_sc_hd__or2b_2
|
||||
X_104_ pad_gpio_dm[2] _104_/A2 _101_/Y _182_/Q vssd vssd vccd vccd _104_/Y sky130_fd_sc_hd__o31ai_2
|
||||
XFILLER_12_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__205__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_2_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_121_ _108__13/Y hold8/X _095_/X _096_/Y vssd vssd vccd vccd _121_/Q _121_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XTAP_65 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_101__6 _103__8/A vssd vssd vccd vccd _101__6/Y sky130_fd_sc_hd__inv_2
|
||||
XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_197_ _209_/A hold8/X resetn vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_2
|
||||
XANTENNA__198__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_103_ pad_gpio_dm[2] _101_/Y _102_/Y vssd vssd vccd vccd _103_/X sky130_fd_sc_hd__o21a_2
|
||||
X_120__5 _136__8/A vssd vssd vccd vccd _120__5/Y sky130_fd_sc_hd__inv_2
|
||||
Xhold1 hold1/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dlygate4sd3_1
|
||||
X_120_ _107__12/Y hold9/X _093_/X _094_/Y vssd vssd vccd vccd _120_/Q _120_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XFILLER_2_42 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_8_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XTAP_66 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_196_ _209_/A _196_/D resetn vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_2
|
||||
XANTENNA__101__A mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_102_ mgmt_gpio_out vssd vssd vccd vccd _102_/Y sky130_fd_sc_hd__inv_2
|
||||
Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xclkbuf_0_serial_load serial_load vssd vssd vccd vccd clkbuf_0_serial_load/X sky130_fd_sc_hd__clkbuf_16
|
||||
Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _130_/CLK
|
||||
+ sky130_fd_sc_hd__clkbuf_16
|
||||
XTAP_67 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xgpio_logic_high gpio_in_buf/TE vccd1 vssd1 gpio_logic_high
|
||||
XFILLER_5_32 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_195_ _209_/A serial_data_in resetn vssd vssd vccd vccd _195_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
X_101_ mgmt_gpio_oeb pad_gpio_dm[1] vssd vssd vccd vccd _101_/Y sky130_fd_sc_hd__nand2_2
|
||||
X_178_ _178_/A vssd vssd vccd vccd _178_/X sky130_fd_sc_hd__buf_1
|
||||
Xclkbuf_1_1_0__049_ clkbuf_0__049_/X vssd vssd vccd vccd _142__9/A sky130_fd_sc_hd__clkbuf_2
|
||||
Xclkbuf_1_0_0_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _179__3/A sky130_fd_sc_hd__clkbuf_2
|
||||
XFILLER_10_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold3 hold3/A vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dlygate4sd3_1
|
||||
X_126__6 _131__7/A vssd vssd vccd vccd _126__6/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_14_42 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_40 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xone_buffer one_buffer/A vssd vssd vccd vccd one sky130_fd_sc_hd__buf_16
|
||||
XFILLER_8_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold3 hold3/A vssd vssd vccd vccd hold3/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XPHY_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_68 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_194_ _179__3/Y _203_/D _178_/X _181_/X vssd vssd vccd vccd pad_gpio_ana_pol _194_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
X_100_ user_gpio_out vssd vssd vccd vccd _100_/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__208__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_177_ _177_/A gpio_defaults[7] vssd vssd vccd vccd _178_/A sky130_fd_sc_hd__or2_2
|
||||
Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_131__7 _131__7/A vssd vssd vccd vccd _131__7/Y sky130_fd_sc_hd__inv_2
|
||||
X_105__10 _104__9/A vssd vssd vccd vccd _105__10/Y sky130_fd_sc_hd__inv_2
|
||||
Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
X_104__9 _104__9/A vssd vssd vccd vccd _104__9/Y sky130_fd_sc_hd__inv_2
|
||||
XTAP_69 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_14_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_56 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_193_ _174__2/Y _202_/D _173_/X _176_/X vssd vssd vccd vccd pad_gpio_ana_sel _193_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA__118__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_176_ _176_/A vssd vssd vccd vccd _176_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold5 hold5/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xdata_delay_1 hold3/A vssd vssd vccd vccd data_delay_2/A sky130_fd_sc_hd__dlygate4sd2_1
|
||||
XFILLER_0_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_17_98 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold5 hold5/A vssd vssd vccd vccd hold5/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_59 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_48 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_192_ _169__1/Y _201_/D _168_/X _171_/X vssd vssd vccd vccd pad_gpio_ana_en _192_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
X_175_ _180_/A gpio_defaults[6] vssd vssd vccd vccd _176_/A sky130_fd_sc_hd__or2b_2
|
||||
XFILLER_2_47 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__129__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__134__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold6 hold6/A vssd vssd vccd vccd hold6/X sky130_fd_sc_hd__clkdlybuf4s50_1
|
||||
X_158_ _158_/A vssd vssd vccd vccd _158_/X sky130_fd_sc_hd__buf_1
|
||||
XTAP_48 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_089_ _089_/A gpio_defaults[12] vssd vssd vccd vccd _089_/X sky130_fd_sc_hd__or2_0
|
||||
Xhold6 hold6/A vssd vssd vccd vccd hold6/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xzero_buffer zero_buffer/A vssd vssd vccd vccd zero sky130_fd_sc_hd__buf_16
|
||||
XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_38 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xclkbuf_1_0_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _207_/CLK sky130_fd_sc_hd__clkbuf_2
|
||||
Xdata_delay_2 data_delay_2/A vssd vssd vccd vccd _107_/B sky130_fd_sc_hd__dlygate4sd2_1
|
||||
XFILLER_0_91 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_11_24 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
|
||||
X_191_ _164__13/Y hold4/X _163_/X _166_/X vssd vssd vccd vccd pad_gpio_dm[2] _191_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_input5_A serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_2_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_157_ _172_/A gpio_defaults[11] vssd vssd vccd vccd _158_/A sky130_fd_sc_hd__or2_2
|
||||
X_209_ _209_/A vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__buf_2
|
||||
XFILLER_17_45 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold7 hold7/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_5_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_142__9 _142__9/A vssd vssd vccd vccd _142__9/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__201__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_39 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_3_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_088_ _089_/A gpio_defaults[11] vssd vssd vccd vccd _088_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xhold7 hold7/A vssd vssd vccd vccd hold7/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_190_ _159__12/Y _190_/D _158_/X _161_/X vssd vssd vccd vccd pad_gpio_dm[1] _190_/Q_N
|
||||
+ sky130_fd_sc_hd__dfbbn_2
|
||||
X_173_ _173_/A vssd vssd vccd vccd _173_/X sky130_fd_sc_hd__buf_1
|
||||
X_156_ _156_/A vssd vssd vccd vccd _156_/X sky130_fd_sc_hd__buf_1
|
||||
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__clkdlybuf4s25_1
|
||||
X_208_ resetn vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_2
|
||||
X_139_ _146_/A gpio_defaults[4] vssd vssd vccd vccd _140_/A sky130_fd_sc_hd__or2_2
|
||||
XFILLER_0_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_087_ _089_/A gpio_defaults[11] vssd vssd vccd vccd _087_/X sky130_fd_sc_hd__or2_0
|
||||
X_099__4 _104__9/A vssd vssd vccd vccd _099__4/Y sky130_fd_sc_hd__inv_2
|
||||
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xclkbuf_1_1__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _104__9/A sky130_fd_sc_hd__clkbuf_16
|
||||
XANTENNA__071__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_139_ _139_/A _063_/Y vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_8
|
||||
XANTENNA__066__B user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_155_ _165_/A gpio_defaults[10] vssd vssd vccd vccd _156_/A sky130_fd_sc_hd__or2b_2
|
||||
X_172_ _172_/A gpio_defaults[6] vssd vssd vccd vccd _173_/A sky130_fd_sc_hd__or2_2
|
||||
XFILLER_3_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_138_ _138_/A vssd vssd vccd vccd _138_/X sky130_fd_sc_hd__buf_1
|
||||
X_086_ _085_/A gpio_defaults[10] vssd vssd vccd vccd _086_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xclkbuf_1_1__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _134_/CLK
|
||||
+ sky130_fd_sc_hd__clkbuf_16
|
||||
XANTENNA__074__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold9 hold9/A vssd vssd vccd vccd hold9/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
X_207_ _207_/CLK _207_/D resetn vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_2
|
||||
XANTENNA__167__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__172__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_069_ input2/X _068_/B _109_/Q vssd vssd vccd vccd _069_/Y sky130_fd_sc_hd__o21ai_2
|
||||
X_108__13 _103__8/A vssd vssd vccd vccd _108__13/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__082__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__077__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_171_ _171_/A vssd vssd vccd vccd _171_/X sky130_fd_sc_hd__buf_1
|
||||
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_17_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_3_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_137_ _137_/A gpio_defaults[3] vssd vssd vccd vccd _138_/A sky130_fd_sc_hd__or2b_2
|
||||
XFILLER_17_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__096__A pad_gpio_inenb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_206_ _209_/A hold6/X resetn vssd vssd vccd vccd _206_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
XFILLER_0_84 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA_input3_A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__090__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__085__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_085_ _085_/A gpio_defaults[10] vssd vssd vccd vccd _085_/X sky130_fd_sc_hd__or2_0
|
||||
X_068_ _116_/Q_N _068_/B vssd vssd vccd vccd _068_/X sky130_fd_sc_hd__and2b_2
|
||||
XPHY_37 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__093__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__121__B_N gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_170_ _180_/A gpio_defaults[5] vssd vssd vccd vccd _171_/A sky130_fd_sc_hd__or2b_2
|
||||
XANTENNA__204__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_153_ _153_/A vssd vssd vccd vccd _153_/X sky130_fd_sc_hd__buf_1
|
||||
XFILLER_12_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_205_ _209_/A _205_/D resetn vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_2
|
||||
XANTENNA__144__B_N gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_119_ _119_/A vssd vssd vccd vccd _119_/X sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__197__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_15_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XANTENNA__088__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_067_ _118_/Q _117_/Q _067_/C vssd vssd vccd vccd _068_/B sky130_fd_sc_hd__and3b_2
|
||||
X_136_ _136_/A vssd vssd vccd vccd _136_/X sky130_fd_sc_hd__buf_2
|
||||
X_084_ _083_/A gpio_defaults[1] vssd vssd vccd vccd _084_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XANTENNA__096__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_119_ _106__11/Y _128_/D _091_/X _092_/Y vssd vssd vccd vccd _119_/Q _119_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_062__14 _130_/CLK vssd vssd vccd vccd _135_/CLK sky130_fd_sc_hd__inv_2
|
||||
XPHY_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_113__4 _136__8/A vssd vssd vccd vccd _113__4/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_12_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_152_ _172_/A gpio_defaults[10] vssd vssd vccd vccd _153_/A sky130_fd_sc_hd__or2_2
|
||||
X_135_ _135_/A vssd vssd vccd vccd _135_/X sky130_fd_sc_hd__buf_1
|
||||
X_204_ _209_/A _204_/D resetn vssd vssd vccd vccd _204_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
X_118_ _180_/A gpio_defaults[2] vssd vssd vccd vccd _119_/A sky130_fd_sc_hd__or2_2
|
||||
X_083_ _083_/A gpio_defaults[1] vssd vssd vccd vccd _083_/X sky130_fd_sc_hd__or2_0
|
||||
X_118_ _105__10/Y hold7/X _089_/X _090_/Y vssd vssd vccd vccd _118_/Q _118_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_135_ _135_/CLK hold7/A _136_/A vssd vssd vccd vccd _135_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
X_061__1 _104__9/A vssd vssd vccd vccd _061__1/Y sky130_fd_sc_hd__inv_2
|
||||
X_066_ _109_/Q user_gpio_out vssd vssd vccd vccd _066_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XFILLER_0_31 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_39 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_0__049_ _141_/X vssd vssd vccd vccd clkbuf_0__049_/X sky130_fd_sc_hd__clkbuf_16
|
||||
Xclkbuf_1_0_0__049_ clkbuf_0__049_/X vssd vssd vccd vccd _164__13/A sky130_fd_sc_hd__clkbuf_2
|
||||
X_134_ _146_/A gpio_defaults[3] vssd vssd vccd vccd _135_/A sky130_fd_sc_hd__or2_2
|
||||
X_203_ _207_/CLK _203_/D resetn vssd vssd vccd vccd _203_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
X_151_ _177_/A vssd vssd vccd vccd _172_/A sky130_fd_sc_hd__buf_1
|
||||
XFILLER_18_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_117_ _117_/A vssd vssd vccd vccd _117_/X sky130_fd_sc_hd__buf_1
|
||||
X_134_ _134_/CLK hold2/X _089_/A vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_065_ user_gpio_oeb _064_/X _109_/Q vssd vssd vccd vccd _065_/X sky130_fd_sc_hd__mux2_4
|
||||
X_082_ _091_/A gpio_defaults[4] vssd vssd vccd vccd _082_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xserial_load_out_buffer _104__9/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__clkbuf_16
|
||||
XANTENNA_input1_A mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_117_ _104__9/Y hold2/X _087_/X _088_/Y vssd vssd vccd vccd _117_/Q _117_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_102__7 _104__9/A vssd vssd vccd vccd _102__7/Y sky130_fd_sc_hd__inv_2
|
||||
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__102__A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_150_ _150_/A vssd vssd vccd vccd _150_/X sky130_fd_sc_hd__buf_1
|
||||
X_159__12 _164__13/A vssd vssd vccd vccd _159__12/Y sky130_fd_sc_hd__inv_2
|
||||
X_133_ _133_/A vssd vssd vccd vccd _133_/X sky130_fd_sc_hd__buf_1
|
||||
X_202_ _207_/CLK _202_/D resetn vssd vssd vccd vccd _202_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
X_116_ _137_/A gpio_defaults[0] vssd vssd vccd vccd _117_/A sky130_fd_sc_hd__or2b_2
|
||||
X_081_ _091_/A gpio_defaults[4] vssd vssd vccd vccd _081_/X sky130_fd_sc_hd__or2_0
|
||||
X_133_ _134_/CLK _133_/D _089_/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_064_ _115_/Q _067_/C vssd vssd vccd vccd _064_/X sky130_fd_sc_hd__and2_0
|
||||
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__180__B_N gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__207__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_116_ _103__8/Y _133_/D _085_/X _086_/Y vssd vssd vccd vccd _116_/Q _116_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA_clkbuf_0_serial_clock_A serial_clock vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__137__B_N gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_132_ _137_/A gpio_defaults[9] vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__or2b_2
|
||||
XANTENNA__099__A2 mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_201_ _207_/CLK _201_/D resetn vssd vssd vccd vccd _201_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
XFILLER_18_63 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XANTENNA__110__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_115_ _177_/A vssd vssd vccd vccd _137_/A sky130_fd_sc_hd__buf_1
|
||||
XANTENNA__211__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__170__B_N gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_063_ _113_/Q _115_/Q vssd vssd vccd vccd _063_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_132_ _134_/CLK hold1/X _085_/A vssd vssd vccd vccd _132_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
X_080_ _083_/A gpio_defaults[3] vssd vssd vccd vccd _080_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_115_ _102__7/Y hold5/X _083_/X _084_/Y vssd vssd vccd vccd _115_/Q _115_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xoutput6 _119_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_16
|
||||
.ends
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -39,6 +39,11 @@
|
|||
* See mprj_ctrl.v for the module that registers the data for each
|
||||
* I/O and drives the input to the shift register.
|
||||
*
|
||||
* Modified 7/24/2022 by Tim Edwards
|
||||
* Replaced the data delay with a negative edge-triggered flop
|
||||
* so that the serial data bit out from the module only changes on
|
||||
* the clock half cycle. This avoids the need to fine-tune the clock
|
||||
* skew between GPIO blocks.
|
||||
*---------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
|
|
@ -141,15 +146,20 @@ module gpio_control_block #(
|
|||
wire user_gpio_in;
|
||||
wire gpio_in_unbuf;
|
||||
wire gpio_logic1;
|
||||
wire serial_data_pre;
|
||||
wire serial_data_post_1;
|
||||
wire serial_data_post_2;
|
||||
reg serial_data_out;
|
||||
|
||||
/* Serial shift for the above (latched) values */
|
||||
reg [PAD_CTRL_BITS-1:0] shift_register;
|
||||
|
||||
/* Create internal reset and load signals from input reset and clock */
|
||||
assign serial_data_pre = shift_register[PAD_CTRL_BITS-1];
|
||||
/* Latch the output on the clock negative edge */
|
||||
always @(negedge serial_clock or negedge resetn) begin
|
||||
if (resetn == 1'b0) begin
|
||||
/* Clear the shift register output */
|
||||
serial_data_out <= 1'b0;
|
||||
end else begin
|
||||
serial_data_out <= shift_register[PAD_CTRL_BITS-1];
|
||||
end
|
||||
end
|
||||
|
||||
/* Propagate the clock and reset signals so that they aren't wired */
|
||||
/* all over the chip, but are just wired between the blocks. */
|
||||
|
|
@ -157,35 +167,6 @@ module gpio_control_block #(
|
|||
assign resetn_out = resetn;
|
||||
assign serial_load_out = serial_load;
|
||||
|
||||
/* Serial data should be buffered again to avoid hold violations */
|
||||
/* Do this in two ways: (1) Add internal delay cells, and (2) */
|
||||
/* add a final logic gate after that. The logic gate is */
|
||||
/* synthesized and will be sized appropriately for an output buffer */
|
||||
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 data_delay_1 (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.X(serial_data_post_1),
|
||||
.A(serial_data_pre)
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__dlygate4sd2_1 data_delay_2 (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd),
|
||||
`endif
|
||||
.X(serial_data_post_2),
|
||||
.A(serial_data_post_1)
|
||||
);
|
||||
|
||||
assign serial_data_out = serial_data_post_2 & one;
|
||||
|
||||
always @(posedge serial_clock or negedge resetn) begin
|
||||
if (resetn == 1'b0) begin
|
||||
/* Clear shift register */
|
||||
|
|
|
|||
|
|
@ -803,7 +803,7 @@ module housekeeping #(
|
|||
assign mgmt_gpio_out_pre[31:16] = mgmt_gpio_data[31:16];
|
||||
assign mgmt_gpio_out_pre[12:11] = mgmt_gpio_data[12:11];
|
||||
|
||||
assign mgmt_gpio_out_pre[10] = (pass_thru_user) ? mgmt_gpio_in[2]
|
||||
assign mgmt_gpio_out_pre[10] = (pass_thru_user_delay) ? mgmt_gpio_in[2]
|
||||
: mgmt_gpio_data[10];
|
||||
assign mgmt_gpio_out_pre[9] = (pass_thru_user) ? mgmt_gpio_in[4]
|
||||
: mgmt_gpio_data[9];
|
||||
|
|
@ -1058,6 +1058,7 @@ module housekeeping #(
|
|||
serial_bb_resetn <= 1'b0;
|
||||
serial_xfer <= 1'b0;
|
||||
hkspi_disable <= 1'b0;
|
||||
pwr_ctrl_out <= 'd0;
|
||||
|
||||
sram_ro_clk <= 1'b0;
|
||||
sram_ro_csb <= 1'b1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue