mirror of https://github.com/efabless/caravel.git
Merge pull request #166 from efabless/gpio_control_block-sparecell
gpio_control_block sparecell
This commit is contained in:
Mohamed Shalan
GitHub
commit
344f806980
File diff suppressed because it is too large
Load Diff
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@ -8,344 +8,258 @@ MACRO gpio_control_block
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ORIGIN 0.000 0.000 ;
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SIZE 170.000 BY 65.000 ;
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PIN gpio_defaults[0]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 4.690 61.000 4.970 65.000 ;
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END
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END gpio_defaults[0]
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PIN gpio_defaults[10]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 27.690 61.000 27.970 65.000 ;
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END
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END gpio_defaults[10]
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PIN gpio_defaults[11]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 29.990 61.000 30.270 65.000 ;
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END
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END gpio_defaults[11]
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PIN gpio_defaults[12]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 32.290 61.000 32.570 65.000 ;
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END
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END gpio_defaults[12]
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PIN gpio_defaults[1]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 6.990 61.000 7.270 65.000 ;
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END
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END gpio_defaults[1]
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PIN gpio_defaults[2]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 9.290 61.000 9.570 65.000 ;
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END
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END gpio_defaults[2]
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PIN gpio_defaults[3]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 11.590 61.000 11.870 65.000 ;
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END
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END gpio_defaults[3]
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PIN gpio_defaults[4]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 13.890 61.000 14.170 65.000 ;
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END
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END gpio_defaults[4]
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PIN gpio_defaults[5]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 16.190 61.000 16.470 65.000 ;
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END
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END gpio_defaults[5]
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PIN gpio_defaults[6]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 18.490 61.000 18.770 65.000 ;
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END
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END gpio_defaults[6]
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PIN gpio_defaults[7]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 20.790 61.000 21.070 65.000 ;
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END
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END gpio_defaults[7]
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PIN gpio_defaults[8]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 23.090 61.000 23.370 65.000 ;
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END
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END gpio_defaults[8]
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PIN gpio_defaults[9]
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met2 ;
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RECT 25.390 61.000 25.670 65.000 ;
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END
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END gpio_defaults[9]
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PIN mgmt_gpio_in
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 4.120 170.000 4.720 ;
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END
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END mgmt_gpio_in
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PIN mgmt_gpio_oeb
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 8.200 170.000 8.800 ;
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END
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END mgmt_gpio_oeb
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PIN mgmt_gpio_out
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 10.240 170.000 10.840 ;
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END
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END mgmt_gpio_out
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PIN one
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 6.160 170.000 6.760 ;
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END
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END one
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PIN pad_gpio_ana_en
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 12.280 170.000 12.880 ;
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END
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END pad_gpio_ana_en
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PIN pad_gpio_ana_pol
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 14.320 170.000 14.920 ;
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END
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END pad_gpio_ana_pol
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PIN pad_gpio_ana_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 16.360 170.000 16.960 ;
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END
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END pad_gpio_ana_sel
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PIN pad_gpio_dm[0]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 18.400 170.000 19.000 ;
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END
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END pad_gpio_dm[0]
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PIN pad_gpio_dm[1]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 20.440 170.000 21.040 ;
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END
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END pad_gpio_dm[1]
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PIN pad_gpio_dm[2]
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 22.480 170.000 23.080 ;
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END
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END pad_gpio_dm[2]
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PIN pad_gpio_holdover
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 24.520 170.000 25.120 ;
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END
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END pad_gpio_holdover
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PIN pad_gpio_ib_mode_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 26.560 170.000 27.160 ;
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END
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END pad_gpio_ib_mode_sel
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PIN pad_gpio_in
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 28.600 170.000 29.200 ;
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END
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END pad_gpio_in
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PIN pad_gpio_inenb
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 30.640 170.000 31.240 ;
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END
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END pad_gpio_inenb
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PIN pad_gpio_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 32.680 170.000 33.280 ;
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END
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END pad_gpio_out
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PIN pad_gpio_outenb
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 34.720 170.000 35.320 ;
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END
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END pad_gpio_outenb
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PIN pad_gpio_slow_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 36.760 170.000 37.360 ;
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END
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END pad_gpio_slow_sel
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PIN pad_gpio_vtrip_sel
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 38.800 170.000 39.400 ;
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END
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END pad_gpio_vtrip_sel
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PIN resetn
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 40.840 170.000 41.440 ;
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END
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END resetn
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PIN resetn_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 42.880 170.000 43.480 ;
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END
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END resetn_out
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PIN serial_clock
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 44.920 170.000 45.520 ;
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END
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END serial_clock
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PIN serial_clock_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 46.960 170.000 47.560 ;
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END
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END serial_clock_out
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PIN serial_data_in
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 49.000 170.000 49.600 ;
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END
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END serial_data_in
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PIN serial_data_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 51.040 170.000 51.640 ;
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END
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END serial_data_out
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PIN serial_load
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 53.080 170.000 53.680 ;
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END
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END serial_load
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PIN serial_load_out
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 55.120 170.000 55.720 ;
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END
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END serial_load_out
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PIN user_gpio_in
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 57.160 170.000 57.760 ;
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END
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END user_gpio_in
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PIN user_gpio_oeb
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 59.200 170.000 59.800 ;
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END
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END user_gpio_oeb
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PIN user_gpio_out
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DIRECTION INPUT ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 61.240 170.000 61.840 ;
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END
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END user_gpio_out
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PIN vccd
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DIRECTION INOUT ;
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USE POWER ;
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PORT
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LAYER met4 ;
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RECT 12.800 2.480 14.400 60.080 ;
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@ -372,8 +286,6 @@ MACRO gpio_control_block
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END
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END vccd
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PIN vccd1
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DIRECTION INOUT ;
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USE POWER ;
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PORT
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LAYER met4 ;
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RECT 17.800 2.480 19.400 60.080 ;
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@ -396,8 +308,6 @@ MACRO gpio_control_block
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END
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END vccd1
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PIN vssd
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DIRECTION INOUT ;
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USE GROUND ;
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PORT
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LAYER met4 ;
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RECT 25.300 2.480 26.900 60.080 ;
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@ -416,8 +326,6 @@ MACRO gpio_control_block
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END
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END vssd
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PIN vssd1
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DIRECTION INOUT ;
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USE GROUND ;
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PORT
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LAYER met4 ;
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RECT 30.300 2.480 31.900 60.080 ;
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||||
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@ -436,8 +344,6 @@ MACRO gpio_control_block
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END
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END vssd1
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PIN zero
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DIRECTION OUTPUT TRISTATE ;
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USE SIGNAL ;
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PORT
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LAYER met3 ;
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RECT 70.000 2.080 170.000 2.680 ;
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||||
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@ -445,272 +351,24 @@ MACRO gpio_control_block
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END zero
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OBS
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LAYER li1 ;
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RECT 0.000 64.930 4.265 65.070 ;
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LAYER li1 ;
|
||||
RECT 4.265 64.930 169.810 65.000 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 64.845 49.815 64.930 ;
|
||||
LAYER li1 ;
|
||||
RECT 49.815 64.845 169.810 64.930 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 59.925 169.810 64.845 ;
|
||||
RECT 0.000 59.755 4.745 59.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 59.755 169.810 59.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 59.585 169.810 59.755 ;
|
||||
RECT 0.000 58.605 6.505 59.585 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.505 58.605 169.810 59.585 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 58.445 6.585 58.605 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.585 58.445 169.810 58.605 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 58.195 6.085 58.445 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.085 58.195 169.810 58.445 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 58.005 6.585 58.195 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.585 58.005 169.810 58.195 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 57.405 6.505 58.005 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.505 57.405 169.810 58.005 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 30.025 4.265 57.405 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.265 30.025 169.810 57.405 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 30.005 16.795 30.025 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 30.005 169.810 30.025 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.835 4.745 30.005 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 29.835 169.810 30.005 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.655 16.795 29.835 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 29.655 169.810 29.835 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.640 16.910 29.655 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.910 29.640 169.810 29.655 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.395 8.925 29.640 ;
|
||||
LAYER li1 ;
|
||||
RECT 8.925 29.395 169.810 29.640 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 29.095 7.545 29.395 ;
|
||||
LAYER li1 ;
|
||||
RECT 7.545 29.095 169.810 29.395 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 28.925 7.845 29.095 ;
|
||||
LAYER li1 ;
|
||||
RECT 7.845 28.925 169.810 29.095 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 28.305 6.125 28.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.125 28.305 169.810 28.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 27.785 7.845 28.305 ;
|
||||
LAYER li1 ;
|
||||
RECT 7.845 27.785 169.810 28.305 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 27.455 7.625 27.785 ;
|
||||
LAYER li1 ;
|
||||
RECT 7.625 27.455 169.810 27.785 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 27.285 16.795 27.455 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 27.285 169.810 27.455 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 27.115 4.745 27.285 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 27.115 169.810 27.285 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 26.095 16.795 27.115 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 26.095 169.810 27.115 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 25.475 16.705 26.095 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.705 25.475 169.810 26.095 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 24.565 16.795 25.475 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 24.565 169.810 25.475 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 24.395 15.325 24.565 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 24.395 169.810 24.565 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 21.845 16.795 24.395 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 21.845 169.810 24.395 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 21.675 15.325 21.845 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 21.675 169.810 21.845 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 20.865 16.950 21.675 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.950 20.865 169.810 21.675 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 20.365 16.795 20.865 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 20.365 169.810 20.865 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 19.805 16.645 20.365 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.645 19.805 169.810 20.365 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 19.635 16.795 19.805 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 19.635 169.810 19.805 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 19.125 16.950 19.635 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.950 19.125 169.810 19.635 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 18.955 15.325 19.125 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 18.955 169.810 19.125 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 16.405 16.795 18.955 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 16.405 169.810 18.955 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 16.235 15.325 16.405 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 16.235 169.810 16.405 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 15.425 16.950 16.235 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.950 15.425 169.810 16.235 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 14.925 16.795 15.425 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 14.925 169.810 15.425 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 14.365 16.645 14.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.645 14.365 169.810 14.925 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 14.195 16.795 14.365 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 14.195 169.810 14.365 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 13.685 16.950 14.195 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.950 13.685 169.810 14.195 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 13.515 15.325 13.685 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 13.515 169.810 13.685 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 12.675 16.910 13.515 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.910 12.675 169.810 13.515 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 12.115 16.795 12.675 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 12.115 169.810 12.675 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 10.965 16.910 12.115 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.910 10.965 169.810 12.115 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 10.795 15.325 10.965 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 10.795 169.810 10.965 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 10.625 16.795 10.795 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 10.625 169.810 10.795 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 8.415 16.645 10.625 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.645 8.415 169.810 10.625 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 8.245 16.795 8.415 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 8.245 169.810 8.415 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 8.075 15.325 8.245 ;
|
||||
LAYER li1 ;
|
||||
RECT 15.325 8.075 169.810 8.245 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 7.905 16.795 8.075 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 7.905 169.810 8.075 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 5.695 16.645 7.905 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.645 5.695 169.810 7.905 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 5.525 16.795 5.695 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 5.525 169.810 5.695 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 5.355 4.745 5.525 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 5.355 169.810 5.525 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 5.185 16.795 5.355 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 5.185 169.810 5.355 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 4.205 6.505 5.185 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.505 4.205 169.810 5.185 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 4.045 6.585 4.205 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.585 4.045 169.810 4.205 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 3.795 6.085 4.045 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.085 3.795 169.810 4.045 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 3.605 6.585 3.795 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.585 3.605 169.810 3.795 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 2.975 6.505 3.605 ;
|
||||
LAYER li1 ;
|
||||
RECT 6.505 2.975 169.810 3.605 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 2.805 16.795 2.975 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 2.805 169.810 2.975 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 2.635 4.745 2.805 ;
|
||||
LAYER li1 ;
|
||||
RECT 4.745 2.635 169.810 2.805 ;
|
||||
LAYER li1 ;
|
||||
RECT 0.000 0.000 16.795 2.635 ;
|
||||
LAYER li1 ;
|
||||
RECT 16.795 0.000 169.810 2.635 ;
|
||||
RECT 4.600 2.635 51.980 59.925 ;
|
||||
LAYER met1 ;
|
||||
RECT 4.600 0.000 170.000 65.000 ;
|
||||
RECT 4.600 2.480 103.890 60.480 ;
|
||||
LAYER met2 ;
|
||||
RECT 5.250 60.720 6.710 65.000 ;
|
||||
RECT 7.550 60.720 9.010 65.000 ;
|
||||
RECT 9.850 60.720 11.310 65.000 ;
|
||||
RECT 12.150 60.720 13.610 65.000 ;
|
||||
RECT 14.450 60.720 15.910 65.000 ;
|
||||
RECT 16.750 60.720 18.210 65.000 ;
|
||||
RECT 19.050 60.720 20.510 65.000 ;
|
||||
RECT 21.350 60.720 22.810 65.000 ;
|
||||
RECT 23.650 60.720 25.110 65.000 ;
|
||||
RECT 25.950 60.720 27.410 65.000 ;
|
||||
RECT 28.250 60.720 29.710 65.000 ;
|
||||
RECT 30.550 60.720 32.010 65.000 ;
|
||||
RECT 32.850 60.720 170.000 65.000 ;
|
||||
RECT 4.970 0.000 170.000 60.720 ;
|
||||
RECT 5.250 60.720 6.710 61.725 ;
|
||||
RECT 7.550 60.720 9.010 61.725 ;
|
||||
RECT 9.850 60.720 11.310 61.725 ;
|
||||
RECT 12.150 60.720 13.610 61.725 ;
|
||||
RECT 14.450 60.720 15.910 61.725 ;
|
||||
RECT 16.750 60.720 18.210 61.725 ;
|
||||
RECT 19.050 60.720 20.510 61.725 ;
|
||||
RECT 21.350 60.720 22.810 61.725 ;
|
||||
RECT 23.650 60.720 25.110 61.725 ;
|
||||
RECT 25.950 60.720 27.410 61.725 ;
|
||||
RECT 28.250 60.720 29.710 61.725 ;
|
||||
RECT 30.550 60.720 32.010 61.725 ;
|
||||
RECT 32.850 60.720 103.870 61.725 ;
|
||||
RECT 4.970 2.195 103.870 60.720 ;
|
||||
LAYER met3 ;
|
||||
RECT 6.045 60.840 69.600 61.705 ;
|
||||
RECT 6.045 60.200 70.000 60.840 ;
|
||||
|
|
@ -772,31 +430,13 @@ MACRO gpio_control_block
|
|||
RECT 6.045 3.080 70.000 3.720 ;
|
||||
RECT 6.045 2.215 69.600 3.080 ;
|
||||
LAYER met4 ;
|
||||
RECT 6.280 60.480 170.000 65.000 ;
|
||||
RECT 6.280 2.080 12.400 60.480 ;
|
||||
RECT 14.800 2.080 17.400 60.480 ;
|
||||
RECT 19.800 2.080 24.900 60.480 ;
|
||||
RECT 27.300 2.080 29.900 60.480 ;
|
||||
RECT 32.300 2.080 37.400 60.480 ;
|
||||
RECT 39.800 2.080 42.400 60.480 ;
|
||||
RECT 44.800 2.080 170.000 60.480 ;
|
||||
RECT 6.280 0.000 170.000 2.080 ;
|
||||
LAYER met5 ;
|
||||
RECT 50.000 59.800 170.000 65.000 ;
|
||||
RECT 51.600 51.790 170.000 59.800 ;
|
||||
RECT 50.000 51.350 170.000 51.790 ;
|
||||
RECT 51.600 43.340 170.000 51.350 ;
|
||||
RECT 50.000 42.900 170.000 43.340 ;
|
||||
RECT 51.600 34.890 170.000 42.900 ;
|
||||
RECT 50.000 34.450 170.000 34.890 ;
|
||||
RECT 51.600 26.440 170.000 34.450 ;
|
||||
RECT 50.000 26.000 170.000 26.440 ;
|
||||
RECT 51.600 17.990 170.000 26.000 ;
|
||||
RECT 50.000 17.550 170.000 17.990 ;
|
||||
RECT 51.600 9.540 170.000 17.550 ;
|
||||
RECT 50.000 9.100 170.000 9.540 ;
|
||||
RECT 51.600 4.300 170.000 9.100 ;
|
||||
RECT 50.000 0.000 170.000 4.300 ;
|
||||
RECT 6.280 8.160 12.400 52.185 ;
|
||||
RECT 14.800 8.160 17.400 52.185 ;
|
||||
RECT 19.800 8.160 24.900 52.185 ;
|
||||
RECT 27.300 8.160 29.900 52.185 ;
|
||||
RECT 32.300 8.160 37.400 52.185 ;
|
||||
RECT 39.800 8.160 42.400 52.185 ;
|
||||
RECT 44.800 8.160 45.705 52.185 ;
|
||||
END
|
||||
END gpio_control_block
|
||||
END LIBRARY
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1665142206
|
||||
timestamp 1665359486
|
||||
<< obsli1 >>
|
||||
rect 0 13000 853 13014
|
||||
rect 0 0 33962 13000
|
||||
|
|
@ -303,8 +303,8 @@ port 47 nsew signal output
|
|||
string FIXED_BBOX 0 0 34000 13000
|
||||
string LEFclass BLOCK
|
||||
string LEFview TRUE
|
||||
string GDS_END 560298
|
||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_10_07_04_28/results/signoff/gpio_control_block.magic.gds
|
||||
string GDS_START 184426
|
||||
string GDS_END 562744
|
||||
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_10_09_16_50/results/signoff/gpio_control_block.magic.gds
|
||||
string GDS_START 196838
|
||||
<< end >>
|
||||
|
||||
|
|
|
|||
2
manifest
2
manifest
|
|
@ -15,7 +15,7 @@ d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
|
|||
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
|
||||
36af0303a0e84ce4a40a854ef1481f8a56bc9989 verilog/rtl/digital_pll.v
|
||||
ce49f9af199b5f16d2c39c417d58e5890bc7bab2 verilog/rtl/digital_pll_controller.v
|
||||
1f894f1c43d42017c157d8dd7d2e4674c1a43303 verilog/rtl/gpio_control_block.v
|
||||
00d2c61e4f424dfce3635f96a1c1bfdeaf7d0cf8 verilog/rtl/gpio_control_block.v
|
||||
9c92ddf1391fa75ee906e452e168ca2cdd23bd18 verilog/rtl/gpio_defaults_block.v
|
||||
32d395d5936632f3c92a0de4867d6dd7cd4af1bb verilog/rtl/gpio_logic_high.v
|
||||
9b602cb0e7f0e6b7e21d87d3a2bd30cb631302c4 verilog/rtl/housekeeping.v
|
||||
|
|
|
|||
|
|
@ -79,7 +79,7 @@ set ::env(FP_PDN_VSPACING) 3.4
|
|||
set ::env(FP_PDN_HSPACING) 3.4
|
||||
|
||||
## Placement
|
||||
set ::env(PL_TARGET_DENSITY) 0.9
|
||||
set ::env(PL_TARGET_DENSITY) 0.95
|
||||
# for some reason resizer is leaving a floating net after running repair_tie_fanout command
|
||||
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 0
|
||||
|
||||
|
|
@ -155,3 +155,4 @@ set ::env(DRC_EXCLUDE_CELL_LIST) $::env(DESIGN_DIR)/drc_exclude_list.txt
|
|||
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) $::env(DESIGN_DIR)/drc_exclude_list.txt
|
||||
set ::env(RSZ_DONT_TOUCH) "user_gpio_out user_gpio_oeb serial_clock_out serial_load_out gpio_defaults*"
|
||||
set ::env(FP_PDN_SKIPTRIM) 1
|
||||
set ::env(MAGIC_NO_DEF_BLOCKAGES) 1
|
||||
|
|
|
|||
|
|
@ -55,9 +55,9 @@ proc custom_run_placement {args} {
|
|||
}
|
||||
|
||||
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
|
||||
prep -design $SCRIPT_DIR -tag $::env(TAG) -overwrite -verbose 0
|
||||
prep -ignore_mismatches -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 0
|
||||
exec rm -rf $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
exec ln -sf $SCRIPT_DIR/runs/$::env(TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/gpio_control_block_interactive
|
||||
run_synthesis
|
||||
|
||||
init_floorplan
|
||||
|
|
@ -107,7 +107,7 @@ run_antenna_check
|
|||
run_lef_cvc
|
||||
calc_total_runtime
|
||||
save_final_views
|
||||
save_final_views -save_path .. -tag $::env(RUN_TAG)
|
||||
save_final_views -save_path .. -tag $::env(RUN_OPENLANE_RUN_TAG)
|
||||
save_state
|
||||
generate_final_summary_report
|
||||
check_timing_violations
|
||||
|
|
|
|||
|
|
@ -1,6 +1,6 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Fri Oct 7 11:29:34 2022
|
||||
# Sun Oct 9 23:50:57 2022
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
###############################################################################
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -1 +1 @@
|
|||
open_pdks fa87f8f4bbcc7255b6f0c0fb506960f531ae2392
|
||||
open_pdks de752ec0ba4da0ecb1fbcd309eeec4993d88f5bc
|
||||
|
|
|
|||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_design_area
|
||||
============================================================================
|
||||
Design area 2408 u^2 89% utilization.
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
|
||||
===========================================================================
|
||||
report_clock_skew
|
||||
============================================================================
|
||||
Clock serial_clock
|
||||
Latency CRPR Skew
|
||||
_122_/CLK ^
|
||||
0.85
|
||||
_123_/CLK ^
|
||||
0.76 -0.06 0.02
|
||||
|
||||
Clock serial_load
|
||||
No launch/capture paths found.
|
||||
|
||||
|
|
@ -0,0 +1,679 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -path_delay max (Setup)
|
||||
============================================================================
|
||||
Startpoint: gpio_defaults[12] (input port clocked by serial_clock)
|
||||
Endpoint: _115_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[12] (in)
|
||||
4 0.02 gpio_defaults[12] (net)
|
||||
5.00 0.00 10.00 v _087_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.73 1.27 11.27 ^ _087_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _020_ (net)
|
||||
0.73 0.00 11.27 ^ _115_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.27 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.82 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.03 0.00 50.82 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.05 50.37 library recovery time
|
||||
50.37 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.37 data required time
|
||||
-11.27 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.11 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[4] (input port clocked by serial_clock)
|
||||
Endpoint: _111_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[4] (in)
|
||||
4 0.03 gpio_defaults[4] (net)
|
||||
5.00 0.00 10.00 v _079_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.70 1.22 11.22 ^ _079_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _012_ (net)
|
||||
0.70 0.00 11.22 ^ _111_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.22 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.18 50.77 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 50.77 ^ _098__6/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.80 v _098__6/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net37 (net)
|
||||
0.03 0.00 50.81 v _111_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.41 clock uncertainty
|
||||
0.00 50.41 clock reconvergence pessimism
|
||||
-0.05 50.36 library recovery time
|
||||
50.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.36 data required time
|
||||
-11.22 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.14 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[5] (input port clocked by serial_clock)
|
||||
Endpoint: _116_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[5] (in)
|
||||
4 0.02 gpio_defaults[5] (net)
|
||||
5.00 0.00 10.00 v _089_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.68 1.20 11.20 ^ _089_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _022_ (net)
|
||||
0.68 0.00 11.20 ^ _116_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.20 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.18 50.77 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 50.77 ^ _103__11/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 50.80 v _103__11/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net42 (net)
|
||||
0.02 0.00 50.80 v _116_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.40 clock uncertainty
|
||||
0.00 50.40 clock reconvergence pessimism
|
||||
-0.05 50.36 library recovery time
|
||||
50.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.36 data required time
|
||||
-11.20 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.16 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[11] (input port clocked by serial_clock)
|
||||
Endpoint: _114_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[11] (in)
|
||||
4 0.02 gpio_defaults[11] (net)
|
||||
5.00 0.00 10.00 v _085_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.70 1.22 11.22 ^ _085_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _018_ (net)
|
||||
0.70 0.00 11.22 ^ _114_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.22 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _101__9/A (sky130_fd_sc_hd__inv_2)
|
||||
0.04 0.05 50.83 v _101__9/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net40 (net)
|
||||
0.04 0.00 50.83 v _114_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.43 clock uncertainty
|
||||
0.00 50.43 clock reconvergence pessimism
|
||||
-0.04 50.38 library recovery time
|
||||
50.38 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.38 data required time
|
||||
-11.22 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.16 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[3] (input port clocked by serial_clock)
|
||||
Endpoint: _110_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[3] (in)
|
||||
4 0.02 gpio_defaults[3] (net)
|
||||
5.00 0.00 10.00 v _077_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.68 1.20 11.20 ^ _077_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _010_ (net)
|
||||
0.68 0.00 11.20 ^ _110_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.20 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _097__5/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _097__5/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net36 (net)
|
||||
0.03 0.00 50.82 v _110_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.04 50.38 library recovery time
|
||||
50.38 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.38 data required time
|
||||
-11.20 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.18 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.22 26.77 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 26.77 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.07 26.84 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.05 0.00 26.84 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.10 0.41 27.25 ^ _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.10 0.00 27.25 ^ output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.27 0.29 27.54 ^ output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.27 0.01 27.55 ^ serial_data_out (out)
|
||||
27.55 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.55 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.05 slack (MET)
|
||||
|
||||
|
||||
Startpoint: serial_load (clock source 'serial_load')
|
||||
Endpoint: serial_load_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_load (fall edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.23 26.77 v clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.06 0.00 26.77 v serial_load_out_buffer/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.26 27.03 v serial_load_out_buffer/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
1 0.25 serial_load_out (net)
|
||||
0.18 0.03 27.06 v serial_load_out (out)
|
||||
27.06 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.06 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.54 slack (MET)
|
||||
|
||||
|
||||
Startpoint: serial_clock (clock source 'serial_clock')
|
||||
Endpoint: serial_clock_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock (fall edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.22 26.76 v clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.04 0.00 26.76 v serial_clock_out_buffer/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.26 27.03 v serial_clock_out_buffer/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
1 0.25 serial_clock_out (net)
|
||||
0.18 0.02 27.04 v serial_clock_out (out)
|
||||
27.04 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.04 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.56 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _131_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.19 0.84 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.84 ^ _131_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.50 1.34 v _131_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
2 0.01 shift_register[12] (net)
|
||||
0.06 0.00 1.34 v _132_/D (sky130_fd_sc_hd__dfrtp_2)
|
||||
1.34 data arrival time
|
||||
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.40 26.40 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.40 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.20 26.60 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 26.60 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.06 26.66 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.05 0.00 26.66 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
-0.40 26.26 clock uncertainty
|
||||
0.06 26.32 clock reconvergence pessimism
|
||||
-0.12 26.20 library setup time
|
||||
26.20 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
26.20 data required time
|
||||
-1.34 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
24.86 slack (MET)
|
||||
|
||||
|
||||
Startpoint: mgmt_gpio_oeb (input port clocked by serial_clock)
|
||||
Endpoint: pad_gpio_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v mgmt_gpio_oeb (in)
|
||||
2 0.01 mgmt_gpio_oeb (net)
|
||||
5.00 0.00 10.00 v input1/A (sky130_fd_sc_hd__buf_2)
|
||||
0.16 1.31 11.31 v input1/X (sky130_fd_sc_hd__buf_2)
|
||||
2 0.01 net1 (net)
|
||||
0.16 0.00 11.31 v _063_/C (sky130_fd_sc_hd__and3b_2)
|
||||
0.06 0.30 11.62 v _063_/X (sky130_fd_sc_hd__and3b_2)
|
||||
2 0.01 _043_ (net)
|
||||
0.06 0.00 11.62 v _064_/B (sky130_fd_sc_hd__and2b_2)
|
||||
0.05 0.23 11.85 v _064_/X (sky130_fd_sc_hd__and2b_2)
|
||||
1 0.01 _044_ (net)
|
||||
0.05 0.00 11.85 v _066_/A1 (sky130_fd_sc_hd__o21ai_4)
|
||||
0.17 0.20 12.04 ^ _066_/Y (sky130_fd_sc_hd__o21ai_4)
|
||||
1 0.02 net16 (net)
|
||||
0.17 0.00 12.04 ^ output16/A (sky130_fd_sc_hd__buf_16)
|
||||
0.27 0.31 12.35 ^ output16/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 pad_gpio_out (net)
|
||||
0.27 0.01 12.36 ^ pad_gpio_out (out)
|
||||
12.36 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-12.36 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
27.24 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.50 1.35 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.06 0.00 1.35 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.09 0.64 1.98 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.09 0.00 1.98 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.98 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 50.82 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.25 library setup time
|
||||
50.25 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.25 data required time
|
||||
-1.98 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _129_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _113_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.19 0.84 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.84 ^ _129_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.48 1.32 v _129_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[10] (net)
|
||||
0.05 0.00 1.32 v hold9/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.09 0.63 1.95 v hold9/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net54 (net)
|
||||
0.09 0.00 1.95 v _113_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.95 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.18 50.77 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 50.77 ^ _100__8/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.03 50.80 v _100__8/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net39 (net)
|
||||
0.02 0.00 50.80 v _113_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.40 clock uncertainty
|
||||
0.00 50.40 clock reconvergence pessimism
|
||||
-0.18 50.22 library setup time
|
||||
50.22 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.22 data required time
|
||||
-1.95 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _120_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _112_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _120_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.49 1.34 v _120_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[1] (net)
|
||||
0.06 0.00 1.34 v hold6/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.63 1.97 v hold6/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net51 (net)
|
||||
0.08 0.00 1.97 v _112_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.97 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _099__7/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.82 v _099__7/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net38 (net)
|
||||
0.03 0.00 50.82 v _112_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.24 library setup time
|
||||
50.24 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.24 data required time
|
||||
-1.97 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _122_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _110_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _122_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.49 1.34 v _122_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[3] (net)
|
||||
0.06 0.00 1.34 v hold7/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.63 1.96 v hold7/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net52 (net)
|
||||
0.08 0.00 1.96 v _110_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.96 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _097__5/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _097__5/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net36 (net)
|
||||
0.03 0.00 50.82 v _110_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.25 library setup time
|
||||
50.25 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.25 data required time
|
||||
-1.96 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.29 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _124_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _116_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _124_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.48 1.32 v _124_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[5] (net)
|
||||
0.05 0.00 1.32 v hold13/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.61 1.94 v hold13/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net58 (net)
|
||||
0.08 0.00 1.94 v _116_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.94 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.18 50.77 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 50.77 ^ _103__11/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 50.80 v _103__11/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net42 (net)
|
||||
0.02 0.00 50.80 v _116_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.40 clock uncertainty
|
||||
0.00 50.40 clock reconvergence pessimism
|
||||
-0.17 50.23 library setup time
|
||||
50.23 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.23 data required time
|
||||
-1.94 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.30 slack (MET)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,714 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -path_delay min (Hold)
|
||||
============================================================================
|
||||
Startpoint: gpio_defaults[0] (input port clocked by serial_clock)
|
||||
Endpoint: _106_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[0] (in)
|
||||
4 0.03 gpio_defaults[0] (net)
|
||||
5.00 0.00 10.00 ^ _068_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.07 0.29 10.29 ^ _068_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _001_ (net)
|
||||
0.07 0.00 10.29 ^ _106_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.29 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _058__1/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 0.91 v _058__1/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net32 (net)
|
||||
0.03 0.00 0.91 v _106_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.07 1.38 library removal time
|
||||
1.38 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.38 data required time
|
||||
-10.29 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.91 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[10] (input port clocked by serial_clock)
|
||||
Endpoint: _113_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[10] (in)
|
||||
4 0.02 gpio_defaults[10] (net)
|
||||
5.00 0.00 10.00 ^ _082_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.06 0.28 10.28 ^ _082_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _015_ (net)
|
||||
0.06 0.00 10.28 ^ _113_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.28 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _100__8/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 0.89 v _100__8/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net39 (net)
|
||||
0.02 0.00 0.89 v _113_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.29 clock uncertainty
|
||||
0.00 1.29 clock reconvergence pessimism
|
||||
0.07 1.36 library removal time
|
||||
1.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.36 data required time
|
||||
-10.28 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[2] (input port clocked by serial_clock)
|
||||
Endpoint: _107_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[2] (in)
|
||||
4 0.02 gpio_defaults[2] (net)
|
||||
5.00 0.00 10.00 ^ _070_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.08 0.30 10.30 ^ _070_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _003_ (net)
|
||||
0.08 0.00 10.30 ^ _107_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.30 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 0.91 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 0.91 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.07 1.38 library removal time
|
||||
1.38 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.38 data required time
|
||||
-10.30 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.92 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[7] (input port clocked by serial_clock)
|
||||
Endpoint: _118_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[7] (in)
|
||||
4 0.02 gpio_defaults[7] (net)
|
||||
5.00 0.00 10.00 ^ _092_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.06 0.28 10.28 ^ _092_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _025_ (net)
|
||||
0.06 0.00 10.28 ^ _118_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.28 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _105__13/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 0.88 v _105__13/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.00 net44 (net)
|
||||
0.02 0.00 0.88 v _118_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.28 clock uncertainty
|
||||
0.00 1.28 clock reconvergence pessimism
|
||||
0.07 1.35 library removal time
|
||||
1.35 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.35 data required time
|
||||
-10.28 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.93 slack (MET)
|
||||
|
||||
|
||||
Startpoint: gpio_defaults[6] (input port clocked by serial_clock)
|
||||
Endpoint: _117_ (removal check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[6] (in)
|
||||
4 0.02 gpio_defaults[6] (net)
|
||||
5.00 0.00 10.00 ^ _090_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.07 0.29 10.29 ^ _090_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.00 _023_ (net)
|
||||
0.07 0.00 10.29 ^ _117_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
10.29 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _104__12/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.04 0.88 v _104__12/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.00 net43 (net)
|
||||
0.02 0.00 0.88 v _117_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.28 clock uncertainty
|
||||
0.00 1.28 clock reconvergence pessimism
|
||||
0.07 1.35 library removal time
|
||||
1.35 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.35 data required time
|
||||
-10.29 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
8.94 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _123_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _124_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _123_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _123_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[4] (net)
|
||||
0.05 0.00 1.13 ^ hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.66 ^ hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net53 (net)
|
||||
0.08 0.00 1.66 ^ _124_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _124_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.25 clock uncertainty
|
||||
-0.06 1.18 clock reconvergence pessimism
|
||||
-0.04 1.14 library hold time
|
||||
1.14 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.14 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.52 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _130_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _131_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _130_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _130_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[11] (net)
|
||||
0.05 0.00 1.13 ^ hold4/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.07 0.53 1.66 ^ hold4/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net49 (net)
|
||||
0.07 0.00 1.66 ^ _131_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.19 0.84 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.84 ^ _131_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.24 clock uncertainty
|
||||
-0.06 1.18 clock reconvergence pessimism
|
||||
-0.04 1.14 library hold time
|
||||
1.14 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.14 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.52 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _127_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _128_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _127_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.14 ^ _127_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[8] (net)
|
||||
0.05 0.00 1.14 ^ hold10/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.67 ^ hold10/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net55 (net)
|
||||
0.08 0.00 1.67 ^ _128_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.67 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.19 0.84 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.84 ^ _128_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.24 clock uncertainty
|
||||
-0.06 1.18 clock reconvergence pessimism
|
||||
-0.04 1.14 library hold time
|
||||
1.14 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.14 data required time
|
||||
-1.67 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.53 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _119_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _120_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _119_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.04 0.36 1.12 ^ _119_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[0] (net)
|
||||
0.04 0.00 1.12 ^ hold1/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.11 0.55 1.68 ^ hold1/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net46 (net)
|
||||
0.11 0.00 1.68 ^ _120_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.68 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _120_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.25 clock uncertainty
|
||||
-0.06 1.19 clock reconvergence pessimism
|
||||
-0.05 1.14 library hold time
|
||||
1.14 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.14 data required time
|
||||
-1.68 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.54 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _125_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _126_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _125_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _125_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[6] (net)
|
||||
0.05 0.00 1.13 ^ hold12/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.67 ^ hold12/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net57 (net)
|
||||
0.08 0.00 1.67 ^ _126_/D (sky130_fd_sc_hd__dfrtp_4)
|
||||
1.67 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _126_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.40 1.25 clock uncertainty
|
||||
-0.08 1.17 clock reconvergence pessimism
|
||||
-0.04 1.13 library hold time
|
||||
1.13 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.13 data required time
|
||||
-1.67 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.54 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _130_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _114_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _130_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _130_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[11] (net)
|
||||
0.05 0.00 1.13 ^ hold4/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.07 0.53 1.66 ^ hold4/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net49 (net)
|
||||
0.07 0.00 1.66 ^ _114_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _101__9/A (sky130_fd_sc_hd__inv_2)
|
||||
0.04 0.05 0.91 v _101__9/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net40 (net)
|
||||
0.04 0.00 0.91 v _114_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.04 1.36 library hold time
|
||||
1.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.36 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.30 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _131_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _115_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _131_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.39 1.15 ^ _131_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
2 0.01 shift_register[12] (net)
|
||||
0.06 0.00 1.15 ^ hold3/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.05 0.51 1.66 ^ hold3/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
1 0.00 net48 (net)
|
||||
0.05 0.00 1.66 ^ _115_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 0.91 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.03 0.00 0.91 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.05 1.36 library hold time
|
||||
1.36 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.36 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.31 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _123_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _111_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _123_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.13 ^ _123_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[4] (net)
|
||||
0.05 0.00 1.13 ^ hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.66 ^ hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net53 (net)
|
||||
0.08 0.00 1.66 ^ _111_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.66 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _098__6/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 0.89 v _098__6/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net37 (net)
|
||||
0.03 0.00 0.89 v _111_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.29 clock uncertainty
|
||||
0.00 1.29 clock reconvergence pessimism
|
||||
0.04 1.33 library hold time
|
||||
1.33 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.33 data required time
|
||||
-1.66 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.33 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _119_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _106_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_1__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.05 0.17 0.76 ^ clkbuf_1_1__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.03 serial_clock_out_buffered (net)
|
||||
0.05 0.00 0.76 ^ _119_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.04 0.36 1.12 ^ _119_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[0] (net)
|
||||
0.04 0.00 1.12 ^ hold1/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.11 0.55 1.68 ^ hold1/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net46 (net)
|
||||
0.11 0.00 1.68 ^ _106_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.68 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.21 0.86 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 0.86 ^ _058__1/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 0.91 v _058__1/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net32 (net)
|
||||
0.03 0.00 0.91 v _106_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.31 clock uncertainty
|
||||
0.00 1.31 clock reconvergence pessimism
|
||||
0.03 1.34 library hold time
|
||||
1.34 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.34 data required time
|
||||
-1.68 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.33 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _127_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _108_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: min
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.59 0.59 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.59 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.17 0.76 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.77 ^ _127_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.37 1.14 ^ _127_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.00 shift_register[8] (net)
|
||||
0.05 0.00 1.14 ^ hold10/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.08 0.53 1.67 ^ hold10/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net55 (net)
|
||||
0.08 0.00 1.67 ^ _108_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.67 data arrival time
|
||||
|
||||
0.00 0.00 clock serial_load' (fall edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.65 0.65 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 0.65 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.20 0.85 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.06 0.00 0.85 ^ _095__3/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 0.89 v _095__3/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net34 (net)
|
||||
0.03 0.00 0.89 v _108_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.40 1.29 clock uncertainty
|
||||
0.00 1.29 clock reconvergence pessimism
|
||||
0.04 1.33 library hold time
|
||||
1.33 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
1.33 data required time
|
||||
-1.67 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
0.34 slack (MET)
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
|
||||
===========================================================================
|
||||
report_power
|
||||
============================================================================
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 2.58e-05 1.05e-06 2.17e-10 2.68e-05 20.0%
|
||||
Combinational 3.88e-05 6.84e-05 7.83e-10 1.07e-04 80.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 6.46e-05 6.95e-05 1.00e-09 1.34e-04 100.0%
|
||||
48.2% 51.8% 0.0%
|
||||
|
|
@ -0,0 +1,145 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -unconstrained
|
||||
============================================================================
|
||||
Startpoint: gpio_defaults[12] (input port clocked by serial_clock)
|
||||
Endpoint: _115_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[12] (in)
|
||||
4 0.02 gpio_defaults[12] (net)
|
||||
5.00 0.00 10.00 v _087_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.73 1.27 11.27 ^ _087_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _020_ (net)
|
||||
0.73 0.00 11.27 ^ _115_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.27 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.82 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.03 0.00 50.82 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.05 50.37 library recovery time
|
||||
50.37 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.37 data required time
|
||||
-11.27 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.11 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.22 26.77 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 26.77 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.07 26.84 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.05 0.00 26.84 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.10 0.41 27.25 ^ _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.10 0.00 27.25 ^ output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.27 0.29 27.54 ^ output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.27 0.01 27.55 ^ serial_data_out (out)
|
||||
27.55 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.55 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.05 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.50 1.35 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.06 0.00 1.35 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.09 0.64 1.98 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.09 0.00 1.98 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.98 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 50.82 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.25 library setup time
|
||||
50.25 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.25 data required time
|
||||
-1.98 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
|
||||
===========================================================================
|
||||
report_checks --slack_max -0.01
|
||||
============================================================================
|
||||
No paths found.
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
|
||||
===========================================================================
|
||||
report_check_types -max_slew -max_cap -max_fanout -violators
|
||||
============================================================================
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
ANTENNA__080__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__081__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_081_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__061__A0/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_087_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__089__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__088__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__084__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__085__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_089_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_086_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_084_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__087__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_085_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__068__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_061_/A0 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__077__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_069_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_079_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__076__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_074_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__074__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__078__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_076_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__086__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__069__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_075_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__062__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_077_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_078_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__091__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_088_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_091_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__090__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__092__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__082__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_082_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_083_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__072__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_073_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_092_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_080_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__079__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__083__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_093_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__093__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_clock_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_clock/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input2_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_071_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_090_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input3_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__075__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__073__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__070__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_068_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input3/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
_070_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input5_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
input2/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_load/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input5/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input4/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input4_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_062_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_load_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input1_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__071__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_072_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input1/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[0] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[10] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[11] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[12] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[1] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[2] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[3] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[4] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[5] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[6] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[7] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[8] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[9] 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
pad_gpio_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
resetn 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_clock 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_data_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_load 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
clkbuf_1_0__f_serial_clock/X 7 9 -2 (VIOLATED)
|
||||
clkbuf_1_1__f_serial_load/X 7 8 (VIOLATED)
|
||||
fanout30/X 7 8 (VIOLATED)
|
||||
|
||||
|
||||
===========================================================================
|
||||
max slew violation count 92
|
||||
max fanout violation count 3
|
||||
max cap violation count 0
|
||||
============================================================================
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_tns
|
||||
============================================================================
|
||||
tns 0.00
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_wns
|
||||
============================================================================
|
||||
wns 0.00
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
===========================================================================
|
||||
report_worst_slack -max (Setup)
|
||||
============================================================================
|
||||
worst slack 12.05
|
||||
|
||||
===========================================================================
|
||||
report_worst_slack -min (Hold)
|
||||
============================================================================
|
||||
worst slack 0.30
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_design_area
|
||||
============================================================================
|
||||
Design area 2408 u^2 89% utilization.
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
|
||||
===========================================================================
|
||||
report_clock_skew
|
||||
============================================================================
|
||||
|
||||
======================== Slowest Corner ==================================
|
||||
|
||||
Clock serial_clock
|
||||
Latency CRPR Skew
|
||||
_122_/CLK ^
|
||||
1.62
|
||||
_123_/CLK ^
|
||||
1.46 -0.12 0.04
|
||||
|
||||
Clock serial_load
|
||||
No launch/capture paths found.
|
||||
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
Clock serial_clock
|
||||
Latency CRPR Skew
|
||||
_122_/CLK ^
|
||||
0.85
|
||||
_123_/CLK ^
|
||||
0.76 -0.06 0.02
|
||||
|
||||
Clock serial_load
|
||||
No launch/capture paths found.
|
||||
|
||||
|
||||
======================= Fastest Corner ===================================
|
||||
|
||||
Clock serial_clock
|
||||
Latency CRPR Skew
|
||||
_122_/CLK ^
|
||||
0.12
|
||||
_123_/CLK ^
|
||||
0.11 -0.00 0.01
|
||||
|
||||
Clock serial_load
|
||||
No launch/capture paths found.
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,45 @@
|
|||
|
||||
===========================================================================
|
||||
report_power
|
||||
============================================================================
|
||||
|
||||
|
||||
======================= Slowest Corner =================================
|
||||
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.96e-05 8.16e-07 4.03e-07 2.08e-05 19.8%
|
||||
Combinational 2.99e-05 5.39e-05 9.49e-07 8.47e-05 80.2%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 4.95e-05 5.47e-05 1.35e-06 1.06e-04 100.0%
|
||||
46.9% 51.8% 1.3%
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 2.58e-05 1.05e-06 2.17e-10 2.68e-05 20.0%
|
||||
Combinational 3.88e-05 6.84e-05 3.83e-09 1.07e-04 80.0%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 6.46e-05 6.95e-05 4.05e-09 1.34e-04 100.0%
|
||||
48.2% 51.8% 0.0%
|
||||
|
||||
|
||||
======================= Fastest Corner =================================
|
||||
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 2.99e-05 1.25e-06 5.32e-10 3.11e-05 18.8%
|
||||
Combinational 5.36e-05 8.05e-05 5.86e-09 1.34e-04 81.2%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 8.35e-05 8.18e-05 6.39e-09 1.65e-04 100.0%
|
||||
50.5% 49.5% 0.0%
|
||||
|
|
@ -0,0 +1,446 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -unconstrained
|
||||
============================================================================
|
||||
|
||||
======================= Slowest Corner ===================================
|
||||
|
||||
Startpoint: gpio_defaults[8] (input port clocked by serial_clock)
|
||||
Endpoint: _108_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
Corner: ss
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 ^ input external delay
|
||||
5.00 0.00 10.00 ^ gpio_defaults[8] (in)
|
||||
4 0.02 gpio_defaults[8] (net)
|
||||
5.00 0.00 10.00 ^ _072_/B (sky130_fd_sc_hd__or2_0)
|
||||
0.29 1.06 11.06 ^ _072_/X (sky130_fd_sc_hd__or2_0)
|
||||
1 0.01 _005_ (net)
|
||||
0.29 0.00 11.07 ^ _108_/RESET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.07 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.18 1.18 51.18 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.18 0.00 51.18 ^ clkbuf_1_0__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.10 0.29 51.47 ^ clkbuf_1_0__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
6 0.04 clknet_1_0__leaf_serial_load (net)
|
||||
0.10 0.00 51.47 ^ _095__3/A (sky130_fd_sc_hd__inv_2)
|
||||
0.04 0.08 51.55 v _095__3/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net34 (net)
|
||||
0.04 0.00 51.55 v _108_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 51.15 clock uncertainty
|
||||
0.00 51.15 clock reconvergence pessimism
|
||||
-0.18 50.96 library recovery time
|
||||
50.96 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.96 data required time
|
||||
-11.07 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.90 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
Corner: ss
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 1.68 26.68 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 26.68 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.07 0.34 27.01 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.07 0.00 27.02 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.09 0.11 27.13 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.09 0.00 27.13 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.13 0.93 28.05 v _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.13 0.00 28.05 v output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.22 0.42 28.48 v output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.22 0.01 28.48 v serial_data_out (out)
|
||||
28.48 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-28.48 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
11.12 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
Corner: ss
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.18 1.31 1.31 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.18 0.00 1.31 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.09 0.31 1.62 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.09 0.00 1.62 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.12 1.05 2.67 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.12 0.00 2.67 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.18 1.31 3.98 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.18 0.00 3.98 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
3.98 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.18 1.18 51.18 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.18 0.00 51.18 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.12 0.30 51.49 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.12 0.00 51.49 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.09 51.58 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.05 0.00 51.58 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 51.18 clock uncertainty
|
||||
0.00 51.18 clock reconvergence pessimism
|
||||
-0.41 50.77 library setup time
|
||||
50.77 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.77 data required time
|
||||
-3.98 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
46.79 slack (MET)
|
||||
|
||||
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
Startpoint: gpio_defaults[12] (input port clocked by serial_clock)
|
||||
Endpoint: _115_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
Corner: tt
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[12] (in)
|
||||
4 0.02 gpio_defaults[12] (net)
|
||||
5.00 0.00 10.00 v _087_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.73 1.27 11.27 ^ _087_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _020_ (net)
|
||||
0.73 0.00 11.27 ^ _115_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.27 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.04 50.82 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.03 0.00 50.82 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.05 50.37 library recovery time
|
||||
50.37 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.37 data required time
|
||||
-11.27 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
39.11 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
Corner: tt
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 1.54 26.54 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.16 0.00 26.54 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.22 26.77 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.03 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 26.77 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.05 0.07 26.84 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.05 0.00 26.84 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.10 0.41 27.25 ^ _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.10 0.00 27.25 ^ output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.27 0.29 27.54 ^ output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.27 0.01 27.55 ^ serial_data_out (out)
|
||||
27.55 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-27.55 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.05 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
Corner: tt
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.17 0.65 0.66 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.17 0.00 0.66 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.19 0.85 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.06 0.00 0.85 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.06 0.50 1.35 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.06 0.00 1.35 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.09 0.64 1.98 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.09 0.00 1.98 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
1.98 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.16 0.59 50.59 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.16 0.00 50.59 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.08 0.19 50.78 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.08 0.00 50.78 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.05 50.82 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 50.82 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 50.42 clock uncertainty
|
||||
0.00 50.42 clock reconvergence pessimism
|
||||
-0.17 50.25 library setup time
|
||||
50.25 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
50.25 data required time
|
||||
-1.98 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.27 slack (MET)
|
||||
|
||||
|
||||
|
||||
======================= Fastest Corner ===================================
|
||||
|
||||
Startpoint: gpio_defaults[12] (input port clocked by serial_clock)
|
||||
Endpoint: _115_ (recovery check against falling-edge clock serial_load')
|
||||
Path Group: **async_default**
|
||||
Path Type: max
|
||||
Corner: ff
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock network delay (propagated)
|
||||
10.00 10.00 v input external delay
|
||||
5.00 0.00 10.00 v gpio_defaults[12] (in)
|
||||
4 0.02 gpio_defaults[12] (net)
|
||||
5.00 0.00 10.00 v _087_/B (sky130_fd_sc_hd__nand2b_2)
|
||||
0.56 1.16 11.16 ^ _087_/Y (sky130_fd_sc_hd__nand2b_2)
|
||||
1 0.01 _020_ (net)
|
||||
0.56 0.00 11.16 ^ _115_/SET_B (sky130_fd_sc_hd__dfbbn_2)
|
||||
11.16 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.13 -0.01 49.99 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.13 0.00 49.99 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.13 50.12 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.06 0.00 50.12 ^ _102__10/A (sky130_fd_sc_hd__inv_2)
|
||||
0.02 0.03 50.14 v _102__10/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net41 (net)
|
||||
0.02 0.00 50.14 v _115_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 49.74 clock uncertainty
|
||||
0.00 49.74 clock reconvergence pessimism
|
||||
0.00 49.75 library recovery time
|
||||
49.75 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
49.75 data required time
|
||||
-11.16 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
38.58 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _132_ (rising edge-triggered flip-flop clocked by serial_clock')
|
||||
Endpoint: serial_data_out (output port clocked by serial_clock)
|
||||
Path Group: serial_clock
|
||||
Path Type: max
|
||||
Corner: ff
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
25.00 25.00 clock serial_clock' (rise edge)
|
||||
0.00 25.00 clock source latency
|
||||
5.00 0.00 25.00 v serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 25.00 v clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.13 1.22 26.22 v clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.13 0.00 26.22 v clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.03 0.16 26.38 v clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.03 0.00 26.38 v _059__14/A (sky130_fd_sc_hd__inv_2)
|
||||
0.04 0.05 26.43 ^ _059__14/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net45 (net)
|
||||
0.04 0.00 26.43 ^ _132_/CLK (sky130_fd_sc_hd__dfrtp_2)
|
||||
0.07 0.26 26.69 ^ _132_/Q (sky130_fd_sc_hd__dfrtp_2)
|
||||
1 0.02 net21 (net)
|
||||
0.07 0.00 26.69 ^ output21/A (sky130_fd_sc_hd__buf_16)
|
||||
0.21 0.21 26.90 ^ output21/X (sky130_fd_sc_hd__buf_16)
|
||||
1 0.25 serial_data_out (net)
|
||||
0.21 0.01 26.91 ^ serial_data_out (out)
|
||||
26.91 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_clock (rise edge)
|
||||
0.00 50.00 clock network delay (propagated)
|
||||
-0.40 49.60 clock uncertainty
|
||||
0.00 49.60 clock reconvergence pessimism
|
||||
-10.00 39.60 output external delay
|
||||
39.60 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
39.60 data required time
|
||||
-26.91 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
12.69 slack (MET)
|
||||
|
||||
|
||||
Startpoint: _121_ (rising edge-triggered flip-flop clocked by serial_clock)
|
||||
Endpoint: _107_ (falling edge-triggered flip-flop clocked by serial_load')
|
||||
Path Group: serial_load
|
||||
Path Type: max
|
||||
Corner: ff
|
||||
|
||||
Fanout Cap Slew Delay Time Description
|
||||
-----------------------------------------------------------------------------
|
||||
0.00 0.00 clock serial_clock (rise edge)
|
||||
0.00 0.00 clock source latency
|
||||
5.00 0.00 0.00 ^ serial_clock (in)
|
||||
2 0.02 serial_clock (net)
|
||||
5.00 0.00 0.00 ^ clkbuf_0_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.13 -0.01 -0.01 ^ clkbuf_0_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_clock (net)
|
||||
0.13 0.00 -0.01 ^ clkbuf_1_0__f_serial_clock/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.04 0.13 0.12 ^ clkbuf_1_0__f_serial_clock/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
9 0.04 clknet_1_0__leaf_serial_clock (net)
|
||||
0.04 0.00 0.12 ^ _121_/CLK (sky130_fd_sc_hd__dfrtp_4)
|
||||
0.05 0.31 0.43 v _121_/Q (sky130_fd_sc_hd__dfrtp_4)
|
||||
1 0.01 shift_register[2] (net)
|
||||
0.05 0.00 0.43 v hold5/A (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
0.06 0.42 0.86 v hold5/X (sky130_fd_sc_hd__dlygate4sd3_1)
|
||||
2 0.01 net50 (net)
|
||||
0.06 0.00 0.86 v _107_/D (sky130_fd_sc_hd__dfbbn_2)
|
||||
0.86 data arrival time
|
||||
|
||||
50.00 50.00 clock serial_load' (fall edge)
|
||||
0.00 50.00 clock source latency
|
||||
5.00 0.00 50.00 ^ serial_load (in)
|
||||
2 0.02 serial_load (net)
|
||||
5.00 0.00 50.00 ^ clkbuf_0_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.13 -0.01 49.99 ^ clkbuf_0_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
2 0.02 clknet_0_serial_load (net)
|
||||
0.13 0.00 49.99 ^ clkbuf_1_1__f_serial_load/A (sky130_fd_sc_hd__clkbuf_16)
|
||||
0.06 0.13 50.12 ^ clkbuf_1_1__f_serial_load/X (sky130_fd_sc_hd__clkbuf_16)
|
||||
8 0.06 serial_load_out_buffered (net)
|
||||
0.06 0.00 50.12 ^ _094__2/A (sky130_fd_sc_hd__inv_2)
|
||||
0.03 0.03 50.14 v _094__2/Y (sky130_fd_sc_hd__inv_2)
|
||||
1 0.01 net33 (net)
|
||||
0.03 0.00 50.14 v _107_/CLK_N (sky130_fd_sc_hd__dfbbn_2)
|
||||
-0.40 49.74 clock uncertainty
|
||||
0.00 49.74 clock reconvergence pessimism
|
||||
-0.10 49.65 library setup time
|
||||
49.65 data required time
|
||||
-----------------------------------------------------------------------------
|
||||
49.65 data required time
|
||||
-0.86 data arrival time
|
||||
-----------------------------------------------------------------------------
|
||||
48.79 slack (MET)
|
||||
|
||||
|
||||
|
||||
===========================================================================
|
||||
report_checks --slack_max -0.01
|
||||
============================================================================
|
||||
|
||||
======================= Slowest Corner ===================================
|
||||
|
||||
No paths found.
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
No paths found.
|
||||
|
||||
======================= Fastest Corner ===================================
|
||||
|
||||
No paths found.
|
||||
|
|
@ -0,0 +1,334 @@
|
|||
|
||||
===========================================================================
|
||||
report_check_types -max_slew -max_cap -max_fanout -violators
|
||||
============================================================================
|
||||
|
||||
======================= Slowest Corner ===================================
|
||||
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
ANTENNA__080__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__081__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_081_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__061__A0/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_087_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__089__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__088__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__084__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__085__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_089_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_086_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_084_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__087__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_085_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__068__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_061_/A0 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__077__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_069_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__076__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_079_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_074_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__074__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__078__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_076_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__086__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__069__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__062__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_075_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_077_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_078_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__091__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_088_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__090__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_091_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__092__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__082__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_082_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__072__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_083_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_092_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_073_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_080_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__079__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__083__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_093_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_clock_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__093__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_clock/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input2_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_071_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_090_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input3_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__075__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__073__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__070__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_068_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input3/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input5_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_070_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input2/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_load/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input5/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input4/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input4_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_062_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_load_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input1_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__071__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_072_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input1/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[0] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[10] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[11] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[12] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[1] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[2] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[3] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[4] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[5] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[6] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[7] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[8] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[9] 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
pad_gpio_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
resetn 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_clock 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_data_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_load 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
clkbuf_1_0__f_serial_clock/X 7 9 -2 (VIOLATED)
|
||||
clkbuf_1_1__f_serial_load/X 7 8 (VIOLATED)
|
||||
fanout30/X 7 8 (VIOLATED)
|
||||
|
||||
|
||||
======================= Typical Corner ===================================
|
||||
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
ANTENNA__080__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__081__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_081_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__061__A0/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_087_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__089__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__088__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__084__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__085__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_089_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_086_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_084_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__087__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_085_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__068__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_061_/A0 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__077__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_069_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_079_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__076__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_074_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__074__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__078__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_076_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__086__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__069__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_075_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__062__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_077_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_078_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__091__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_088_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_091_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__090__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__092__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__082__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_082_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_083_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__072__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_073_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_092_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_080_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__079__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__083__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_093_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__093__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_clock_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_clock/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input2_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_071_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_090_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input3_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__075__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__073__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__070__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_068_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input3/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
_070_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input5_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
input2/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_load/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input5/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input4/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input4_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_062_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_load_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input1_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__071__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_072_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input1/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[0] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[10] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[11] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[12] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[1] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[2] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[3] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[4] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[5] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[6] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[7] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[8] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[9] 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
pad_gpio_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
resetn 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_clock 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_data_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_load 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
clkbuf_1_0__f_serial_clock/X 7 9 -2 (VIOLATED)
|
||||
clkbuf_1_1__f_serial_load/X 7 8 (VIOLATED)
|
||||
fanout30/X 7 8 (VIOLATED)
|
||||
|
||||
|
||||
======================= Fastest Corner ===================================
|
||||
|
||||
max slew
|
||||
|
||||
Pin Limit Slew Slack
|
||||
------------------------------------------------------------
|
||||
ANTENNA__080__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__081__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_081_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__061__A0/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_087_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__089__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__084__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__085__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__088__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_086_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_089_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_084_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__087__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_085_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__068__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_061_/A0 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__077__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_069_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_079_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__076__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_074_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__074__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__078__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_076_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__086__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__069__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_075_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__062__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_077_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_078_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_088_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__091__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_091_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__090__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__092__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__082__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_082_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_083_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_092_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
_073_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__072__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_080_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__079__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__083__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_093_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__093__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_clock_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_clock/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
_071_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input2_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_090_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input3_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__075__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__073__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_068_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__070__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
input3/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
_070_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input5_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
input2/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
clkbuf_0_serial_load/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input5/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
input4/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input4_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_062_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_clkbuf_0_serial_load_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA_input1_A/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
ANTENNA__071__B/DIODE 1.25 5.00 -3.75 (VIOLATED)
|
||||
_072_/B 1.25 5.00 -3.75 (VIOLATED)
|
||||
input1/A 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[0] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[10] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[11] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[12] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[1] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[2] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[3] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[4] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[5] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[6] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[7] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[8] 1.25 5.00 -3.75 (VIOLATED)
|
||||
gpio_defaults[9] 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
mgmt_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
pad_gpio_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
resetn 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_clock 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_data_in 1.25 5.00 -3.75 (VIOLATED)
|
||||
serial_load 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_oeb 1.25 5.00 -3.75 (VIOLATED)
|
||||
user_gpio_out 1.25 5.00 -3.75 (VIOLATED)
|
||||
|
||||
max fanout
|
||||
|
||||
Pin Limit Fanout Slack
|
||||
---------------------------------------------------------
|
||||
clkbuf_1_0__f_serial_clock/X 7 9 -2 (VIOLATED)
|
||||
clkbuf_1_1__f_serial_load/X 7 8 (VIOLATED)
|
||||
fanout30/X 7 8 (VIOLATED)
|
||||
|
||||
|
||||
===========================================================================
|
||||
max slew violation count 92
|
||||
max fanout violation count 3
|
||||
max cap violation count 0
|
||||
============================================================================
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_tns
|
||||
============================================================================
|
||||
tns 0.00
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_wns
|
||||
============================================================================
|
||||
wns 0.00
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
===========================================================================
|
||||
report_worst_slack -max (Setup)
|
||||
============================================================================
|
||||
worst slack 11.12
|
||||
|
||||
===========================================================================
|
||||
report_worst_slack -min (Hold)
|
||||
============================================================================
|
||||
worst slack 0.11
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
Instance name, X location, Y location, Voltage
|
||||
_131_, 38.6, 59.84, 1.8
|
||||
_071_, 38.6, 54.4, 1.8
|
||||
_115_, 38.6, 54.4, 1.8
|
||||
hold3, 38.6, 54.4, 1.8
|
||||
_114_, 38.6, 48.96, 1.8
|
||||
hold5, 38.6, 48.96, 1.8
|
||||
hold6, 38.6, 48.96, 1.8
|
||||
hold7, 38.6, 48.96, 1.8
|
||||
_100__8, 38.6, 43.52, 1.8
|
||||
_109_, 38.6, 43.52, 1.8
|
||||
hold10, 38.6, 43.52, 1.8
|
||||
hold2, 38.6, 43.52, 1.8
|
||||
ANTENNA__070__B, 38.6, 38.08, 1.8
|
||||
_108_, 38.6, 38.08, 1.8
|
||||
_129_, 38.6, 38.08, 1.8
|
||||
hold9, 38.6, 38.08, 1.8
|
||||
ANTENNA__093__B, 38.6, 32.64, 1.8
|
||||
_061_, 38.6, 32.64, 1.8
|
||||
_096__4, 38.6, 32.64, 1.8
|
||||
_113_, 38.6, 32.64, 1.8
|
||||
ANTENNA__083__B, 38.6, 27.2, 1.8
|
||||
_066_, 38.6, 27.2, 1.8
|
||||
_082_, 38.6, 27.2, 1.8
|
||||
_083_, 38.6, 27.2, 1.8
|
||||
output17, 38.6, 27.2, 1.8
|
||||
ANTENNA__069__B, 38.6, 21.76, 1.8
|
||||
ANTENNA__092__B, 38.6, 21.76, 1.8
|
||||
_069_, 38.6, 21.76, 1.8
|
||||
_074_, 38.6, 21.76, 1.8
|
||||
_085_, 38.6, 21.76, 1.8
|
||||
output16, 38.6, 21.76, 1.8
|
||||
ANTENNA__074__B, 38.6, 16.32, 1.8
|
||||
_058__1, 38.6, 16.32, 1.8
|
||||
_067_, 38.6, 16.32, 1.8
|
||||
_084_, 38.6, 16.32, 1.8
|
||||
_102__10, 38.6, 16.32, 1.8
|
||||
output15, 38.6, 16.32, 1.8
|
||||
spare_cell, 38.6, 16.32, 1.8
|
||||
_133_, 38.6, 10.88, 1.8
|
||||
fanout31, 38.6, 10.88, 1.8
|
||||
ANTENNA__081__B, 38.6, 5.44, 1.8
|
||||
ANTENNA__082__A, 38.6, 5.44, 1.8
|
||||
ANTENNA__084__B, 38.6, 5.44, 1.8
|
||||
ANTENNA__085__B, 38.6, 5.44, 1.8
|
||||
ANTENNA__087__B, 38.6, 5.44, 1.8
|
||||
ANTENNA_input5_A, 38.6, 5.44, 1.8
|
||||
input1, 38.6, 5.44, 1.8
|
||||
output12, 38.6, 5.44, 1.8
|
||||
output7, 38.6, 5.44, 1.8
|
||||
_072_, 13.6, 54.4, 1.8
|
||||
_107_, 13.6, 54.4, 1.8
|
||||
_110_, 13.6, 48.96, 1.8
|
||||
_119_, 13.6, 48.96, 1.8
|
||||
fanout26, 13.6, 48.96, 1.8
|
||||
_130_, 13.6, 43.52, 1.8
|
||||
hold8, 13.6, 43.52, 1.8
|
||||
output20, 13.6, 43.52, 1.8
|
||||
_111_, 13.6, 38.08, 1.8
|
||||
_123_, 13.6, 38.08, 1.8
|
||||
_116_, 13.6, 32.64, 1.8
|
||||
hold12, 13.6, 32.64, 1.8
|
||||
_126_, 13.6, 27.2, 1.8
|
||||
clkbuf_1_1__f_serial_clock, 13.6, 27.2, 1.8
|
||||
fanout23, 13.6, 27.2, 1.8
|
||||
ANTENNA__077__B, 13.6, 5.44, 1.8
|
||||
ANTENNA__078__B, 13.6, 5.44, 1.8
|
||||
ANTENNA__080__B, 13.6, 5.44, 1.8
|
||||
ANTENNA_fanout27_A, 13.6, 5.44, 1.8
|
||||
ANTENNA_input2_A, 13.6, 5.44, 1.8
|
||||
PHY_2, 13.6, 5.44, 1.8
|
||||
_059__14, 13.6, 5.44, 1.8
|
||||
_098__6, 13.6, 5.44, 1.8
|
||||
PHY_12, 15.18, 21.76, 1.8
|
||||
PHY_14, 15.18, 21.76, 1.8
|
||||
PHY_16, 15.18, 21.76, 1.8
|
||||
_077_, 15.18, 21.76, 1.8
|
||||
_090_, 15.18, 21.76, 1.8
|
||||
clkbuf_1_0__f_serial_load, 15.18, 21.76, 1.8
|
||||
fanout25, 15.18, 21.76, 1.8
|
||||
PHY_13, 51.98, 21.76, 1.8
|
||||
PHY_15, 51.98, 21.76, 1.8
|
||||
_064_, 51.98, 21.76, 1.8
|
||||
input5, 51.98, 21.76, 1.8
|
||||
_117_, 26.89, 21.76, 1.8
|
||||
_134_, 26.89, 21.76, 1.8
|
||||
output18, 26.89, 21.76, 1.8
|
||||
ANTENNA_clkbuf_0_serial_clock_A, 15.18, 16.32, 1.8
|
||||
PHY_10, 15.18, 16.32, 1.8
|
||||
PHY_8, 15.18, 16.32, 1.8
|
||||
_091_, 15.18, 16.32, 1.8
|
||||
output10, 15.18, 16.32, 1.8
|
||||
serial_load_out_buffer, 15.18, 16.32, 1.8
|
||||
PHY_11, 51.98, 16.32, 1.8
|
||||
PHY_9, 51.98, 16.32, 1.8
|
||||
_087_, 51.98, 16.32, 1.8
|
||||
_076_, 26.89, 16.32, 1.8
|
||||
input4, 26.89, 16.32, 1.8
|
||||
output13, 26.89, 16.32, 1.8
|
||||
output14, 26.89, 16.32, 1.8
|
||||
ANTENNA__090__B, 15.18, 10.88, 1.8
|
||||
PHY_4, 15.18, 10.88, 1.8
|
||||
PHY_6, 15.18, 10.88, 1.8
|
||||
_089_, 15.18, 10.88, 1.8
|
||||
_094__2, 15.18, 10.88, 1.8
|
||||
_097__5, 15.18, 10.88, 1.8
|
||||
fanout28, 15.18, 10.88, 1.8
|
||||
serial_clock_out_buffer, 15.18, 10.88, 1.8
|
||||
zero_buffer, 15.18, 10.88, 1.8
|
||||
PHY_5, 51.98, 10.88, 1.8
|
||||
PHY_7, 51.98, 10.88, 1.8
|
||||
_086_, 51.98, 10.88, 1.8
|
||||
input3, 51.98, 10.88, 1.8
|
||||
ANTENNA__061__A0, 26.89, 10.88, 1.8
|
||||
ANTENNA__062__B, 26.89, 10.88, 1.8
|
||||
ANTENNA__076__B, 26.89, 10.88, 1.8
|
||||
ANTENNA__086__B, 26.89, 10.88, 1.8
|
||||
ANTENNA_input3_A, 26.89, 10.88, 1.8
|
||||
ANTENNA_input4_A, 26.89, 10.88, 1.8
|
||||
_103__11, 26.89, 10.88, 1.8
|
||||
_104__12, 26.89, 10.88, 1.8
|
||||
_105__13, 26.89, 10.88, 1.8
|
||||
output11, 26.89, 10.88, 1.8
|
||||
output9, 26.89, 10.88, 1.8
|
||||
PHY_40, 4.6, 59.84, 1.8
|
||||
PHY_41, 51.98, 59.84, 1.8
|
||||
_065_, 51.98, 59.84, 1.8
|
||||
output21, 26.1, 59.84, 1.8
|
||||
PHY_36, 4.6, 54.4, 1.8
|
||||
PHY_38, 4.6, 54.4, 1.8
|
||||
_099__7, 4.6, 54.4, 1.8
|
||||
_132_, 4.6, 54.4, 1.8
|
||||
fanout27, 4.6, 54.4, 1.8
|
||||
output22, 4.6, 54.4, 1.8
|
||||
PHY_37, 51.98, 54.4, 1.8
|
||||
PHY_39, 51.98, 54.4, 1.8
|
||||
_062_, 51.98, 54.4, 1.8
|
||||
fanout24, 26.1, 54.4, 1.8
|
||||
hold1, 26.1, 54.4, 1.8
|
||||
ANTENNA__071__B, 4.6, 48.96, 1.8
|
||||
ANTENNA_clkbuf_0_serial_load_A, 4.6, 48.96, 1.8
|
||||
PHY_32, 4.6, 48.96, 1.8
|
||||
PHY_34, 4.6, 48.96, 1.8
|
||||
_120_, 4.6, 48.96, 1.8
|
||||
_122_, 4.6, 48.96, 1.8
|
||||
PHY_33, 51.98, 48.96, 1.8
|
||||
PHY_35, 51.98, 48.96, 1.8
|
||||
_068_, 51.98, 48.96, 1.8
|
||||
_081_, 51.98, 48.96, 1.8
|
||||
_106_, 26.1, 48.96, 1.8
|
||||
_112_, 26.1, 48.96, 1.8
|
||||
hold4, 26.1, 48.96, 1.8
|
||||
ANTENNA__079__B, 4.6, 43.52, 1.8
|
||||
PHY_28, 4.6, 43.52, 1.8
|
||||
PHY_30, 4.6, 43.52, 1.8
|
||||
_121_, 4.6, 43.52, 1.8
|
||||
hold13, 4.6, 43.52, 1.8
|
||||
PHY_29, 51.98, 43.52, 1.8
|
||||
PHY_31, 51.98, 43.52, 1.8
|
||||
_079_, 51.98, 43.52, 1.8
|
||||
_070_, 26.1, 43.52, 1.8
|
||||
PHY_24, 4.6, 38.08, 1.8
|
||||
PHY_26, 4.6, 38.08, 1.8
|
||||
_080_, 4.6, 38.08, 1.8
|
||||
_095__3, 4.6, 38.08, 1.8
|
||||
clkbuf_0_serial_load, 4.6, 38.08, 1.8
|
||||
output19, 4.6, 38.08, 1.8
|
||||
PHY_25, 51.98, 38.08, 1.8
|
||||
PHY_27, 51.98, 38.08, 1.8
|
||||
_075_, 51.98, 38.08, 1.8
|
||||
_073_, 26.1, 38.08, 1.8
|
||||
_093_, 26.1, 38.08, 1.8
|
||||
_127_, 26.1, 38.08, 1.8
|
||||
_128_, 26.1, 38.08, 1.8
|
||||
ANTENNA__073__B, 4.6, 32.64, 1.8
|
||||
ANTENNA__075__B, 4.6, 32.64, 1.8
|
||||
PHY_20, 4.6, 32.64, 1.8
|
||||
PHY_22, 4.6, 32.64, 1.8
|
||||
_124_, 4.6, 32.64, 1.8
|
||||
_125_, 4.6, 32.64, 1.8
|
||||
PHY_21, 51.98, 32.64, 1.8
|
||||
PHY_23, 51.98, 32.64, 1.8
|
||||
_060_, 51.98, 32.64, 1.8
|
||||
hold11, 26.1, 32.64, 1.8
|
||||
PHY_18, 4.6, 27.2, 1.8
|
||||
_078_, 4.6, 27.2, 1.8
|
||||
_088_, 4.6, 27.2, 1.8
|
||||
clkbuf_0_serial_clock, 4.6, 27.2, 1.8
|
||||
clkbuf_1_1__f_serial_load, 4.6, 27.2, 1.8
|
||||
ANTENNA__082__B, 51.98, 27.2, 1.8
|
||||
PHY_17, 51.98, 27.2, 1.8
|
||||
PHY_19, 51.98, 27.2, 1.8
|
||||
_063_, 51.98, 27.2, 1.8
|
||||
_092_, 26.1, 27.2, 1.8
|
||||
_118_, 26.1, 27.2, 1.8
|
||||
PHY_0, 4.6, 5.44, 1.8
|
||||
clkbuf_1_0__f_serial_clock, 4.6, 5.44, 1.8
|
||||
ANTENNA__068__B, 51.98, 5.44, 1.8
|
||||
PHY_1, 51.98, 5.44, 1.8
|
||||
PHY_3, 51.98, 5.44, 1.8
|
||||
const_source, 51.98, 5.44, 1.8
|
||||
fanout29, 51.98, 5.44, 1.8
|
||||
fanout30, 51.98, 5.44, 1.8
|
||||
input2, 51.98, 5.44, 1.8
|
||||
ANTENNA__072__B, 26.1, 5.44, 1.8
|
||||
ANTENNA__088__B, 26.1, 5.44, 1.8
|
||||
ANTENNA__089__B, 26.1, 5.44, 1.8
|
||||
ANTENNA__091__B, 26.1, 5.44, 1.8
|
||||
ANTENNA_fanout28_A, 26.1, 5.44, 1.8
|
||||
ANTENNA_fanout29_A, 26.1, 5.44, 1.8
|
||||
ANTENNA_input1_A, 26.1, 5.44, 1.8
|
||||
_101__9, 26.1, 5.44, 1.8
|
||||
one_buffer, 26.1, 5.44, 1.8
|
||||
output6, 26.1, 5.44, 1.8
|
||||
output8, 26.1, 5.44, 1.8
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" ?>
|
||||
<report-database>
|
||||
<categories/>
|
||||
<cells>
|
||||
<cell>
|
||||
<name>gpio_control_block</name>
|
||||
</cell>
|
||||
</cells>
|
||||
<items/>
|
||||
</report-database>
|
||||
|
|
@ -0,0 +1 @@
|
|||
$gpio_control_block 100
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
gpio_control_block
|
||||
----------------------------------------
|
||||
[INFO]: COUNT: 0
|
||||
[INFO]: Should be divided by 3 or 4
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,9 +1,5 @@
|
|||
* NGSPICE file created from gpio_control_block.ext - technology: sky130A
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_4 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
|
@ -12,6 +8,10 @@
|
|||
.subckt sky130_fd_sc_hd__nand2b_2 A_N B VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfrtp_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfrtp_4 CLK D RESET_B VGND VNB VPB VPWR Q
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__dfbbn_2 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
|
||||
.ends
|
||||
|
|
@ -52,10 +52,6 @@
|
|||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
|
@ -68,18 +64,14 @@
|
|||
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__macro_sparecell abstract view
|
||||
.subckt sky130_fd_sc_hd__macro_sparecell VGND VNB VPB VPWR LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for gpio_logic_high abstract view
|
||||
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__and2_2 A B VGND VNB VPB VPWR X
|
||||
.ends
|
||||
|
|
@ -112,40 +104,43 @@
|
|||
+ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
|
||||
+ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
|
||||
+ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
|
||||
X_131_ _131_/CLK hold1/X _086_/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_4
|
||||
XFILLER_9_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_3_89 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_062_ _106_/Q user_gpio_out vssd vssd vccd vccd _062_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_131_ _131_/CLK hold4/X _086_/A vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_4
|
||||
XFILLER_0_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_114_ _101__9/Y hold1/X _084_/X _085_/Y vssd vssd vccd vccd _114_/Q _114_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_114_ _101__9/Y hold4/X _084_/X _085_/Y vssd vssd vccd vccd _114_/Q _114_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xoutput20 _134_/X vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_16
|
||||
Xoutput7 _116_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_16
|
||||
X_104__12 _100__8/A vssd vssd vccd vccd _104__12/Y sky130_fd_sc_hd__inv_2
|
||||
X_130_ _131_/CLK hold9/X _086_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_4
|
||||
Xoutput7 _116_/Q vssd vssd vccd vccd pad_gpio_ana_en sky130_fd_sc_hd__buf_16
|
||||
X_130_ _130_/CLK hold9/X _086_/A vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_094__2 _101__9/A vssd vssd vccd vccd _094__2/Y sky130_fd_sc_hd__inv_2
|
||||
X_061_ user_gpio_oeb _060_/X _106_/Q vssd vssd vccd vccd _061_/X sky130_fd_sc_hd__mux2_4
|
||||
X_113_ _100__8/Y hold9/X _082_/X _083_/Y vssd vssd vccd vccd _113_/Q _113_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xclkbuf_1_0__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _100__8/A sky130_fd_sc_hd__clkbuf_16
|
||||
X_059__14 _126_/CLK vssd vssd vccd vccd _132_/CLK sky130_fd_sc_hd__inv_2
|
||||
X_059__14 _130_/CLK vssd vssd vccd vccd _132_/CLK sky130_fd_sc_hd__inv_2
|
||||
Xoutput21 _132_/Q vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_16
|
||||
Xoutput8 _118_/Q vssd vssd vccd vccd pad_gpio_ana_pol sky130_fd_sc_hd__buf_16
|
||||
Xoutput10 _113_/Q vssd vssd vccd vccd pad_gpio_dm[0] sky130_fd_sc_hd__buf_16
|
||||
X_060_ _112_/Q _063_/C vssd vssd vccd vccd _060_/X sky130_fd_sc_hd__and2_0
|
||||
X_112_ _099__7/Y hold3/X _080_/X _081_/Y vssd vssd vccd vccd _112_/Q _112_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold10 _123_/Q vssd vssd vccd vccd _124_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
X_112_ _099__7/Y hold6/X _080_/X _081_/Y vssd vssd vccd vccd _112_/Q _112_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold10 _127_/Q vssd vssd vccd vccd _128_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xoutput22 _067_/X vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__buf_16
|
||||
Xoutput11 _114_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_16
|
||||
Xoutput9 _117_/Q vssd vssd vccd vccd pad_gpio_ana_sel sky130_fd_sc_hd__buf_16
|
||||
X_111_ _098__6/Y _124_/D _078_/X _079_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xoutput11 _114_/Q vssd vssd vccd vccd pad_gpio_dm[1] sky130_fd_sc_hd__buf_16
|
||||
X_111_ _098__6/Y hold8/X _078_/X _079_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XFILLER_0_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_15_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold11 _126_/Q vssd vssd vccd vccd _127_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xoutput12 _115_/Q vssd vssd vccd vccd pad_gpio_dm[2] sky130_fd_sc_hd__buf_16
|
||||
XANTENNA__072__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_110_ _097__5/Y hold6/X _076_/X _077_/Y vssd vssd vccd vccd _110_/Q _110_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_110_ _097__5/Y hold7/X _076_/X _077_/Y vssd vssd vccd vccd _110_/Q _110_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xhold12 _125_/Q vssd vssd vccd vccd _126_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA_fanout29_A _082_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__072__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_097__5 _101__9/A vssd vssd vccd vccd _097__5/Y sky130_fd_sc_hd__inv_2
|
||||
Xoutput13 _107_/Q vssd vssd vccd vccd pad_gpio_holdover sky130_fd_sc_hd__buf_16
|
||||
XANTENNA__080__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__075__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_4_60 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold13 _124_/Q vssd vssd vccd vccd _125_/D sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA__083__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput14 _111_/Q vssd vssd vccd vccd pad_gpio_ib_mode_sel sky130_fd_sc_hd__buf_16
|
||||
|
|
@ -153,123 +148,115 @@ XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
|||
XANTENNA__078__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__091__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__086__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xoutput15 _110_/Q vssd vssd vccd vccd pad_gpio_inenb sky130_fd_sc_hd__buf_16
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__089__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xconst_source vssd vssd vccd vccd one_buffer/A zero_buffer/A sky130_fd_sc_hd__conb_1
|
||||
XFILLER_10_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_1_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XANTENNA_fanout27_A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_fanout27_A _082_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xoutput16 _066_/Y vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__buf_16
|
||||
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_12_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xoutput17 _061_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__buf_16
|
||||
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xfanout30 input4/X vssd vssd vccd vccd fanout30/X sky130_fd_sc_hd__buf_2
|
||||
Xoutput18 _108_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_16
|
||||
Xfanout30 fanout31/X vssd vssd vccd vccd _082_/A sky130_fd_sc_hd__buf_2
|
||||
X_079_ _088_/A gpio_defaults[4] vssd vssd vccd vccd _079_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xoutput18 _108_/Q vssd vssd vccd vccd pad_gpio_slow_sel sky130_fd_sc_hd__buf_16
|
||||
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_serial_load_out_buffer_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_100__8 _100__8/A vssd vssd vccd vccd _100__8/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA_input4_A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xfanout31 input4/X vssd vssd vccd vccd fanout31/X sky130_fd_sc_hd__buf_2
|
||||
Xoutput19 _109_/Q vssd vssd vccd vccd pad_gpio_vtrip_sel sky130_fd_sc_hd__buf_16
|
||||
XANTENNA__061__A0 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_103__11 _100__8/A vssd vssd vccd vccd _103__11/Y sky130_fd_sc_hd__inv_2
|
||||
X_078_ _088_/A gpio_defaults[4] vssd vssd vccd vccd _078_/X sky130_fd_sc_hd__or2_0
|
||||
XANTENNA__097__5_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_103__11 _100__8/A vssd vssd vccd vccd _103__11/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__061__A0 user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__058__1_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_1_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_129_ _131_/CLK hold4/X _074_/A vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_129_ _131_/CLK hold2/X _074_/A vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_077_ _076_/A gpio_defaults[3] vssd vssd vccd vccd _077_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_093_ _092_/A gpio_defaults[7] vssd vssd vccd vccd _093_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_076_ _076_/A gpio_defaults[3] vssd vssd vccd vccd _076_/X sky130_fd_sc_hd__or2_0
|
||||
Xinput1 mgmt_gpio_oeb vssd vssd vccd vccd _063_/C sky130_fd_sc_hd__buf_2
|
||||
X_128_ _131_/CLK hold7/X _074_/A vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_128_ _131_/CLK _128_/D _074_/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_13_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xfanout23 _092_/A vssd vssd vccd vccd _088_/A sky130_fd_sc_hd__buf_2
|
||||
X_092_ _092_/A gpio_defaults[7] vssd vssd vccd vccd _092_/X sky130_fd_sc_hd__or2_0
|
||||
Xinput2 mgmt_gpio_out vssd vssd vccd vccd input2/X sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_input2_A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_075_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _075_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_127_ _131_/CLK _127_/D _092_/A vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_4
|
||||
Xinput2 mgmt_gpio_out vssd vssd vccd vccd input2/X sky130_fd_sc_hd__buf_2
|
||||
XANTENNA_clkbuf_0_serial_load_A serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_075_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _075_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_127_ _130_/CLK _127_/D _092_/A vssd vssd vccd vccd _127_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xfanout24 fanout31/X vssd vssd vccd vccd _092_/A sky130_fd_sc_hd__buf_2
|
||||
X_095__3 _100__8/A vssd vssd vccd vccd _095__3/Y sky130_fd_sc_hd__inv_2
|
||||
Xfanout24 fanout30/X vssd vssd vccd vccd _092_/A sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__102__10_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_074_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _074_/X sky130_fd_sc_hd__or2_0
|
||||
XTAP_70 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput3 pad_gpio_in vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__buf_2
|
||||
X_074_ _074_/A gpio_defaults[9] vssd vssd vccd vccd _074_/X sky130_fd_sc_hd__or2_0
|
||||
X_091_ _088_/A gpio_defaults[6] vssd vssd vccd vccd _091_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_126_ _126_/CLK _126_/D _088_/A vssd vssd vccd vccd _126_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
Xinput3 pad_gpio_in vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__buf_2
|
||||
X_126_ _130_/CLK _126_/D _088_/A vssd vssd vccd vccd _126_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_109_ _096__4/Y hold4/X _074_/X _075_/Y vssd vssd vccd vccd _109_/Q _109_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_109_ _096__4/Y hold2/X _074_/X _075_/Y vssd vssd vccd vccd _109_/Q _109_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xfanout25 _080_/A vssd vssd vccd vccd _076_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_71 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_60 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_090_ _092_/A gpio_defaults[6] vssd vssd vccd vccd _090_/X sky130_fd_sc_hd__or2_0
|
||||
Xinput4 resetn vssd vssd vccd vccd input4/X sky130_fd_sc_hd__buf_2
|
||||
X_090_ _092_/A gpio_defaults[6] vssd vssd vccd vccd _090_/X sky130_fd_sc_hd__or2_0
|
||||
XFILLER_5_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_073_ _074_/A gpio_defaults[8] vssd vssd vccd vccd _073_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_125_ _126_/CLK _125_/D _088_/A vssd vssd vccd vccd _125_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XFILLER_7_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_125_ _130_/CLK _125_/D _088_/A vssd vssd vccd vccd _125_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__062__B user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_108_ _095__3/Y hold7/X _072_/X _073_/Y vssd vssd vccd vccd _108_/Q _108_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XANTENNA__070__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__098__6_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xfanout26 fanout30/X vssd vssd vccd vccd _080_/A sky130_fd_sc_hd__buf_2
|
||||
X_108_ _095__3/Y _128_/D _072_/X _073_/Y vssd vssd vccd vccd _108_/Q _108_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xfanout26 fanout31/X vssd vssd vccd vccd _080_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_72 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_072_ _074_/A gpio_defaults[8] vssd vssd vccd vccd _072_/X sky130_fd_sc_hd__or2_0
|
||||
XTAP_61 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xinput5 serial_data_in vssd vssd vccd vccd _119_/D sky130_fd_sc_hd__buf_2
|
||||
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA__073__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_124_ _126_/CLK _124_/D _092_/A vssd vssd vccd vccd _124_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__101__9_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_124_ _130_/CLK hold8/X _092_/A vssd vssd vccd vccd _124_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
XANTENNA__068__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_107_ _094__2/Y hold8/X _070_/X _071_/Y vssd vssd vccd vccd _107_/Q _107_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xfanout27 _134_/A vssd vssd vccd vccd _074_/A sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__081__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_107_ _094__2/Y hold5/X _070_/X _071_/Y vssd vssd vccd vccd _107_/Q _107_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xfanout27 _082_/A vssd vssd vccd vccd _074_/A sky130_fd_sc_hd__buf_2
|
||||
XANTENNA__076__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__081__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_73 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_071_ _076_/A gpio_defaults[2] vssd vssd vccd vccd _071_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XTAP_62 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_106_ _058__1/Y hold5/X _068_/X _069_/Y vssd vssd vccd vccd _106_/Q _106_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_123_ _126_/CLK hold6/X _092_/A vssd vssd vccd vccd _123_/Q sky130_fd_sc_hd__dfrtp_4
|
||||
X_098__6 _101__9/A vssd vssd vccd vccd _098__6/Y sky130_fd_sc_hd__inv_2
|
||||
X_106_ _058__1/Y hold1/X _068_/X _069_/Y vssd vssd vccd vccd _106_/Q _106_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_123_ _131_/CLK hold7/X _092_/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_098__6 _100__8/A vssd vssd vccd vccd _098__6/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA__084__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__079__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xfanout28 _134_/A vssd vssd vccd vccd _086_/A sky130_fd_sc_hd__buf_2
|
||||
Xfanout28 _082_/A vssd vssd vccd vccd _086_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_63 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_070_ _076_/A gpio_defaults[2] vssd vssd vccd vccd _070_/X sky130_fd_sc_hd__or2_0
|
||||
XANTENNA__092__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA__087__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_122_ _126_/CLK hold8/X _076_/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_4
|
||||
Xserial_clock_out_buffer _126_/CLK vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_16
|
||||
Xfanout29 fanout30/X vssd vssd vccd vccd _134_/A sky130_fd_sc_hd__buf_2
|
||||
X_122_ _130_/CLK hold5/X _076_/A vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_4
|
||||
Xspare_cell vssd vssd vccd vccd spare_cell/LO sky130_fd_sc_hd__macro_sparecell
|
||||
Xserial_clock_out_buffer _131_/CLK vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__clkbuf_16
|
||||
Xfanout29 _082_/A vssd vssd vccd vccd _134_/A sky130_fd_sc_hd__buf_2
|
||||
XTAP_64 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
X_121_ _126_/CLK hold3/X _080_/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_121_ _130_/CLK hold6/X _076_/A vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_4
|
||||
XTAP_65 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_120_ _126_/CLK hold5/X _076_/A vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_120_ _130_/CLK hold1/X _076_/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_102__10 _101__9/A vssd vssd vccd vccd _102__10/Y sky130_fd_sc_hd__inv_2
|
||||
X_058__1 _101__9/A vssd vssd vccd vccd _058__1/Y sky130_fd_sc_hd__inv_2
|
||||
Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA__099__7_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XTAP_66 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_32 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xclkbuf_0_serial_load serial_load vssd vssd vccd vccd clkbuf_0_serial_load/X sky130_fd_sc_hd__clkbuf_16
|
||||
Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _126_/CLK
|
||||
Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _130_/CLK
|
||||
+ sky130_fd_sc_hd__clkbuf_16
|
||||
XTAP_67 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
|
|
@ -277,24 +264,21 @@ Xgpio_logic_high _067_/A vccd1 vssd1 gpio_logic_high
|
|||
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_40 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xone_buffer one_buffer/A vssd vssd vccd vccd one sky130_fd_sc_hd__buf_16
|
||||
XFILLER_8_65 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold3 hold3/A vssd vssd vccd vccd hold3/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_5_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_101__9 _101__9/A vssd vssd vccd vccd _101__9/Y sky130_fd_sc_hd__inv_2
|
||||
XTAP_68 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
X_101__9 _101__9/A vssd vssd vccd vccd _101__9/Y sky130_fd_sc_hd__inv_2
|
||||
XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XANTENNA_fanout28_A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_fanout28_A _082_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_8_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_69 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__134__A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
Xhold5 hold5/A vssd vssd vccd vccd hold5/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_59 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
|
|
@ -307,88 +291,85 @@ X_089_ _088_/A gpio_defaults[5] vssd vssd vccd vccd _089_/Y sky130_fd_sc_hd__nan
|
|||
Xzero_buffer zero_buffer/A vssd vssd vccd vccd zero sky130_fd_sc_hd__buf_16
|
||||
XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
|
||||
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
|
||||
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_input5_A serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_105__13 _100__8/A vssd vssd vccd vccd _105__13/Y sky130_fd_sc_hd__inv_2
|
||||
XANTENNA_input5_A serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_088_ _088_/A gpio_defaults[5] vssd vssd vccd vccd _088_/X sky130_fd_sc_hd__or2_0
|
||||
XFILLER_3_80 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xhold7 hold7/A vssd vssd vccd vccd hold7/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_5_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_096__4 _100__8/A vssd vssd vccd vccd _096__4/Y sky130_fd_sc_hd__inv_2
|
||||
X_096__4 _101__9/A vssd vssd vccd vccd _096__4/Y sky130_fd_sc_hd__inv_2
|
||||
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_2_49 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XFILLER_17_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_087_ _086_/A gpio_defaults[12] vssd vssd vccd vccd _087_/Y sky130_fd_sc_hd__nand2b_2
|
||||
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
Xclkbuf_1_1__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _101__9/A sky130_fd_sc_hd__clkbuf_16
|
||||
XANTENNA__082__A _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_087_ _134_/A gpio_defaults[12] vssd vssd vccd vccd _087_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XANTENNA__071__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__082__A _082_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xclkbuf_1_1__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _131_/CLK
|
||||
+ sky130_fd_sc_hd__clkbuf_16
|
||||
X_086_ _086_/A gpio_defaults[12] vssd vssd vccd vccd _086_/X sky130_fd_sc_hd__or2_0
|
||||
XANTENNA__074__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_069_ _080_/A gpio_defaults[0] vssd vssd vccd vccd _069_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_086_ _086_/A gpio_defaults[12] vssd vssd vccd vccd _086_/X sky130_fd_sc_hd__or2_0
|
||||
Xhold9 hold9/A vssd vssd vccd vccd hold9/X sky130_fd_sc_hd__dlygate4sd3_1
|
||||
XANTENNA__069__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_069_ _086_/A gpio_defaults[0] vssd vssd vccd vccd _069_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XANTENNA__082__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__077__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__132__RESET_B _134_/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__077__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA_input3_A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_085_ _086_/A gpio_defaults[11] vssd vssd vccd vccd _085_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XANTENNA__090__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__085__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_068_ _086_/A gpio_defaults[0] vssd vssd vccd vccd _068_/X sky130_fd_sc_hd__or2_0
|
||||
XFILLER_0_95 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_37 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__093__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA__093__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__088__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XANTENNA__094__2_A _101__9/A vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
XFILLER_3_84 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_084_ _086_/A gpio_defaults[11] vssd vssd vccd vccd _084_/X sky130_fd_sc_hd__or2_0
|
||||
X_099__7 _101__9/A vssd vssd vccd vccd _099__7/Y sky130_fd_sc_hd__inv_2
|
||||
XFILLER_0_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_084_ _086_/A gpio_defaults[11] vssd vssd vccd vccd _084_/X sky130_fd_sc_hd__or2_0
|
||||
X_067_ _067_/A _133_/A vssd vssd vccd vccd _067_/X sky130_fd_sc_hd__and2_2
|
||||
X_119_ _126_/CLK _119_/D _080_/A vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_4
|
||||
X_119_ _131_/CLK _119_/D _080_/A vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_4
|
||||
XPHY_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_15_71 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_083_ _074_/A gpio_defaults[10] vssd vssd vccd vccd _083_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XFILLER_3_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_066_ _064_/X _065_/Y _062_/Y vssd vssd vccd vccd _066_/Y sky130_fd_sc_hd__o21ai_4
|
||||
X_118_ _105__13/Y _127_/D _092_/X _093_/Y vssd vssd vccd vccd _118_/Q _118_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XFILLER_0_31 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_39 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_15_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_065_ input2/X _064_/B _106_/Q vssd vssd vccd vccd _065_/Y sky130_fd_sc_hd__o21ai_2
|
||||
X_082_ _134_/A gpio_defaults[10] vssd vssd vccd vccd _082_/X sky130_fd_sc_hd__or2_0
|
||||
X_082_ _082_/A gpio_defaults[10] vssd vssd vccd vccd _082_/X sky130_fd_sc_hd__or2_0
|
||||
X_134_ _134_/A vssd vssd vccd vccd _134_/X sky130_fd_sc_hd__buf_2
|
||||
Xserial_load_out_buffer _101__9/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__clkbuf_16
|
||||
XANTENNA_input1_A mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_117_ _104__12/Y _126_/D _090_/X _091_/Y vssd vssd vccd vccd _117_/Q _117_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
X_081_ _076_/A gpio_defaults[1] vssd vssd vccd vccd _081_/Y sky130_fd_sc_hd__nand2b_2
|
||||
XFILLER_3_43 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_081_ _080_/A gpio_defaults[1] vssd vssd vccd vccd _081_/Y sky130_fd_sc_hd__nand2b_2
|
||||
X_064_ _113_/Q_N _064_/B vssd vssd vccd vccd _064_/X sky130_fd_sc_hd__and2b_2
|
||||
XFILLER_0_33 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_133_ _133_/A vssd vssd vccd vccd _133_/X sky130_fd_sc_hd__buf_2
|
||||
X_116_ _103__11/Y _125_/D _088_/X _089_/Y vssd vssd vccd vccd _116_/Q _116_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XANTENNA_clkbuf_0_serial_clock_A serial_clock vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
|
||||
X_132_ _132_/CLK hold2/A _134_/A vssd vssd vccd vccd _132_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
X_063_ _115_/Q _114_/Q _063_/C vssd vssd vccd vccd _064_/B sky130_fd_sc_hd__and3b_2
|
||||
XFILLER_3_99 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
X_132_ _132_/CLK hold3/A _134_/A vssd vssd vccd vccd _132_/Q sky130_fd_sc_hd__dfrtp_2
|
||||
X_080_ _080_/A gpio_defaults[1] vssd vssd vccd vccd _080_/X sky130_fd_sc_hd__or2_0
|
||||
X_115_ _102__10/Y hold2/X _086_/X _087_/Y vssd vssd vccd vccd _115_/Q _115_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
X_063_ _115_/Q _114_/Q _063_/C vssd vssd vccd vccd _064_/B sky130_fd_sc_hd__and3b_2
|
||||
X_115_ _102__10/Y hold3/X _086_/X _087_/Y vssd vssd vccd vccd _115_/Q _115_/Q_N sky130_fd_sc_hd__dfbbn_2
|
||||
Xoutput6 _133_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__buf_16
|
||||
.ends
|
||||
|
||||
|
|
|
|||
|
|
@ -111,8 +111,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
wire _057_;
|
||||
wire clknet_0_serial_clock;
|
||||
wire clknet_0_serial_load;
|
||||
wire clknet_1_0__leaf_serial_clock;
|
||||
wire clknet_1_0__leaf_serial_load;
|
||||
wire clknet_1_1__leaf_serial_clock;
|
||||
wire gpio_logic1;
|
||||
wire gpio_outenb;
|
||||
wire mgmt_ena;
|
||||
|
|
@ -169,6 +169,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
wire net55;
|
||||
wire net56;
|
||||
wire net57;
|
||||
wire net58;
|
||||
wire net6;
|
||||
wire net7;
|
||||
wire net8;
|
||||
|
|
@ -191,11 +192,6 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
wire \shift_register[9] ;
|
||||
wire zero_buffered;
|
||||
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__058__1_A (.DIODE(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__061__A0 (.DIODE(user_gpio_oeb),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
@ -276,7 +272,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__082__A (.DIODE(net29),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__082__A (.DIODE(net30),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
|
|
@ -341,46 +337,6 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__094__2_A (.DIODE(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__097__5_A (.DIODE(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__098__6_A (.DIODE(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__099__7_A (.DIODE(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__101__9_A (.DIODE(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__102__10_A (.DIODE(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__132__RESET_B (.DIODE(net29),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA__134__A (.DIODE(net29),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_clkbuf_0_serial_clock_A (.DIODE(serial_clock),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
@ -391,12 +347,17 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_fanout27_A (.DIODE(net29),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_fanout27_A (.DIODE(net30),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_fanout28_A (.DIODE(net29),
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_fanout28_A (.DIODE(net30),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_fanout29_A (.DIODE(net30),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
|
|
@ -426,16 +387,11 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__diode_2 ANTENNA_serial_load_out_buffer_A (.DIODE(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_27 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_33 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_31 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
|
|
@ -443,11 +399,27 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_10_83 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_85 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_15_50 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_0_95 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_12_29 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_13_99 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_15_57 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_15_71 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
|
|
@ -459,43 +431,23 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_4 FILLER_1_30 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_1_34 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_2_32 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_80 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__decap_8 FILLER_2_41 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_89 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_2 FILLER_2_49 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_99 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_43 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_52 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_3_84 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_5_26 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_5_34 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_4_60 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
|
|
@ -503,19 +455,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_7_26 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_8_65 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_8_99 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__fill_1 FILLER_9_99 (.VGND(vssd),
|
||||
sky130_fd_sc_hd__fill_1 FILLER_5_99 (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
|
|
@ -756,13 +696,13 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net31));
|
||||
sky130_fd_sc_hd__inv_2 _059__14 (.A(serial_clock_out_buffered),
|
||||
.Y(net32));
|
||||
sky130_fd_sc_hd__inv_2 _059__14 (.A(clknet_1_0__leaf_serial_clock),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net44));
|
||||
.Y(net45));
|
||||
sky130_fd_sc_hd__and2_0 _060_ (.A(gpio_outenb),
|
||||
.B(net1),
|
||||
.VGND(vssd),
|
||||
|
|
@ -830,7 +770,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(_001_));
|
||||
sky130_fd_sc_hd__nand2b_2 _069_ (.A_N(net26),
|
||||
sky130_fd_sc_hd__nand2b_2 _069_ (.A_N(net28),
|
||||
.B(gpio_defaults[0]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
@ -914,14 +854,14 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(_013_));
|
||||
sky130_fd_sc_hd__nand2b_2 _081_ (.A_N(net25),
|
||||
sky130_fd_sc_hd__nand2b_2 _081_ (.A_N(net26),
|
||||
.B(gpio_defaults[1]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(_014_));
|
||||
sky130_fd_sc_hd__or2_0 _082_ (.A(net29),
|
||||
sky130_fd_sc_hd__or2_0 _082_ (.A(net30),
|
||||
.B(gpio_defaults[10]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
@ -956,7 +896,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(_019_));
|
||||
sky130_fd_sc_hd__nand2b_2 _087_ (.A_N(net28),
|
||||
sky130_fd_sc_hd__nand2b_2 _087_ (.A_N(net29),
|
||||
.B(gpio_defaults[12]),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
@ -1010,75 +950,75 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net32));
|
||||
.Y(net33));
|
||||
sky130_fd_sc_hd__inv_2 _095__3 (.A(clknet_1_0__leaf_serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net33));
|
||||
sky130_fd_sc_hd__inv_2 _096__4 (.A(clknet_1_0__leaf_serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net34));
|
||||
sky130_fd_sc_hd__inv_2 _097__5 (.A(serial_load_out_buffered),
|
||||
sky130_fd_sc_hd__inv_2 _096__4 (.A(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net35));
|
||||
sky130_fd_sc_hd__inv_2 _098__6 (.A(serial_load_out_buffered),
|
||||
sky130_fd_sc_hd__inv_2 _097__5 (.A(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net36));
|
||||
sky130_fd_sc_hd__inv_2 _099__7 (.A(serial_load_out_buffered),
|
||||
sky130_fd_sc_hd__inv_2 _098__6 (.A(clknet_1_0__leaf_serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net37));
|
||||
sky130_fd_sc_hd__inv_2 _100__8 (.A(clknet_1_0__leaf_serial_load),
|
||||
sky130_fd_sc_hd__inv_2 _099__7 (.A(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net38));
|
||||
sky130_fd_sc_hd__inv_2 _101__9 (.A(serial_load_out_buffered),
|
||||
sky130_fd_sc_hd__inv_2 _100__8 (.A(clknet_1_0__leaf_serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net39));
|
||||
sky130_fd_sc_hd__inv_2 _102__10 (.A(serial_load_out_buffered),
|
||||
sky130_fd_sc_hd__inv_2 _101__9 (.A(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net40));
|
||||
sky130_fd_sc_hd__inv_2 _103__11 (.A(clknet_1_0__leaf_serial_load),
|
||||
sky130_fd_sc_hd__inv_2 _102__10 (.A(serial_load_out_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net41));
|
||||
sky130_fd_sc_hd__inv_2 _104__12 (.A(clknet_1_0__leaf_serial_load),
|
||||
sky130_fd_sc_hd__inv_2 _103__11 (.A(clknet_1_0__leaf_serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net42));
|
||||
sky130_fd_sc_hd__inv_2 _105__13 (.A(clknet_1_0__leaf_serial_load),
|
||||
sky130_fd_sc_hd__inv_2 _104__12 (.A(clknet_1_0__leaf_serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net43));
|
||||
sky130_fd_sc_hd__dfbbn_2 _106_ (.CLK_N(net31),
|
||||
.D(net49),
|
||||
sky130_fd_sc_hd__inv_2 _105__13 (.A(clknet_1_0__leaf_serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Y(net44));
|
||||
sky130_fd_sc_hd__dfbbn_2 _106_ (.CLK_N(net32),
|
||||
.D(net46),
|
||||
.RESET_B(_001_),
|
||||
.SET_B(_002_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1087,8 +1027,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(mgmt_ena),
|
||||
.Q_N(_056_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _107_ (.CLK_N(net32),
|
||||
.D(net52),
|
||||
sky130_fd_sc_hd__dfbbn_2 _107_ (.CLK_N(net33),
|
||||
.D(net50),
|
||||
.RESET_B(_003_),
|
||||
.SET_B(_004_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1097,8 +1037,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net13),
|
||||
.Q_N(_055_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _108_ (.CLK_N(net33),
|
||||
.D(net51),
|
||||
sky130_fd_sc_hd__dfbbn_2 _108_ (.CLK_N(net34),
|
||||
.D(net55),
|
||||
.RESET_B(_005_),
|
||||
.SET_B(_006_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1107,8 +1047,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net18),
|
||||
.Q_N(_054_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _109_ (.CLK_N(net34),
|
||||
.D(net48),
|
||||
sky130_fd_sc_hd__dfbbn_2 _109_ (.CLK_N(net35),
|
||||
.D(net47),
|
||||
.RESET_B(_007_),
|
||||
.SET_B(_008_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1117,8 +1057,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net19),
|
||||
.Q_N(_053_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _110_ (.CLK_N(net35),
|
||||
.D(net50),
|
||||
sky130_fd_sc_hd__dfbbn_2 _110_ (.CLK_N(net36),
|
||||
.D(net52),
|
||||
.RESET_B(_009_),
|
||||
.SET_B(_010_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1127,8 +1067,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net15),
|
||||
.Q_N(_052_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _111_ (.CLK_N(net36),
|
||||
.D(net54),
|
||||
sky130_fd_sc_hd__dfbbn_2 _111_ (.CLK_N(net37),
|
||||
.D(net53),
|
||||
.RESET_B(_011_),
|
||||
.SET_B(_012_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1137,8 +1077,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net14),
|
||||
.Q_N(_051_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _112_ (.CLK_N(net37),
|
||||
.D(net47),
|
||||
sky130_fd_sc_hd__dfbbn_2 _112_ (.CLK_N(net38),
|
||||
.D(net51),
|
||||
.RESET_B(_013_),
|
||||
.SET_B(_014_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1147,8 +1087,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(gpio_outenb),
|
||||
.Q_N(_050_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _113_ (.CLK_N(net38),
|
||||
.D(net53),
|
||||
sky130_fd_sc_hd__dfbbn_2 _113_ (.CLK_N(net39),
|
||||
.D(net54),
|
||||
.RESET_B(_015_),
|
||||
.SET_B(_016_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1157,8 +1097,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net10),
|
||||
.Q_N(_000_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _114_ (.CLK_N(net39),
|
||||
.D(net45),
|
||||
sky130_fd_sc_hd__dfbbn_2 _114_ (.CLK_N(net40),
|
||||
.D(net49),
|
||||
.RESET_B(_017_),
|
||||
.SET_B(_018_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1167,8 +1107,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net11),
|
||||
.Q_N(_049_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _115_ (.CLK_N(net40),
|
||||
.D(net46),
|
||||
sky130_fd_sc_hd__dfbbn_2 _115_ (.CLK_N(net41),
|
||||
.D(net48),
|
||||
.RESET_B(_019_),
|
||||
.SET_B(_020_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1177,8 +1117,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net12),
|
||||
.Q_N(_048_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _116_ (.CLK_N(net41),
|
||||
.D(net57),
|
||||
sky130_fd_sc_hd__dfbbn_2 _116_ (.CLK_N(net42),
|
||||
.D(net58),
|
||||
.RESET_B(_021_),
|
||||
.SET_B(_022_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1187,8 +1127,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net7),
|
||||
.Q_N(_047_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _117_ (.CLK_N(net42),
|
||||
.D(net56),
|
||||
sky130_fd_sc_hd__dfbbn_2 _117_ (.CLK_N(net43),
|
||||
.D(net57),
|
||||
.RESET_B(_023_),
|
||||
.SET_B(_024_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1197,8 +1137,8 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(net9),
|
||||
.Q_N(_046_));
|
||||
sky130_fd_sc_hd__dfbbn_2 _118_ (.CLK_N(net43),
|
||||
.D(net55),
|
||||
sky130_fd_sc_hd__dfbbn_2 _118_ (.CLK_N(net44),
|
||||
.D(net56),
|
||||
.RESET_B(_025_),
|
||||
.SET_B(_026_),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1215,24 +1155,24 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[0] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _120_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net49),
|
||||
sky130_fd_sc_hd__dfrtp_4 _120_ (.CLK(clknet_1_0__leaf_serial_clock),
|
||||
.D(net46),
|
||||
.RESET_B(net25),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[1] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _121_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net47),
|
||||
.RESET_B(net26),
|
||||
sky130_fd_sc_hd__dfrtp_4 _121_ (.CLK(clknet_1_0__leaf_serial_clock),
|
||||
.D(net51),
|
||||
.RESET_B(net25),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[2] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _122_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net52),
|
||||
sky130_fd_sc_hd__dfrtp_4 _122_ (.CLK(clknet_1_0__leaf_serial_clock),
|
||||
.D(net50),
|
||||
.RESET_B(net25),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
@ -1240,78 +1180,78 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPWR(vccd),
|
||||
.Q(\shift_register[3] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _123_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net50),
|
||||
.D(net52),
|
||||
.RESET_B(net24),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[4] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _124_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net54),
|
||||
sky130_fd_sc_hd__dfrtp_4 _124_ (.CLK(clknet_1_0__leaf_serial_clock),
|
||||
.D(net53),
|
||||
.RESET_B(net24),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[5] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _125_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net57),
|
||||
sky130_fd_sc_hd__dfrtp_4 _125_ (.CLK(clknet_1_0__leaf_serial_clock),
|
||||
.D(net58),
|
||||
.RESET_B(net23),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[6] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _126_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net56),
|
||||
sky130_fd_sc_hd__dfrtp_4 _126_ (.CLK(clknet_1_0__leaf_serial_clock),
|
||||
.D(net57),
|
||||
.RESET_B(net23),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[7] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _127_ (.CLK(clknet_1_1__leaf_serial_clock),
|
||||
.D(net55),
|
||||
sky130_fd_sc_hd__dfrtp_4 _127_ (.CLK(clknet_1_0__leaf_serial_clock),
|
||||
.D(net56),
|
||||
.RESET_B(net24),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[8] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _128_ (.CLK(clknet_1_1__leaf_serial_clock),
|
||||
.D(net51),
|
||||
sky130_fd_sc_hd__dfrtp_4 _128_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net55),
|
||||
.RESET_B(net27),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[9] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _129_ (.CLK(clknet_1_1__leaf_serial_clock),
|
||||
.D(net48),
|
||||
sky130_fd_sc_hd__dfrtp_4 _129_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net47),
|
||||
.RESET_B(net27),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[10] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _130_ (.CLK(clknet_1_1__leaf_serial_clock),
|
||||
.D(net53),
|
||||
sky130_fd_sc_hd__dfrtp_4 _130_ (.CLK(clknet_1_0__leaf_serial_clock),
|
||||
.D(net54),
|
||||
.RESET_B(net28),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[11] ));
|
||||
sky130_fd_sc_hd__dfrtp_4 _131_ (.CLK(clknet_1_1__leaf_serial_clock),
|
||||
.D(net45),
|
||||
sky130_fd_sc_hd__dfrtp_4 _131_ (.CLK(serial_clock_out_buffered),
|
||||
.D(net49),
|
||||
.RESET_B(net28),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.Q(\shift_register[12] ));
|
||||
sky130_fd_sc_hd__dfrtp_2 _132_ (.CLK(net44),
|
||||
sky130_fd_sc_hd__dfrtp_2 _132_ (.CLK(net45),
|
||||
.D(\shift_register[12] ),
|
||||
.RESET_B(net29),
|
||||
.VGND(vssd),
|
||||
|
|
@ -1348,7 +1288,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(serial_clock_out_buffered));
|
||||
.X(clknet_1_0__leaf_serial_clock));
|
||||
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_0__f_serial_load (.A(clknet_0_serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
@ -1360,7 +1300,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(clknet_1_1__leaf_serial_clock));
|
||||
.X(serial_clock_out_buffered));
|
||||
sky130_fd_sc_hd__clkbuf_16 clkbuf_1_1__f_serial_load (.A(clknet_0_serial_load),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
@ -1379,7 +1319,7 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net23));
|
||||
sky130_fd_sc_hd__buf_2 fanout24 (.A(net30),
|
||||
sky130_fd_sc_hd__buf_2 fanout24 (.A(net31),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
|
|
@ -1391,19 +1331,19 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net25));
|
||||
sky130_fd_sc_hd__buf_2 fanout26 (.A(net30),
|
||||
sky130_fd_sc_hd__buf_2 fanout26 (.A(net31),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net26));
|
||||
sky130_fd_sc_hd__buf_2 fanout27 (.A(net29),
|
||||
sky130_fd_sc_hd__buf_2 fanout27 (.A(net30),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net27));
|
||||
sky130_fd_sc_hd__buf_2 fanout28 (.A(net29),
|
||||
sky130_fd_sc_hd__buf_2 fanout28 (.A(net30),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
|
|
@ -1415,93 +1355,99 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net29));
|
||||
sky130_fd_sc_hd__buf_2 fanout30 (.A(net4),
|
||||
sky130_fd_sc_hd__buf_2 fanout30 (.A(net31),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net30));
|
||||
sky130_fd_sc_hd__buf_2 fanout31 (.A(net4),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net31));
|
||||
gpio_logic_high gpio_logic_high (.gpio_logic1(gpio_logic1),
|
||||
.vccd1(vccd1),
|
||||
.vssd1(vssd1));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold1 (.A(\shift_register[11] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net45));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold10 (.A(\shift_register[4] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net54));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold11 (.A(\shift_register[7] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net55));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold12 (.A(\shift_register[6] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net56));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold13 (.A(\shift_register[5] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net57));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold2 (.A(\shift_register[12] ),
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold1 (.A(\shift_register[0] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net46));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold3 (.A(\shift_register[1] ),
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold10 (.A(\shift_register[8] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net55));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold11 (.A(\shift_register[7] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net56));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold12 (.A(\shift_register[6] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net57));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold13 (.A(\shift_register[5] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net58));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold2 (.A(\shift_register[9] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net47));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold4 (.A(\shift_register[9] ),
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold3 (.A(\shift_register[12] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net48));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold5 (.A(\shift_register[0] ),
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold4 (.A(\shift_register[11] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net49));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold6 (.A(\shift_register[3] ),
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold5 (.A(\shift_register[2] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net50));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold7 (.A(\shift_register[8] ),
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold6 (.A(\shift_register[1] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net51));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold8 (.A(\shift_register[2] ),
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold7 (.A(\shift_register[3] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net52));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold9 (.A(\shift_register[10] ),
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold8 (.A(\shift_register[4] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net53));
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 hold9 (.A(\shift_register[10] ),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(net54));
|
||||
sky130_fd_sc_hd__buf_2 input1 (.A(mgmt_gpio_oeb),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
@ -1652,6 +1598,10 @@ module gpio_control_block (mgmt_gpio_in,
|
|||
.VPB(vccd),
|
||||
.VPWR(vccd),
|
||||
.X(serial_load_out));
|
||||
sky130_fd_sc_hd__macro_sparecell spare_cell (.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
.VPB(vccd),
|
||||
.VPWR(vccd));
|
||||
sky130_fd_sc_hd__buf_16 zero_buffer (.A(zero_buffered),
|
||||
.VGND(vssd),
|
||||
.VNB(vssd),
|
||||
|
|
|
|||
|
|
@ -260,6 +260,16 @@ module gpio_control_block #(
|
|||
/* going to the user project. */
|
||||
assign user_gpio_in = pad_gpio_in & gpio_logic1;
|
||||
|
||||
(* keep *)
|
||||
sky130_fd_sc_hd__macro_sparecell spare_cell (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
.VPB(vccd),
|
||||
.VNB(vssd)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_fd_sc_hd__conb_1 const_source (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
|
|
|
|||
Loading…
Reference in New Issue