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harden: gpio_control_block with updated rtl 

TODO: run full verification
This commit is contained in:
kareem 2022-08-15 02:28:54 -07:00
parent 54901e267c
commit ac1928a45b
15 changed files with 19088 additions and 19717 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5041
def/gpio_control_block.def
View File

File diff suppressed because it is too large Load Diff

417
lef/gpio_control_block.lef
View File

@ -344,91 +344,71 @@ MACRO gpio_control_block
END
END user_gpio_out
PIN vccd
DIRECTION INPUT ;
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER met5 ;
RECT 4.600 5.900 49.220 7.500 ;
END
PORT
LAYER met5 ;
RECT 4.600 22.800 49.220 24.400 ;
END
PORT
LAYER met5 ;
RECT 4.600 39.700 49.220 41.300 ;
END
PORT
LAYER met4 ;
RECT 12.800 5.440 14.400 57.360 ;
RECT 12.800 26.400 14.400 57.360 ;
END
PORT
LAYER met4 ;
RECT 37.800 5.200 39.400 57.360 ;
END
PORT
LAYER met5 ;
RECT 4.360 6.140 49.460 7.740 ;
END
PORT
LAYER met5 ;
RECT 4.360 39.940 49.460 41.540 ;
END
END vccd
PIN vccd1
DIRECTION INPUT ;
DIRECTION INOUT ;
USE POWER ;
PORT
LAYER met5 ;
RECT 4.600 11.140 49.220 12.740 ;
END
PORT
LAYER met5 ;
RECT 4.600 28.040 49.220 29.640 ;
END
PORT
LAYER met5 ;
RECT 4.600 44.940 49.220 46.540 ;
END
PORT
LAYER met4 ;
RECT 17.800 5.440 19.400 57.120 ;
END
PORT
LAYER met4 ;
RECT 42.800 5.440 44.400 57.120 ;
END
END vccd1
PIN vssd
DIRECTION INPUT ;
USE GROUND ;
PORT
LAYER met5 ;
RECT 4.600 14.350 49.220 15.950 ;
END
PORT
LAYER met5 ;
RECT 4.600 31.250 49.220 32.850 ;
END
PORT
LAYER met5 ;
RECT 4.600 48.150 49.220 49.750 ;
END
PORT
LAYER met4 ;
RECT 25.300 5.200 26.900 57.360 ;
END
END vssd
PIN vssd1
DIRECTION INPUT ;
PORT
LAYER met5 ;
RECT 4.360 14.590 49.460 16.190 ;
END
END vccd1
PIN vssd
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER met5 ;
RECT 4.600 19.590 49.220 21.190 ;
END
PORT
LAYER met5 ;
RECT 4.600 36.490 49.220 38.090 ;
END
PORT
LAYER met5 ;
RECT 4.600 53.390 49.220 54.990 ;
LAYER met4 ;
RECT 19.050 5.200 20.650 57.360 ;
END
PORT
LAYER met4 ;
RECT 30.300 5.440 31.900 57.120 ;
RECT 44.050 5.200 45.650 57.360 ;
END
PORT
LAYER met5 ;
RECT 4.360 10.365 49.460 11.965 ;
END
PORT
LAYER met5 ;
RECT 4.360 27.265 49.460 28.865 ;
END
PORT
LAYER met5 ;
RECT 4.360 44.165 49.460 45.765 ;
END
END vssd
PIN vssd1
DIRECTION INOUT ;
USE GROUND ;
PORT
LAYER met4 ;
RECT 31.550 5.200 33.150 57.360 ;
END
PORT
LAYER met5 ;
RECT 4.360 18.815 49.460 20.415 ;
END
END vssd1
PIN zero
@ -440,32 +420,280 @@ MACRO gpio_control_block
END
END zero
OBS
LAYER nwell ;
RECT 4.410 55.705 49.410 57.310 ;
RECT 4.410 50.265 49.410 53.095 ;
RECT 4.410 44.825 49.410 47.655 ;
RECT 4.410 39.385 49.410 42.215 ;
RECT 4.410 33.945 49.410 36.775 ;
RECT 4.410 28.505 49.410 31.335 ;
LAYER li1 ;
RECT 4.600 5.355 49.220 57.205 ;
RECT 0.000 64.930 4.265 65.070 ;
LAYER li1 ;
RECT 4.265 64.930 169.810 65.000 ;
LAYER li1 ;
RECT 0.000 64.845 49.815 64.930 ;
LAYER li1 ;
RECT 49.815 64.845 169.810 64.930 ;
LAYER li1 ;
RECT 0.000 57.405 169.810 64.845 ;
RECT 0.000 30.025 4.265 57.405 ;
LAYER li1 ;
RECT 4.265 30.025 169.810 57.405 ;
LAYER li1 ;
RECT 0.000 30.005 16.795 30.025 ;
LAYER li1 ;
RECT 16.795 30.005 169.810 30.025 ;
LAYER li1 ;
RECT 0.000 29.835 4.745 30.005 ;
LAYER li1 ;
RECT 4.745 29.835 169.810 30.005 ;
LAYER li1 ;
RECT 0.000 29.665 16.795 29.835 ;
LAYER li1 ;
RECT 16.795 29.665 169.810 29.835 ;
LAYER li1 ;
RECT 0.000 27.455 6.985 29.665 ;
LAYER li1 ;
RECT 6.985 27.455 169.810 29.665 ;
LAYER li1 ;
RECT 0.000 27.285 16.795 27.455 ;
LAYER li1 ;
RECT 16.795 27.285 169.810 27.455 ;
LAYER li1 ;
RECT 0.000 27.115 4.745 27.285 ;
LAYER li1 ;
RECT 4.745 27.115 169.810 27.285 ;
LAYER li1 ;
RECT 0.000 26.855 16.795 27.115 ;
LAYER li1 ;
RECT 16.795 26.855 169.810 27.115 ;
LAYER li1 ;
RECT 0.000 26.565 16.905 26.855 ;
LAYER li1 ;
RECT 16.905 26.565 169.810 26.855 ;
LAYER li1 ;
RECT 0.000 26.395 17.400 26.565 ;
LAYER li1 ;
RECT 17.400 26.395 169.810 26.565 ;
LAYER li1 ;
RECT 0.000 26.225 16.795 26.395 ;
LAYER li1 ;
RECT 16.795 26.225 169.810 26.395 ;
LAYER li1 ;
RECT 0.000 25.575 16.650 26.225 ;
LAYER li1 ;
RECT 16.650 25.575 169.810 26.225 ;
LAYER li1 ;
RECT 0.000 25.405 16.795 25.575 ;
LAYER li1 ;
RECT 16.795 25.405 169.810 25.575 ;
LAYER li1 ;
RECT 0.000 25.235 17.400 25.405 ;
LAYER li1 ;
RECT 17.400 25.235 169.810 25.405 ;
LAYER li1 ;
RECT 0.000 24.735 16.905 25.235 ;
LAYER li1 ;
RECT 16.905 24.735 169.810 25.235 ;
LAYER li1 ;
RECT 0.000 24.565 16.795 24.735 ;
LAYER li1 ;
RECT 16.795 24.565 169.810 24.735 ;
LAYER li1 ;
RECT 0.000 24.395 15.325 24.565 ;
LAYER li1 ;
RECT 15.325 24.395 169.810 24.565 ;
LAYER li1 ;
RECT 0.000 24.225 16.795 24.395 ;
LAYER li1 ;
RECT 16.795 24.225 169.810 24.395 ;
LAYER li1 ;
RECT 0.000 23.725 16.905 24.225 ;
LAYER li1 ;
RECT 16.905 23.725 169.810 24.225 ;
LAYER li1 ;
RECT 0.000 23.555 17.400 23.725 ;
LAYER li1 ;
RECT 17.400 23.555 169.810 23.725 ;
LAYER li1 ;
RECT 0.000 23.385 16.795 23.555 ;
LAYER li1 ;
RECT 16.795 23.385 169.810 23.555 ;
LAYER li1 ;
RECT 0.000 22.735 16.650 23.385 ;
LAYER li1 ;
RECT 16.650 22.735 169.810 23.385 ;
LAYER li1 ;
RECT 0.000 22.565 16.795 22.735 ;
LAYER li1 ;
RECT 16.795 22.565 169.810 22.735 ;
LAYER li1 ;
RECT 0.000 22.395 17.400 22.565 ;
LAYER li1 ;
RECT 17.400 22.395 169.810 22.565 ;
LAYER li1 ;
RECT 0.000 22.105 16.905 22.395 ;
LAYER li1 ;
RECT 16.905 22.105 169.810 22.395 ;
LAYER li1 ;
RECT 0.000 21.845 16.795 22.105 ;
LAYER li1 ;
RECT 16.795 21.845 169.810 22.105 ;
LAYER li1 ;
RECT 0.000 21.675 15.325 21.845 ;
LAYER li1 ;
RECT 15.325 21.675 169.810 21.845 ;
LAYER li1 ;
RECT 0.000 21.505 16.795 21.675 ;
LAYER li1 ;
RECT 16.795 21.505 169.810 21.675 ;
LAYER li1 ;
RECT 0.000 19.295 16.645 21.505 ;
LAYER li1 ;
RECT 16.645 19.295 169.810 21.505 ;
LAYER li1 ;
RECT 0.000 19.125 16.795 19.295 ;
LAYER li1 ;
RECT 16.795 19.125 169.810 19.295 ;
LAYER li1 ;
RECT 0.000 18.955 15.325 19.125 ;
LAYER li1 ;
RECT 15.325 18.955 169.810 19.125 ;
LAYER li1 ;
RECT 0.000 18.210 17.005 18.955 ;
LAYER li1 ;
RECT 17.005 18.210 169.810 18.955 ;
LAYER li1 ;
RECT 0.000 18.040 16.795 18.210 ;
LAYER li1 ;
RECT 16.795 18.040 169.810 18.210 ;
LAYER li1 ;
RECT 0.000 17.055 16.735 18.040 ;
LAYER li1 ;
RECT 16.735 17.055 169.810 18.040 ;
LAYER li1 ;
RECT 0.000 16.885 16.795 17.055 ;
LAYER li1 ;
RECT 16.795 16.885 169.810 17.055 ;
LAYER li1 ;
RECT 0.000 16.405 17.035 16.885 ;
LAYER li1 ;
RECT 17.035 16.405 169.810 16.885 ;
LAYER li1 ;
RECT 0.000 16.235 15.325 16.405 ;
LAYER li1 ;
RECT 15.325 16.235 169.810 16.405 ;
LAYER li1 ;
RECT 0.000 16.065 16.795 16.235 ;
LAYER li1 ;
RECT 16.795 16.065 169.810 16.235 ;
LAYER li1 ;
RECT 0.000 13.855 16.645 16.065 ;
LAYER li1 ;
RECT 16.645 13.855 169.810 16.065 ;
LAYER li1 ;
RECT 0.000 13.685 16.795 13.855 ;
LAYER li1 ;
RECT 16.795 13.685 169.810 13.855 ;
LAYER li1 ;
RECT 0.000 13.515 15.325 13.685 ;
LAYER li1 ;
RECT 15.325 13.515 169.810 13.685 ;
LAYER li1 ;
RECT 0.000 13.345 16.795 13.515 ;
LAYER li1 ;
RECT 16.795 13.345 169.810 13.515 ;
LAYER li1 ;
RECT 0.000 11.135 16.645 13.345 ;
LAYER li1 ;
RECT 16.645 11.135 169.810 13.345 ;
LAYER li1 ;
RECT 0.000 10.965 16.795 11.135 ;
LAYER li1 ;
RECT 16.795 10.965 169.810 11.135 ;
LAYER li1 ;
RECT 0.000 10.795 15.325 10.965 ;
LAYER li1 ;
RECT 15.325 10.795 169.810 10.965 ;
LAYER li1 ;
RECT 0.000 10.535 16.795 10.795 ;
LAYER li1 ;
RECT 16.795 10.535 169.810 10.795 ;
LAYER li1 ;
RECT 0.000 10.245 16.905 10.535 ;
LAYER li1 ;
RECT 16.905 10.245 169.810 10.535 ;
LAYER li1 ;
RECT 0.000 10.075 17.400 10.245 ;
LAYER li1 ;
RECT 17.400 10.075 169.810 10.245 ;
LAYER li1 ;
RECT 0.000 9.905 16.795 10.075 ;
LAYER li1 ;
RECT 16.795 9.905 169.810 10.075 ;
LAYER li1 ;
RECT 0.000 9.255 16.645 9.905 ;
LAYER li1 ;
RECT 16.645 9.255 169.810 9.905 ;
LAYER li1 ;
RECT 0.000 9.085 16.795 9.255 ;
LAYER li1 ;
RECT 16.795 9.085 169.810 9.255 ;
LAYER li1 ;
RECT 0.000 8.915 17.400 9.085 ;
LAYER li1 ;
RECT 17.400 8.915 169.810 9.085 ;
LAYER li1 ;
RECT 0.000 8.415 16.905 8.915 ;
LAYER li1 ;
RECT 16.905 8.415 169.810 8.915 ;
LAYER li1 ;
RECT 0.000 8.245 16.795 8.415 ;
LAYER li1 ;
RECT 16.795 8.245 169.810 8.415 ;
LAYER li1 ;
RECT 0.000 8.075 15.325 8.245 ;
LAYER li1 ;
RECT 15.325 8.075 169.810 8.245 ;
LAYER li1 ;
RECT 0.000 7.330 17.005 8.075 ;
LAYER li1 ;
RECT 17.005 7.330 169.810 8.075 ;
LAYER li1 ;
RECT 0.000 7.160 16.795 7.330 ;
LAYER li1 ;
RECT 16.795 7.160 169.810 7.330 ;
LAYER li1 ;
RECT 0.000 6.175 16.735 7.160 ;
LAYER li1 ;
RECT 16.735 6.175 169.810 7.160 ;
LAYER li1 ;
RECT 0.000 6.005 16.795 6.175 ;
LAYER li1 ;
RECT 16.795 6.005 169.810 6.175 ;
LAYER li1 ;
RECT 0.000 5.525 17.035 6.005 ;
LAYER li1 ;
RECT 17.035 5.525 169.810 6.005 ;
LAYER li1 ;
RECT 0.000 5.355 15.325 5.525 ;
LAYER li1 ;
RECT 15.325 5.355 169.810 5.525 ;
LAYER li1 ;
RECT 0.000 0.000 16.795 5.355 ;
LAYER li1 ;
RECT 16.795 0.000 169.810 5.355 ;
LAYER met1 ;
RECT 4.600 4.800 83.190 57.360 ;
RECT 4.600 0.000 170.000 65.000 ;
LAYER met2 ;
RECT 5.250 60.720 6.710 61.725 ;
RECT 7.550 60.720 9.010 61.725 ;
RECT 9.850 60.720 11.310 61.725 ;
RECT 12.150 60.720 13.610 61.725 ;
RECT 14.450 60.720 15.910 61.725 ;
RECT 16.750 60.720 18.210 61.725 ;
RECT 19.050 60.720 20.510 61.725 ;
RECT 21.350 60.720 22.810 61.725 ;
RECT 23.650 60.720 25.110 61.725 ;
RECT 25.950 60.720 27.410 61.725 ;
RECT 28.250 60.720 29.710 61.725 ;
RECT 30.550 60.720 32.010 61.725 ;
RECT 32.850 60.720 83.170 61.725 ;
RECT 4.970 2.195 83.170 60.720 ;
RECT 5.250 60.720 6.710 65.000 ;
RECT 7.550 60.720 9.010 65.000 ;
RECT 9.850 60.720 11.310 65.000 ;
RECT 12.150 60.720 13.610 65.000 ;
RECT 14.450 60.720 15.910 65.000 ;
RECT 16.750 60.720 18.210 65.000 ;
RECT 19.050 60.720 20.510 65.000 ;
RECT 21.350 60.720 22.810 65.000 ;
RECT 23.650 60.720 25.110 65.000 ;
RECT 25.950 60.720 27.410 65.000 ;
RECT 28.250 60.720 29.710 65.000 ;
RECT 30.550 60.720 32.010 65.000 ;
RECT 32.850 60.720 170.000 65.000 ;
RECT 4.700 0.000 170.000 60.720 ;
LAYER met3 ;
RECT 6.280 60.840 69.600 61.705 ;
RECT 6.280 60.200 70.000 60.840 ;
@ -527,7 +755,18 @@ MACRO gpio_control_block
RECT 6.280 3.080 70.000 3.720 ;
RECT 6.280 2.215 69.600 3.080 ;
LAYER met4 ;
RECT 6.280 8.160 11.380 22.240 ;
RECT 6.280 57.760 170.000 65.000 ;
RECT 6.280 26.000 12.400 57.760 ;
RECT 14.800 26.000 18.650 57.760 ;
RECT 6.280 4.800 18.650 26.000 ;
RECT 21.050 4.800 24.900 57.760 ;
RECT 27.300 4.800 31.150 57.760 ;
RECT 33.550 4.800 37.400 57.760 ;
RECT 39.800 4.800 43.650 57.760 ;
RECT 46.050 4.800 170.000 57.760 ;
RECT 6.280 0.000 170.000 4.800 ;
LAYER met5 ;
RECT 67.000 0.000 170.000 65.000 ;
END
END gpio_control_block
END LIBRARY

16939
mag/gpio_control_block.mag
View File

File diff suppressed because it is too large Load Diff

148
maglef/gpio_control_block.mag
View File

@ -1,18 +1,12 @@
magic
tech sky130A
magscale 1 2
timestamp 1649688057
<< nwell >>
rect 882 11141 9882 11462
rect 882 10053 9882 10619
rect 882 8965 9882 9531
rect 882 7877 9882 8443
rect 882 6789 9882 7355
rect 882 5701 9882 6267
timestamp 1659794614
<< obsli1 >>
rect 920 1071 9844 11441
rect 0 13000 853 13014
rect 0 0 33962 13000
<< obsm1 >>
rect 920 960 16638 11472
rect 920 0 34000 13000
<< metal2 >>
rect 938 12200 994 13000
rect 1398 12200 1454 13000
@ -28,20 +22,20 @@ rect 5538 12200 5594 13000
rect 5998 12200 6054 13000
rect 6458 12200 6514 13000
<< obsm2 >>
rect 1050 12144 1342 12345
rect 1510 12144 1802 12345
rect 1970 12144 2262 12345
rect 2430 12144 2722 12345
rect 2890 12144 3182 12345
rect 3350 12144 3642 12345
rect 3810 12144 4102 12345
rect 4270 12144 4562 12345
rect 4730 12144 5022 12345
rect 5190 12144 5482 12345
rect 5650 12144 5942 12345
rect 6110 12144 6402 12345
rect 6570 12144 16634 12345
rect 994 439 16634 12144
rect 1050 12144 1342 13000
rect 1510 12144 1802 13000
rect 1970 12144 2262 13000
rect 2430 12144 2722 13000
rect 2890 12144 3182 13000
rect 3350 12144 3642 13000
rect 3810 12144 4102 13000
rect 4270 12144 4562 13000
rect 4730 12144 5022 13000
rect 5190 12144 5482 13000
rect 5650 12144 5942 13000
rect 6110 12144 6402 13000
rect 6570 12144 34000 13000
rect 940 0 34000 12144
<< metal3 >>
rect 14000 12248 34000 12368
rect 14000 11840 34000 11960
@ -134,27 +128,33 @@ rect 1256 744 13920 1024
rect 1256 616 14000 744
rect 1256 443 13920 616
<< metal4 >>
rect 2560 1088 2880 11472
rect 3560 1088 3880 11424
rect 2560 5280 2880 11472
rect 3810 1040 4130 11472
rect 5060 1040 5380 11472
rect 6060 1088 6380 11424
rect 6310 1040 6630 11472
rect 7560 1040 7880 11472
rect 8560 1088 8880 11424
rect 8810 1040 9130 11472
<< obsm4 >>
rect 1256 1632 2276 4448
rect 1256 11552 34000 13000
rect 1256 5200 2480 11552
rect 2960 5200 3730 11552
rect 1256 960 3730 5200
rect 4210 960 4980 11552
rect 5460 960 6230 11552
rect 6710 960 7480 11552
rect 7960 960 8730 11552
rect 9210 960 34000 11552
rect 1256 0 34000 960
<< metal5 >>
rect 920 10678 9844 10998
rect 920 9630 9844 9950
rect 920 8988 9844 9308
rect 920 7940 9844 8260
rect 920 7298 9844 7618
rect 920 6250 9844 6570
rect 920 5608 9844 5928
rect 920 4560 9844 4880
rect 920 3918 9844 4238
rect 920 2870 9844 3190
rect 920 2228 9844 2548
rect 920 1180 9844 1500
rect 872 8833 9892 9153
rect 872 7988 9892 8308
rect 872 5453 9892 5773
rect 872 3763 9892 4083
rect 872 2918 9892 3238
rect 872 2073 9892 2393
rect 872 1228 9892 1548
<< obsm5 >>
rect 13400 0 34000 13000
<< labels >>
rlabel metal2 s 938 12200 994 13000 6 gpio_defaults[0]
port 1 nsew signal input
@ -240,50 +240,40 @@ rlabel metal3 s 14000 11840 34000 11960 6 user_gpio_oeb
port 41 nsew signal input
rlabel metal3 s 14000 12248 34000 12368 6 user_gpio_out
port 42 nsew signal input
rlabel metal5 s 920 1180 9844 1500 6 vccd
port 43 nsew power input
rlabel metal5 s 920 4560 9844 4880 6 vccd
port 43 nsew power input
rlabel metal5 s 920 7940 9844 8260 6 vccd
port 43 nsew power input
rlabel metal4 s 2560 1088 2880 11472 6 vccd
port 43 nsew power input
rlabel metal4 s 2560 5280 2880 11472 6 vccd
port 43 nsew power bidirectional
rlabel metal4 s 7560 1040 7880 11472 6 vccd
port 43 nsew power input
rlabel metal5 s 920 2228 9844 2548 6 vccd1
port 44 nsew power input
rlabel metal5 s 920 5608 9844 5928 6 vccd1
port 44 nsew power input
rlabel metal5 s 920 8988 9844 9308 6 vccd1
port 44 nsew power input
rlabel metal4 s 3560 1088 3880 11424 6 vccd1
port 44 nsew power input
rlabel metal4 s 8560 1088 8880 11424 6 vccd1
port 44 nsew power input
rlabel metal5 s 920 2870 9844 3190 6 vssd
port 45 nsew ground input
rlabel metal5 s 920 6250 9844 6570 6 vssd
port 45 nsew ground input
rlabel metal5 s 920 9630 9844 9950 6 vssd
port 45 nsew ground input
rlabel metal4 s 5060 1040 5380 11472 6 vssd
port 45 nsew ground input
rlabel metal5 s 920 3918 9844 4238 6 vssd1
port 46 nsew ground input
rlabel metal5 s 920 7298 9844 7618 6 vssd1
port 46 nsew ground input
rlabel metal5 s 920 10678 9844 10998 6 vssd1
port 46 nsew ground input
rlabel metal4 s 6060 1088 6380 11424 6 vssd1
port 46 nsew ground input
port 43 nsew power bidirectional
rlabel metal5 s 872 1228 9892 1548 6 vccd
port 43 nsew power bidirectional
rlabel metal5 s 872 7988 9892 8308 6 vccd
port 43 nsew power bidirectional
rlabel metal4 s 5060 1040 5380 11472 6 vccd1
port 44 nsew power bidirectional
rlabel metal5 s 872 2918 9892 3238 6 vccd1
port 44 nsew power bidirectional
rlabel metal4 s 3810 1040 4130 11472 6 vssd
port 45 nsew ground bidirectional
rlabel metal4 s 8810 1040 9130 11472 6 vssd
port 45 nsew ground bidirectional
rlabel metal5 s 872 2073 9892 2393 6 vssd
port 45 nsew ground bidirectional
rlabel metal5 s 872 5453 9892 5773 6 vssd
port 45 nsew ground bidirectional
rlabel metal5 s 872 8833 9892 9153 6 vssd
port 45 nsew ground bidirectional
rlabel metal4 s 6310 1040 6630 11472 6 vssd1
port 46 nsew ground bidirectional
rlabel metal5 s 872 3763 9892 4083 6 vssd1
port 46 nsew ground bidirectional
rlabel metal3 s 14000 416 34000 536 6 zero
port 47 nsew signal output
<< properties >>
string FIXED_BBOX 0 0 34000 13000
string LEFclass BLOCK
string LEFview TRUE
string GDS_END 563480
string GDS_FILE /home/marwan/work/caravel_user_project/caravel/openlane/gpio_control_block/runs/gpio_control_block/results/finishing/gpio_control_block.magic.gds
string GDS_START 197174
string GDS_END 456894
string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_08_06_07_01/results/signoff/gpio_control_block.magic.gds
string GDS_START 156052
<< end >>

124
openlane/Makefile
View File

@ -13,74 +13,77 @@
#
# SPDX-License-Identifier: Apache-2.0
BLOCKS = $(shell find * -maxdepth 0 -type d)
CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
MAKEFLAGS+=--warn-undefined-variables
export OPENLANE_RUN_TAG = $(shell date '+%y_%m_%d_%H_%M')
OPENLANE_TAG ?= 2021.11.23_01.42.34
OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
OPENLANE_BASIC_COMMAND = "cd $(PWD)/../openlane && flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite"
OPENLANE_INTERACTIVE_COMMAND = "cd $(PWD)/../openlane && flow.tcl -it -file ./$*/interactive.tcl"
designs = $(shell find * -maxdepth 0 -type d)
current_design = null
all: $(BLOCKS)
openlane_cmd = \
"flow.tcl \
-design $$(realpath ./$*) \
-save_path $$(realpath ..) \
-save \
-tag $(OPENLANE_RUN_TAG) \
-overwrite"
openlane_cmd_interactive = "flow.tcl -it -file $$(realpath ./$*/interactive.tcl)"
$(CONFIG) :
@echo "Missing $@. Please create a configuration for that design"
@exit 1
docker_mounts = \
-v $$(realpath $(PWD)/..):$$(realpath $(PWD)/..) \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
-v $(PWD):$(PWD) \
.PHONY: $(BLOCKS)
$(BLOCKS) : % : ./%/config.tcl
ifeq ($(OPENLANE_ROOT),)
@echo "Please export OPENLANE_ROOT"
@exit 1
docker_env = \
-e PDK_ROOT=$(PDK_ROOT) \
-e PDK=$(PDK) \
-e MISMATCHES_OK=1 \
-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-e OPENLANE_RUN_TAG=$(OPENLANE_RUN_TAG) \
-w $(PWD)
ifneq ($(MCW_ROOT),)
docker_env += -e MCW_ROOT=$(MCW_ROOT)
docker_mounts += -v $(MCW_ROOT):$(MCW_ROOT)
endif
ifeq ($(PDK_ROOT),)
@echo "Please export PDK_ROOT"
@exit 1
endif
@echo "###############################################"
@sleep 1
@if [ -f ./$*/interactive.tcl ]; then\
docker run --rm -v $(OPENLANE_ROOT):/openlane \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:$(PWD)/.. \
-v $(MCW_ROOT):$(MCW_ROOT) \
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
-e MCW_ROOT=$(MCW_ROOT) \
-e PDK_ROOT=$(PDK_ROOT) \
-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-e PDK=$(PDK) \
-e TEST_MISMATCHES=tools \
-e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_INTERACTIVE_COMMAND);\
else\
docker run --rm -v $(OPENLANE_ROOT):/openlane \
-v $(PDK_ROOT):$(PDK_ROOT) \
-v $(PWD)/..:$(PWD)/.. \
-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
-v $(MCW_ROOT):$(MCW_ROOT) \
-e MCW_ROOT=$(MCW_ROOT) \
-e PDK=$(PDK) \
-e PDK_ROOT=$(PDK_ROOT) \
-e CARAVEL_ROOT=$(CARAVEL_ROOT) \
-e TEST_MISMATCHES=tools \
-e MISMATCHES_OK=1 \
-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
$(OPENLANE_IMAGE_NAME) sh -c $(OPENLANE_BASIC_COMMAND);\
fi
mkdir -p ../signoff/$*/
cp $*/runs/$*/OPENLANE_VERSION ../signoff/$*/
cp $*/runs/$*/PDK_SOURCES ../signoff/$*/
cp $*/runs/$*/reports/final_summary_report.csv ../signoff/$*/
docker_startup_mode = $(shell test -t 0 && echo "-it" || echo "--rm" )
docker_run = \
docker run $(docker_startup_mode) \
$(docker_mounts) \
$(docker_env) \
-u $(shell id -u $(USER)):$(shell id -g $(USER))
list:
@echo $(designs)
.PHONY: $(designs)
$(designs) : export current_design=$@
$(designs) : % : ./%/config.tcl
ifeq (,$(wildcard ./$(current_design)/interactive.tcl))
# $(current_design)
mkdir -p ./$*/runs/$(OPENLANE_RUN_TAG)
rm -rf ./$*/runs/$*
ln -s $$(realpath ./$*/runs/$(OPENLANE_RUN_TAG)) ./$*/runs/$*
$(docker_run) \
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd)
else
$(docker_run) \
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_interactive)
endif
@mkdir -p ../signoff/$*/
@cp ./$*/runs/$*/OPENLANE_VERSION ../signoff/$*/
@cp ./$*/runs/$*/PDK_SOURCES ../signoff/$*/
@cp ./$*/runs/$*/reports/*.csv ../signoff/$*/
.PHONY: openlane
openlane: check-openlane-env
if [ -d "$(OPENLANE_ROOT)" ]; then\
echo "Deleting exisiting $(OPENLANE_ROOT)" && \
rm -rf $(OPENLANE_ROOT) && sleep 2; \
fi
fi
git clone https://github.com/The-OpenROAD-Project/OpenLane --branch=$(OPENLANE_TAG) --depth=1 $(OPENLANE_ROOT) && \
cd $(OPENLANE_ROOT) && \
export OPENLANE_IMAGE_NAME=efabless/openlane:$(OPENLANE_TAG) && \
@ -93,16 +96,3 @@ ifeq ($(OPENLANE_ROOT),)
@echo "Please export OPENLANE_ROOT"
@exit 1
endif
FORCE:
clean:
@echo "Use clean_all to clean everything :)"
clean_all: $(CLEAN)
$(CLEAN): clean-% :
rm -rf runs/$*
rm -rf ../gds/$**
rm -rf ../mag/$**
rm -rf ../lef/$**

55
openlane/gpio_control_block/config.tcl
View File

@ -13,29 +13,30 @@
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) gpio_control_block
set ::env(VERILOG_FILES) "\
$script_dir/../../verilog/rtl/defines.v\
$script_dir/../../verilog/rtl/gpio_control_block.v"
$::env(DESIGN_DIR)/../../verilog/rtl/defines.v\
$::env(DESIGN_DIR)/../../verilog/rtl/gpio_control_block.v"
set ::env(CLOCK_PORT) "serial_clock"
set ::env(FP_DEF_TEMPLATE) "$::env(DESIGN_DIR)/template/gpio_control_block.def"
# This needs to be half the mgmt_core clock frequency
set ::env(CLOCK_PERIOD) "50"
set ::env(VDD_NETS) "vccd vccd1"
set ::env(GND_NETS) "vssd vssd1"
set ::env(BASE_SDC_FILE) $script_dir/base.sdc
set ::env(BASE_SDC_FILE) $::env(DESIGN_DIR)/base.sdc
## Synthesis
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
set ::env(SYNTH_USE_PG_PINS_DEFINES) "USE_POWER_PINS"
set ::env(SYNTH_STRATEGY) "DELAY 0"
set ::env(SYNTH_STRATEGY) "AREA 0"
## Floorplan
set ::env(FP_SIZING) absolute
@ -51,10 +52,13 @@ set ::env(LEFT_MARGIN_MULT) 10
set ::env(TOP_MARGIN_MULT) 2
set ::env(BOTTOM_MARGIN_MULT) 2
set ::env(CELL_PAD) 0
set ::env(DPL_CELL_PADDING) 0
## PDN
set ::env(PDN_CFG) $script_dir/pdn.tcl
set ::env(FP_PDN_MACRO_HOOKS) "\
gpio_logic_high vccd1 vssd1 vccd1 vssd1"
#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
set ::env(FP_PDN_AUTO_ADJUST) 0
set ::env(FP_PDN_VWIDTH) 1.6
@ -81,12 +85,12 @@ set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) 0
# set ::env(DONT_BUFFER_PORTS) "mgmt_gpio_in"
## Routing
set ::env(GLB_RT_MINLAYER) 2
set ::env(GLB_RT_MAXLAYER) 4
set ::env(GLB_RT_ADJUSTMENT) 0.05
set ::env(GRT_MINLAYER) 2
set ::env(GRT_MAXLAYER) 4
set ::env(GRT_ADJUSTMENT) 0.05
# Add obstructions on the areas that will lie underneath the padframe
set ::env(GLB_RT_OBS) "\
set ::env(GRT_OBS) "\
li1 0 0 16.79500 30.02500,
li1 0 29.96500 4.26500 65.07000,
li1 4.21500 57.40500 49.81500 64.93000,
@ -104,28 +108,37 @@ set ::env(FP_TAP_HORIZONTAL_HALO) {2}
set ::env(FP_TAP_VERTICAL_HALO) {2}
## Internal macros
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(MACRO_PLACEMENT_CFG) $::env(DESIGN_DIR)/macro_placement.cfg
set ::env(VERILOG_FILES_BLACKBOX) "\
$script_dir/../../verilog/rtl/gpio_logic_high.v"
$::env(DESIGN_DIR)/../../verilog/rtl/gpio_logic_high.v"
set ::env(EXTRA_LEFS) "\
$script_dir/../../lef/gpio_logic_high.lef"
$::env(DESIGN_DIR)/../../lef/gpio_logic_high.lef"
set ::env(EXTRA_GDS_FILES) "\
$script_dir/../../gds/gpio_logic_high.gds"
$::env(DESIGN_DIR)/../../gds/gpio_logic_high.gds"
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
set ::env(CLOCK_TREE_SYNTH) 1
set ::env(SYNTH_BUFFERING) 0
set ::env(SYNTH_SIZING) 0
# 0.07 ns 70 ps
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.05
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
#set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 2
# set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) 0.07
# set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
# set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 2
set ::env(QUIT_ON_MAGIC_DRC) 0
set ::env(QUIT_ON_LVS_ERROR) 0
set ::env(SYNTH_EXTRA_MAPPING_FILE) $script_dir/yosys_mapping.v
set ::env(SYNTH_EXTRA_MAPPING_FILE) $::env(DESIGN_DIR)/yosys_mapping.v
set ::env(DECAP_CELL) {sky130_fd_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}

87
openlane/gpio_control_block/interactive.tcl
View File

@ -1,87 +0,0 @@
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
package require openlane
set script_dir [file dirname [file normalize [info script]]]
set save_path $script_dir/../..
prep -design $script_dir -tag gpio_control_block -overwrite
run_synthesis
init_floorplan
set ::env(SAVE_DEF) [index_file $::env(floorplan_tmpfiles)/gpio_control_block.io.def]
try_catch openroad -exit $script_dir/io_place.tcl |& tee $::env(TERMINAL_OUTPUT) [index_file $::env(floorplan_logs)/io.log 0]
set_def $::env(SAVE_DEF)
file copy -force $::env(MACRO_PLACEMENT_CFG) $::env(TMP_DIR)/placement/macro_placement.cfg
manual_macro_placement f
tap_decap_or
run_power_grid_generation
run_placement
run_cts
run_resizer_timing
run_routing
if { ($::env(DIODE_INSERTION_STRATEGY) == 2) || ($::env(DIODE_INSERTION_STRATEGY) == 5) } {
run_antenna_check
heal_antenna_violators; # modifies the routed DEF
}
run_magic
run_magic_spice_export
set powered_netlist_name [index_file $::env(finishing_tmpfiles)/powered_netlist.v]
set powered_def_name [index_file $::env(finishing_tmpfiles)/powered_def.def]
write_powered_verilog\
-output_verilog $powered_netlist_name\
-output_def $powered_def_name\
-log $::env(finishing_logs)/write_verilog.log\
-def_log $::env(finishing_logs)/write_powered_def.log
set_netlist $powered_netlist_name
run_magic_drc
run_lvs
run_antenna_check
run_lef_cvc
save_views -save_path $save_path \
-def_path $::env(CURRENT_DEF) \
-lef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef \
-gds_path $::env(finishing_results)/$::env(DESIGN_NAME).gds \
-mag_path $::env(finishing_results)/$::env(DESIGN_NAME).mag \
-maglef_path $::env(finishing_results)/$::env(DESIGN_NAME).lef.mag \
-spice_path $::env(finishing_results)/$::env(DESIGN_NAME).spice \
-verilog_path $::env(CURRENT_NETLIST) \
-spef_path $::env(SPEF_TYPICAL) \
-sdf_path $::env(CURRENT_SDF) \
-sdc_path $::env(CURRENT_SDC)
calc_total_runtime
save_state
generate_final_summary_report
check_timing_violations

3044
openlane/gpio_control_block/template/gpio_control_block.def Normal file
View File

File diff suppressed because it is too large Load Diff

2
sdc/gpio_control_block.sdc
View File

@ -1,6 +1,6 @@
###############################################################################
# Created by write_sdc
# Mon Apr 11 14:40:34 2022
# Sat Aug 6 14:03:05 2022
###############################################################################
current_design gpio_control_block
###############################################################################

2713
sdf/gpio_control_block.sdf
View File

File diff suppressed because it is too large Load Diff

2
signoff/gpio_control_block/OPENLANE_VERSION
View File

@ -1 +1 @@
openlane 302609248b0947f2497a4684c503deca03ad0259
openlane 4476a58407d670d251aa0be6a55e5391bb181c4e

2
signoff/gpio_control_block/PDK_SOURCES
View File

@ -1 +1 @@
open_pdks 7519dfb04400f224f140749cda44ee7de6f5e095
open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066

7982
spef/gpio_control_block.spef
View File

File diff suppressed because it is too large Load Diff

617
spi/lvs/gpio_control_block.spice
View File

@ -4,84 +4,84 @@
.subckt sky130_fd_sc_hd__dfrtp_2 CLK D RESET_B VGND VNB VPB VPWR Q
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and2b_2 abstract view
.subckt sky130_fd_sc_hd__and2b_2 A_N B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__diode_2 abstract view
.subckt sky130_fd_sc_hd__diode_2 DIODE VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__buf_1 abstract view
.subckt sky130_fd_sc_hd__buf_1 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__clkdlybuf4s50_1 abstract view
.subckt sky130_fd_sc_hd__clkdlybuf4s50_1 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbn_2 abstract view
.subckt sky130_fd_sc_hd__dfbbn_2 CLK_N D RESET_B SET_B VGND VNB VPB VPWR Q Q_N
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_2 abstract view
.subckt sky130_fd_sc_hd__clkbuf_2 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__clkdlybuf4s25_1 abstract view
.subckt sky130_fd_sc_hd__clkdlybuf4s25_1 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd3_1 abstract view
.subckt sky130_fd_sc_hd__dlygate4sd3_1 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_2 abstract view
.subckt sky130_fd_sc_hd__or2_2 A B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__a31o_2 abstract view
.subckt sky130_fd_sc_hd__a31o_2 A1 A2 A3 B1 VGND VNB VPB VPWR X
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and2b_2 abstract view
.subckt sky130_fd_sc_hd__and2b_2 A_N B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__or2b_2 abstract view
.subckt sky130_fd_sc_hd__or2b_2 A B_N VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
* Black-box entry subcircuit for sky130_fd_sc_hd__nand2b_2 abstract view
.subckt sky130_fd_sc_hd__nand2b_2 A_N B VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__clkbuf_16 abstract view
.subckt sky130_fd_sc_hd__clkbuf_16 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__inv_2 abstract view
.subckt sky130_fd_sc_hd__inv_2 A VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd3_1 abstract view
.subckt sky130_fd_sc_hd__dlygate4sd3_1 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_12 abstract view
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_4 abstract view
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__or2_2 abstract view
.subckt sky130_fd_sc_hd__or2_2 A B VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__einvp_8 abstract view
.subckt sky130_fd_sc_hd__einvp_8 A TE VGND VNB VPB VPWR Z
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
.ends
* Black-box entry subcircuit for gpio_logic_high abstract view
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__tapvpwrvgnd_1 abstract view
.subckt sky130_fd_sc_hd__tapvpwrvgnd_1 VGND VPWR
* Black-box entry subcircuit for sky130_fd_sc_hd__mux2_1 abstract view
.subckt sky130_fd_sc_hd__mux2_1 A0 A1 S VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__ebufn_2 abstract view
@ -92,36 +92,12 @@
.subckt sky130_fd_sc_hd__buf_2 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__and2_2 abstract view
.subckt sky130_fd_sc_hd__and2_2 A B VGND VNB VPB VPWR X
* Black-box entry subcircuit for sky130_fd_sc_hd__and3b_2 abstract view
.subckt sky130_fd_sc_hd__and3b_2 A_N B C VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__o22ai_2 abstract view
.subckt sky130_fd_sc_hd__o22ai_2 A1 A2 B1 B2 VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__o31ai_2 abstract view
.subckt sky130_fd_sc_hd__o31ai_2 A1 A2 A3 B1 VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__o21a_2 abstract view
.subckt sky130_fd_sc_hd__o21a_2 A1 A2 B1 VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for gpio_logic_high abstract view
.subckt gpio_logic_high gpio_logic1 vccd1 vssd1
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__nand2_2 abstract view
.subckt sky130_fd_sc_hd__nand2_2 A B VGND VNB VPB VPWR Y
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__dlygate4sd2_1 abstract view
.subckt sky130_fd_sc_hd__dlygate4sd2_1 A VGND VNB VPB VPWR X
.ends
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
* Black-box entry subcircuit for sky130_fd_sc_hd__a31o_2 abstract view
.subckt sky130_fd_sc_hd__a31o_2 A1 A2 A3 B1 VGND VNB VPB VPWR X
.ends
.subckt gpio_control_block gpio_defaults[0] gpio_defaults[10] gpio_defaults[11] gpio_defaults[12]
@ -132,331 +108,318 @@
+ pad_gpio_in pad_gpio_inenb pad_gpio_out pad_gpio_outenb pad_gpio_slow_sel pad_gpio_vtrip_sel
+ resetn resetn_out serial_clock serial_clock_out serial_data_in serial_data_out serial_load
+ serial_load_out user_gpio_in user_gpio_oeb user_gpio_out vccd vccd1 vssd vssd1 zero
X_200_ _207_/CLK hold2/X resetn vssd vssd vccd vccd _200_/Q sky130_fd_sc_hd__dfrtp_2
XANTENNA__127__B_N gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_31 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_114_ resetn vssd vssd vccd vccd _177_/A sky130_fd_sc_hd__buf_1
XFILLER_13_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_3_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_130_ _130_/A vssd vssd vccd vccd _130_/X sky130_fd_sc_hd__buf_1
XANTENNA__124__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__160__B_N gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_0_47 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold20 _201_/Q vssd vssd vccd vccd _202_/D sky130_fd_sc_hd__clkdlybuf4s50_1
X_179__3 _179__3/A vssd vssd vccd vccd _179__3/Y sky130_fd_sc_hd__inv_2
X_189_ _154__11/Y hold6/X _153_/X _156_/X vssd vssd vccd vccd pad_gpio_dm[0] _104_/A2
X_131_ _131_/CLK hold1/A resetn vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__dfrtp_2
X_062_ _105_/Q user_gpio_oeb vssd vssd vccd vccd _062_/X sky130_fd_sc_hd__and2b_2
XANTENNA__132__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_114_ _101__10/Y hold1/X _085_/X _086_/Y vssd vssd vccd vccd pad_gpio_dm[2] _114_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA__200__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xclkbuf_1_1_0__077_ clkbuf_0__077_/X vssd vssd vccd vccd _131__7/A sky130_fd_sc_hd__clkbuf_2
X_112_ _210_/A vssd vssd vccd vccd _112_/X sky130_fd_sc_hd__buf_1
Xhold10 hold9/X vssd vssd vccd vccd _198_/D sky130_fd_sc_hd__clkdlybuf4s50_1
Xhold21 _200_/Q vssd vssd vccd vccd _201_/D sky130_fd_sc_hd__clkdlybuf4s50_1
XFILLER_3_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_111_ _111_/A vssd vssd vccd vccd _111_/X sky130_fd_sc_hd__buf_1
XANTENNA__146__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_188_ _148__10/Y hold8/X _147_/X _150_/X vssd vssd vccd vccd _188_/Q _188_/Q_N sky130_fd_sc_hd__dfbbn_2
Xhold22 _205_/D vssd vssd vccd vccd _185_/D sky130_fd_sc_hd__clkdlybuf4s25_1
Xhold11 _195_/Q vssd vssd vccd vccd hold12/A sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_15_24 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_187_ _142__9/Y hold2/X _140_/X _145_/X vssd vssd vccd vccd pad_gpio_ib_mode_sel
+ _187_/Q_N sky130_fd_sc_hd__dfbbn_2
X_110_ _180_/A gpio_defaults[0] vssd vssd vccd vccd _111_/A sky130_fd_sc_hd__or2_2
Xhold12 hold12/A vssd vssd vccd vccd _196_/D sky130_fd_sc_hd__clkdlybuf4s50_1
Xhold23 _207_/D vssd vssd vccd vccd _190_/D sky130_fd_sc_hd__clkdlybuf4s25_1
XANTENNA__162__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__157__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_186_ _136__8/Y _199_/D _135_/X _138_/X vssd vssd vccd vccd pad_gpio_inenb _186_/Q_N
XFILLER_13_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_15_65 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_130_ _133_/A _130_/D resetn vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_2
X_061_ pad_gpio_inenb _111_/Q vssd vssd vccd vccd _061_/Y sky130_fd_sc_hd__nand2b_2
X_113_ _100__9/Y _130_/D _083_/X _084_/Y vssd vssd vccd vccd pad_gpio_dm[1] _113_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
Xhold13 _198_/Q vssd vssd vccd vccd hold14/A sky130_fd_sc_hd__dlygate4sd3_1
Xclkbuf_1_0__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _100__9/A sky130_fd_sc_hd__clkbuf_16
XANTENNA__135__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_104__13 _100__9/A vssd vssd vccd vccd _104__13/Y sky130_fd_sc_hd__inv_2
X_094__3 _134_/A vssd vssd vccd vccd _094__3/Y sky130_fd_sc_hd__inv_2
XFILLER_18_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_18_44 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
Xhold10 _124_/Q vssd vssd vccd vccd _125_/D sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__122__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_112_ _099__8/Y hold8/X _081_/X _082_/Y vssd vssd vccd vccd pad_gpio_dm[0] _065_/A1
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA__065__A0 mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__061__A_N pad_gpio_inenb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__084__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_111_ _098__7/Y hold5/X _079_/X _080_/Y vssd vssd vccd vccd _111_/Q _111_/Q_N sky130_fd_sc_hd__dfbbn_2
XANTENNA__067__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold11 _125_/Q vssd vssd vccd vccd _126_/D sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_11_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
XANTENNA__075__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_79 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__131__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_24 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
XANTENNA__072__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__074__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_110_ _097__6/Y hold9/X _077_/X _078_/Y vssd vssd vccd vccd pad_gpio_ib_mode_sel
+ _110_/Q_N sky130_fd_sc_hd__dfbbn_2
Xhold12 _123_/Q vssd vssd vccd vccd _124_/D sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_1_71 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
XFILLER_1_82 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__067__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__083__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__080__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_12_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
XFILLER_3_39 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__064__C mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__075__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__091__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold13 _129_/Q vssd vssd vccd vccd _130_/D sky130_fd_sc_hd__dlygate4sd3_1
X_097__6 _100__9/A vssd vssd vccd vccd _097__6/Y sky130_fd_sc_hd__inv_2
XANTENNA__083__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__078__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_7_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__203__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_185_ _131__7/Y _185_/D _130_/X _133_/X vssd vssd vccd vccd pad_gpio_vtrip_sel _185_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA__196__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_099_ _188_/Q mgmt_gpio_oeb _182_/Q _098_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__a31o_2
Xhold14 hold14/A vssd vssd vccd vccd _199_/D sky130_fd_sc_hd__clkdlybuf4s50_1
X_168_ _168_/A vssd vssd vccd vccd _168_/X sky130_fd_sc_hd__buf_1
XFILLER_6_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__064__A_N pad_gpio_dm[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__089__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__125__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__091__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__086__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_48 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
XFILLER_18_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_164__13 _164__13/A vssd vssd vccd vccd _164__13/Y sky130_fd_sc_hd__inv_2
X_184_ _126__6/Y _204_/D _125_/X _128_/X vssd vssd vccd vccd pad_gpio_slow_sel _184_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XFILLER_18_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__089__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xconst_source vssd vssd vccd vccd one zero sky130_fd_sc_hd__conb_1
X_098_ _182_/Q user_gpio_oeb vssd vssd vccd vccd _098_/X sky130_fd_sc_hd__and2b_2
X_167_ _172_/A gpio_defaults[5] vssd vssd vccd vccd _168_/A sky130_fd_sc_hd__or2_2
Xhold15 _203_/Q vssd vssd vccd vccd hold16/A sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_16_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__119__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_183_ _120__5/Y _198_/D _119_/X _122_/X vssd vssd vccd vccd pad_gpio_holdover _183_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
X_166_ _166_/A vssd vssd vccd vccd _166_/X sky130_fd_sc_hd__buf_1
X_097_ _097_/A vssd vssd vccd vccd _097_/X sky130_fd_sc_hd__buf_1
X_149_ _165_/A gpio_defaults[1] vssd vssd vccd vccd _150_/A sky130_fd_sc_hd__or2b_2
Xhold16 hold16/A vssd vssd vccd vccd _204_/D sky130_fd_sc_hd__clkdlybuf4s50_1
XFILLER_1_75 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__100__A user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_182_ _113__4/Y _196_/D _111_/X _117_/X vssd vssd vccd vccd _182_/Q _182_/Q_N sky130_fd_sc_hd__dfbbn_2
Xhold17 _204_/Q vssd vssd vccd vccd _205_/D sky130_fd_sc_hd__clkdlybuf4s50_1
X_096_ pad_gpio_inenb _188_/Q vssd vssd vccd vccd _097_/A sky130_fd_sc_hd__or2b_2
X_165_ _165_/A gpio_defaults[12] vssd vssd vccd vccd _166_/A sky130_fd_sc_hd__or2b_2
XANTENNA__206__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_079_ resetn gpio_defaults[1] vssd vssd vccd vccd _079_/X sky130_fd_sc_hd__or2_2
XANTENNA__128__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__199__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__195__D serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xclkbuf_1_1_0_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _210_/A sky130_fd_sc_hd__clkbuf_2
X_181_ _181_/A vssd vssd vccd vccd _181_/X sky130_fd_sc_hd__buf_1
XFILLER_18_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
X_147_ _147_/A vssd vssd vccd vccd _147_/X sky130_fd_sc_hd__buf_1
XANTENNA__106__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold18 _206_/Q vssd vssd vccd vccd _207_/D sky130_fd_sc_hd__clkdlybuf4s50_1
XANTENNA__090__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
X_078_ resetn gpio_defaults[4] vssd vssd vccd vccd _078_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_7_76 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__114__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_180_ _180_/A gpio_defaults[7] vssd vssd vccd vccd _181_/A sky130_fd_sc_hd__or2b_2
X_169__1 _179__3/A vssd vssd vccd vccd _169__1/Y sky130_fd_sc_hd__inv_2
XANTENNA__109__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__149__B_N gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold19 _202_/Q vssd vssd vccd vccd _203_/D sky130_fd_sc_hd__clkdlybuf4s25_1
XANTENNA__080__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_10_76 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_1_56 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
XFILLER_1_78 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_163_ _163_/A vssd vssd vccd vccd _163_/X sky130_fd_sc_hd__buf_1
X_129_ _146_/A gpio_defaults[9] vssd vssd vccd vccd _130_/A sky130_fd_sc_hd__or2_2
Xclkbuf_0__077_ _112_/X vssd vssd vccd vccd clkbuf_0__077_/X sky130_fd_sc_hd__clkbuf_16
Xclkbuf_1_0_0__077_ clkbuf_0__077_/X vssd vssd vccd vccd _136__8/A sky130_fd_sc_hd__clkbuf_2
X_146_ _146_/A gpio_defaults[1] vssd vssd vccd vccd _147_/A sky130_fd_sc_hd__or2_2
X_100__9 _100__9/A vssd vssd vccd vccd _100__9/Y sky130_fd_sc_hd__inv_2
X_077_ resetn gpio_defaults[4] vssd vssd vccd vccd _077_/X sky130_fd_sc_hd__or2_2
X_129_ _133_/A hold8/X resetn vssd vssd vccd vccd _129_/Q sky130_fd_sc_hd__dfrtp_2
X_103__12 _100__9/A vssd vssd vccd vccd _103__12/Y sky130_fd_sc_hd__inv_2
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_174__2 _179__3/A vssd vssd vccd vccd _174__2/Y sky130_fd_sc_hd__inv_2
X_162_ _172_/A gpio_defaults[12] vssd vssd vccd vccd _163_/A sky130_fd_sc_hd__or2_2
X_145_ _145_/A vssd vssd vccd vccd _145_/X sky130_fd_sc_hd__buf_1
XANTENNA__116__B_N gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_128_ _128_/A vssd vssd vccd vccd _128_/X sky130_fd_sc_hd__buf_1
XFILLER_7_34 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_8_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
X_076_ resetn gpio_defaults[3] vssd vssd vccd vccd _076_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_10_44 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_1_68 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__070__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_128_ _133_/A hold2/X resetn vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dfrtp_2
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_161_ _161_/A vssd vssd vccd vccd _161_/X sky130_fd_sc_hd__buf_1
Xgpio_in_buf _106_/Y gpio_in_buf/TE vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__einvp_8
XANTENNA__121__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_092_ resetn gpio_defaults[7] vssd vssd vccd vccd _092_/Y sky130_fd_sc_hd__nand2b_2
Xgpio_in_buf _058_/Y gpio_in_buf/TE vssd vssd vccd vccd user_gpio_in sky130_fd_sc_hd__einvp_8
XFILLER_16_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
X_075_ resetn gpio_defaults[3] vssd vssd vccd vccd _075_/X sky130_fd_sc_hd__or2_2
X_058_ pad_gpio_in vssd vssd vccd vccd _058_/Y sky130_fd_sc_hd__inv_2
XANTENNA_clkbuf_0_serial_load_A serial_load vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_127_ _137_/A gpio_defaults[8] vssd vssd vccd vccd _128_/A sky130_fd_sc_hd__or2b_2
XFILLER_16_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_144_ _165_/A gpio_defaults[4] vssd vssd vccd vccd _145_/A sky130_fd_sc_hd__or2b_2
X_127_ _133_/A hold7/X resetn vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dfrtp_2
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_143_ _177_/A vssd vssd vccd vccd _165_/A sky130_fd_sc_hd__buf_1
X_136__8 _136__8/A vssd vssd vccd vccd _136__8/Y sky130_fd_sc_hd__inv_2
X_160_ _165_/A gpio_defaults[11] vssd vssd vccd vccd _161_/A sky130_fd_sc_hd__or2b_2
XFILLER_1_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
X_074_ resetn gpio_defaults[9] vssd vssd vccd vccd _074_/Y sky130_fd_sc_hd__nand2b_2
X_091_ resetn gpio_defaults[7] vssd vssd vccd vccd _091_/X sky130_fd_sc_hd__or2_2
X_126_ _126_/CLK _126_/D resetn vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_2
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__139__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_109_ resetn vssd vssd vccd vccd _180_/A sky130_fd_sc_hd__buf_1
X_095__4 _134_/A vssd vssd vccd vccd _095__4/Y sky130_fd_sc_hd__inv_2
XFILLER_13_35 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_109_ _096__5/Y hold4/X _075_/X _076_/Y vssd vssd vccd vccd pad_gpio_inenb _109_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA__130__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_60 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__152__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_125_ _125_/A vssd vssd vccd vccd _125_/X sky130_fd_sc_hd__buf_1
X_211_ pad_gpio_in _097_/X vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_2
X_108_ _108_/A vssd vssd vccd vccd serial_data_out sky130_fd_sc_hd__buf_1
X_154__11 _142__9/A vssd vssd vccd vccd _154__11/Y sky130_fd_sc_hd__inv_2
XFILLER_13_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__175__B_N gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_210_ _210_/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__buf_2
X_090_ resetn gpio_defaults[6] vssd vssd vccd vccd _090_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA__073__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__062__B user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_073_ resetn gpio_defaults[9] vssd vssd vccd vccd _073_/X sky130_fd_sc_hd__or2_2
XFILLER_2_70 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_125_ _126_/CLK _125_/D resetn vssd vssd vccd vccd _125_/Q sky130_fd_sc_hd__dfrtp_2
XANTENNA__070__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_108_ _095__4/Y hold2/X _073_/X _074_/Y vssd vssd vccd vccd pad_gpio_vtrip_sel _108_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA__081__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_61 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_072_ resetn gpio_defaults[8] vssd vssd vccd vccd _072_/Y sky130_fd_sc_hd__nand2b_2
XTAP_50 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_141_ _210_/A vssd vssd vccd vccd _141_/X sky130_fd_sc_hd__buf_1
Xclkbuf_1_1_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _209_/A sky130_fd_sc_hd__clkbuf_2
X_124_ _146_/A gpio_defaults[8] vssd vssd vccd vccd _125_/A sky130_fd_sc_hd__or2_2
XANTENNA__202__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__195__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_14_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_107_ one _107_/B vssd vssd vccd vccd _108_/A sky130_fd_sc_hd__and2_2
XANTENNA__165__B_N gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__086__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__068__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__073__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_124_ _126_/CLK _124_/D resetn vssd vssd vccd vccd _124_/Q sky130_fd_sc_hd__dfrtp_2
XANTENNA__079__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_14_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
X_107_ _094__3/Y hold7/X _071_/X _072_/Y vssd vssd vccd vccd pad_gpio_slow_sel _107_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA__124__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_060__14 _133_/A vssd vssd vccd vccd _131_/CLK sky130_fd_sc_hd__inv_2
XANTENNA__076__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__081__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_62 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_140_ _140_/A vssd vssd vccd vccd _140_/X sky130_fd_sc_hd__buf_1
X_071_ resetn gpio_defaults[8] vssd vssd vccd vccd _071_/X sky130_fd_sc_hd__or2_2
XFILLER_10_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_51 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__087__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_40 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_123_ _177_/A vssd vssd vccd vccd _146_/A sky130_fd_sc_hd__buf_1
X_106_ pad_gpio_in vssd vssd vccd vccd _106_/Y sky130_fd_sc_hd__inv_2
X_148__10 _142__9/A vssd vssd vccd vccd _148__10/Y sky130_fd_sc_hd__inv_2
XANTENNA__132__B_N gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_2_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_106_ _093__2/Y hold3/X _069_/X _070_/Y vssd vssd vccd vccd pad_gpio_holdover _106_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
X_123_ _126_/CLK hold9/X resetn vssd vssd vccd vccd _123_/Q sky130_fd_sc_hd__dfrtp_2
XANTENNA__084__B gpio_defaults[11] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__079__B gpio_defaults[1] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__076__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_070_ resetn gpio_defaults[2] vssd vssd vccd vccd _070_/Y sky130_fd_sc_hd__nand2b_2
XTAP_63 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__177__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__118__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_52 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__092__B gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__087__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_41 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__155__B_N gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_16_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_11_60 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_122_ _122_/A vssd vssd vccd vccd _122_/X sky130_fd_sc_hd__buf_1
X_199_ _207_/CLK _199_/D resetn vssd vssd vccd vccd hold1/A sky130_fd_sc_hd__dfrtp_2
X_105_ _182_/Q _100_/Y _103_/X _104_/Y vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__o22ai_2
X_098__7 _134_/A vssd vssd vccd vccd _098__7/Y sky130_fd_sc_hd__inv_2
X_122_ _126_/CLK hold4/X resetn vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_2
XFILLER_2_40 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_105_ _059__1/Y hold6/X _067_/X _068_/Y vssd vssd vccd vccd _105_/Q _105_/Q_N sky130_fd_sc_hd__dfbbn_2
XTAP_64 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_14_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_53 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_198_ _209_/A _198_/D resetn vssd vssd vccd vccd _198_/Q sky130_fd_sc_hd__dfrtp_2
XTAP_42 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__098__B user_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_121_ _137_/A gpio_defaults[2] vssd vssd vccd vccd _122_/A sky130_fd_sc_hd__or2b_2
X_104_ pad_gpio_dm[2] _104_/A2 _101_/Y _182_/Q vssd vssd vccd vccd _104_/Y sky130_fd_sc_hd__o31ai_2
XFILLER_12_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__205__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_121_ _126_/CLK hold3/X resetn vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dfrtp_2
XFILLER_12_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
XTAP_65 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XFILLER_14_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_54 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_43 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_197_ _209_/A hold8/X resetn vssd vssd vccd vccd hold9/A sky130_fd_sc_hd__dfrtp_2
XANTENNA__198__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_103_ pad_gpio_dm[2] _101_/Y _102_/Y vssd vssd vccd vccd _103_/X sky130_fd_sc_hd__o21a_2
X_120__5 _136__8/A vssd vssd vccd vccd _120__5/Y sky130_fd_sc_hd__inv_2
Xhold1 hold1/A vssd vssd vccd vccd hold2/A sky130_fd_sc_hd__dlygate4sd3_1
X_120_ _126_/CLK hold5/X resetn vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_2
XANTENNA__127__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_17_72 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold1 hold1/A vssd vssd vccd vccd hold1/X sky130_fd_sc_hd__dlygate4sd3_1
XTAP_55 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_196_ _209_/A _196_/D resetn vssd vssd vccd vccd hold7/A sky130_fd_sc_hd__dfrtp_2
XANTENNA__101__A mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_44 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_102_ mgmt_gpio_out vssd vssd vccd vccd _102_/Y sky130_fd_sc_hd__inv_2
X_102__11 _100__9/A vssd vssd vccd vccd _102__11/Y sky130_fd_sc_hd__inv_2
Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__dlygate4sd3_1
Xclkbuf_0_serial_load serial_load vssd vssd vccd vccd clkbuf_0_serial_load/X sky130_fd_sc_hd__clkbuf_16
Xhold2 hold2/A vssd vssd vccd vccd hold2/X sky130_fd_sc_hd__clkdlybuf4s50_1
Xclkbuf_1_0__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _126_/CLK
+ sky130_fd_sc_hd__clkbuf_16
XFILLER_14_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XTAP_56 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_45 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
Xgpio_logic_high gpio_in_buf/TE vccd1 vssd1 gpio_logic_high
XFILLER_5_32 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_195_ _209_/A serial_data_in resetn vssd vssd vccd vccd _195_/Q sky130_fd_sc_hd__dfrtp_2
X_101_ mgmt_gpio_oeb pad_gpio_dm[1] vssd vssd vccd vccd _101_/Y sky130_fd_sc_hd__nand2_2
X_178_ _178_/A vssd vssd vccd vccd _178_/X sky130_fd_sc_hd__buf_1
Xclkbuf_1_1_0__049_ clkbuf_0__049_/X vssd vssd vccd vccd _142__9/A sky130_fd_sc_hd__clkbuf_2
Xclkbuf_1_0_0_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _179__3/A sky130_fd_sc_hd__clkbuf_2
XFILLER_10_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold3 hold3/A vssd vssd vccd vccd hold4/A sky130_fd_sc_hd__dlygate4sd3_1
X_126__6 _131__7/A vssd vssd vccd vccd _126__6/Y sky130_fd_sc_hd__inv_2
XFILLER_14_42 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_2_44 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold3 hold3/A vssd vssd vccd vccd hold3/X sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_10_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_57 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XPHY_30 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_46 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_194_ _179__3/Y _203_/D _178_/X _181_/X vssd vssd vccd vccd pad_gpio_ana_pol _194_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
X_100_ user_gpio_out vssd vssd vccd vccd _100_/Y sky130_fd_sc_hd__inv_2
XANTENNA__208__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_177_ _177_/A gpio_defaults[7] vssd vssd vccd vccd _178_/A sky130_fd_sc_hd__or2_2
Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__clkdlybuf4s25_1
X_131__7 _131__7/A vssd vssd vccd vccd _131__7/Y sky130_fd_sc_hd__inv_2
XANTENNA__120__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold4 hold4/A vssd vssd vccd vccd hold4/X sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__092__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_58 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_47 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
X_093__2 _134_/A vssd vssd vccd vccd _093__2/Y sky130_fd_sc_hd__inv_2
XPHY_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_193_ _174__2/Y _202_/D _173_/X _176_/X vssd vssd vccd vccd pad_gpio_ana_sel _193_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA__118__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_176_ _176_/A vssd vssd vccd vccd _176_/X sky130_fd_sc_hd__buf_1
Xhold5 hold5/A vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dlygate4sd3_1
Xdata_delay_1 hold3/A vssd vssd vccd vccd data_delay_2/A sky130_fd_sc_hd__dlygate4sd2_1
Xhold5 hold5/A vssd vssd vccd vccd hold5/X sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__082__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_32 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_59 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XPHY_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XTAP_48 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_192_ _169__1/Y _201_/D _168_/X _171_/X vssd vssd vccd vccd pad_gpio_ana_en _192_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
X_175_ _180_/A gpio_defaults[6] vssd vssd vccd vccd _176_/A sky130_fd_sc_hd__or2b_2
XFILLER_2_47 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__129__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__134__B gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold6 hold6/A vssd vssd vccd vccd hold6/X sky130_fd_sc_hd__clkdlybuf4s50_1
X_158_ _158_/A vssd vssd vccd vccd _158_/X sky130_fd_sc_hd__buf_1
XFILLER_17_11 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold6 hold6/A vssd vssd vccd vccd hold6/X sky130_fd_sc_hd__dlygate4sd3_1
X_089_ resetn gpio_defaults[6] vssd vssd vccd vccd _089_/X sky130_fd_sc_hd__or2_2
XTAP_49 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XTAP_38 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
Xclkbuf_1_0_0_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _207_/CLK sky130_fd_sc_hd__clkbuf_2
Xdata_delay_2 data_delay_2/A vssd vssd vccd vccd _107_/B sky130_fd_sc_hd__dlygate4sd2_1
XFILLER_0_80 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
XPHY_33 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_11_24 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__072__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xclkbuf_0_serial_clock serial_clock vssd vssd vccd vccd clkbuf_0_serial_clock/X sky130_fd_sc_hd__clkbuf_16
X_191_ _164__13/Y hold4/X _163_/X _166_/X vssd vssd vccd vccd pad_gpio_dm[2] _191_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__063__A2 mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_157_ _172_/A gpio_defaults[11] vssd vssd vccd vccd _158_/A sky130_fd_sc_hd__or2_2
X_209_ _209_/A vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__buf_2
XFILLER_17_45 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
Xhold7 hold7/A vssd vssd vccd vccd hold8/A sky130_fd_sc_hd__dlygate4sd3_1
XFILLER_5_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_142__9 _142__9/A vssd vssd vccd vccd _142__9/Y sky130_fd_sc_hd__inv_2
XANTENNA__201__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__118__D serial_data_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_088_ resetn gpio_defaults[5] vssd vssd vccd vccd _088_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA__058__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold7 hold7/A vssd vssd vccd vccd hold7/X sky130_fd_sc_hd__dlygate4sd3_1
XANTENNA__071__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XTAP_39 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
XANTENNA__066__A0 user_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_190_ _159__12/Y _190_/D _158_/X _161_/X vssd vssd vccd vccd pad_gpio_dm[1] _190_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
X_173_ _173_/A vssd vssd vccd vccd _173_/X sky130_fd_sc_hd__buf_1
X_156_ _156_/A vssd vssd vccd vccd _156_/X sky130_fd_sc_hd__buf_1
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__clkdlybuf4s25_1
X_208_ resetn vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_2
X_139_ _146_/A gpio_defaults[4] vssd vssd vccd vccd _140_/A sky130_fd_sc_hd__or2_2
XFILLER_0_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__123__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xclkbuf_1_1__f_serial_load clkbuf_0_serial_load/X vssd vssd vccd vccd _134_/A sky130_fd_sc_hd__clkbuf_16
XANTENNA__069__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_087_ resetn gpio_defaults[5] vssd vssd vccd vccd _087_/X sky130_fd_sc_hd__or2_2
Xhold8 hold8/A vssd vssd vccd vccd hold8/X sky130_fd_sc_hd__dlygate4sd3_1
X_096__5 _134_/A vssd vssd vccd vccd _096__5/Y sky130_fd_sc_hd__inv_2
XANTENNA__071__B gpio_defaults[8] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_155_ _165_/A gpio_defaults[10] vssd vssd vccd vccd _156_/A sky130_fd_sc_hd__or2b_2
X_172_ _172_/A gpio_defaults[6] vssd vssd vccd vccd _173_/A sky130_fd_sc_hd__or2_2
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
XANTENNA__077__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_086_ resetn gpio_defaults[12] vssd vssd vccd vccd _086_/Y sky130_fd_sc_hd__nand2b_2
XANTENNA__074__B gpio_defaults[9] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xclkbuf_1_1__f_serial_clock clkbuf_0_serial_clock/X vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__clkbuf_16
XFILLER_11_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_11_15 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_3_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_138_ _138_/A vssd vssd vccd vccd _138_/X sky130_fd_sc_hd__buf_1
XANTENNA__085__A resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_069_ resetn gpio_defaults[2] vssd vssd vccd vccd _069_/X sky130_fd_sc_hd__or2_2
XANTENNA__069__B gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
Xhold9 hold9/A vssd vssd vccd vccd hold9/X sky130_fd_sc_hd__dlygate4sd3_1
X_207_ _207_/CLK _207_/D resetn vssd vssd vccd vccd hold3/A sky130_fd_sc_hd__dfrtp_2
XANTENNA__167__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__172__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_0_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_6_60 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__082__B gpio_defaults[10] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_171_ _171_/A vssd vssd vccd vccd _171_/X sky130_fd_sc_hd__buf_1
XANTENNA__077__B gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_17_48 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_3_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_137_ _137_/A gpio_defaults[3] vssd vssd vccd vccd _138_/A sky130_fd_sc_hd__or2b_2
XFILLER_17_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__096__A pad_gpio_inenb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_206_ _209_/A hold6/X resetn vssd vssd vccd vccd _206_/Q sky130_fd_sc_hd__dfrtp_2
XFILLER_0_84 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__085__B gpio_defaults[12] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_085_ resetn gpio_defaults[12] vssd vssd vccd vccd _085_/X sky130_fd_sc_hd__or2_2
XANTENNA__090__B gpio_defaults[6] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_068_ resetn gpio_defaults[0] vssd vssd vccd vccd _068_/Y sky130_fd_sc_hd__nand2b_2
XFILLER_17_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
XPHY_37 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XFILLER_14_38 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XPHY_26 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__121__B_N gpio_defaults[2] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_170_ _180_/A gpio_defaults[5] vssd vssd vccd vccd _171_/A sky130_fd_sc_hd__or2b_2
XANTENNA__204__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_153_ _153_/A vssd vssd vccd vccd _153_/X sky130_fd_sc_hd__buf_1
XFILLER_12_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_205_ _209_/A _205_/D resetn vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_2
XANTENNA__144__B_N gpio_defaults[4] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_119_ _119_/A vssd vssd vccd vccd _119_/X sky130_fd_sc_hd__buf_1
XANTENNA__197__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_15_93 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_6_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XANTENNA__088__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__088__B gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_067_ resetn gpio_defaults[0] vssd vssd vccd vccd _067_/X sky130_fd_sc_hd__or2_2
XFILLER_8_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_0_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
X_084_ resetn gpio_defaults[11] vssd vssd vccd vccd _084_/Y sky130_fd_sc_hd__nand2b_2
X_119_ _126_/CLK hold6/X resetn vssd vssd vccd vccd hold5/A sky130_fd_sc_hd__dfrtp_2
XANTENNA__126__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_101__10 _134_/A vssd vssd vccd vccd _101__10/Y sky130_fd_sc_hd__inv_2
XPHY_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_113__4 _136__8/A vssd vssd vccd vccd _113__4/Y sky130_fd_sc_hd__inv_2
XFILLER_12_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_152_ _172_/A gpio_defaults[10] vssd vssd vccd vccd _153_/A sky130_fd_sc_hd__or2_2
X_135_ _135_/A vssd vssd vccd vccd _135_/X sky130_fd_sc_hd__buf_1
X_204_ _209_/A _204_/D resetn vssd vssd vccd vccd _204_/Q sky130_fd_sc_hd__dfrtp_2
X_118_ _180_/A gpio_defaults[2] vssd vssd vccd vccd _119_/A sky130_fd_sc_hd__or2_2
XANTENNA__078__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_083_ resetn gpio_defaults[11] vssd vssd vccd vccd _083_/X sky130_fd_sc_hd__or2_2
X_099__8 _100__9/A vssd vssd vccd vccd _099__8/Y sky130_fd_sc_hd__inv_2
XFILLER_18_71 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_118_ _133_/A serial_data_in resetn vssd vssd vccd vccd hold6/A sky130_fd_sc_hd__dfrtp_2
X_066_ user_gpio_out _065_/X _105_/Q vssd vssd vccd vccd pad_gpio_out sky130_fd_sc_hd__mux2_1
X_135_ pad_gpio_in _061_/Y vssd vssd vccd vccd mgmt_gpio_in sky130_fd_sc_hd__ebufn_2
XFILLER_0_64 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
XPHY_28 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
Xclkbuf_0__049_ _141_/X vssd vssd vccd vccd clkbuf_0__049_/X sky130_fd_sc_hd__clkbuf_16
Xclkbuf_1_0_0__049_ clkbuf_0__049_/X vssd vssd vccd vccd _164__13/A sky130_fd_sc_hd__clkbuf_2
X_134_ _146_/A gpio_defaults[3] vssd vssd vccd vccd _135_/A sky130_fd_sc_hd__or2_2
X_203_ _207_/CLK _203_/D resetn vssd vssd vccd vccd _203_/Q sky130_fd_sc_hd__dfrtp_2
X_151_ _177_/A vssd vssd vccd vccd _172_/A sky130_fd_sc_hd__buf_1
XFILLER_18_83 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_117_ _117_/A vssd vssd vccd vccd _117_/X sky130_fd_sc_hd__buf_1
X_134_ _134_/A vssd vssd vccd vccd serial_load_out sky130_fd_sc_hd__buf_2
X_059__1 _134_/A vssd vssd vccd vccd _059__1/Y sky130_fd_sc_hd__inv_2
XFILLER_0_76 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
X_082_ resetn gpio_defaults[10] vssd vssd vccd vccd _082_/Y sky130_fd_sc_hd__nand2b_2
X_065_ mgmt_gpio_out _065_/A1 _065_/S vssd vssd vccd vccd _065_/X sky130_fd_sc_hd__mux2_1
XANTENNA__068__A_N resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_61 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_15_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
X_117_ _104__13/Y _126_/D _091_/X _092_/Y vssd vssd vccd vccd pad_gpio_ana_pol _117_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XPHY_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__102__A mgmt_gpio_out vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_150_ _150_/A vssd vssd vccd vccd _150_/X sky130_fd_sc_hd__buf_1
X_159__12 _164__13/A vssd vssd vccd vccd _159__12/Y sky130_fd_sc_hd__inv_2
X_133_ _133_/A vssd vssd vccd vccd _133_/X sky130_fd_sc_hd__buf_1
X_202_ _207_/CLK _202_/D resetn vssd vssd vccd vccd _202_/Q sky130_fd_sc_hd__dfrtp_2
X_116_ _137_/A gpio_defaults[0] vssd vssd vccd vccd _117_/A sky130_fd_sc_hd__or2b_2
X_081_ resetn gpio_defaults[10] vssd vssd vccd vccd _081_/X sky130_fd_sc_hd__or2_2
X_133_ _133_/A vssd vssd vccd vccd serial_clock_out sky130_fd_sc_hd__buf_2
X_064_ pad_gpio_dm[2] pad_gpio_dm[1] mgmt_gpio_oeb vssd vssd vccd vccd _065_/S sky130_fd_sc_hd__and3b_2
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
XANTENNA__180__B_N gpio_defaults[7] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__207__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_116_ _103__12/Y _125_/D _089_/X _090_/Y vssd vssd vccd vccd pad_gpio_ana_sel _116_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
XANTENNA_clkbuf_0_serial_clock_A serial_clock vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__137__B_N gpio_defaults[3] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_132_ _137_/A gpio_defaults[9] vssd vssd vccd vccd _133_/A sky130_fd_sc_hd__or2b_2
XANTENNA__099__A2 mgmt_gpio_oeb vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_201_ _207_/CLK _201_/D resetn vssd vssd vccd vccd _201_/Q sky130_fd_sc_hd__dfrtp_2
XFILLER_18_63 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
XANTENNA__110__B gpio_defaults[0] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_115_ _177_/A vssd vssd vccd vccd _137_/A sky130_fd_sc_hd__buf_1
XANTENNA__211__A pad_gpio_in vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XANTENNA__170__B_N gpio_defaults[5] vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
X_080_ resetn gpio_defaults[1] vssd vssd vccd vccd _080_/Y sky130_fd_sc_hd__nand2b_2
X_132_ resetn vssd vssd vccd vccd resetn_out sky130_fd_sc_hd__buf_2
X_063_ _111_/Q mgmt_gpio_oeb _105_/Q _062_/X vssd vssd vccd vccd pad_gpio_outenb sky130_fd_sc_hd__a31o_2
XANTENNA__129__RESET_B resetn vssd vssd vccd vccd sky130_fd_sc_hd__diode_2
XFILLER_18_85 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
XFILLER_18_52 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
X_115_ _102__11/Y _124_/D _087_/X _088_/Y vssd vssd vccd vccd pad_gpio_ana_en _115_/Q_N
+ sky130_fd_sc_hd__dfbbn_2
.ends

1632
verilog/gl/gpio_control_block.v
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