riscv
/
caravel
mirror of https://github.com/efabless/caravel.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

reharden!: caravel 

~ update the following views:
def
mag
verilog
spef(all corners)
+ add the ability to override the interactive script filename
+ add the ability to run openlane regression using regression.config
file
~ change GRT ADJUSTMENT values
~ change pointers to some files for workarounds

!important the interactive script still needs updates
!important this was done using old openlane v0.22 and its matching
pdk
!important known workarounds:
- a custom techlef is used where large metal spacing rules are the
only ones present to avoid violations by the router
- some odd behaviour happening when a macro has a lef view
with a non zero origin. so the power routing cell is (temporarily)
modified to have a zero origin and its placement has been shifted
which doesn't match the power routing mag.
- the old openlane doesn't generate multi spef corners. they
are generated using timing-scripts repo
This commit is contained in:
kareem 2022-10-10 04:51:05 -07:00
parent 2459b3583e
commit 285ef6b642
15 changed files with 393059 additions and 94618 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

53013
def/caravel.def
View File

File diff suppressed because it is too large Load Diff

161176
mag/caravel.mag
View File

File diff suppressed because it is too large Load Diff

25
openlane/Makefile
View File

@ -15,9 +15,10 @@
MAKEFLAGS+=--warn-undefined-variables
export OPENLANE_RUN_TAG = $(shell date '+%y_%m_%d_%H_%M')
export OPENLANE_RUN_TAG ?= $(shell date '+%y_%m_%d_%H_%M')
OPENLANE_TAG ?= 2021.11.23_01.42.34
OPENLANE_IMAGE_NAME ?= efabless/openlane:$(OPENLANE_TAG)
IT_SCRIPT ?= ./interactive.tcl
designs = $(shell find * -maxdepth 0 -type d)
current_design = null
@ -26,9 +27,14 @@ openlane_cmd = \
-design $$(realpath ./$*) \
-save_path $$(realpath ..) \
-save \
-tag $(OPENLANE_RUN_TAG) \
-OPENLANE_RUN_TAG $(OPENLAN_RUN_TAG) \
-verbose 1 \
-overwrite"
openlane_cmd_interactive = "flow.tcl -it -file $$(realpath ./$*/interactive.tcl)"
openlane_cmd_interactive = "flow.tcl -ignore_mismatches -it -file $$(realpath ./$*/$(IT_SCRIPT))"
openlane_cmd_regression = "cd /openlane && ./run_designs.py \
--regression $$(realpath ./$*/regression.config) \
--threads 6 \
$$(realpath ./$*)"
docker_mounts = \
-v $$(realpath $(PWD)/..):$$(realpath $(PWD)/..) \
@ -45,6 +51,12 @@ docker_env = \
-e OPENLANE_RUN_TAG=$(OPENLANE_RUN_TAG) \
-w $(PWD)
ifneq ($(OPENLANE_ROOT),)
$(info openlane $(OPENLANE_ROOT))
docker_mounts += -v $(OPENLANE_ROOT):/openlane
docker_mounts += -v $(OPENLANE_ROOT):/openLANE_flow
endif
ifneq ($(MCW_ROOT),)
docker_env += -e MCW_ROOT=$(MCW_ROOT)
docker_mounts += -v $(MCW_ROOT):$(MCW_ROOT)
@ -60,6 +72,13 @@ docker_run = \
list:
@echo $(designs)
regression-designs=$(designs:%=%-regression)
.PHONY: $(regression-designs)
$(regression-designs): %-regression: ./%/regression.config
$(docker_run) \
$(OPENLANE_IMAGE_NAME) sh -c $(openlane_cmd_regression)
.PHONY: $(designs)
$(designs) : % : ./%/config.tcl
ifneq (,$(wildcard ./$(MAKECMDGOALS)/interactive.tcl)))

BIN
openlane/caravel/caravel_power_routing-shifted.gds Normal file
View File

Binary file not shown.

5347
openlane/caravel/caravel_power_routing-shifted.lef Normal file
View File

File diff suppressed because it is too large Load Diff

50
openlane/caravel/config.tcl
View File

@ -14,15 +14,15 @@
# SPDX-License-Identifier: Apache-2.0
# User config
set script_dir [file dirname [file normalize [info script]]]
set ::env(DESIGN_NAME) caravel
set ::env(ROUTING_CORES) 50
set ::env(STD_CELL_LIBRARY_OPT) "sky130_fd_sc_hd"
set verilog_root $script_dir/../../verilog/
set lef_root $script_dir/../../lef/
set gds_root $script_dir/../../gds/
set verilog_root $::env(CARAVEL_ROOT)/verilog/
set lef_root $::env(CARAVEL_ROOT)/lef/
set gds_root $::env(CARAVEL_ROOT)/gds/
set mgmt_area_verilog_root $::env(MCW_ROOT)/verilog/
set mgmt_area_lef_root $::env(MCW_ROOT)/lef/
@ -50,10 +50,12 @@ set ::env(VERILOG_FILES_BLACKBOX) "\
$verilog_root/rtl/simple_por.v\
$verilog_root/rtl/spare_logic_block.v\
$verilog_root/rtl/xres_buf.v \
$verilog_root/rtl/caravel_power_routing.v \
$mgmt_area_verilog_root/rtl/mgmt_core_wrapper.v \
"
set ::env(EXTRA_LEFS) "\
$::env(DESIGN_DIR)/caravel_power_routing-shifted.lef \
$lef_root/chip_io.lef \
$lef_root/user_project_wrapper.lef \
$lef_root/mgmt_protect.lef \
@ -70,12 +72,11 @@ set ::env(EXTRA_LEFS) "\
"
set ::env(EXTRA_GDS_FILES) "\
$::env(DESIGN_DIR)/caravel_power_routing-shifted.gds \
$gds_root/chip_io.gds \
$gds_root/user_project_wrapper.gds \
$gds_root/mgmt_protect.gds \
$gds_root/gpio_control_block.gds \
$gds_root/gpio_defaults_block.gds \
$gds_root/user_id_programming.gds \
$gds_root/housekeeping.gds \
$gds_root/digital_pll.gds \
$gds_root/caravel_clocking.gds \
@ -97,7 +98,7 @@ set ::env(LEC_ENABLE) 0
set ::env(FP_SIZING) absolute
set fd [open "$script_dir/../chip_dimensions.txt" "r"]
set fd [open "$::env(DESIGN_DIR)/../chip_dimensions.txt" "r"]
set ::env(DIE_AREA) [read $fd]
close $fd
@ -109,21 +110,16 @@ set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(DIODE_INSERTION_STRATEGY) 0
set ::env(GLB_RT_ALLOW_CONGESTION) 1
set ::env(GLB_RT_OVERFLOW_ITERS) 50
set ::env(GLB_RT_TILES) 30
set ::env(GLB_RT_MINLAYER) 2
set ::env(GLB_RT_MAXLAYER) 6
#set ::env(RT_MIN_LAYER) met1
#set ::env(RT_MAX_LAYER) met5
set ::env(GLB_RT_ADJUSTMENT) "0"
set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
set ::env(GLB_RT_L2_ADJUSTMENT) "0.1"
set ::env(GLB_RT_L3_ADJUSTMENT) "0.15"
set ::env(GLB_RT_L4_ADJUSTMENT) "0.15"
set ::env(GLB_RT_L5_ADJUSTMENT) "0.15"
set ::env(GLB_RT_L6_ADJUSTMENT) "0"
#set ::env(GLB_RT_ADJUSTMENT) "0"
#set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
#set ::env(GLB_RT_L2_ADJUSTMENT) "0.1"
#set ::env(GLB_RT_L3_ADJUSTMENT) "0.15"
#set ::env(GLB_RT_L4_ADJUSTMENT) "0.15"
#set ::env(GLB_RT_L5_ADJUSTMENT) "0.15"
#set ::env(GLB_RT_L6_ADJUSTMENT) "0"
#set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
#set ::env(GLB_RT_L2_ADJUSTMENT) "0"
#set ::env(GLB_RT_L3_ADJUSTMENT) "0"
@ -138,7 +134,7 @@ set ::env(GLB_RT_L6_ADJUSTMENT) "0"
#set ::env(GLB_RT_L6_ADJUSTMENT) "0"
# set ::env(ROUTING_OPT_ITERS) 7
# set ::env(GLB_RT_UNIDIRECTIONAL) 0
set ::env(GLB_RT_UNIDIRECTIONAL) 0
set ::env(FILL_INSERTION) 0
@ -151,5 +147,17 @@ set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0
set ::env(QUIT_ON_TR_DRC) 0
set ::env(QUIT_ON_LVS_ERROR) 0
#set ::env(TRACKS_INFO_FILE) $script_dir/tracks.info
#set ::env(TRACKS_INFO_FILE) $::env(DESIGN_DIR)/tracks.info
#
set ::env(ROUTING_OPT_ITERS) 100
set ::env(TECH_LEF) $::env(DESIGN_DIR)/sky130_fd_sc_hd.tlef
set ::env(GLB_RT_ADJUSTMENT) "0"
set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
set ::env(GLB_RT_L2_ADJUSTMENT) "0.2"
set ::env(GLB_RT_L3_ADJUSTMENT) "0.45"
set ::env(GLB_RT_L4_ADJUSTMENT) "0.45"
set ::env(GLB_RT_L5_ADJUSTMENT) "0.45"
set ::env(GLB_RT_L6_ADJUSTMENT) "0"

265
openlane/caravel/interactive-old.tcl Normal file
View File

@ -0,0 +1,265 @@
# SPDX-FileCopyrightText: 2020 Efabless Corporation
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
# SPDX-License-Identifier: Apache-2.0
package require openlane
set script_dir [file dirname [file normalize [info script]]]
set save_path $::env(CARAVEL_ROOT)
# FOR LVS AND CREATING PORT LABELS
# ACTUAL CHIP INTEGRATION
variable SCRIPT_DIR [file dirname [file normalize [info script]]]
prep -design $SCRIPT_DIR -tag caravel_lvs -overwrite --verbose 2
set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
verilog_elaborate
file copy -force $::env(CURRENT_NETLIST) $::env(TMP_DIR)/lvs.v
prep -ignore_mismatches -design $SCRIPT_DIR -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 2
set ::env(GLB_RT_ALLOW_CONGESTION) 1
set ::env(GLB_RT_OVERFLOW_ITERS) 50
set ::env(GLB_RT_TILES) 30
set ::env(GLB_RT_MINLAYER) 2
set ::env(GLB_RT_MAXLAYER) 6
exec rm -rf $SCRIPT_DIR/runs/caravel
exec ln -sf $SCRIPT_DIR/runs/$::env(OPENLANE_RUN_TAG) $SCRIPT_DIR/runs/caravel
file copy -force $::env(CARAVEL_ROOT)/openlane/caravel/runs/caravel_lvs/tmp/lvs.v $::env(RUN_DIR)/caravel.v
set ::env(SYNTH_DEFINES) "TOP_ROUTING"
verilog_elaborate
#logic_equiv_check -lhs $top_rtl -rhs $::env(yosys_result_file_tag).v
init_floorplan
#set ::env(GLB_RT_ADJUSTMENT) "0"
#set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
#set ::env(GLB_RT_L2_ADJUSTMENT) "0.1"
#set ::env(GLB_RT_L3_ADJUSTMENT) "0.3"
#set ::env(GLB_RT_L4_ADJUSTMENT) "0.3"
#set ::env(GLB_RT_L5_ADJUSTMENT) "0.3"
#set ::env(GLB_RT_L6_ADJUSTMENT) "0"
set mprj_x 326.540
set mprj_y 1393.590
set soc_x 260.170
set soc_y 265.010
add_macro_placement caravel_power_routing 30.11 169.5 N
add_macro_placement padframe 0 0 N
add_macro_placement soc $soc_x $soc_y N
add_macro_placement housekeeping 2962.17 500.010 N
add_macro_placement mprj $mprj_x $mprj_y N
add_macro_placement mgmt_buffers 640.900 1160.180 N
# add_macro_placement mgmt_buffers 1060.850 1234.090 N
add_macro_placement rstb_level 708.550 235.440 S
add_macro_placement user_id_value 3283.120 440.630 N
add_macro_placement por 3250.730 234.721 MX
add_macro_placement pll 3140.730 404.721 N
add_macro_placement spare_logic\\\[0\\\] 443.16 1162.64 N
add_macro_placement spare_logic\\\[1\\\] 446.75500 1243.36700 N
add_macro_placement spare_logic\\\[2\\\] 2875.72600 1234.93300 N
add_macro_placement spare_logic\\\[3\\\] 3067.79200 1229.28000 N
add_macro_placement clock_ctrl 3133.820 316.420 N
#add_macro_placement clocking 1028.730 27.440 N
# west
set west_x 38.155
add_macro_placement "gpio_control_bidir_2\\\[2\\\]" $west_x 1013.000 R0
add_macro_placement "gpio_defaults_block_37" [expr $west_x + 3.6815559] [expr 1013.000 + 65] R0
add_macro_placement "gpio_control_bidir_2\\\[1\\\]" $west_x 1229.000 R0
add_macro_placement "gpio_defaults_block_36" [expr $west_x + 3.6815559] [expr 1229.000 + 65] R0
add_macro_placement "gpio_control_bidir_2\\\[0\\\]" $west_x 1445.000 R0
add_macro_placement "gpio_defaults_block_35" [expr $west_x + 3.6815559] [expr 1445.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[15\\\]" $west_x 1661.000 R0
add_macro_placement "gpio_defaults_block_34" [expr $west_x + 3.6815559] [expr 1661.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[14\\\]" $west_x 1877.000 R0
add_macro_placement "gpio_defaults_block_33" [expr $west_x + 3.6815559] [expr 1877.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[13\\\]" $west_x 2093.000 R0
add_macro_placement "gpio_defaults_block_32" [expr $west_x + 3.6815559] [expr 2093.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[12\\\]" $west_x 2731.000 R0
add_macro_placement "gpio_defaults_block_31" [expr $west_x + 3.6815559] [expr 2731.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[11\\\]" $west_x 2947.000 R0
add_macro_placement "gpio_defaults_block_30" [expr $west_x + 3.6815559] [expr 2947.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[10\\\]" $west_x 3163.000 R0
add_macro_placement "gpio_defaults_block_29" [expr $west_x + 3.6815559] [expr 3163.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[9\\\]" $west_x 3379.000 R0
add_macro_placement "gpio_defaults_block_28" [expr $west_x + 3.6815559] [expr 3379.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[8\\\]" $west_x 3595.000 R0
add_macro_placement "gpio_defaults_block_27" [expr $west_x + 3.6815559] [expr 3595.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[7\\\]" $west_x 3811.000 R0
add_macro_placement "gpio_defaults_block_26" [expr $west_x + 3.6815559] [expr 3811.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[6\\\]" $west_x 4027.000 R0
add_macro_placement "gpio_defaults_block_25" [expr $west_x + 3.6815559] [expr 4027.000 + 65] R0
add_macro_placement "gpio_control_in_2\\\[5\\\]" $west_x 4656.000 R0
add_macro_placement "gpio_defaults_block_24" [expr $west_x + 3.6815559] [expr 4656.000 + 65] R0
# north
set north_y 4980.385
add_macro_placement "gpio_control_in_2\\\[4\\\]" 486.000 $north_y R270
add_macro_placement "gpio_defaults_block_23" [expr 486.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_2\\\[3\\\]" 743.000 $north_y R270
add_macro_placement "gpio_defaults_block_22" [expr 743.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_2\\\[2\\\]" 1000.000 $north_y R270
add_macro_placement "gpio_defaults_block_21" [expr 1000.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_2\\\[1\\\]" 1257.000 $north_y R270
add_macro_placement "gpio_defaults_block_20" [expr 1257.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_2\\\[0\\\]" 1515.000 $north_y R270
add_macro_placement "gpio_defaults_block_19" [expr 1515.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_1\\\[10\\\]" 1767.000 $north_y R270
add_macro_placement "gpio_defaults_block_18" [expr 1767.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_1\\\[9\\\]" 2104.000 $north_y R270
add_macro_placement "gpio_defaults_block_17" [expr 2104.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_1\\\[8\\\]" 2489.000 $north_y R270
add_macro_placement "gpio_defaults_block_16" [expr 2489.00 + 64.968717] [expr $north_y + 136.3215974] R270
add_macro_placement "gpio_control_in_1\\\[7\\\]" 2746.000 $north_y R270
add_macro_placement "gpio_defaults_block_15" [expr 2746.00 + 64.968717] [expr $north_y + 136.3215974] R270
# east
set east_x 3381.015
add_macro_placement "gpio_defaults_block_0" [expr $east_x+136.320042674] 670.000 FN
add_macro_placement "gpio_control_bidir_1\\\[0\\\]" $east_x 605.000 MY
add_macro_placement "gpio_defaults_block_1" [expr $east_x+136.320042674] 896.000 FN
add_macro_placement "gpio_control_bidir_1\\\[1\\\]" $east_x 831.000 MY
add_macro_placement "gpio_defaults_block_2" [expr $east_x+136.320042674] 1121.000 FN
add_macro_placement "gpio_control_in_1a\\\[0\\\]" $east_x 1056.000 MY
add_macro_placement "gpio_defaults_block_3" [expr $east_x+136.320042674] 1347.000 FN
add_macro_placement "gpio_control_in_1a\\\[1\\\]" $east_x 1282.000 MY
add_macro_placement "gpio_defaults_block_4" [expr $east_x+136.320042674] 1572.000 FN
add_macro_placement "gpio_control_in_1a\\\[2\\\]" $east_x 1507.000 MY
add_macro_placement "gpio_defaults_block_5" [expr $east_x+136.320042674] 1797.000 FN
add_macro_placement "gpio_control_in_1a\\\[3\\\]" $east_x 1732.000 MY
add_macro_placement "gpio_defaults_block_6" [expr $east_x+136.320042674] 2023.000 FN
add_macro_placement "gpio_control_in_1a\\\[4\\\]" $east_x 1958.000 MY
add_macro_placement "gpio_defaults_block_7" [expr $east_x+136.320042674] 2464.000 FN
add_macro_placement "gpio_control_in_1a\\\[5\\\]" $east_x 2399.000 MY
add_macro_placement "gpio_defaults_block_8" [expr $east_x+136.320042674] 2684.000 FN
add_macro_placement "gpio_control_in_1\\\[0\\\]" $east_x 2619.000 MY
add_macro_placement "gpio_defaults_block_9" [expr $east_x+136.320042674] 2909.000 FN
add_macro_placement "gpio_control_in_1\\\[1\\\]" $east_x 2844.000 MY
add_macro_placement "gpio_defaults_block_10" [expr $east_x+136.320042674] 3135.000 FN
add_macro_placement "gpio_control_in_1\\\[2\\\]" $east_x 3070.000 MY
add_macro_placement "gpio_defaults_block_11" [expr $east_x+136.320042674] [expr 3295.000+65] FN
add_macro_placement "gpio_control_in_1\\\[3\\\]" $east_x 3295.000 MY
add_macro_placement "gpio_defaults_block_12" [expr $east_x+136.320042674] [expr 3521.000+65] FN
add_macro_placement "gpio_control_in_1\\\[4\\\]" $east_x 3521.000 MY
add_macro_placement "gpio_defaults_block_13" [expr $east_x+136.320042674] [expr 3746.000+65] FN
add_macro_placement "gpio_control_in_1\\\[5\\\]" $east_x 3746.000 MY
add_macro_placement "gpio_defaults_block_14" [expr $east_x+136.320042674] [expr 4638.000+65] FN
add_macro_placement "gpio_control_in_1\\\[6\\\]" $east_x 4638.000 MY
manual_macro_placement f
# modify to a different file
remove_pins -input $::env(CURRENT_DEF)
remove_empty_nets -input $::env(CURRENT_DEF)
# add routing obstruction around the user_project_wrapper to prevent
# having shorts with the core ring or signal routing inside the wrapper
set gap 0.4
set user_project_wrapper_obs [list [expr $mprj_x-$gap] [expr $mprj_y-$gap] [expr $mprj_x+$gap+2920] [expr $mprj_y+$gap+3520]]
set user_project_wrapper_core_ring_obs [list [expr $mprj_x-43.63] [expr $mprj_y-38.34] [expr $mprj_x+2963.25] [expr $mprj_y+$gap+3557.96]]
# add routing obstructions on the management area
set mgmt_area_obs [list $soc_x $soc_y [expr $soc_x+2620] [expr $soc_y+820]]
set routing_vio_obs [list 106.26803 2098.54857 108.85254 2096.63000]
set ::env(GLB_RT_OBS) "
met1 $user_project_wrapper_obs,\
met2 $user_project_wrapper_obs,\
met3 $user_project_wrapper_obs,\
met4 $user_project_wrapper_core_ring_obs,\
met4 $mgmt_area_obs,\
met5 $user_project_wrapper_core_ring_obs,\
met5 $mgmt_area_obs"
try_catch openroad -python $::env(SCRIPTS_DIR)/add_def_obstructions.py \
--input-def $::env(CURRENT_DEF) \
--lef $::env(MERGED_LEF) \
--obstructions $::env(GLB_RT_OBS) \
--output [file rootname $::env(CURRENT_DEF)].obs.def |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/obs.log
set_def [file rootname $::env(CURRENT_DEF)].obs.def
# add_macro_obs \
# -defFile $::env(CURRENT_DEF) \
# -lefFile $::env(MERGED_LEF_UNPADDED) \
# -obstruction vddio_obs \
# -placementX 103.400 \
# -placementY 607.150 \
# -sizeWidth 94.500 \
# -sizeHeight 30 \
# -fixed 1 \
# -layerNames "met2 met4"
# add_macro_obs \
# -defFile $::env(CURRENT_DEF) \
# -lefFile $::env(MERGED_LEF_UNPADDED) \
# -obstruction vddio_pad_obs \
# -placementX 33.375 \
# -placementY 557.100 \
# -sizeWidth 62.615 \
# -sizeHeight 62.700 \
# -fixed 1 \
# -layerNames "li1 met1 met2 met3 met4 met5"
li1_hack_start
global_routing
detailed_routing
li1_hack_end
remove_component -input $::env(CURRENT_DEF) -instance_name obs_li1
run_magic
save_views -def_path $::env(CURRENT_DEF) \
-gds_path $::env(magic_result_file_tag).gds \
-mag_path $::env(magic_result_file_tag).mag \
-verilog_path $::env(RUN_DIR)/caravel.v \
-save_path $save_path \
-tag caravel
exit
label_macro_pins\
-lef $::env(TMP_DIR)/lvs.lef\
-netlist_def $::env(TMP_DIR)/lvs.def
# -extra_args {-v\
# --map padframe vddio vddio INOUT\
# --map padframe vssio vssio INOUT\
# --map padframe vssa vssa INOUT\
# --map padframe vccd vccd INOUT\
# --map padframe vssd vssd INOUT}
run_magic
run_magic_spice_export
save_views -lef_path $::env(magic_result_file_tag).lef \
-def_path $::env(tritonRoute_result_file_tag).def \
-gds_path $::env(magic_result_file_tag).gds \
-mag_path $::env(magic_result_file_tag).mag \
-verilog_path $::env(TMP_DIR)/lvs.v \
-spice_path $::env(magic_result_file_tag).spice \
-save_path $save_path \
-tag $::env(RUN_TAG)
run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v

788
openlane/caravel/sky130_fd_sc_hd.tlef Normal file
View File

@ -0,0 +1,788 @@
# Copyright 2020 The SkyWater PDK Authors
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# https://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# SPDX-License-Identifier: Apache-2.0
VERSION 5.7 ;
BUSBITCHARS "[]" ;
DIVIDERCHAR "/" ;
UNITS
TIME NANOSECONDS 1 ;
CAPACITANCE PICOFARADS 1 ;
RESISTANCE OHMS 1 ;
DATABASE MICRONS 1000 ;
END UNITS
MANUFACTURINGGRID 0.005 ;
USEMINSPACING OBS OFF ;
PROPERTYDEFINITIONS
LAYER LEF58_TYPE STRING ;
END PROPERTYDEFINITIONS
# High density, single height
SITE unithd
SYMMETRY Y ;
CLASS CORE ;
SIZE 0.46 BY 2.72 ;
END unithd
# High density, double height
SITE unithddbl
SYMMETRY Y ;
CLASS CORE ;
SIZE 0.46 BY 5.44 ;
END unithddbl
LAYER nwell
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE NWELL ;" ;
END nwell
LAYER pwell
TYPE MASTERSLICE ;
PROPERTY LEF58_TYPE "TYPE PWELL ;" ;
END pwell
LAYER li1
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.46 0.34 ;
OFFSET 0.23 0.17 ;
WIDTH 0.17 ; # LI 1
# SPACING 0.17 ; # LI 2
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.17 ;
AREA 0.0561 ; # LI 6
THICKNESS 0.1 ;
EDGECAPACITANCE 40.697E-6 ;
CAPACITANCE CPERSQDIST 36.9866E-6 ;
RESISTANCE RPERSQ 12.2 ;
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 75 ) ( 0.0125 75 ) ( 0.0225 85.125 ) ( 22.5 10200 ) ) ;
END li1
LAYER mcon
TYPE CUT ;
WIDTH 0.17 ; # Mcon 1
SPACING 0.19 ; # Mcon 2
ENCLOSURE BELOW 0 0 ; # Mcon 4
ENCLOSURE ABOVE 0.03 0.06 ; # Met1 4 / Met1 5
ANTENNADIFFAREARATIO PWL ( ( 0 3 ) ( 0.0125 3 ) ( 0.0225 3.405 ) ( 22.5 408 ) ) ;
DCCURRENTDENSITY AVERAGE 0.36 ; # mA per via Iavg_max at Tj = 90oC
END mcon
LAYER met1
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.34 ;
OFFSET 0.17 ;
WIDTH 0.14 ; # Met1 1
# SPACING 0.14 ; # Met1 2
# SPACING 0.28 RANGE 3.001 100 ; # Met1 3b
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.28 ;
AREA 0.083 ; # Met1 6
THICKNESS 0.35 ;
MINENCLOSEDAREA 0.14 ;
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
EDGECAPACITANCE 40.567E-6 ;
CAPACITANCE CPERSQDIST 25.7784E-6 ;
DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 700 700 ;
DENSITYCHECKSTEP 70 ;
RESISTANCE RPERSQ 0.125 ;
END met1
LAYER via
TYPE CUT ;
WIDTH 0.15 ; # Via 1a
SPACING 0.17 ; # Via 2
ENCLOSURE BELOW 0.055 0.085 ; # Via 4a / Via 5a
ENCLOSURE ABOVE 0.055 0.085 ; # Met2 4 / Met2 5
ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
DCCURRENTDENSITY AVERAGE 0.29 ; # mA per via Iavg_max at Tj = 90oC
END via
LAYER met2
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.46 ;
OFFSET 0.23 ;
WIDTH 0.14 ; # Met2 1
# SPACING 0.14 ; # Met2 2
# SPACING 0.28 RANGE 3.001 100 ; # Met2 3b
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.28 ;
AREA 0.0676 ; # Met2 6
THICKNESS 0.35 ;
MINENCLOSEDAREA 0.14 ;
EDGECAPACITANCE 37.759E-6 ;
CAPACITANCE CPERSQDIST 16.9423E-6 ;
RESISTANCE RPERSQ 0.125 ;
DCCURRENTDENSITY AVERAGE 2.8 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 6.1 ; # mA/um Irms_max at Tj = 90oC
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 700 700 ;
DENSITYCHECKSTEP 70 ;
END met2
# ******** Layer via2, type routing, number 44 **************
LAYER via2
TYPE CUT ;
WIDTH 0.2 ; # Via2 1
SPACING 0.2 ; # Via2 2
ENCLOSURE BELOW 0.04 0.085 ; # Via2 4
ENCLOSURE ABOVE 0.065 0.065 ; # Met3 4
ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
END via2
LAYER met3
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 0.68 ;
OFFSET 0.34 ;
WIDTH 0.3 ; # Met3 1
# SPACING 0.3 ; # Met3 2
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.4 ;
AREA 0.24 ; # Met3 6
THICKNESS 0.8 ;
EDGECAPACITANCE 40.989E-6 ;
CAPACITANCE CPERSQDIST 12.3729E-6 ;
RESISTANCE RPERSQ 0.047 ;
DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 700 700 ;
DENSITYCHECKSTEP 70 ;
END met3
LAYER via3
TYPE CUT ;
WIDTH 0.2 ; # Via3 1
SPACING 0.2 ; # Via3 2
ENCLOSURE BELOW 0.06 0.09 ; # Via3 4 / Via3 5
ENCLOSURE ABOVE 0.065 0.065 ; # Met4 3
ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
DCCURRENTDENSITY AVERAGE 0.48 ; # mA per via Iavg_max at Tj = 90oC
END via3
LAYER met4
TYPE ROUTING ;
DIRECTION VERTICAL ;
PITCH 0.92 ;
OFFSET 0.46 ;
WIDTH 0.3 ; # Met4 1
# SPACING 0.3 ; # Met4 2
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 0.4 ;
AREA 0.24 ; # Met4 4a
THICKNESS 0.8 ;
EDGECAPACITANCE 36.676E-6 ;
CAPACITANCE CPERSQDIST 8.41537E-6 ;
RESISTANCE RPERSQ 0.047 ;
DCCURRENTDENSITY AVERAGE 6.8 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 14.9 ; # mA/um Irms_max at Tj = 90oC
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
MAXIMUMDENSITY 70 ;
DENSITYCHECKWINDOW 700 700 ;
DENSITYCHECKSTEP 70 ;
END met4
LAYER via4
TYPE CUT ;
WIDTH 0.8 ; # Via4 1
SPACING 0.8 ; # Via4 2
ENCLOSURE BELOW 0.19 0.19 ; # Via4 4
ENCLOSURE ABOVE 0.31 0.31 ; # Met5 3
ANTENNADIFFAREARATIO PWL ( ( 0 6 ) ( 0.0125 6 ) ( 0.0225 6.81 ) ( 22.5 816 ) ) ;
DCCURRENTDENSITY AVERAGE 2.49 ; # mA per via Iavg_max at Tj = 90oC
END via4
LAYER met5
TYPE ROUTING ;
DIRECTION HORIZONTAL ;
PITCH 3.4 ;
OFFSET 1.7 ;
WIDTH 1.6 ; # Met5 1
#SPACING 1.6 ; # Met5 2
SPACINGTABLE
PARALLELRUNLENGTH 0
WIDTH 0 1.6 ;
AREA 4 ; # Met5 4
THICKNESS 1.2 ;
EDGECAPACITANCE 38.851E-6 ;
CAPACITANCE CPERSQDIST 6.32063E-6 ;
RESISTANCE RPERSQ 0.0285 ;
DCCURRENTDENSITY AVERAGE 10.17 ; # mA/um Iavg_max at Tj = 90oC
ACCURRENTDENSITY RMS 22.34 ; # mA/um Irms_max at Tj = 90oC
ANTENNAMODEL OXIDE1 ;
ANTENNADIFFSIDEAREARATIO PWL ( ( 0 400 ) ( 0.0125 400 ) ( 0.0225 2609 ) ( 22.5 11600 ) ) ;
END met5
### Routing via cells section ###
# Plus via rule, metals are along the prefered direction
VIA L1M1_PR DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.145 -0.115 0.145 0.115 ;
END L1M1_PR
VIARULE L1M1_PR GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.06 0.03 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR
# Plus via rule, metals are along the non prefered direction
VIA L1M1_PR_R DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.115 -0.145 0.115 0.145 ;
END L1M1_PR_R
VIARULE L1M1_PR_R GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.03 0.06 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA L1M1_PR_M DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.115 -0.145 0.115 0.145 ;
END L1M1_PR_M
VIARULE L1M1_PR_M GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.03 0.06 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA L1M1_PR_MR DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.145 -0.115 0.145 0.115 ;
END L1M1_PR_MR
VIARULE L1M1_PR_MR GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.06 0.03 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR_MR
# Centered via rule, we really do not want to use it
VIA L1M1_PR_C DEFAULT
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER li1 ;
RECT -0.085 -0.085 0.085 0.085 ;
LAYER met1 ;
RECT -0.145 -0.145 0.145 0.145 ;
END L1M1_PR_C
VIARULE L1M1_PR_C GENERATE
LAYER li1 ;
ENCLOSURE 0 0 ;
LAYER met1 ;
ENCLOSURE 0.06 0.06 ;
LAYER mcon ;
RECT -0.085 -0.085 0.085 0.085 ;
SPACING 0.36 BY 0.36 ;
END L1M1_PR_C
# Plus via rule, metals are along the prefered direction
VIA M1M2_PR DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.16 -0.13 0.16 0.13 ;
LAYER met2 ;
RECT -0.13 -0.16 0.13 0.16 ;
END M1M2_PR
VIARULE M1M2_PR GENERATE
LAYER met1 ;
ENCLOSURE 0.085 0.055 ;
LAYER met2 ;
ENCLOSURE 0.055 0.085 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR
# Plus via rule, metals are along the non prefered direction
VIA M1M2_PR_R DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.13 -0.16 0.13 0.16 ;
LAYER met2 ;
RECT -0.16 -0.13 0.16 0.13 ;
END M1M2_PR_R
VIARULE M1M2_PR_R GENERATE
LAYER met1 ;
ENCLOSURE 0.055 0.085 ;
LAYER met2 ;
ENCLOSURE 0.085 0.055 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA M1M2_PR_M DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.16 -0.13 0.16 0.13 ;
LAYER met2 ;
RECT -0.16 -0.13 0.16 0.13 ;
END M1M2_PR_M
VIARULE M1M2_PR_M GENERATE
LAYER met1 ;
ENCLOSURE 0.085 0.055 ;
LAYER met2 ;
ENCLOSURE 0.085 0.055 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA M1M2_PR_MR DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.13 -0.16 0.13 0.16 ;
LAYER met2 ;
RECT -0.13 -0.16 0.13 0.16 ;
END M1M2_PR_MR
VIARULE M1M2_PR_MR GENERATE
LAYER met1 ;
ENCLOSURE 0.055 0.085 ;
LAYER met2 ;
ENCLOSURE 0.055 0.085 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR_MR
# Centered via rule, we really do not want to use it
VIA M1M2_PR_C DEFAULT
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
LAYER met1 ;
RECT -0.16 -0.16 0.16 0.16 ;
LAYER met2 ;
RECT -0.16 -0.16 0.16 0.16 ;
END M1M2_PR_C
VIARULE M1M2_PR_C GENERATE
LAYER met1 ;
ENCLOSURE 0.085 0.085 ;
LAYER met2 ;
ENCLOSURE 0.085 0.085 ;
LAYER via ;
RECT -0.075 -0.075 0.075 0.075 ;
SPACING 0.32 BY 0.32 ;
END M1M2_PR_C
# Plus via rule, metals are along the prefered direction
VIA M2M3_PR DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.14 -0.185 0.14 0.185 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR
VIARULE M2M3_PR GENERATE
LAYER met2 ;
ENCLOSURE 0.04 0.085 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR
# Plus via rule, metals are along the non prefered direction
VIA M2M3_PR_R DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.185 -0.14 0.185 0.14 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_R
VIARULE M2M3_PR_R GENERATE
LAYER met2 ;
ENCLOSURE 0.085 0.04 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA M2M3_PR_M DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.14 -0.185 0.14 0.185 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_M
VIARULE M2M3_PR_M GENERATE
LAYER met2 ;
ENCLOSURE 0.04 0.085 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA M2M3_PR_MR DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.185 -0.14 0.185 0.14 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_MR
VIARULE M2M3_PR_MR GENERATE
LAYER met2 ;
ENCLOSURE 0.085 0.04 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR_MR
# Centered via rule, we really do not want to use it
VIA M2M3_PR_C DEFAULT
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met2 ;
RECT -0.185 -0.185 0.185 0.185 ;
LAYER met3 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M2M3_PR_C
VIARULE M2M3_PR_C GENERATE
LAYER met2 ;
ENCLOSURE 0.085 0.085 ;
LAYER met3 ;
ENCLOSURE 0.065 0.065 ;
LAYER via2 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M2M3_PR_C
# Plus via rule, metals are along the prefered direction
VIA M3M4_PR DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.19 -0.16 0.19 0.16 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR
VIARULE M3M4_PR GENERATE
LAYER met3 ;
ENCLOSURE 0.09 0.06 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR
# Plus via rule, metals are along the non prefered direction
VIA M3M4_PR_R DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.16 -0.19 0.16 0.19 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_R
VIARULE M3M4_PR_R GENERATE
LAYER met3 ;
ENCLOSURE 0.06 0.09 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA M3M4_PR_M DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.19 -0.16 0.19 0.16 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_M
VIARULE M3M4_PR_M GENERATE
LAYER met3 ;
ENCLOSURE 0.09 0.06 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA M3M4_PR_MR DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.16 -0.19 0.16 0.19 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_MR
VIARULE M3M4_PR_MR GENERATE
LAYER met3 ;
ENCLOSURE 0.06 0.09 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR_MR
# Centered via rule, we really do not want to use it
VIA M3M4_PR_C DEFAULT
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
LAYER met3 ;
RECT -0.19 -0.19 0.19 0.19 ;
LAYER met4 ;
RECT -0.165 -0.165 0.165 0.165 ;
END M3M4_PR_C
VIARULE M3M4_PR_C GENERATE
LAYER met3 ;
ENCLOSURE 0.09 0.09 ;
LAYER met4 ;
ENCLOSURE 0.065 0.065 ;
LAYER via3 ;
RECT -0.1 -0.1 0.1 0.1 ;
SPACING 0.4 BY 0.4 ;
END M3M4_PR_C
# Plus via rule, metals are along the prefered direction
VIA M4M5_PR DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR
VIARULE M4M5_PR GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR
# Plus via rule, metals are along the non prefered direction
VIA M4M5_PR_R DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_R
VIARULE M4M5_PR_R GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR_R
# Minus via rule, lower layer metal is along prefered direction
VIA M4M5_PR_M DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_M
VIARULE M4M5_PR_M GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR_M
# Minus via rule, upper layer metal is along prefered direction
VIA M4M5_PR_MR DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_MR
VIARULE M4M5_PR_MR GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR_MR
# Centered via rule, we really do not want to use it
VIA M4M5_PR_C DEFAULT
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
LAYER met4 ;
RECT -0.59 -0.59 0.59 0.59 ;
LAYER met5 ;
RECT -0.71 -0.71 0.71 0.71 ;
END M4M5_PR_C
VIARULE M4M5_PR_C GENERATE
LAYER met4 ;
ENCLOSURE 0.19 0.19 ;
LAYER met5 ;
ENCLOSURE 0.31 0.31 ;
LAYER via4 ;
RECT -0.4 -0.4 0.4 0.4 ;
SPACING 1.6 BY 1.6 ;
END M4M5_PR_C
### end of single via cells ###
END LIBRARY

1
signoff/caravel/OPENLANE_VERSION Normal file
View File

@ -0,0 +1 @@
openlane v0.22

6
signoff/caravel/PDK_SOURCES Normal file
View File

@ -0,0 +1,6 @@
-ne openlane
02c16938aea3770c1d2e03fc8beed763fa83f30f
-ne skywater-pdk
ea95157faad3a3f5c560aaec3f1841ee5a2aa2db
-ne open_pdks
1d93a6bd9d6e481acfdf88f26aa3bb0600303d98

94964
spef/multicorner/caravel.max.spef Normal file
View File

File diff suppressed because it is too large Load Diff

83450
spef/multicorner/caravel.min.spef Normal file
View File

File diff suppressed because it is too large Load Diff

87818
spef/multicorner/caravel.nom.spef Normal file
View File

File diff suppressed because it is too large Load Diff

772
verilog/gl/caravel.v
View File

File diff suppressed because it is too large Load Diff

2
verilog/rtl/caravel_power_routing.v Normal file
View File

@ -0,0 +1,2 @@
module caravel_power_routing ();
endmodule