mirror of https://github.com/efabless/caravel.git
openlane!: reharden gpio_control_block
update gpio_control_block config for new openlane versions: - disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size and fit the floorplan - change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells - disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and enable `GLB_RESIZER_TIMING_OPTIMIZATIONS` - remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement - set `DECAP_CELL` to not use ef decaps.. i think that was for simulations? - enable some turned off `QUIT_*` variables - replace deprecated variables such as `GLB_RT_*` - customize `pdn.tcl` to force pdn straps to follow the old pattern - replace `$script_dir` with `$::env(DESIGN_DIR)` !IMPORTANT - still need to run dynamic simulations
This commit is contained in:
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commit
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Load Diff
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@ -348,7 +348,7 @@ MACRO gpio_control_block
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USE POWER ;
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PORT
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LAYER met4 ;
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RECT 12.800 26.400 14.400 57.360 ;
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RECT 12.800 5.200 14.400 57.360 ;
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END
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PORT
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LAYER met4 ;
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@ -356,11 +356,15 @@ MACRO gpio_control_block
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END
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PORT
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LAYER met5 ;
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RECT 4.360 6.140 49.460 7.740 ;
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RECT 4.360 5.900 49.460 7.500 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 39.940 49.460 41.540 ;
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RECT 4.360 22.800 49.460 24.400 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 39.700 49.460 41.300 ;
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END
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END vccd
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PIN vccd1
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@ -368,11 +372,23 @@ MACRO gpio_control_block
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USE POWER ;
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PORT
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LAYER met4 ;
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RECT 25.300 5.200 26.900 57.360 ;
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RECT 17.800 5.200 19.400 57.360 ;
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END
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PORT
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LAYER met4 ;
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RECT 42.800 5.200 44.400 57.360 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 14.590 49.460 16.190 ;
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RECT 4.360 11.140 49.460 12.740 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 28.040 49.460 29.640 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 44.940 49.460 46.540 ;
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END
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END vccd1
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PIN vssd
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@ -380,23 +396,19 @@ MACRO gpio_control_block
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USE GROUND ;
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PORT
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LAYER met4 ;
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RECT 19.050 5.200 20.650 57.360 ;
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END
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PORT
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LAYER met4 ;
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RECT 44.050 5.200 45.650 57.360 ;
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RECT 25.300 5.200 26.900 57.360 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 10.365 49.460 11.965 ;
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RECT 4.360 14.350 49.460 15.950 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 27.265 49.460 28.865 ;
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RECT 4.360 31.250 49.460 32.850 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 44.165 49.460 45.765 ;
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RECT 4.360 48.150 49.460 49.750 ;
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END
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END vssd
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PIN vssd1
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@ -404,11 +416,19 @@ MACRO gpio_control_block
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USE GROUND ;
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PORT
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LAYER met4 ;
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RECT 31.550 5.200 33.150 57.360 ;
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RECT 30.300 5.200 31.900 57.360 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 18.815 49.460 20.415 ;
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RECT 4.360 19.590 49.460 21.190 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 36.490 49.460 38.090 ;
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END
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PORT
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LAYER met5 ;
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RECT 4.360 53.390 49.460 54.990 ;
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END
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END vssd1
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PIN zero
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@ -693,7 +713,7 @@ MACRO gpio_control_block
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RECT 28.250 60.720 29.710 65.000 ;
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RECT 30.550 60.720 32.010 65.000 ;
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RECT 32.850 60.720 170.000 65.000 ;
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RECT 4.700 0.000 170.000 60.720 ;
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RECT 4.970 0.000 170.000 60.720 ;
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LAYER met3 ;
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RECT 6.280 60.840 69.600 61.705 ;
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RECT 6.280 60.200 70.000 60.840 ;
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@ -756,14 +776,13 @@ MACRO gpio_control_block
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RECT 6.280 2.215 69.600 3.080 ;
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LAYER met4 ;
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RECT 6.280 57.760 170.000 65.000 ;
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RECT 6.280 26.000 12.400 57.760 ;
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RECT 14.800 26.000 18.650 57.760 ;
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RECT 6.280 4.800 18.650 26.000 ;
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RECT 21.050 4.800 24.900 57.760 ;
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RECT 27.300 4.800 31.150 57.760 ;
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RECT 33.550 4.800 37.400 57.760 ;
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RECT 39.800 4.800 43.650 57.760 ;
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RECT 46.050 4.800 170.000 57.760 ;
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RECT 6.280 4.800 12.400 57.760 ;
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RECT 14.800 4.800 17.400 57.760 ;
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RECT 19.800 4.800 24.900 57.760 ;
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RECT 27.300 4.800 29.900 57.760 ;
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RECT 32.300 4.800 37.400 57.760 ;
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RECT 39.800 4.800 42.400 57.760 ;
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RECT 44.800 4.800 170.000 57.760 ;
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RECT 6.280 0.000 170.000 4.800 ;
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LAYER met5 ;
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RECT 67.000 0.000 170.000 65.000 ;
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File diff suppressed because it is too large
Load Diff
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@ -1,7 +1,7 @@
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magic
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tech sky130A
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magscale 1 2
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timestamp 1659794614
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timestamp 1663176680
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<< obsli1 >>
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rect 0 13000 853 13014
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rect 0 0 33962 13000
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@ -35,7 +35,7 @@ rect 5190 12144 5482 13000
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rect 5650 12144 5942 13000
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rect 6110 12144 6402 13000
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rect 6570 12144 34000 13000
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rect 940 0 34000 12144
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rect 994 0 34000 12144
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<< metal3 >>
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rect 14000 12248 34000 12368
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rect 14000 11840 34000 11960
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@ -128,31 +128,35 @@ rect 1256 744 13920 1024
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rect 1256 616 14000 744
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rect 1256 443 13920 616
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<< metal4 >>
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rect 2560 5280 2880 11472
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rect 3810 1040 4130 11472
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rect 2560 1040 2880 11472
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rect 3560 1040 3880 11472
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rect 5060 1040 5380 11472
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rect 6310 1040 6630 11472
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rect 6060 1040 6380 11472
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rect 7560 1040 7880 11472
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rect 8810 1040 9130 11472
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rect 8560 1040 8880 11472
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<< obsm4 >>
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rect 1256 11552 34000 13000
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rect 1256 5200 2480 11552
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rect 2960 5200 3730 11552
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rect 1256 960 3730 5200
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rect 4210 960 4980 11552
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rect 5460 960 6230 11552
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rect 6710 960 7480 11552
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rect 7960 960 8730 11552
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rect 9210 960 34000 11552
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rect 1256 960 2480 11552
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rect 2960 960 3480 11552
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rect 3960 960 4980 11552
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rect 5460 960 5980 11552
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rect 6460 960 7480 11552
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rect 7960 960 8480 11552
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rect 8960 960 34000 11552
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rect 1256 0 34000 960
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<< metal5 >>
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rect 872 8833 9892 9153
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rect 872 7988 9892 8308
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rect 872 5453 9892 5773
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rect 872 3763 9892 4083
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rect 872 2918 9892 3238
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rect 872 2073 9892 2393
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rect 872 1228 9892 1548
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rect 872 10678 9892 10998
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rect 872 9630 9892 9950
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rect 872 8988 9892 9308
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rect 872 7940 9892 8260
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rect 872 7298 9892 7618
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rect 872 6250 9892 6570
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rect 872 5608 9892 5928
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rect 872 4560 9892 4880
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rect 872 3918 9892 4238
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rect 872 2870 9892 3190
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rect 872 2228 9892 2548
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rect 872 1180 9892 1500
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<< obsm5 >>
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rect 13400 0 34000 13000
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<< labels >>
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@ -240,31 +244,41 @@ rlabel metal3 s 14000 11840 34000 11960 6 user_gpio_oeb
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port 41 nsew signal input
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rlabel metal3 s 14000 12248 34000 12368 6 user_gpio_out
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port 42 nsew signal input
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rlabel metal4 s 2560 5280 2880 11472 6 vccd
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rlabel metal4 s 2560 1040 2880 11472 6 vccd
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port 43 nsew power bidirectional
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rlabel metal4 s 7560 1040 7880 11472 6 vccd
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port 43 nsew power bidirectional
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rlabel metal5 s 872 1228 9892 1548 6 vccd
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rlabel metal5 s 872 1180 9892 1500 6 vccd
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port 43 nsew power bidirectional
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rlabel metal5 s 872 7988 9892 8308 6 vccd
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rlabel metal5 s 872 4560 9892 4880 6 vccd
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port 43 nsew power bidirectional
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rlabel metal4 s 5060 1040 5380 11472 6 vccd1
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rlabel metal5 s 872 7940 9892 8260 6 vccd
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port 43 nsew power bidirectional
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rlabel metal4 s 3560 1040 3880 11472 6 vccd1
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port 44 nsew power bidirectional
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rlabel metal5 s 872 2918 9892 3238 6 vccd1
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rlabel metal4 s 8560 1040 8880 11472 6 vccd1
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port 44 nsew power bidirectional
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rlabel metal4 s 3810 1040 4130 11472 6 vssd
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rlabel metal5 s 872 2228 9892 2548 6 vccd1
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port 44 nsew power bidirectional
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rlabel metal5 s 872 5608 9892 5928 6 vccd1
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port 44 nsew power bidirectional
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rlabel metal5 s 872 8988 9892 9308 6 vccd1
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port 44 nsew power bidirectional
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rlabel metal4 s 5060 1040 5380 11472 6 vssd
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port 45 nsew ground bidirectional
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rlabel metal4 s 8810 1040 9130 11472 6 vssd
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rlabel metal5 s 872 2870 9892 3190 6 vssd
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port 45 nsew ground bidirectional
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rlabel metal5 s 872 2073 9892 2393 6 vssd
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rlabel metal5 s 872 6250 9892 6570 6 vssd
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port 45 nsew ground bidirectional
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rlabel metal5 s 872 5453 9892 5773 6 vssd
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rlabel metal5 s 872 9630 9892 9950 6 vssd
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port 45 nsew ground bidirectional
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rlabel metal5 s 872 8833 9892 9153 6 vssd
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port 45 nsew ground bidirectional
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rlabel metal4 s 6310 1040 6630 11472 6 vssd1
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rlabel metal4 s 6060 1040 6380 11472 6 vssd1
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port 46 nsew ground bidirectional
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rlabel metal5 s 872 3763 9892 4083 6 vssd1
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rlabel metal5 s 872 3918 9892 4238 6 vssd1
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port 46 nsew ground bidirectional
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rlabel metal5 s 872 7298 9892 7618 6 vssd1
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port 46 nsew ground bidirectional
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rlabel metal5 s 872 10678 9892 10998 6 vssd1
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port 46 nsew ground bidirectional
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rlabel metal3 s 14000 416 34000 536 6 zero
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port 47 nsew signal output
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@ -272,8 +286,8 @@ port 47 nsew signal output
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string FIXED_BBOX 0 0 34000 13000
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string LEFclass BLOCK
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string LEFview TRUE
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string GDS_END 456894
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string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_08_06_07_01/results/signoff/gpio_control_block.magic.gds
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string GDS_END 446664
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string GDS_FILE /home/kareem_farid/caravel/openlane/gpio_control_block/runs/22_09_14_10_30/results/signoff/gpio_control_block.magic.gds
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string GDS_START 156052
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<< end >>
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@ -42,11 +42,6 @@ set ::env(SYNTH_STRATEGY) "AREA 0"
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set ::env(FP_SIZING) absolute
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set ::env(DIE_AREA) "0 0 170 65"
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set ::env(FP_IO_VEXTEND) 0
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set ::env(FP_IO_HEXTEND) 0
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set ::env(FP_IO_HLENGTH) 100
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set ::env(FP_IO_VLENGTH) 4
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set ::env(RIGHT_MARGIN_MULT) 262
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set ::env(LEFT_MARGIN_MULT) 10
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set ::env(TOP_MARGIN_MULT) 2
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@ -58,19 +53,23 @@ set ::env(DPL_CELL_PADDING) 0
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set ::env(FP_PDN_MACRO_HOOKS) "\
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gpio_logic_high vccd1 vssd1 vccd1 vssd1"
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#set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
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set ::env(PDN_CFG) $::env(DESIGN_DIR)/pdn.tcl
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set ::env(FP_PDN_AUTO_ADJUST) 0
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set ::env(FP_PDN_VWIDTH) 1.6
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set ::env(FP_PDN_HWIDTH) 1.6
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set ::env(FP_PDN_HORIZONTAL_HALO) 2
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set ::env(FP_PDN_VERTICAL_HALO) 2
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set ::env(FP_PDN_HORIZONTAL_HALO) 0
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set ::env(FP_PDN_VERTICAL_HALO) 0
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set ::env(FP_PDN_CHECK_NODES) 0
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# these PDN vars are mostly hard coded in the custom ./pdn.tcl file
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# keeping them in case openlane depends on the variable definition
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set ::env(FP_PDN_HOFFSET) 1.5
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set ::env(FP_PDN_VOFFSET) 9.0
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set ::env(FP_PDN_HPITCH) 16.9
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set ::env(FP_PDN_HPITCH) 20
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set ::env(FP_PDN_VPITCH) 25
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set ::env(FP_PDN_VSPACING) 3.4
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@ -129,6 +128,7 @@ set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) 0
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set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) 0
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set ::env(CLOCK_TREE_SYNTH) 1
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set ::env(FP_DEF_TEMPLATE) $::env(DESIGN_DIR)/gpio_control_block.def
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set ::env(SYNTH_BUFFERING) 0
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set ::env(SYNTH_SIZING) 0
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# 0.07 ns 70 ps
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@ -136,8 +136,8 @@ set ::env(SYNTH_SIZING) 0
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# set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) 1
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# set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) 2
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set ::env(QUIT_ON_MAGIC_DRC) 0
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set ::env(QUIT_ON_LVS_ERROR) 0
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set ::env(QUIT_ON_MAGIC_DRC) 1
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set ::env(QUIT_ON_LVS_ERROR) 1
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set ::env(SYNTH_EXTRA_MAPPING_FILE) $::env(DESIGN_DIR)/yosys_mapping.v
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@ -1,104 +1,154 @@
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# Power nets
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if { ! [info exists ::env(VDD_NET)] } {
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set ::env(VDD_NET) $::env(VDD_PIN)
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}
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if { ! [info exists ::env(GND_NET)] } {
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set ::env(GND_NET) $::env(GND_PIN)
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}
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set ::power_nets $::env(VDD_NET)
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set ::ground_nets $::env(GND_NET)
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if { [info exists ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS)] } {
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if { $::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) == 1 } {
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foreach power_pin $::env(STD_CELL_POWER_PINS) {
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add_global_connection -net $::env(VDD_NET) -inst_pattern .* -pin_pattern $power_pin -power
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add_global_connection \
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-net $::env(VDD_NET) \
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-inst_pattern .* \
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-pin_pattern $power_pin \
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-power
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}
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foreach ground_pin $::env(STD_CELL_GROUND_PINS) {
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add_global_connection -net $::env(GND_NET) -inst_pattern .* -pin_pattern $ground_pin -ground
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add_global_connection \
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-net $::env(GND_NET) \
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-inst_pattern .* \
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-pin_pattern $ground_pin \
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-ground
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}
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}
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}
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set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET)
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if { $::env(FP_PDN_ENABLE_MACROS_GRID) == 1 &&
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[info exists ::env(FP_PDN_MACRO_HOOKS)]} {
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set pdn_hooks [split $::env(FP_PDN_MACRO_HOOKS) ","]
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foreach pdn_hook $pdn_hooks {
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set instance_name [lindex $pdn_hook 0]
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set power_net [lindex $pdn_hook 1]
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set ground_net [lindex $pdn_hook 2]
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set power_pin [lindex $pdn_hook 3]
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set ground_pin [lindex $pdn_hook 4]
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# Assesses whether the deisgn is the core of the chip or not based on the
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if { $power_pin == "" || $ground_pin == "" } {
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puts "FP_PDN_MACRO_HOOKS missing power and ground pin names"
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exit -1
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}
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add_global_connection \
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-net $power_net \
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-inst_pattern $instance_name \
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-pin_pattern $power_pin \
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-power
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add_global_connection \
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-net $ground_net \
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-inst_pattern $instance_name \
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-pin_pattern $ground_pin \
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-ground
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}
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}
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set secondary []
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foreach vdd $::env(VDD_NETS) gnd $::env(GND_NETS) {
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if { $vdd != $::env(VDD_NET)} {
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lappend secondary $vdd
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set db_net [[ord::get_db_block] findNet $vdd]
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if {$db_net == "NULL"} {
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set net [odb::dbNet_create [ord::get_db_block] $vdd]
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$net setSpecial
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||||
$net setSigType "POWER"
|
||||
}
|
||||
}
|
||||
|
||||
if { $gnd != $::env(GND_NET)} {
|
||||
lappend secondary $gnd
|
||||
|
||||
set db_net [[ord::get_db_block] findNet $gnd]
|
||||
if {$db_net == "NULL"} {
|
||||
set net [odb::dbNet_create [ord::get_db_block] $gnd]
|
||||
$net setSpecial
|
||||
$net setSigType "GROUND"
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
puts "set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
|
||||
-secondary_power $secondary"
|
||||
set_voltage_domain -name CORE -power $::env(VDD_NET) -ground $::env(GND_NET) \
|
||||
-secondary_power $secondary
|
||||
|
||||
# Assesses whether the design is the core of the chip or not based on the
|
||||
# value of $::env(DESIGN_IS_CORE) and uses the appropriate stdcell section
|
||||
define_pdn_grid \
|
||||
-name stdcell_grid \
|
||||
-starts_with POWER \
|
||||
-voltage_domain CORE \
|
||||
-pins [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
-pins "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
|
||||
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_LOWER_LAYER) \
|
||||
-width $::env(FP_PDN_VWIDTH) \
|
||||
-pitch $::env(FP_PDN_VPITCH) \
|
||||
-offset $::env(FP_PDN_VOFFSET) \
|
||||
-starts_with POWER
|
||||
-pitch 25 \
|
||||
-offset 9.0 \
|
||||
-spacing 10.9 \
|
||||
-nets "vccd vssd" \
|
||||
-starts_with POWER -extend_to_core_ring
|
||||
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_LOWER_LAYER) \
|
||||
-width $::env(FP_PDN_VWIDTH) \
|
||||
-pitch 25 \
|
||||
-offset 14.0 \
|
||||
-spacing 10.9 \
|
||||
-nets "vccd1 vssd1" \
|
||||
-starts_with POWER -extend_to_core_ring
|
||||
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_UPPER_LAYER) \
|
||||
-width $::env(FP_PDN_HWIDTH) \
|
||||
-pitch $::env(FP_PDN_HPITCH) \
|
||||
-offset $::env(FP_PDN_HOFFSET) \
|
||||
-starts_with POWER
|
||||
-pitch 16.9 \
|
||||
-offset 6.5 \
|
||||
-spacing 6.85 \
|
||||
-nets "vccd1 vssd1"\
|
||||
-starts_with POWER -extend_to_core_ring
|
||||
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_UPPER_LAYER) \
|
||||
-width $::env(FP_PDN_HWIDTH) \
|
||||
-pitch 16.9 \
|
||||
-offset 1.26 \
|
||||
-spacing 6.85 \
|
||||
-nets "vccd vssd"\
|
||||
-starts_with POWER -extend_to_core_ring
|
||||
|
||||
add_pdn_connect \
|
||||
-grid stdcell_grid \
|
||||
-layers [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}]
|
||||
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
|
||||
|
||||
# Adds the standard cell rails if enabled.
|
||||
if { $::env(FP_PDN_ENABLE_RAILS) == 1 } {
|
||||
add_pdn_stripe -grid stdcell_grid -layer $::env(FP_PDN_RAILS_LAYER) -width $::env(FP_PDN_RAIL_WIDTH) -followpins -starts_with POWER
|
||||
add_pdn_connect -grid stdcell_grid -layers [subst {$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)}]
|
||||
}
|
||||
add_pdn_stripe \
|
||||
-grid stdcell_grid \
|
||||
-layer $::env(FP_PDN_RAILS_LAYER) \
|
||||
-width $::env(FP_PDN_RAIL_WIDTH) \
|
||||
-followpins \
|
||||
-starts_with POWER
|
||||
|
||||
# Adds the core ring if enabled.
|
||||
if { $::env(FP_PDN_CORE_RING) == 1 } {
|
||||
add_pdn_ring -grid stdcell_grid -layer [subst {$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)}] \
|
||||
-widths [subst {$::env(FP_PDN_CORE_RING_VWIDTH) $::env(FP_PDN_CORE_RING_HWIDTH)}] \
|
||||
-spacings [subst {$::env(FP_PDN_CORE_RING_VSPACING) $::env(FP_PDN_CORE_RING_HSPACING)}] \
|
||||
-core_offset [subst {$::env(FP_PDN_CORE_RING_VOFFSET) $::env(FP_PDN_CORE_RING_HOFFSET)}]
|
||||
}
|
||||
add_pdn_connect \
|
||||
-grid stdcell_grid \
|
||||
-layers "$::env(FP_PDN_RAILS_LAYER) $::env(FP_PDN_LOWER_LAYER)"
|
||||
|
||||
if { $::env(VDD_NET) == "vccd1" } {
|
||||
add_global_connection -net vccd1 -inst_pattern gpio_logic_high -pin_pattern vccd1
|
||||
add_global_connection -net vssd1 -inst_pattern gpio_logic_high -pin_pattern vssd1
|
||||
define_pdn_grid \
|
||||
-macro \
|
||||
-orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
add_pdn_connect \
|
||||
-layers { met4_PIN_ver met5 }
|
||||
# set macro {
|
||||
# orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
# power_pins "vccd1"
|
||||
# ground_pins "vssd1"
|
||||
# blockages "met1 met2 met3 met4 met5"
|
||||
# straps {
|
||||
# }
|
||||
# connect {{$::env(FP_PDN_LOWER_LAYER)_PIN_ver $::env(FP_PDN_UPPER_LAYER)}}
|
||||
# }
|
||||
# pdngen::specify_grid macro [subst $macro]
|
||||
set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
|
||||
} else {
|
||||
# set macro {
|
||||
# orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
# power_pins "vccd1"
|
||||
# ground_pins "vssd1"
|
||||
# blockages "met1 met2 met3 met4 met5"
|
||||
# straps {
|
||||
# }
|
||||
# }
|
||||
# pdngen::specify_grid macro [subst $macro]
|
||||
define_pdn_grid \
|
||||
-macro \
|
||||
-orient {R0 R180 MX MY R90 R270 MXR90 MYR90}
|
||||
set ::halo [list $::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)]
|
||||
}
|
||||
|
||||
# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
|
||||
set ::rails_start_with "POWER" ;
|
||||
define_pdn_grid \
|
||||
-macro \
|
||||
-default \
|
||||
-name macro \
|
||||
-starts_with POWER \
|
||||
-halo "$::env(FP_PDN_HORIZONTAL_HALO) $::env(FP_PDN_VERTICAL_HALO)"
|
||||
|
||||
# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
|
||||
set ::stripes_start_with "POWER" ;
|
||||
add_pdn_connect \
|
||||
-grid macro \
|
||||
-layers "$::env(FP_PDN_LOWER_LAYER) $::env(FP_PDN_UPPER_LAYER)"
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
###############################################################################
|
||||
# Created by write_sdc
|
||||
# Sat Aug 6 14:03:05 2022
|
||||
# Wed Sep 14 17:30:57 2022
|
||||
###############################################################################
|
||||
current_design gpio_control_block
|
||||
###############################################################################
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "gpio_control_block")
|
||||
(DATE "Sat Aug 6 14:03:29 2022")
|
||||
(DATE "Wed Sep 14 17:31:16 2022")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.1")
|
||||
|
@ -15,36 +15,36 @@
|
|||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT gpio_defaults[0] _067_.B (0.044:0.044:0.044) (0.020:0.020:0.020))
|
||||
(INTERCONNECT gpio_defaults[0] _068_.B (0.044:0.044:0.044) (0.020:0.020:0.020))
|
||||
(INTERCONNECT gpio_defaults[0] ANTENNA__068__B.DIODE (0.043:0.043:0.043) (0.020:0.020:0.020))
|
||||
(INTERCONNECT gpio_defaults[0] ANTENNA__067__B.DIODE (0.043:0.043:0.043) (0.020:0.020:0.020))
|
||||
(INTERCONNECT gpio_defaults[0] _067_.B (0.039:0.039:0.039) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[0] _068_.B (0.039:0.039:0.039) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[0] ANTENNA__068__B.DIODE (0.038:0.038:0.038) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[0] ANTENNA__067__B.DIODE (0.038:0.038:0.038) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[10] _081_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[10] _082_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[10] ANTENNA__082__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[10] ANTENNA__081__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[11] _083_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[11] _084_.B (0.046:0.046:0.046) (0.022:0.022:0.022))
|
||||
(INTERCONNECT gpio_defaults[11] _084_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[11] ANTENNA__084__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[11] ANTENNA__083__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[12] _085_.B (0.037:0.037:0.037) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[12] _086_.B (0.037:0.037:0.037) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[12] ANTENNA__086__B.DIODE (0.037:0.037:0.037) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[12] ANTENNA__085__B.DIODE (0.037:0.037:0.037) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[12] _085_.B (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT gpio_defaults[12] _086_.B (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT gpio_defaults[12] ANTENNA__086__B.DIODE (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT gpio_defaults[12] ANTENNA__085__B.DIODE (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT gpio_defaults[1] _079_.B (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT gpio_defaults[1] _080_.B (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT gpio_defaults[1] ANTENNA__080__B.DIODE (0.035:0.035:0.035) (0.016:0.016:0.016))
|
||||
(INTERCONNECT gpio_defaults[1] ANTENNA__080__B.DIODE (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT gpio_defaults[1] ANTENNA__079__B.DIODE (0.036:0.036:0.036) (0.016:0.016:0.016))
|
||||
(INTERCONNECT gpio_defaults[2] _069_.B (0.040:0.040:0.040) (0.018:0.018:0.018))
|
||||
(INTERCONNECT gpio_defaults[2] _070_.B (0.040:0.040:0.040) (0.018:0.018:0.018))
|
||||
(INTERCONNECT gpio_defaults[2] ANTENNA__070__B.DIODE (0.040:0.040:0.040) (0.018:0.018:0.018))
|
||||
(INTERCONNECT gpio_defaults[2] ANTENNA__069__B.DIODE (0.040:0.040:0.040) (0.018:0.018:0.018))
|
||||
(INTERCONNECT gpio_defaults[3] _075_.B (0.037:0.037:0.037) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[3] _076_.B (0.037:0.037:0.037) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[3] _075_.B (0.038:0.038:0.038) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[3] _076_.B (0.038:0.038:0.038) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[3] ANTENNA__076__B.DIODE (0.037:0.037:0.037) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[3] ANTENNA__075__B.DIODE (0.037:0.037:0.037) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[4] _077_.B (0.042:0.042:0.042) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[4] _078_.B (0.042:0.042:0.042) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[4] _077_.B (0.041:0.041:0.041) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[4] _078_.B (0.041:0.041:0.041) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[4] ANTENNA__078__B.DIODE (0.041:0.041:0.041) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[4] ANTENNA__077__B.DIODE (0.041:0.041:0.041) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[5] _087_.B (0.045:0.045:0.045) (0.021:0.021:0.021))
|
||||
|
@ -54,111 +54,111 @@
|
|||
(INTERCONNECT gpio_defaults[6] _089_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[6] _090_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[6] ANTENNA__090__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[6] ANTENNA__089__B.DIODE (0.045:0.045:0.045) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[6] ANTENNA__089__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[7] _091_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[7] _092_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[7] ANTENNA__092__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[7] ANTENNA__091__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[8] _071_.B (0.047:0.047:0.047) (0.022:0.022:0.022))
|
||||
(INTERCONNECT gpio_defaults[8] _072_.B (0.047:0.047:0.047) (0.022:0.022:0.022))
|
||||
(INTERCONNECT gpio_defaults[8] ANTENNA__072__B.DIODE (0.047:0.047:0.047) (0.022:0.022:0.022))
|
||||
(INTERCONNECT gpio_defaults[8] ANTENNA__071__B.DIODE (0.047:0.047:0.047) (0.022:0.022:0.022))
|
||||
(INTERCONNECT gpio_defaults[9] _073_.B (0.042:0.042:0.042) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[7] _092_.B (0.047:0.047:0.047) (0.022:0.022:0.022))
|
||||
(INTERCONNECT gpio_defaults[7] ANTENNA__092__B.DIODE (0.047:0.047:0.047) (0.022:0.022:0.022))
|
||||
(INTERCONNECT gpio_defaults[7] ANTENNA__091__B.DIODE (0.047:0.047:0.047) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[8] _071_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[8] _072_.B (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[8] ANTENNA__072__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[8] ANTENNA__071__B.DIODE (0.046:0.046:0.046) (0.021:0.021:0.021))
|
||||
(INTERCONNECT gpio_defaults[9] _073_.B (0.041:0.041:0.041) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[9] _074_.B (0.042:0.042:0.042) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[9] ANTENNA__074__B.DIODE (0.042:0.042:0.042) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[9] ANTENNA__073__B.DIODE (0.042:0.042:0.042) (0.019:0.019:0.019))
|
||||
(INTERCONNECT mgmt_gpio_oeb _063_.A2 (0.036:0.036:0.036) (0.017:0.017:0.017))
|
||||
(INTERCONNECT mgmt_gpio_oeb _064_.C (0.036:0.036:0.036) (0.017:0.017:0.017))
|
||||
(INTERCONNECT mgmt_gpio_oeb ANTENNA__064__C.DIODE (0.036:0.036:0.036) (0.017:0.017:0.017))
|
||||
(INTERCONNECT mgmt_gpio_oeb ANTENNA__063__A2.DIODE (0.036:0.036:0.036) (0.017:0.017:0.017))
|
||||
(INTERCONNECT gpio_defaults[9] ANTENNA__074__B.DIODE (0.041:0.041:0.041) (0.019:0.019:0.019))
|
||||
(INTERCONNECT gpio_defaults[9] ANTENNA__073__B.DIODE (0.041:0.041:0.041) (0.019:0.019:0.019))
|
||||
(INTERCONNECT mgmt_gpio_oeb _063_.A2 (0.035:0.035:0.035) (0.016:0.016:0.016))
|
||||
(INTERCONNECT mgmt_gpio_oeb _064_.C (0.035:0.035:0.035) (0.016:0.016:0.016))
|
||||
(INTERCONNECT mgmt_gpio_oeb ANTENNA__064__C.DIODE (0.035:0.035:0.035) (0.016:0.016:0.016))
|
||||
(INTERCONNECT mgmt_gpio_oeb ANTENNA__063__A2.DIODE (0.035:0.035:0.035) (0.016:0.016:0.016))
|
||||
(INTERCONNECT mgmt_gpio_out _065_.A0 (0.018:0.018:0.018) (0.008:0.008:0.008))
|
||||
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(INSTANCE _078_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A_N Y (0.243:0.243:0.243) (0.300:0.300:0.300))
|
||||
(IOPATH A_N Y (0.242:0.242:0.242) (0.297:0.297:0.297))
|
||||
(IOPATH B Y (0.053:0.053:0.053) (0.054:0.054:0.054))
|
||||
)
|
||||
)
|
||||
|
@ -541,8 +541,8 @@
|
|||
(INSTANCE _079_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.220:0.220:0.220) (0.392:0.392:0.392))
|
||||
(IOPATH B X (0.095:0.095:0.095) (0.256:0.256:0.256))
|
||||
(IOPATH A X (0.219:0.219:0.219) (0.389:0.389:0.389))
|
||||
(IOPATH B X (0.094:0.094:0.094) (0.256:0.256:0.256))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
@ -551,7 +551,7 @@
|
|||
(INSTANCE _080_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A_N Y (0.244:0.244:0.244) (0.301:0.301:0.301))
|
||||
(IOPATH A_N Y (0.243:0.243:0.243) (0.299:0.299:0.299))
|
||||
(IOPATH B Y (0.052:0.052:0.052) (0.053:0.053:0.053))
|
||||
)
|
||||
)
|
||||
|
@ -561,7 +561,7 @@
|
|||
(INSTANCE _081_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.219:0.219:0.219) (0.391:0.391:0.391))
|
||||
(IOPATH A X (0.218:0.218:0.218) (0.389:0.389:0.389))
|
||||
(IOPATH B X (0.099:0.099:0.099) (0.257:0.257:0.257))
|
||||
)
|
||||
)
|
||||
|
@ -571,7 +571,7 @@
|
|||
(INSTANCE _082_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A_N Y (0.243:0.243:0.243) (0.300:0.300:0.300))
|
||||
(IOPATH A_N Y (0.242:0.242:0.242) (0.297:0.297:0.297))
|
||||
(IOPATH B Y (0.054:0.054:0.054) (0.055:0.055:0.055))
|
||||
)
|
||||
)
|
||||
|
@ -581,8 +581,8 @@
|
|||
(INSTANCE _083_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.219:0.219:0.219) (0.391:0.391:0.391))
|
||||
(IOPATH B X (0.100:0.100:0.100) (0.258:0.258:0.258))
|
||||
(IOPATH A X (0.219:0.219:0.219) (0.389:0.389:0.389))
|
||||
(IOPATH B X (0.099:0.099:0.099) (0.258:0.258:0.258))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
@ -591,7 +591,7 @@
|
|||
(INSTANCE _084_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A_N Y (0.244:0.244:0.244) (0.301:0.301:0.301))
|
||||
(IOPATH A_N Y (0.243:0.243:0.243) (0.299:0.299:0.299))
|
||||
(IOPATH B Y (0.055:0.055:0.055) (0.056:0.056:0.056))
|
||||
)
|
||||
)
|
||||
|
@ -601,8 +601,8 @@
|
|||
(INSTANCE _085_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.218:0.218:0.218) (0.390:0.390:0.390))
|
||||
(IOPATH B X (0.094:0.094:0.094) (0.254:0.254:0.254))
|
||||
(IOPATH A X (0.217:0.217:0.217) (0.387:0.387:0.387))
|
||||
(IOPATH B X (0.093:0.093:0.093) (0.253:0.253:0.253))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
@ -611,7 +611,7 @@
|
|||
(INSTANCE _086_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A_N Y (0.242:0.242:0.242) (0.299:0.299:0.299))
|
||||
(IOPATH A_N Y (0.241:0.241:0.241) (0.296:0.296:0.296))
|
||||
(IOPATH B Y (0.051:0.051:0.051) (0.052:0.052:0.052))
|
||||
)
|
||||
)
|
||||
|
@ -621,7 +621,7 @@
|
|||
(INSTANCE _087_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.219:0.219:0.219) (0.391:0.391:0.391))
|
||||
(IOPATH A X (0.218:0.218:0.218) (0.389:0.389:0.389))
|
||||
(IOPATH B X (0.099:0.099:0.099) (0.257:0.257:0.257))
|
||||
)
|
||||
)
|
||||
|
@ -631,7 +631,7 @@
|
|||
(INSTANCE _088_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A_N Y (0.243:0.243:0.243) (0.299:0.299:0.299))
|
||||
(IOPATH A_N Y (0.242:0.242:0.242) (0.297:0.297:0.297))
|
||||
(IOPATH B Y (0.054:0.054:0.054) (0.055:0.055:0.055))
|
||||
)
|
||||
)
|
||||
|
@ -641,7 +641,7 @@
|
|||
(INSTANCE _089_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.217:0.217:0.217) (0.389:0.389:0.389))
|
||||
(IOPATH A X (0.217:0.217:0.217) (0.387:0.387:0.387))
|
||||
(IOPATH B X (0.098:0.098:0.098) (0.255:0.255:0.255))
|
||||
)
|
||||
)
|
||||
|
@ -651,7 +651,7 @@
|
|||
(INSTANCE _090_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A_N Y (0.244:0.244:0.244) (0.301:0.301:0.301))
|
||||
(IOPATH A_N Y (0.243:0.243:0.243) (0.299:0.299:0.299))
|
||||
(IOPATH B Y (0.055:0.055:0.055) (0.056:0.056:0.056))
|
||||
)
|
||||
)
|
||||
|
@ -661,7 +661,7 @@
|
|||
(INSTANCE _091_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.217:0.217:0.217) (0.389:0.389:0.389))
|
||||
(IOPATH A X (0.217:0.217:0.217) (0.387:0.387:0.387))
|
||||
(IOPATH B X (0.098:0.098:0.098) (0.255:0.255:0.255))
|
||||
)
|
||||
)
|
||||
|
@ -671,7 +671,7 @@
|
|||
(INSTANCE _092_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A_N Y (0.242:0.242:0.242) (0.299:0.299:0.299))
|
||||
(IOPATH A_N Y (0.241:0.241:0.241) (0.297:0.297:0.297))
|
||||
(IOPATH B Y (0.054:0.054:0.054) (0.055:0.055:0.055))
|
||||
)
|
||||
)
|
||||
|
@ -790,7 +790,7 @@
|
|||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK_N Q_N (0.476:0.476:0.476) (0.376:0.376:0.376))
|
||||
(IOPATH CLK_N Q (0.540:0.540:0.540) (0.604:0.604:0.604))
|
||||
(IOPATH CLK_N Q (0.539:0.539:0.539) (0.603:0.603:0.603))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
|
@ -814,7 +814,7 @@
|
|||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK_N Q_N (0.475:0.475:0.475) (0.376:0.376:0.376))
|
||||
(IOPATH CLK_N Q (0.638:0.638:0.638) (0.662:0.662:0.662))
|
||||
(IOPATH CLK_N Q (0.639:0.639:0.639) (0.663:0.663:0.663))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
|
@ -886,7 +886,7 @@
|
|||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK_N Q_N (0.475:0.475:0.475) (0.376:0.376:0.376))
|
||||
(IOPATH CLK_N Q (0.646:0.646:0.646) (0.666:0.666:0.666))
|
||||
(IOPATH CLK_N Q (0.644:0.644:0.644) (0.664:0.664:0.664))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
|
@ -896,7 +896,7 @@
|
|||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (negedge CLK_N) (0.064:0.063:0.062))
|
||||
(RECOVERY (posedge SET_B) (negedge CLK_N) (-0.058:-0.057:-0.056))
|
||||
(REMOVAL (posedge RESET_B) (negedge CLK_N) (0.075:0.072:0.070))
|
||||
(REMOVAL (posedge RESET_B) (negedge CLK_N) (0.074:0.072:0.070))
|
||||
(RECOVERY (posedge RESET_B) (negedge CLK_N) (0.075:0.077:0.079))
|
||||
(HOLD (posedge D) (negedge CLK_N) (0.035:0.035:0.035))
|
||||
(HOLD (negedge D) (negedge CLK_N) (-0.147:-0.147:-0.147))
|
||||
|
@ -910,7 +910,7 @@
|
|||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK_N Q_N (0.475:0.475:0.475) (0.375:0.375:0.375))
|
||||
(IOPATH CLK_N Q (0.632:0.632:0.632) (0.659:0.659:0.659))
|
||||
(IOPATH CLK_N Q (0.631:0.631:0.631) (0.659:0.659:0.659))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
|
@ -934,7 +934,7 @@
|
|||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK_N Q_N (0.476:0.476:0.476) (0.376:0.376:0.376))
|
||||
(IOPATH CLK_N Q (0.540:0.540:0.540) (0.604:0.604:0.604))
|
||||
(IOPATH CLK_N Q (0.539:0.539:0.539) (0.603:0.603:0.603))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
|
@ -957,8 +957,8 @@
|
|||
(INSTANCE _112_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK_N Q_N (0.491:0.491:0.491) (0.391:0.391:0.391))
|
||||
(IOPATH CLK_N Q (0.628:0.628:0.628) (0.657:0.657:0.657))
|
||||
(IOPATH CLK_N Q_N (0.489:0.489:0.489) (0.389:0.389:0.389))
|
||||
(IOPATH CLK_N Q (0.629:0.629:0.629) (0.657:0.657:0.657))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
|
@ -982,7 +982,7 @@
|
|||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK_N Q_N (0.475:0.475:0.475) (0.376:0.376:0.376))
|
||||
(IOPATH CLK_N Q (0.634:0.634:0.634) (0.660:0.660:0.660))
|
||||
(IOPATH CLK_N Q (0.633:0.633:0.633) (0.660:0.660:0.660))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
|
@ -990,7 +990,7 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (negedge CLK_N) (0.063:0.062:0.061))
|
||||
(REMOVAL (posedge SET_B) (negedge CLK_N) (0.063:0.062:0.062))
|
||||
(RECOVERY (posedge SET_B) (negedge CLK_N) (-0.057:-0.056:-0.055))
|
||||
(REMOVAL (posedge RESET_B) (negedge CLK_N) (0.074:0.072:0.070))
|
||||
(RECOVERY (posedge RESET_B) (negedge CLK_N) (0.075:0.077:0.079))
|
||||
|
@ -1041,9 +1041,9 @@
|
|||
(REMOVAL (posedge SET_B) (negedge CLK_N) (0.064:0.063:0.062))
|
||||
(RECOVERY (posedge SET_B) (negedge CLK_N) (-0.057:-0.056:-0.055))
|
||||
(REMOVAL (posedge RESET_B) (negedge CLK_N) (0.075:0.073:0.071))
|
||||
(RECOVERY (posedge RESET_B) (negedge CLK_N) (0.074:0.076:0.079))
|
||||
(RECOVERY (posedge RESET_B) (negedge CLK_N) (0.074:0.076:0.078))
|
||||
(HOLD (posedge D) (negedge CLK_N) (0.034:0.034:0.034))
|
||||
(HOLD (negedge D) (negedge CLK_N) (-0.148:-0.148:-0.148))
|
||||
(HOLD (negedge D) (negedge CLK_N) (-0.149:-0.149:-0.149))
|
||||
(SETUP (posedge D) (negedge CLK_N) (0.097:0.097:0.097))
|
||||
(SETUP (negedge D) (negedge CLK_N) (0.168:0.168:0.168))
|
||||
)
|
||||
|
@ -1088,7 +1088,7 @@
|
|||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (negedge CLK_N) (0.064:0.063:0.062))
|
||||
(RECOVERY (posedge SET_B) (negedge CLK_N) (-0.057:-0.056:-0.055))
|
||||
(REMOVAL (posedge RESET_B) (negedge CLK_N) (0.075:0.073:0.070))
|
||||
(REMOVAL (posedge RESET_B) (negedge CLK_N) (0.075:0.073:0.071))
|
||||
(RECOVERY (posedge RESET_B) (negedge CLK_N) (0.074:0.077:0.079))
|
||||
(HOLD (posedge D) (negedge CLK_N) (0.033:0.033:0.033))
|
||||
(HOLD (negedge D) (negedge CLK_N) (-0.149:-0.149:-0.149))
|
||||
|
@ -1106,8 +1106,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.503:0.503:0.503))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.035:-0.035:-0.035))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.033:-0.033:-0.033))
|
||||
(SETUP (posedge D) (posedge CLK) (0.064:0.064:0.064))
|
||||
|
@ -1124,8 +1124,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.502:0.502:0.502))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.499:0.499:0.499))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.042:-0.042:-0.042))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.052:-0.052:-0.052))
|
||||
(SETUP (posedge D) (posedge CLK) (0.072:0.072:0.072))
|
||||
|
@ -1142,8 +1142,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.502:0.502:0.502))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.499:0.499:0.499))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.039:-0.039:-0.039))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.049:-0.049:-0.049))
|
||||
(SETUP (posedge D) (posedge CLK) (0.069:0.069:0.069))
|
||||
|
@ -1160,8 +1160,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.502:0.502:0.502))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.499:0.499:0.499))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.041:-0.041:-0.041))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.050:-0.050:-0.050))
|
||||
(SETUP (posedge D) (posedge CLK) (0.071:0.071:0.071))
|
||||
|
@ -1178,8 +1178,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.502:0.502:0.502))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.041:-0.041:-0.041))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.050:-0.050:-0.050))
|
||||
(SETUP (posedge D) (posedge CLK) (0.070:0.070:0.070))
|
||||
|
@ -1191,13 +1191,13 @@
|
|||
(INSTANCE _123_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.329:0.329:0.329) (0.376:0.376:0.376))
|
||||
(IOPATH CLK Q (0.330:0.330:0.330) (0.376:0.376:0.376))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.502:0.502:0.502))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.040:-0.040:-0.040))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.050:-0.050:-0.050))
|
||||
(SETUP (posedge D) (posedge CLK) (0.070:0.070:0.070))
|
||||
|
@ -1209,14 +1209,14 @@
|
|||
(INSTANCE _124_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.326:0.326:0.326) (0.373:0.373:0.373))
|
||||
(IOPATH CLK Q (0.327:0.327:0.327) (0.373:0.373:0.373))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.502:0.502:0.502))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.041:-0.041:-0.041))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.042:-0.042:-0.042))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.051:-0.051:-0.051))
|
||||
(SETUP (posedge D) (posedge CLK) (0.071:0.071:0.071))
|
||||
(SETUP (negedge D) (posedge CLK) (0.125:0.125:0.125))
|
||||
|
@ -1232,8 +1232,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.502:0.502:0.502))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.041:-0.041:-0.041))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.050:-0.050:-0.050))
|
||||
(SETUP (posedge D) (posedge CLK) (0.070:0.070:0.070))
|
||||
|
@ -1250,10 +1250,10 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.502:0.502:0.502))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.042:-0.042:-0.042))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.052:-0.052:-0.052))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.051:-0.051:-0.051))
|
||||
(SETUP (posedge D) (posedge CLK) (0.072:0.072:0.072))
|
||||
(SETUP (negedge D) (posedge CLK) (0.126:0.126:0.126))
|
||||
)
|
||||
|
@ -1263,14 +1263,14 @@
|
|||
(INSTANCE _127_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.327:0.327:0.327) (0.374:0.374:0.374))
|
||||
(IOPATH CLK Q (0.328:0.328:0.328) (0.374:0.374:0.374))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.503:0.503:0.503))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.039:-0.039:-0.039))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.040:-0.040:-0.040))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.049:-0.049:-0.049))
|
||||
(SETUP (posedge D) (posedge CLK) (0.069:0.069:0.069))
|
||||
(SETUP (negedge D) (posedge CLK) (0.123:0.123:0.123))
|
||||
|
@ -1281,13 +1281,13 @@
|
|||
(INSTANCE _128_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q (0.330:0.330:0.330) (0.376:0.376:0.376))
|
||||
(IOPATH CLK Q (0.329:0.329:0.329) (0.376:0.376:0.376))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.503:0.503:0.503))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.041:-0.041:-0.041))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.050:-0.050:-0.050))
|
||||
(SETUP (posedge D) (posedge CLK) (0.071:0.071:0.071))
|
||||
|
@ -1304,8 +1304,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.503:0.503:0.503))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.005:-0.005:-0.005))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.041:-0.041:-0.041))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.051:-0.051:-0.051))
|
||||
(SETUP (posedge D) (posedge CLK) (0.071:0.071:0.071))
|
||||
|
@ -1322,11 +1322,11 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.503:0.503:0.503))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.006:-0.006:-0.006))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.500:0.500:0.500))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.009:-0.009:-0.009))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.043:-0.043:-0.043))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.052:-0.052:-0.052))
|
||||
(SETUP (posedge D) (posedge CLK) (0.072:0.072:0.072))
|
||||
(SETUP (posedge D) (posedge CLK) (0.073:0.073:0.073))
|
||||
(SETUP (negedge D) (posedge CLK) (0.126:0.126:0.126))
|
||||
)
|
||||
)
|
||||
|
@ -1340,8 +1340,8 @@
|
|||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.496:0.496:0.496))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.003:0.003:0.003))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.493:0.493:0.493))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (-0.001:-0.001:-0.001))
|
||||
(HOLD (posedge D) (posedge CLK) (-0.039:-0.039:-0.039))
|
||||
(HOLD (negedge D) (posedge CLK) (-0.048:-0.048:-0.048))
|
||||
(SETUP (posedge D) (posedge CLK) (0.068:0.068:0.068))
|
||||
|
@ -1353,7 +1353,7 @@
|
|||
(INSTANCE _132_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.341:0.341:0.341) (0.308:0.308:0.308))
|
||||
(IOPATH A X (0.340:0.340:0.340) (0.307:0.307:0.307))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
@ -1380,7 +1380,7 @@
|
|||
(INSTANCE _135_)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Z (0.432:0.432:0.432) (0.232:0.232:0.232))
|
||||
(IOPATH A Z (0.431:0.431:0.431) (0.231:0.231:0.231))
|
||||
(IOPATH TE_B Z (0.382:0.385:0.388) (0.201:0.204:0.207))
|
||||
)
|
||||
)
|
||||
|
@ -1408,7 +1408,7 @@
|
|||
(INSTANCE clkbuf_1_0__f_serial_clock)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.123:0.123:0.123) (0.140:0.140:0.140))
|
||||
(IOPATH A X (0.124:0.124:0.124) (0.141:0.141:0.141))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
@ -1481,7 +1481,7 @@
|
|||
(INSTANCE hold12)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.553:0.553:0.553) (0.562:0.562:0.562))
|
||||
(IOPATH A X (0.554:0.554:0.554) (0.563:0.563:0.563))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
@ -1535,7 +1535,7 @@
|
|||
(INSTANCE hold6)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.557:0.557:0.557) (0.566:0.566:0.566))
|
||||
(IOPATH A X (0.557:0.557:0.557) (0.565:0.565:0.565))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
@ -1544,7 +1544,7 @@
|
|||
(INSTANCE hold7)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A X (0.544:0.544:0.544) (0.555:0.555:0.555))
|
||||
(IOPATH A X (0.545:0.545:0.545) (0.555:0.555:0.555))
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
|
@ -1 +1 @@
|
|||
openlane 4476a58407d670d251aa0be6a55e5391bb181c4e
|
||||
openlane 37faafee20ec76a349fb817d7a75ed26d94be904
|
||||
|
|
|
@ -1 +1 @@
|
|||
open_pdks e8294524e5f67c533c5d0c3afa0bcc5b2a5fa066
|
||||
open_pdks fa87f8f4bbcc7255b6f0c0fb506960f531ae2392
|
||||
|
|
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue