Go to file
kareem c1e0d5ba06 openlane!: reharden gpio_control_block
update gpio_control_block config for new openlane versions:
- disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size
and fit the floorplan
- change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells
- disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and
enable `GLB_RESIZER_TIMING_OPTIMIZATIONS`
- remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement
- set `DECAP_CELL` to not use ef decaps.. i think that was for simulations?
- enable some turned off `QUIT_*` variables
- replace deprecated variables such as `GLB_RT_*`
- customize `pdn.tcl` to force pdn straps to follow the old pattern
- replace `$script_dir` with `$::env(DESIGN_DIR)`

!IMPORTANT - still need to run dynamic simulations
2022-09-14 11:06:23 -07:00
.github/workflows Update auto-update-caravel-lite.yml 2022-02-02 00:52:23 +02:00
.travisCI add documentation 2021-12-17 11:55:08 -08:00
def openlane!: reharden gpio_control_block 2022-09-14 11:06:23 -07:00
docs add links to litex core (#96) 2022-05-08 22:52:47 -07:00
gds Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) 2022-05-08 22:51:29 -07:00
lef openlane!: reharden gpio_control_block 2022-09-14 11:06:23 -07:00
mag openlane!: reharden gpio_control_block 2022-09-14 11:06:23 -07:00
maglef openlane!: reharden gpio_control_block 2022-09-14 11:06:23 -07:00
openlane openlane!: reharden gpio_control_block 2022-09-14 11:06:23 -07:00
scripts issue-105: caravel & caravan.mag: relabel top-level v*_core power nets (label PLUS underlying met5); (#110) 2022-08-26 23:03:00 -07:00
sdc openlane!: reharden gpio_control_block 2022-09-14 11:06:23 -07:00
sdf openlane!: reharden gpio_control_block 2022-09-14 11:06:23 -07:00
signoff openlane!: reharden gpio_control_block 2022-09-14 11:06:23 -07:00
spef openlane!: reharden gpio_control_block 2022-09-14 11:06:23 -07:00
spi/lvs Merge branch 'main' into fix_serial_loader_data_timing 2022-09-02 10:02:36 -04:00
verilog harden: gpio_control_block with updated rtl 2022-08-15 02:29:01 -07:00
xschem Fix the simple_por to (logically) isolate the 1.8V and 3.3V grounds. (#90) 2022-05-08 22:51:29 -07:00
.gitignore - update gpio_control_block config (#57) 2022-04-08 09:27:51 -07:00
.readthedocs.yml add documentation 2021-12-17 11:55:08 -08:00
.travis.yml add documentation 2021-12-17 11:55:08 -08:00
LICENSE Create LICENSE 2021-12-15 23:53:39 -08:00
Makefile Update Makefile 2022-07-07 15:36:19 -07:00
README.rst Quick fix to a layout route for DRC (#84) 2022-04-22 15:10:31 -07:00
README.src.rst add documentation 2021-12-17 11:55:08 -08:00
manifest Apply automatic changes to Manifest and README.rst 2022-07-24 20:21:58 +00:00

README.src.rst

.. raw:: html

   <!---
   # SPDX-FileCopyrightText: 2020 Efabless Corporation
   #
   # Licensed under the Apache License, Version 2.0 (the "License");
   # you may not use this file except in compliance with the License.
   # You may obtain a copy of the License at
   #
   #      http://www.apache.org/licenses/LICENSE-2.0
   #
   # Unless required by applicable law or agreed to in writing, software
   # distributed under the License is distributed on an "AS IS" BASIS,
   # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
   # See the License for the specific language governing permissions and
   # limitations under the License.
   #
   # SPDX-License-Identifier: Apache-2.0
   -->

Caravel Harness
===============

|License| |Documentation Status| |Build Status|

.. note::

   Documentation for this project is being updated to reflect the changes
   for the new redesigned version of Caravel.

Table of contents
=================

-  `Overview <#overview>`__
-  `Caravel Architecture <#caravel-architecture>`__
-  `Quick Start for User Projects  <#quick-start-for-user-projects>`__

   - `Digital User Project <#digital-user-project>`__
   - `Analog User Project <#analog-user-project>`__

-  `Required Directory Structure <#required-directory-structure>`__
-  `Additional Material <#additional-material>`__

Overview
========

Caravel is a template SoC for Efabless Open MPW and chipIgnite shuttles based on the Sky130 node from SkyWater Technologies. The
current SoC architecture is given below.

.. image:: docs/source/_static/caravel_block_diagram.jpg
    :align: center

Datasheet and detailed documentation exist `here <https://caravel-harness.readthedocs.io/>`__

.. include:: docs/source/getting-started.rst

.. |License| image:: https://img.shields.io/github/license/efabless/caravel
   :alt: GitHub license - Apache 2.0
   :target: https://github.com/efabless/caravel
.. |Documentation Status| image:: https://readthedocs.org/projects/caravel-harness/badge/?version=latest
   :alt: ReadTheDocs Badge - https://caravel-harness.rtfd.io
   :target: https://caravel-harness.readthedocs.io/en/latest/?badge=latest
.. |Build Status| image:: https://travis-ci.com/efabless/caravel.svg?branch=master
   :alt: Travis Badge - https://travis-ci.org/efabless/caravel
   :target: https://travis-ci.com/efabless/caravel