tangxifan
|
decc1dc4b2
|
debugged global gp input/output port support
|
2020-04-05 17:39:30 -06:00 |
|
tangxifan
|
bcb86801fa
|
bug fixed in gpio naming for module manager ports
|
2020-04-05 17:26:44 -06:00 |
|
tangxifan
|
5f4e7dc5d4
|
support gpinput and gpoutput ports in module manager and circuit library
|
2020-04-05 16:52:21 -06:00 |
|
tangxifan
|
bc47b3ca94
|
update verilog module writer to the global spy ports
|
2020-04-05 16:04:13 -06:00 |
|
tangxifan
|
8b583b7917
|
debugging spy port builder in module manager
|
2020-04-05 16:01:25 -06:00 |
|
tangxifan
|
836f722f20
|
start supporting global output ports in module manager
|
2020-04-05 15:19:46 -06:00 |
|
tangxifan
|
63306ce3a0
|
add comments to explain the memory organization in the top-level module
|
2020-04-01 11:05:30 -06:00 |
|
tangxifan
|
ff9cc50527
|
relax I/O circuit model checking to fit AIB interface. Adapt testbench generation for multiple types of I/O pads
|
2020-03-27 20:09:50 -06:00 |
|
tangxifan
|
e601a648cc
|
relax asseration to allow AIB (non-I/O) blocks on the side of FPGA fabrics
|
2020-03-27 19:07:34 -06:00 |
|
tangxifan
|
4bf0a63ae6
|
bug fixed for multiple io types defined in FPGA architectures
|
2020-03-27 16:32:15 -06:00 |
|
tangxifan
|
7c9c2451f2
|
debugging multiple io_types; bug fixed to support I/Os in more flexible location of FPGA fabric
|
2020-03-27 16:03:42 -06:00 |
|
tangxifan
|
329b0a9cf1
|
add options to enable SDC constraints on zero-delay paths
|
2020-03-25 15:55:30 -06:00 |
|
tangxifan
|
4a0128f240
|
minor fix on the SDC format
|
2020-03-25 14:46:31 -06:00 |
|
tangxifan
|
c2e5d6b8e2
|
add options to dsiable SDC for non-clock global ports
|
2020-03-25 14:38:13 -06:00 |
|
tangxifan
|
787dc8ce83
|
added ASCII OpenFPGA logo in shell interface
|
2020-03-25 11:16:04 -06:00 |
|
tangxifan
|
b6bdf78d95
|
bug fixed for heterogeneous block instances in top module
|
2020-03-24 17:39:26 -06:00 |
|
tangxifan
|
9e4e12aae9
|
fixed echo message in the compression rate of gsb uniquifying
|
2020-03-22 16:13:04 -06:00 |
|
tangxifan
|
ff474d87de
|
fixed critical bug in uniquifying GSBs. Now it can guarantee minimum number of unique GSBs
|
2020-03-22 16:11:00 -06:00 |
|
tangxifan
|
fdf6a6bd3e
|
use chan_node_in_edges from rr_gsb in XML writer
|
2020-03-22 15:48:11 -06:00 |
|
tangxifan
|
3958ac2494
|
fix bugs in flow manager on default compress routing problems
|
2020-03-22 15:26:15 -06:00 |
|
tangxifan
|
fc6abc13fd
|
add physical tile utils to identify pins that have Fc=0
|
2020-03-21 21:02:47 -06:00 |
|
tangxifan
|
7b9384f3b2
|
add write_gsb command to shell interface
|
2020-03-21 19:40:26 -06:00 |
|
tangxifan
|
637be076dc
|
adding xml writer for device rr_gsb to help debugging the compress routing; current compress routing is not working
|
2020-03-21 18:49:20 -06:00 |
|
tangxifan
|
9a518e8bb6
|
bug fixed for tileable rr_graph builder for more 4x4 fabrics
|
2020-03-21 18:07:00 -06:00 |
|
tangxifan
|
c0e8d98c6f
|
bug fixed in tile direct builder
|
2020-03-21 12:43:56 -06:00 |
|
tangxifan
|
8f35f191eb
|
use the formalized function in FPGA-SDC to identify direct connection
|
2020-03-21 11:42:00 -06:00 |
|
tangxifan
|
28123b8052
|
remove the direct connected IPIN/OPIN from RR GSB builder
|
2020-03-21 11:38:39 -06:00 |
|
tangxifan
|
682b667a3c
|
minor bug fix for direct connection in FPGA-SDC
|
2020-03-20 21:44:01 -06:00 |
|
tangxifan
|
05ec86430a
|
temp fix for direct connections. Should notify VPR team about this issue: delayless switch is used in direct connection but it is considered as configurable....which is actually NOT!
|
2020-03-20 17:56:03 -06:00 |
|
tangxifan
|
2c0c5a061b
|
spot a bug in assigning rr_switch in tileable routing
|
2020-03-20 16:53:43 -06:00 |
|
tangxifan
|
a46fc9f028
|
add debugging information for tile direct builder
|
2020-03-20 14:59:46 -06:00 |
|
tangxifan
|
808853db0b
|
critical bug fixed for find proper pb_route traceback
|
2020-03-13 12:26:37 -06:00 |
|
tangxifan
|
81e5af464e
|
improve lb_route to avoid routing combinational loops
|
2020-03-12 23:58:56 -06:00 |
|
tangxifan
|
773e6da308
|
Spot a bug in lb router where path finder fail to use low-occupancy node when expanding the tree
|
2020-03-12 22:53:17 -06:00 |
|
tangxifan
|
29450f3472
|
debugging multi-source lb router
|
2020-03-12 20:42:41 -06:00 |
|
tangxifan
|
8921905bec
|
annotate multiple-source and multiple-sink nets from pb to lb router
|
2020-03-12 19:21:13 -06:00 |
|
tangxifan
|
f0b22aaa11
|
Make lb router support multiple sources to be routed
|
2020-03-12 13:44:14 -06:00 |
|
tangxifan
|
c40675ca9d
|
minor code formatting
|
2020-03-12 11:55:25 -06:00 |
|
tangxifan
|
f1e8e78410
|
minor code formatting
|
2020-03-12 11:47:42 -06:00 |
|
tangxifan
|
689c50dff1
|
label the routing status for each sink in lb_router
|
2020-03-12 11:36:31 -06:00 |
|
tangxifan
|
a1f19e776e
|
Add comments to lb router and extract a private function for routing a single net
|
2020-03-12 11:05:38 -06:00 |
|
tangxifan
|
cd50155e29
|
rename variables in lb router
|
2020-03-12 10:24:38 -06:00 |
|
tangxifan
|
17a1c61b9d
|
minor change in variable names in lb_router
|
2020-03-11 21:10:16 -06:00 |
|
tangxifan
|
8e796f152f
|
add comments to lb_router about how-to-use
|
2020-03-11 21:05:06 -06:00 |
|
tangxifan
|
aff73bdd74
|
deployed edge sorting and make it as an option to link_arch command
|
2020-03-08 15:59:53 -06:00 |
|
tangxifan
|
b80e26e711
|
update bitstream generator to use sorted edges
|
2020-03-08 15:36:47 -06:00 |
|
tangxifan
|
5558932762
|
use sorted edges in building routing modules
|
2020-03-08 15:31:41 -06:00 |
|
tangxifan
|
f9499afe04
|
remove unused variable
|
2020-03-08 15:00:01 -06:00 |
|
tangxifan
|
0c7aa2581d
|
update vpr8 version with hotfix on undriven pins in GSB
|
2020-03-08 14:58:56 -06:00 |
|
tangxifan
|
ca92c2717f
|
bug fix for tile directs
|
2020-03-07 16:00:32 -07:00 |
|
tangxifan
|
37423729ec
|
bug fixing for naming the duplicated pins
|
2020-03-07 15:44:57 -07:00 |
|
tangxifan
|
6e83154703
|
move rr_gsb and rr_chan to tileable rr_graph builder
|
2020-03-04 14:14:28 -07:00 |
|
tangxifan
|
4b7d2221d1
|
adapt rr_graph builder utilized functions and move rr_graph utils from openfpga to vpr
|
2020-03-04 13:55:53 -07:00 |
|
tangxifan
|
7fcd27e000
|
now we give explicit instance name to each interconnect inside grid. Thus resolve the problem in sdc writer
|
2020-03-03 12:29:58 -07:00 |
|
tangxifan
|
3241d8bd37
|
put analysis sdc writer online. Minor bug in redudant '/' to be fixed
|
2020-03-02 19:54:18 -07:00 |
|
tangxifan
|
037c7e5c43
|
adapt top-level function for analysis SDC writer
|
2020-03-02 17:58:44 -07:00 |
|
tangxifan
|
24f7416c71
|
adapt analysis SDC writer for grids
|
2020-03-02 17:15:01 -07:00 |
|
tangxifan
|
6474183539
|
adapt analysis SDC writer for routing modules
|
2020-03-02 14:29:58 -07:00 |
|
tangxifan
|
543cff58b9
|
start porting analysis SDC writer
|
2020-03-02 13:44:08 -07:00 |
|
tangxifan
|
a17c14c363
|
clean-up command addition and add fabric bitstream building to sample script
|
2020-03-02 10:39:19 -07:00 |
|
tangxifan
|
aa66042dfb
|
move simulation setting annotation to a separated source file
|
2020-02-29 15:19:02 -07:00 |
|
tangxifan
|
7b18f7cd09
|
now the auto select number of clocks in simulation is online
|
2020-02-29 13:29:16 -07:00 |
|
tangxifan
|
3807a940f4
|
fixed critical bugs in bitstream generation and now we pass microbenchmarks
|
2020-02-28 16:45:50 -07:00 |
|
tangxifan
|
a6c2d2c7d1
|
bug fixed for io location mapping
|
2020-02-28 14:46:01 -07:00 |
|
tangxifan
|
80bb2baae5
|
start verification and bug fixing
|
2020-02-28 14:29:01 -07:00 |
|
tangxifan
|
542fadaaae
|
allow users to use VPR critical path delay in OpenFPGA simulation
|
2020-02-28 12:10:27 -07:00 |
|
tangxifan
|
de8425874c
|
use user defined critical path delay in SDC generation
|
2020-02-28 11:24:39 -07:00 |
|
tangxifan
|
092e10afda
|
bring pnr sdc generator online and fixed minor bugs in bitstream writing
|
2020-02-28 11:14:50 -07:00 |
|
tangxifan
|
e45fa18c4c
|
adapt PnR SDC writer
|
2020-02-28 10:06:35 -07:00 |
|
tangxifan
|
89c51b70e3
|
split sdc option into two categories which will be called by different commands
|
2020-02-28 09:48:58 -07:00 |
|
tangxifan
|
fdcb982903
|
adapt pnr sdc grid writer
|
2020-02-27 21:06:33 -07:00 |
|
tangxifan
|
b4ed931ac6
|
adapt sdc routing writer
|
2020-02-27 20:35:56 -07:00 |
|
tangxifan
|
d136ac236f
|
adapt sdc memory utils
|
2020-02-27 19:39:57 -07:00 |
|
tangxifan
|
78476ca774
|
adapt sdc writer utils
|
2020-02-27 19:36:28 -07:00 |
|
tangxifan
|
8322b1623d
|
start porting SDC generator
|
2020-02-27 19:30:36 -07:00 |
|
tangxifan
|
65c81e14b2
|
add simulation ini file writer
|
2020-02-27 18:01:47 -07:00 |
|
tangxifan
|
ae899f3b11
|
bug fixed for clock names
|
2020-02-27 16:51:55 -07:00 |
|
tangxifan
|
9b769cd8e4
|
bug fix for using renamed i/o names
|
2020-02-27 16:37:20 -07:00 |
|
tangxifan
|
b010fc1983
|
add warning to force formal_verification_top_netlist enabled
|
2020-02-27 13:28:21 -07:00 |
|
tangxifan
|
078f72320f
|
debugging Verilog testbench generator. Bug spotted in using renamed atom_block and clock ports
|
2020-02-27 13:24:26 -07:00 |
|
tangxifan
|
f558405887
|
ported verilog testbench generator online. Split from fabric generator. Testing to be done
|
2020-02-27 12:33:09 -07:00 |
|
tangxifan
|
77529f4957
|
adapt top Verilog testbench generation
|
2020-02-26 21:30:21 -07:00 |
|
tangxifan
|
bb671acac3
|
add formal random Verilog testbench generation
|
2020-02-26 20:58:16 -07:00 |
|
tangxifan
|
e9adb4fdbc
|
add preconfig top module Verilog generation
|
2020-02-26 20:38:01 -07:00 |
|
tangxifan
|
b3796b0818
|
build io location map
|
2020-02-26 19:58:18 -07:00 |
|
tangxifan
|
25e0583636
|
add io location map data structure and start porting verilog testbench generator
|
2020-02-26 17:10:57 -07:00 |
|
tangxifan
|
410dcf6ab6
|
debugged LUT bitstream
|
2020-02-26 11:42:18 -07:00 |
|
tangxifan
|
a26d31b87f
|
make write bitstream online
|
2020-02-26 11:09:23 -07:00 |
|
tangxifan
|
759758421d
|
found the bug in physical pb mode bits and fixed
|
2020-02-25 23:45:49 -07:00 |
|
tangxifan
|
075264e3e3
|
debugging LUT bitstream generation
|
2020-02-25 23:29:16 -07:00 |
|
tangxifan
|
4024ed63cb
|
add truth table build up for physical LUTs
|
2020-02-25 22:39:42 -07:00 |
|
tangxifan
|
2dd80e4830
|
add more methods to acquire physical truth table from physical pb
|
2020-02-25 21:21:44 -07:00 |
|
tangxifan
|
ca038857d3
|
add lut physical truth table to physical pb
|
2020-02-25 13:34:13 -07:00 |
|
tangxifan
|
2d86a02358
|
refactored LUT bitstream generation to use vtr logic
|
2020-02-25 12:45:13 -07:00 |
|
tangxifan
|
2c44c70557
|
bring pb interconnection bitstream generation online
|
2020-02-25 00:28:06 -07:00 |
|
tangxifan
|
04c69d30c2
|
start adding grid bitstream builder. TODO: lut and interconnect bitstream decoding
|
2020-02-24 19:38:02 -07:00 |
|
tangxifan
|
8e9660b816
|
add mapped block fast look-up as placement annotation
|
2020-02-24 16:09:29 -07:00 |
|
tangxifan
|
712eeb1340
|
bring bitstream generator for routing modules online
|
2020-02-23 22:09:46 -07:00 |
|
tangxifan
|
86c7c24701
|
add fabric bitstream generation online
|
2020-02-23 20:58:17 -07:00 |
|
tangxifan
|
8723007f68
|
Bring mux bitstream generation online
|
2020-02-23 20:53:24 -07:00 |
|
tangxifan
|
51439ba3b4
|
add bitstream writer to be integrated
|
2020-02-23 20:40:18 -07:00 |
|
tangxifan
|
2d17395e13
|
start integrating fpga_bitstream. Bring data structures online
|
2020-02-22 23:04:42 -07:00 |
|
tangxifan
|
9583731531
|
add results saver for lb router
|
2020-02-22 22:10:32 -07:00 |
|
tangxifan
|
921bf7dd7b
|
use constant in device annotation
|
2020-02-21 20:45:22 -07:00 |
|
tangxifan
|
926e429374
|
add save repacking results in physical pb
|
2020-02-21 20:39:49 -07:00 |
|
tangxifan
|
12f2888c7c
|
add physical pb data structure and basic allocator
|
2020-02-21 17:47:27 -07:00 |
|
tangxifan
|
b035b4c87f
|
debugged with Lbrouter. Next step is to output routing traces to physical pb data structure
|
2020-02-21 12:16:50 -07:00 |
|
tangxifan
|
1b66e837ba
|
bug fixing for lb router. Add physical mode to default node expanding settings
|
2020-02-21 11:29:00 -07:00 |
|
tangxifan
|
0b0e00b5f4
|
debugging the LbRouter
|
2020-02-20 21:56:15 -07:00 |
|
tangxifan
|
4abaef14b5
|
bug fixed in pb_pin fix-up. This is due to A CRITICAL BUG IN PHYSICAL_TILE PIN MAPPING!!!
|
2020-02-20 20:50:59 -07:00 |
|
tangxifan
|
3e07d7d5e0
|
finish net addition to LbRouter. Found a bug in pb pin fix-up. Need to consider clustered I/O block z offset
|
2020-02-20 20:26:20 -07:00 |
|
tangxifan
|
fdb27c5a6b
|
move lb_rr_graph construction to repack command
|
2020-02-20 13:24:34 -07:00 |
|
tangxifan
|
d8ab5536e1
|
add advanced check codes for lb_rr_graph
|
2020-02-19 21:41:05 -07:00 |
|
tangxifan
|
ed5d83178f
|
add fundamental check codes for LbRRGraph
|
2020-02-19 21:07:31 -07:00 |
|
tangxifan
|
bc27f9dd0c
|
add check codes for nets inside LbRouter
|
2020-02-19 20:34:30 -07:00 |
|
tangxifan
|
43f15e4d6f
|
add methods to LbRouter for nets to be routed and access to routing traceback
|
2020-02-19 16:40:53 -07:00 |
|
tangxifan
|
444b994285
|
flatten the t_net inside LbRouter into internal data
|
2020-02-19 15:37:22 -07:00 |
|
tangxifan
|
2b37fcb296
|
use strong id for nets to be routed in LbRouter
|
2020-02-19 15:09:25 -07:00 |
|
tangxifan
|
2f1bcdd27d
|
use local data to store illegal modes for pb_graph_node inside LbRouter
|
2020-02-19 14:53:35 -07:00 |
|
tangxifan
|
5ccb4adb08
|
refactored LB router main function
|
2020-02-19 11:09:24 -07:00 |
|
tangxifan
|
3d5a15d41e
|
refactored most functions except echo and try_route() in LbRouter
|
2020-02-19 00:07:36 -07:00 |
|
tangxifan
|
80fa6f8a0a
|
refactored skip nets in LbRouter
|
2020-02-18 22:08:51 -07:00 |
|
tangxifan
|
289c869caf
|
refactored expand rt_node in LbRouter
|
2020-02-18 22:01:22 -07:00 |
|
tangxifan
|
c7ef14fc23
|
refactoring node expansion in LbRouter
|
2020-02-18 21:51:03 -07:00 |
|
tangxifan
|
11879d43b4
|
add methods one by one to LbRouter from cluster_router.cpp
|
2020-02-18 19:22:36 -07:00 |
|
tangxifan
|
0310dafe42
|
add accessors to LBRouter
|
2020-02-18 18:35:00 -07:00 |
|
tangxifan
|
1799db810d
|
compilation error fix
|
2020-02-18 17:04:36 -07:00 |
|
tangxifan
|
d58d14df8e
|
start encapsulate the whole lb router in an object
|
2020-02-18 16:50:56 -07:00 |
|
tangxifan
|
ed25ccc70f
|
start refactoring lb router in openfpga namespace
|
2020-02-18 12:00:27 -07:00 |
|
tangxifan
|
6060440b97
|
fine tuning for the verbose output
|
2020-02-17 21:14:15 -07:00 |
|
tangxifan
|
409b3f6896
|
add lb_rr_graph builder for the refactored version
|
2020-02-17 21:11:56 -07:00 |
|
tangxifan
|
8e97443410
|
start working on repack
|
2020-02-17 17:57:43 -07:00 |
|
tangxifan
|
62e4f14e30
|
add lb_rr_graph to device annotation
|
2020-02-17 17:26:27 -07:00 |
|
tangxifan
|
6c69b52ded
|
Add missing file
|
2020-02-17 17:11:29 -07:00 |
|
tangxifan
|
92076c1460
|
refactored lb_rr_graph in the same principle of RRGraph object
|
2020-02-17 16:59:24 -07:00 |
|
tangxifan
|
60f40a9657
|
use constant module manager as much as possible in Verilog writer
|
2020-02-16 16:35:26 -07:00 |
|
tangxifan
|
11775c370b
|
bring FPGA top module verilog writer online. Fabric Verilog generator done
|
2020-02-16 16:18:14 -07:00 |
|
tangxifan
|
e37ac8a098
|
add grid module Verilog writer
|
2020-02-16 16:04:41 -07:00 |
|
tangxifan
|
c20caa1fa3
|
routing module Verilog writer is online
|
2020-02-16 14:47:54 -07:00 |
|
tangxifan
|
c6c3ef71f3
|
adapt all the Verilog submodule writers and bring it onlien
|
2020-02-16 13:35:18 -07:00 |
|
tangxifan
|
99c3712b6f
|
adapt Verilog wire module writer
|
2020-02-16 12:59:37 -07:00 |
|
tangxifan
|
5cc68b0730
|
adapt LUT Verilog writer
|
2020-02-16 12:45:58 -07:00 |
|
tangxifan
|
105ccabecc
|
adapt memroy writer for verilog
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2020-02-16 12:41:43 -07:00 |
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tangxifan
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c9d8120ae0
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adapt Verilog mux writer
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2020-02-16 12:35:41 -07:00 |
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tangxifan
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a88c4bc954
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add decode utils to libopenfpga and adapt local decoder writer in Verilog
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2020-02-16 12:21:59 -07:00 |
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tangxifan
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3efd1a2a6d
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print verilog module writer online
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2020-02-16 12:04:03 -07:00 |
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tangxifan
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cf34339e96
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adapt essential gates for submodule generation
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2020-02-16 11:57:19 -07:00 |
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tangxifan
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2eba882332
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put verilog submodules online. ready to bring the how submodule writer online
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2020-02-16 11:41:20 -07:00 |
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tangxifan
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4cb61e2138
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bring preprocessing flag Verilog netlists online
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2020-02-16 00:03:24 -07:00 |
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tangxifan
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0d5292ad0d
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adapt verilog writer utils
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2020-02-15 23:26:59 -07:00 |