put verilog submodules online. ready to bring the how submodule writer online

This commit is contained in:
tangxifan 2020-02-16 11:41:20 -07:00
parent 4cb61e2138
commit 2eba882332
3 changed files with 304 additions and 24 deletions

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@ -0,0 +1,243 @@
/************************************************
* This file includes most utilized functions for
* generating Verilog sub-modules
* such as timing matrix and signal initialization
***********************************************/
#include <fstream>
#include <limits>
#include <iomanip>
/* Headers from vtrutil library */
#include "vtr_assert.h"
#include "vtr_log.h"
/* Headers from openfpgautil library */
#include "openfpga_port.h"
#include "openfpga_digest.h"
/* Headers from readarchopenfpga library */
#include "circuit_types.h"
#include "module_manager_utils.h"
#include "verilog_constants.h"
#include "verilog_writer_utils.h"
#include "verilog_submodule_utils.h"
/* begin namespace openfpga */
namespace openfpga {
/* All values are printed with this precision value. The higher the
* value, the more accurate timing assignment is. Using a number of 6
* guarentees that a precision of femtosecond which is sufficent for
* electrical simulation (simulation timescale is 10-9
*/
/* constexpr int FLOAT_PRECISION = std::numeric_limits<float>::max_digits10; */
constexpr int FLOAT_PRECISION = 6;
/************************************************
* Print a timing matrix defined in theecircuit model
* into a Verilog format.
* This function print all the timing edges available
* in the circuit model (any pin-to-pin delay)
***********************************************/
void print_verilog_submodule_timing(std::fstream& fp,
const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
/* return if there is no delay info */
if ( 0 == circuit_lib.num_delay_info(circuit_model)) {
return;
}
/* Return if there is no ports */
if (0 == circuit_lib.num_model_ports(circuit_model)) {
return;
}
/* Ensure a valid file handler*/
VTR_ASSERT(true == valid_file_stream(fp));
fp << std::endl;
fp << "`ifdef " << VERILOG_TIMING_PREPROC_FLAG << std::endl;
print_verilog_comment(fp, std::string("------ BEGIN Pin-to-pin Timing constraints -----"));
fp << "\tspecify" << std::endl;
/* Read out pin-to-pin delays by finding out all the edges belonging to a circuit model */
for (const auto& timing_edge : circuit_lib.timing_edges_by_model(circuit_model)) {
CircuitPortId src_port = circuit_lib.timing_edge_src_port(timing_edge);
size_t src_pin = circuit_lib.timing_edge_src_pin(timing_edge);
BasicPort src_port_info(circuit_lib.port_lib_name(src_port), src_pin, src_pin);
CircuitPortId sink_port = circuit_lib.timing_edge_sink_port(timing_edge);
size_t sink_pin = circuit_lib.timing_edge_sink_pin(timing_edge);
BasicPort sink_port_info(circuit_lib.port_lib_name(sink_port), sink_pin, sink_pin);
fp << "\t\t";
fp << "(" << generate_verilog_port(VERILOG_PORT_CONKT, src_port_info);
fp << " => ";
fp << generate_verilog_port(VERILOG_PORT_CONKT, sink_port_info) << ")";
fp << " = ";
fp << "(" << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, CIRCUIT_MODEL_DELAY_RISE) / VERILOG_SIM_TIMESCALE;
fp << ", ";
fp << std::setprecision(FLOAT_PRECISION) << circuit_lib.timing_edge_delay(timing_edge, CIRCUIT_MODEL_DELAY_FALL) / VERILOG_SIM_TIMESCALE << ")";
fp << ";" << std::endl;
}
fp << "\tendspecify" << std::endl;
print_verilog_comment(fp, std::string("------ END Pin-to-pin Timing constraints -----"));
fp << "`endif" << std::endl;
}
void print_verilog_submodule_signal_init(std::fstream& fp,
const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
/* Ensure a valid file handler*/
VTR_ASSERT(true == valid_file_stream(fp));
fp << std::endl;
fp << "`ifdef " << VERILOG_SIGNAL_INIT_PREPROC_FLAG << std::endl;
print_verilog_comment(fp, std::string("------ BEGIN driver initialization -----"));
fp << "\tinitial begin" << std::endl;
fp << "\t`ifdef " << VERILOG_FORMAL_VERIFICATION_PREPROC_FLAG << std::endl;
/* Only for formal verification: deposite a zero signal values */
/* Initialize each input port */
for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) {
BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
fp << "\t\t$deposit(";
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
fp << ", " << circuit_lib.port_size(input_port) << "'b" << std::string(circuit_lib.port_size(input_port), '0');
fp << ");" << std::endl;
}
fp << "\t`else" << std::endl;
/* Regular case: deposite initial signal values: a random value */
for (const auto& input_port : circuit_lib.model_input_ports(circuit_model)) {
BasicPort input_port_info(circuit_lib.port_lib_name(input_port), circuit_lib.port_size(input_port));
fp << "\t\t$deposit(";
fp << generate_verilog_port(VERILOG_PORT_CONKT, input_port_info);
fp << ", $random);" << std::endl;
}
fp << "\t`endif\n" << std::endl;
fp << "\tend" << std::endl;
print_verilog_comment(fp, std::string("------ END driver initialization -----"));
fp << "`endif" << std::endl;
}
/*********************************************************************
* Register all the user-defined modules in the module manager
* Walk through the circuit library and add user-defined circuit models
* to the module_manager
********************************************************************/
void add_user_defined_verilog_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib) {
/* Iterate over Verilog modules */
for (const auto& model : circuit_lib.models()) {
/* We only care about user-defined models */
if (true == circuit_lib.model_verilog_netlist(model).empty()) {
continue;
}
/* Skip Routing channel wire models because they need a different name. Do it later */
if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
continue;
}
/* Reach here, the model requires a user-defined Verilog netlist,
* Try to find it in the module manager
* If not found, register it in the module_manager
*/
ModuleId module_id = module_manager.find_module(circuit_lib.model_name(model));
if (ModuleId::INVALID() == module_id) {
add_circuit_model_to_module_manager(module_manager, circuit_lib, model);
}
}
}
/*********************************************************************
* Print a template for a user-defined circuit model
* The template will include just the port declaration of the Verilog module
* The template aims to help user to write Verilog codes with a guaranteed
* module definition, which can be correctly instanciated (with correct
* port mapping) in the FPGA fabric
********************************************************************/
static
void print_one_verilog_template_module(const ModuleManager& module_manager,
std::fstream& fp,
const std::string& module_name) {
/* Ensure a valid file handler*/
VTR_ASSERT(true == valid_file_stream(fp));
print_verilog_comment(fp, std::string("----- Template Verilog module for " + module_name + " -----"));
/* Find the module in module manager, which should be already registered */
/* TODO: routing channel wire model may have a different name! */
ModuleId template_module = module_manager.find_module(module_name);
VTR_ASSERT(ModuleId::INVALID() != template_module);
/* dump module definition + ports */
print_verilog_module_declaration(fp, module_manager, template_module);
/* Finish dumping ports */
print_verilog_comment(fp, std::string("----- Internal logic should start here -----"));
/* Add some empty lines as placeholders for the internal logic*/
fp << std::endl << std::endl;
print_verilog_comment(fp, std::string("----- Internal logic should end here -----"));
/* Put an end to the Verilog module */
print_verilog_module_end(fp, module_name);
/* Add an empty line as a splitter */
fp << std::endl;
}
/*********************************************************************
* Print a template of all the submodules that are user-defined
* The template will include just the port declaration of the submodule
* The template aims to help user to write Verilog codes with a guaranteed
* module definition, which can be correctly instanciated (with correct
* port mapping) in the FPGA fabric
********************************************************************/
void print_verilog_submodule_templates(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir) {
std::string verilog_fname(submodule_dir + USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME);
/* Create the file stream */
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
check_file_stream(verilog_fname.c_str(), fp);
/* Print out debugging information for if the file is not opened/created properly */
VTR_LOG("Creating template for user-defined Verilog modules '%s'...",
verilog_fname.c_str());
print_verilog_file_header(fp, "Template for user-defined Verilog modules");
print_verilog_include_defines_preproc_file(fp, verilog_dir);
/* Output essential models*/
for (const auto& model : circuit_lib.models()) {
/* Focus on user-defined modules, which must have a Verilog netlist defined */
if (circuit_lib.model_verilog_netlist(model).empty()) {
continue;
}
/* Skip Routing channel wire models because they need a different name. Do it later */
if (CIRCUIT_MODEL_CHAN_WIRE == circuit_lib.model_type(model)) {
continue;
}
/* Print a Verilog template for the circuit model */
print_one_verilog_template_module(module_manager, fp, circuit_lib.model_name(model));
}
/* close file stream */
fp.close();
/* No need to add the template to the subckt include files! */
VTR_LOG("Done\n");
}
} /* end namespace openfpga */

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@ -0,0 +1,37 @@
#ifndef VERILOG_SUBMODULE_UTILS_H
#define VERILOG_SUBMODULE_UTILS_H
/********************************************************************
* Include header files that are required by function declaration
*******************************************************************/
#include <fstream>
#include <string>
#include "module_manager.h"
#include "circuit_library.h"
/********************************************************************
* Function declaration
*******************************************************************/
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_submodule_timing(std::fstream& fp,
const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
void print_verilog_submodule_signal_init(std::fstream& fp,
const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model);
void add_user_defined_verilog_modules(ModuleManager& module_manager,
const CircuitLibrary& circuit_lib);
void print_verilog_submodule_templates(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,
const std::string& submodule_dir);
} /* end namespace openfpga */
#endif

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@ -32,7 +32,7 @@ namespace openfpga {
***********************************************/
void print_verilog_file_header(std::fstream& fp,
const std::string& usage) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
auto end = std::chrono::system_clock::now();
std::time_t end_time = std::chrono::system_clock::to_time_t(end);
@ -54,7 +54,7 @@ void print_verilog_file_header(std::fstream& fp,
*******************************************************************/
void print_verilog_include_netlist(std::fstream& fp,
const std::string& netlist_name) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
fp << "`include \"" << netlist_name << "\"" << std::endl;
}
@ -65,7 +65,7 @@ void print_verilog_include_netlist(std::fstream& fp,
void print_verilog_define_flag(std::fstream& fp,
const std::string& flag_name,
const int& flag_value) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
fp << "`define " << flag_name << " " << flag_value << std::endl;
}
@ -88,7 +88,7 @@ void print_verilog_include_defines_preproc_file(std::fstream& fp,
***********************************************/
void print_verilog_comment(std::fstream& fp,
const std::string& comment) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
fp << "// " << comment << std::endl;
}
@ -98,7 +98,7 @@ void print_verilog_comment(std::fstream& fp,
***********************************************/
void print_verilog_preprocessing_flag(std::fstream& fp,
const std::string& preproc_flag) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
fp << "`ifdef " << preproc_flag << std::endl;
}
@ -107,7 +107,7 @@ void print_verilog_preprocessing_flag(std::fstream& fp,
* Print the endif of a Verilog preprocessing flag
***********************************************/
void print_verilog_endif(std::fstream& fp) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
fp << "`endif" << std::endl;
}
@ -119,7 +119,7 @@ void print_verilog_endif(std::fstream& fp) {
***********************************************/
void print_verilog_module_definition(std::fstream& fp,
const ModuleManager& module_manager, const ModuleId& module_id) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
print_verilog_comment(fp, std::string("----- Verilog module for " + module_manager.module_name(module_id) + " -----"));
@ -183,7 +183,7 @@ void print_verilog_module_definition(std::fstream& fp,
***********************************************/
void print_verilog_module_ports(std::fstream& fp,
const ModuleManager& module_manager, const ModuleId& module_id) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* port type2type mapping */
std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
@ -292,7 +292,7 @@ void print_verilog_module_ports(std::fstream& fp,
***********************************************/
void print_verilog_module_declaration(std::fstream& fp,
const ModuleManager& module_manager, const ModuleId& module_id) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
print_verilog_module_definition(fp, module_manager, module_id);
@ -327,7 +327,7 @@ void print_verilog_module_instance(std::fstream& fp,
const std::map<std::string, BasicPort>& port2port_name_map,
const bool& use_explicit_port_map) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* Check: all the key ports in the port2port_name_map does exist in the child module */
for (const auto& kv : port2port_name_map) {
@ -418,7 +418,7 @@ void print_verilog_module_instance(std::fstream& fp,
***********************************************/
void print_verilog_module_end(std::fstream& fp,
const std::string& module_name) {
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
fp << "endmodule" << std::endl;
print_verilog_comment(fp, std::string("----- END Verilog module for " + module_name + " -----"));
@ -672,7 +672,7 @@ void print_verilog_wire_constant_values(std::fstream& fp,
const BasicPort& output_port,
const std::vector<size_t>& const_values) {
/* Make sure we have a valid file handler*/
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
fp << "\t";
fp << "assign ";
@ -687,7 +687,7 @@ void print_verilog_deposit_wire_constant_values(std::fstream& fp,
const BasicPort& output_port,
const std::vector<size_t>& const_values) {
/* Make sure we have a valid file handler*/
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
fp << "\t";
fp << "$deposit(";
@ -705,7 +705,7 @@ void print_verilog_force_wire_constant_values(std::fstream& fp,
const BasicPort& output_port,
const std::vector<size_t>& const_values) {
/* Make sure we have a valid file handler*/
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
fp << "\t";
fp << "force ";
@ -722,7 +722,7 @@ void print_verilog_wire_connection(std::fstream& fp,
const BasicPort& input_port,
const bool& inverted) {
/* Make sure we have a valid file handler*/
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* Must check: the port width matches */
VTR_ASSERT( input_port.get_width() == output_port.get_width() );
@ -749,7 +749,7 @@ void print_verilog_register_connection(std::fstream& fp,
const BasicPort& input_port,
const bool& inverted) {
/* Make sure we have a valid file handler*/
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* Must check: the port width matches */
VTR_ASSERT( input_port.get_width() == output_port.get_width() );
@ -787,7 +787,7 @@ void print_verilog_buffer_instance(std::fstream& fp,
const BasicPort& instance_input_port,
const BasicPort& instance_output_port) {
/* Make sure we have a valid file handler*/
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* To match the context, Buffer should have only 2 non-global ports: 1 input port and 1 output port */
std::vector<CircuitPortId> buffer_model_input_ports = circuit_lib.model_ports_by_type(buffer_model, CIRCUIT_MODEL_PORT_INPUT, true);
@ -903,7 +903,7 @@ void print_verilog_local_sram_wires(std::fstream& fp,
const e_config_protocol_type sram_orgz_type,
const size_t& port_size) {
/* Make sure we have a valid file handler*/
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* Port size must be at least one! */
if (0 == port_size) {
@ -1013,7 +1013,7 @@ void print_verilog_local_config_bus(std::fstream& fp,
const size_t& instance_id,
const size_t& num_conf_bits) {
/* Make sure we have a valid file handler*/
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
switch(sram_orgz_type) {
case CONFIG_MEM_STANDALONE:
@ -1081,7 +1081,7 @@ void print_verilog_rram_mux_config_bus(std::fstream& fp,
const size_t& num_reserved_conf_bits,
const size_t& num_conf_bits) {
/* Make sure we have a valid file handler*/
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
switch(sram_orgz_type) {
case CONFIG_MEM_STANDALONE:
@ -1236,7 +1236,7 @@ void print_verilog_pulse_stimuli(std::fstream& fp,
const float& pulse_width,
const size_t& flip_value) {
/* Validate the file stream */
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* Config_done signal: indicate when configuration is finished */
fp << "initial" << std::endl;
@ -1280,7 +1280,7 @@ void print_verilog_pulse_stimuli(std::fstream& fp,
const std::vector<size_t>& flip_values,
const std::string& wait_condition) {
/* Validate the file stream */
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* Config_done signal: indicate when configuration is finished */
fp << "initial" << std::endl;
@ -1330,7 +1330,7 @@ void print_verilog_clock_stimuli(std::fstream& fp,
const float& pulse_width,
const std::string& wait_condition) {
/* Validate the file stream */
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* Config_done signal: indicate when configuration is finished */
fp << "initial" << std::endl;
@ -1380,7 +1380,7 @@ void print_verilog_netlist_include_header_file(const std::vector<std::string>& n
std::fstream fp;
fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
valid_file_stream(fp);
VTR_ASSERT(true == valid_file_stream(fp));
/* Generate the descriptions*/
print_verilog_file_header(fp, "Header file to include other Verilog netlists");