adapt memroy writer for verilog
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tangxifan
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c9d8120ae0
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105ccabecc
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@ -42,5 +42,6 @@ constexpr char* CONFIG_PERIPHERAL_VERILOG_FILE_NAME = "config_peripherals.v";
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constexpr char* USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME = "user_defined_templates.v";
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constexpr char* VERILOG_MUX_BASIS_POSTFIX = "_basis";
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constexpr char* VERILOG_MEM_POSTFIX = "_mem";
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#endif
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@ -0,0 +1,195 @@
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/*********************************************************************
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* This file includes functions to generate Verilog submodules for
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* the memories that are affiliated to multiplexers and other programmable
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* circuit models, such as IOPADs, LUTs, etc.
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********************************************************************/
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#include <string>
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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#include "vtr_log.h"
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/* Headers from openfpgautil library */
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#include "openfpga_digest.h"
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#include "mux_graph.h"
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#include "module_manager.h"
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#include "circuit_library_utils.h"
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#include "mux_utils.h"
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#include "openfpga_naming.h"
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#include "verilog_constants.h"
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#include "verilog_writer_utils.h"
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#include "verilog_module_writer.h"
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#include "verilog_memory.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/*********************************************************************
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* Generate Verilog modules for the memories that are used
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* by multiplexers
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*
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* +----------------+
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* mem_in --->| Memory Module |---> mem_out
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* +----------------+
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* | | ... | |
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* v v v v SRAM ports of multiplexer
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* +---------------------+
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* in--->| Multiplexer Module |---> out
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* +---------------------+
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********************************************************************/
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static
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void print_verilog_mux_memory_module(ModuleManager& module_manager,
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const CircuitLibrary& circuit_lib,
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std::fstream& fp,
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const CircuitModelId& mux_model,
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const MuxGraph& mux_graph,
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const bool& use_explicit_port_map) {
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/* Multiplexers built with different technology is in different organization */
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switch (circuit_lib.design_tech_type(mux_model)) {
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case CIRCUIT_MODEL_DESIGN_CMOS: {
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/* Generate module name */
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std::string module_name = generate_mux_subckt_name(circuit_lib, mux_model,
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find_mux_num_datapath_inputs(circuit_lib, mux_model, mux_graph.num_inputs()),
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std::string(VERILOG_MEM_POSTFIX));
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ModuleId mem_module = module_manager.find_module(module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
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/* Write the module content in Verilog format */
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write_verilog_module_to_file(fp, module_manager, mem_module,
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use_explicit_port_map || circuit_lib.dump_explicit_port_map(mux_model));
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/* Add an empty line as a splitter */
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fp << std::endl;
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break;
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}
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case CIRCUIT_MODEL_DESIGN_RRAM:
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/* We do not need a memory submodule for RRAM MUX,
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* RRAM are embedded in the datapath
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* TODO: generate local encoders for RRAM-based multiplexers here!!!
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*/
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break;
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default:
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid design technology of multiplexer '%s'\n",
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circuit_lib.model_name(mux_model).c_str());
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exit(1);
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}
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}
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/*********************************************************************
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* Generate Verilog modules for
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* the memories that are affiliated to multiplexers and other programmable
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* circuit models, such as IOPADs, LUTs, etc.
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*
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* We keep the memory modules separated from the multiplexers and other
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* programmable circuit models, for the sake of supporting
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* various configuration schemes.
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* By following such organiztion, the Verilog modules of the circuit models
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* implements the functionality (circuit logic) only, while the memory Verilog
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* modules implements the memory circuits as well as configuration protocols.
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* For example, the local decoders of multiplexers are implemented in the
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* memory modules.
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* Take another example, the memory circuit can implement the scan-chain or
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* memory-bank organization for the memories.
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********************************************************************/
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void print_verilog_submodule_memories(ModuleManager& module_manager,
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std::vector<std::string>& netlist_names,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib,
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const std::string& verilog_dir,
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const std::string& submodule_dir,
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const bool& use_explicit_port_map) {
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/* Plug in with the mux subckt */
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std::string verilog_fname(submodule_dir + std::string(MEMORIES_VERILOG_FILE_NAME));
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/* Create the file stream */
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std::fstream fp;
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fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
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check_file_stream(verilog_fname.c_str(), fp);
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/* Print out debugging information for if the file is not opened/created properly */
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VTR_LOG("Writing Verilog netlist for memories '%s' ...",
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verilog_fname.c_str());
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print_verilog_file_header(fp, "Memories used in FPGA");
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print_verilog_include_defines_preproc_file(fp, verilog_dir);
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/* Create the memory circuits for the multiplexer */
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for (auto mux : mux_lib.muxes()) {
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const MuxGraph& mux_graph = mux_lib.mux_graph(mux);
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CircuitModelId mux_model = mux_lib.mux_circuit_model(mux);
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/* Bypass the non-MUX circuit models (i.e., LUTs).
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* They should be handled in a different way
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* Memory circuits of LUT includes both regular and mode-select ports
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*/
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if (CIRCUIT_MODEL_MUX != circuit_lib.model_type(mux_model)) {
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continue;
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}
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/* Create a Verilog module for the memories used by the multiplexer */
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print_verilog_mux_memory_module(module_manager, circuit_lib, fp, mux_model, mux_graph, use_explicit_port_map);
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}
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/* Create the memory circuits for non-MUX circuit models.
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* In this case, the memory modules are designed to interface
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* the mode-select ports
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*/
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for (const auto& model : circuit_lib.models()) {
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/* Bypass MUXes, they have already been considered */
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if (CIRCUIT_MODEL_MUX == circuit_lib.model_type(model)) {
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continue;
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}
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/* Bypass those modules without any SRAM ports */
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std::vector<CircuitPortId> sram_ports = circuit_lib.model_ports_by_type(model, CIRCUIT_MODEL_PORT_SRAM, true);
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if (0 == sram_ports.size()) {
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continue;
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}
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/* Find the name of memory module */
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/* Get the total number of SRAMs */
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size_t num_mems = 0;
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for (const auto& port : sram_ports) {
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num_mems += circuit_lib.port_size(port);
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}
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/* Get the circuit model for the memory circuit used by the multiplexer */
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std::vector<CircuitModelId> sram_models;
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for (const auto& port : sram_ports) {
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CircuitModelId sram_model = circuit_lib.port_tri_state_model(port);
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VTR_ASSERT(CircuitModelId::INVALID() != sram_model);
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/* Found in the vector of sram_models, do not update and go to the next */
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if (sram_models.end() != std::find(sram_models.begin(), sram_models.end(), sram_model)) {
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continue;
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}
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/* sram_model not found in the vector, update the sram_models */
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sram_models.push_back(sram_model);
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}
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/* Should have only 1 SRAM model */
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VTR_ASSERT( 1 == sram_models.size() );
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/* Create the module name for the memory block */
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std::string module_name = generate_memory_module_name(circuit_lib, model, sram_models[0], std::string(VERILOG_MEM_POSTFIX));
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ModuleId mem_module = module_manager.find_module(module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(mem_module));
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/* Write the module content in Verilog format */
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write_verilog_module_to_file(fp, module_manager, mem_module,
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use_explicit_port_map || circuit_lib.dump_explicit_port_map(model));
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/* Add an empty line as a splitter */
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fp << std::endl;
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}
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/* Close the file stream */
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fp.close();
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/* Add fname to the netlist name list */
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netlist_names.push_back(verilog_fname);
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VTR_LOG("Done\n");
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}
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} /* end namespace openfpga */
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@ -0,0 +1,31 @@
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#ifndef VERILOG_MEMORY_H
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#define VERILOG_MEMORY_H
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/********************************************************************
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* Include header files that are required by function declaration
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*******************************************************************/
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#include <fstream>
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#include "circuit_library.h"
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#include "mux_graph.h"
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#include "mux_library.h"
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#include "module_manager.h"
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/********************************************************************
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* Function declaration
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*******************************************************************/
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/* begin namespace openfpga */
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namespace openfpga {
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void print_verilog_submodule_memories(ModuleManager& module_manager,
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std::vector<std::string>& netlist_names,
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const MuxLibrary& mux_lib,
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const CircuitLibrary& circuit_lib,
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const std::string& verilog_dir,
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const std::string& submodule_dir,
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const bool& use_explicit_port_map);
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} /* end namespace openfpga */
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#endif
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