adapt Verilog mux writer

openfpga/src/fpga_verilog/verilog_constants.h

@@ -41,4 +41,6 @@ constexpr char* ESSENTIALS_VERILOG_FILE_NAME = "inv_buf_passgate.v";
 constexpr char* CONFIG_PERIPHERAL_VERILOG_FILE_NAME = "config_peripherals.v";
 constexpr char* USER_DEFINED_TEMPLATE_VERILOG_FILE_NAME = "user_defined_templates.v";
 
+constexpr char* VERILOG_MUX_BASIS_POSTFIX = "_basis";
+
 #endif

openfpga/src/fpga_verilog/verilog_mux.h

@@ -0,0 +1,32 @@
+#ifndef VERILOG_MUX_H
+#define VERILOG_MUX_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <fstream>
+#include <vector>
+
+#include "circuit_library.h"
+#include "mux_graph.h"
+#include "mux_library.h"
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_submodule_muxes(ModuleManager& module_manager,
+                                   std::vector<std::string>& netlist_names,
+                                   const MuxLibrary& mux_lib,
+                                   const CircuitLibrary& circuit_lib,
+                                   const std::string& verilog_dir,
+                                   const std::string& submodule_dir,
+                                   const bool& use_explicit_port_map);
+
+} /* end namespace openfpga */
+
+#endif