move lb_rr_graph construction to repack command

openfpga/src/base/openfpga_link_arch.cpp

@@ -15,7 +15,6 @@
 #include "annotate_rr_graph.h"
 #include "mux_library_builder.h"
 #include "build_tile_direct.h"
-#include "build_physical_lb_rr_graph.h"
 #include "openfpga_link_arch.h"
 
 /* Include global variables of VPR */
@@ -112,11 +111,6 @@ void link_arch(OpenfpgaContext& openfpga_ctx,
   /* Build tile direct annotation */
   openfpga_ctx.mutable_tile_direct() =  build_device_tile_direct(g_vpr_ctx.device(),
                                                                  openfpga_ctx.arch().arch_direct);
-
-
-  build_physical_lb_rr_graphs(g_vpr_ctx.device(),
-                              openfpga_ctx.mutable_vpr_device_annotation(),
-                              cmd_context.option_enable(cmd, opt_verbose));
 } 
 
 } /* end namespace openfpga */

openfpga/src/base/openfpga_repack.cpp

@@ -24,7 +24,7 @@ void repack(OpenfpgaContext& openfpga_ctx,
   CommandOptionId opt_verbose = cmd.option("verbose");
 
   pack_physical_pbs(g_vpr_ctx.device(),
-                    openfpga_ctx.vpr_device_annotation(),
+                    openfpga_ctx.mutable_vpr_device_annotation(),
                     openfpga_ctx.mutable_vpr_clustering_annotation(),
                     openfpga_ctx.vpr_routing_annotation(),
                     cmd_context.option_enable(cmd, opt_verbose));

openfpga/src/repack/repack.cpp

@@ -7,6 +7,7 @@
 #include "vtr_assert.h"
 #include "vtr_time.h"
 
+#include "build_physical_lb_rr_graph.h"
 #include "repack.h"
 
 /* begin namespace openfpga */
@@ -16,17 +17,22 @@ namespace openfpga {
  * Top-level function to pack physical pb_graph 
  * This function will do :
  *  - create physical lb_rr_graph for each pb_graph considering physical modes only
- *    the lb_rr_graph willbe added to device annotation
+ *    the lb_rr_graph will be added to device annotation
  *  - annotate nets to be routed for each clustered block from operating modes of pb_graph 
  *    to physical modes of pb_graph
  *  - rerun the routing for each clustered block
  *  - store the packing results to clustering annotation
  ***************************************************************************************/
 void pack_physical_pbs(const DeviceContext& device_ctx,
-                       const VprDeviceAnnotation& device_annotation,
+                       VprDeviceAnnotation& device_annotation,
                        VprClusteringAnnotation& clustering_annotation,
                        const VprRoutingAnnotation& routing_annotation,
                        const bool& verbose) {
+
+  build_physical_lb_rr_graphs(device_ctx,
+                              device_annotation,
+                              verbose);
+
 }
 
 } /* end namespace openfpga */

openfpga/src/repack/repack.h

@@ -17,7 +17,7 @@
 namespace openfpga {
 
 void pack_physical_pbs(const DeviceContext& device_ctx,
-                       const VprDeviceAnnotation& device_annotation,
+                       VprDeviceAnnotation& device_annotation,
                        VprClusteringAnnotation& clustering_annotation,
                        const VprRoutingAnnotation& routing_annotation,
                        const bool& verbose);

openfpga/test_script/s298_k6_frac.openfpga

@@ -21,6 +21,11 @@ lut_truth_table_fixup #--verbose
 #  - Enable pin duplication on grid modules 
 build_fabric --compress_routing --duplicate_grid_pin --verbose
 
+# Repack the netlist to physical pbs
+# This must be done before bitstream generator and testbench generation
+# Strongly recommend it is done after all the fix-up have been applied
+repack --verbose
+
 # Write the Verilog netlit for FPGA fabric
 #  - Enable the use of explicit port mapping in Verilog netlist
 write_fabric_verilog --file /var/tmp/xtang/openfpga_test_src --explicit_port_mapping --include_timing --include_signal_init --support_icarus_simulator --print_user_defined_template --verbose