print verilog module writer online
This commit is contained in:
tangxifan
parent
cf34339e96
commit
3efd1a2a6d
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@ -0,0 +1,502 @@
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/********************************************************************
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* This file includes functions to write a Verilog module
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* based on its definition in Module Manager
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*
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* Note that Verilog writer functions are just an outputter for the
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* module definition.
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* You should NOT modify any content of the module manager
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* Please use const keyword to restrict this!
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*******************************************************************/
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#include <algorithm>
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/* Headers from vtrutil library */
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#include "vtr_assert.h"
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/* Headers from openfpgautil library */
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#include "openfpga_port.h"
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#include "openfpga_digest.h"
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#include "module_manager_utils.h"
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#include "verilog_port_types.h"
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#include "verilog_writer_utils.h"
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#include "verilog_module_writer.h"
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/* begin namespace openfpga */
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namespace openfpga {
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/********************************************************************
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* Generate the name of a local wire for a undriven port inside Verilog
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* module
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*******************************************************************/
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static
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std::string generate_verilog_undriven_local_wire_name(const ModuleManager& module_manager,
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const ModuleId& module,
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const ModulePortId& module_port_id) {
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return module_manager.module_port(module, module_port_id).get_name();
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}
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/********************************************************************
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* Name a net for a local wire for a verilog module
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* 1. If this is a local wire, name it after the <src_module_name>_<instance_id>_<src_port_name>
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* 2. If this is not a local wire, name it after the port name of parent module
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*
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* In addition, it will assign the pin index as well
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*
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* Restriction: this function requires each net has single driver
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* which is definitely always true in circuits.
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*******************************************************************/
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static
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BasicPort generate_verilog_port_for_module_net(const ModuleManager& module_manager,
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const ModuleId& module_id,
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const ModuleNetId& module_net) {
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/* Check all the sink modules of the net,
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* if we have a source module is the current module, this is not local wire
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*/
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for (ModuleNetSrcId src_id : module_manager.module_net_sources(module_id, module_net)) {
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if (module_id == module_manager.net_source_modules(module_id, module_net)[src_id]) {
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/* Here, this is not a local wire, return the port name of the src_port */
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ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[src_id];
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size_t src_pin_index = module_manager.net_source_pins(module_id, module_net)[src_id];
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return BasicPort(module_manager.module_port(module_id, net_src_port).get_name(), src_pin_index, src_pin_index);
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}
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}
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/* Check all the sink modules of the net */
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for (ModuleNetSinkId sink_id : module_manager.module_net_sinks(module_id, module_net)) {
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if (module_id == module_manager.net_sink_modules(module_id, module_net)[sink_id]) {
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/* Here, this is not a local wire, return the port name of the sink_port */
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ModulePortId net_sink_port = module_manager.net_sink_ports(module_id, module_net)[sink_id];
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size_t sink_pin_index = module_manager.net_sink_pins(module_id, module_net)[sink_id];
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return BasicPort(module_manager.module_port(module_id, net_sink_port).get_name(), sink_pin_index, sink_pin_index);
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}
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}
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/* Reach here, this is a local wire */
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std::string net_name;
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/* Each net must only one 1 source */
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VTR_ASSERT(1 == module_manager.net_source_modules(module_id, module_net).size());
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/* Get the source module */
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ModuleId net_src_module = module_manager.net_source_modules(module_id, module_net)[ModuleNetSrcId(0)];
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/* Get the instance id */
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size_t net_src_instance = module_manager.net_source_instances(module_id, module_net)[ModuleNetSrcId(0)];
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/* Get the port id */
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ModulePortId net_src_port = module_manager.net_source_ports(module_id, module_net)[ModuleNetSrcId(0)];
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/* Get the pin id */
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size_t net_src_pin = module_manager.net_source_pins(module_id, module_net)[ModuleNetSrcId(0)];
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/* Load user-defined name if we have it */
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if (false == module_manager.net_name(module_id, module_net).empty()) {
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net_name = module_manager.net_name(module_id, module_net);
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} else {
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net_name = module_manager.module_name(net_src_module);
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net_name += std::string("_") + std::to_string(net_src_instance) + std::string("_");
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net_name += module_manager.module_port(net_src_module, net_src_port).get_name();
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}
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return BasicPort(net_name, net_src_pin, net_src_pin);
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}
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/********************************************************************
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* Find all the nets that are going to be local wires
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* And organize it in a vector of ports
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* Verilog wire writter function will use the output of this function
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* to write up local wire declaration in Verilog format
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*******************************************************************/
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static
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std::map<std::string, std::vector<BasicPort>> find_verilog_module_local_wires(const ModuleManager& module_manager,
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const ModuleId& module_id) {
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std::map<std::string, std::vector<BasicPort>> local_wires;
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/* Local wires come from the child modules */
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for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
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/* Bypass dangling nets:
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* Xifan Tang: I comment this part because it will shadow our problems in creating module graph
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* Indeed this make a robust and a smooth Verilog module writing
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* But I do want the module graph create is nice and clean !!!
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*/
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/*
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if ( (0 == module_manager.net_source_modules(module_id, module_net).size())
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&& (0 == module_manager.net_source_modules(module_id, module_net).size()) ) {
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continue;
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}
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*/
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/* We only care local wires */
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if (false == module_net_is_local_wire(module_manager, module_id, module_net)) {
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continue;
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}
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/* Find the name for this local wire */
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BasicPort local_wire_candidate = generate_verilog_port_for_module_net(module_manager, module_id, module_net);
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/* Cache the net name, try to find it in the cache.
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* If you can find one, it means this port may be mergeable, try to do merging. If merge fail, add to the local wire list
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* If you cannot find one, it means that this port is not mergeable, add to the local wire list immediately.
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*/
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std::map<std::string, std::vector<BasicPort>>::iterator it = local_wires.find(local_wire_candidate.get_name());
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bool merged = false;
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if (it != local_wires.end()) {
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/* Try to merge to one the port in the list that can absorb the current local wire */
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for (BasicPort& local_wire : local_wires[local_wire_candidate.get_name()]) {
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/* check if the candidate can be combined to an existing local wire */
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if (true == two_verilog_ports_mergeable(local_wire, local_wire_candidate)) {
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/* Merge the ports */
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local_wire = merge_two_verilog_ports(local_wire, local_wire_candidate);
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merged = true;
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break;
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}
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}
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}
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/* If not merged/not found in the cache, push the port to the list */
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if (false == merged) {
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local_wires[local_wire_candidate.get_name()].push_back(local_wire_candidate);
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}
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}
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/* Local wires could also happen for undriven ports of child module */
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for (const ModuleId& child : module_manager.child_modules(module_id)) {
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for (size_t instance : module_manager.child_module_instances(module_id, child)) {
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for (const ModulePortId& child_port_id : module_manager.module_ports(child)) {
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BasicPort child_port = module_manager.module_port(child, child_port_id);
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std::vector<size_t> undriven_pins;
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for (size_t child_pin : child_port.pins()) {
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/* Find the net linked to the pin */
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ModuleNetId net = module_manager.module_instance_port_net(module_id, child, instance,
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child_port_id, child_pin);
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/* We only care undriven ports */
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if (ModuleNetId::INVALID() == net) {
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undriven_pins.push_back(child_pin);
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}
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}
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if (true == undriven_pins.empty()) {
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continue;
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}
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/* Reach here, we need a local wire, we will create a port only for the undriven pins of the port! */
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BasicPort instance_port;
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instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child, child_port_id));
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/* We give the same port name as child module, this case happens to global ports */
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instance_port.set_width(*std::min_element(undriven_pins.begin(), undriven_pins.end()),
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*std::max_element(undriven_pins.begin(), undriven_pins.end()));
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local_wires[instance_port.get_name()].push_back(instance_port);
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}
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}
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}
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return local_wires;
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}
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/********************************************************************
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* Print a Verilog wire connection
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* We search all the sinks of the net,
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* if we find a module output, we try to find the next module output
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* among the sinks of the net
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* For each module output (except the first one), we print a wire connection
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*******************************************************************/
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static
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void print_verilog_module_output_short_connection(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const ModuleNetId& module_net) {
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/* Ensure a valid file stream */
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VTR_ASSERT(true == valid_file_stream(fp));
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bool first_port = true;
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BasicPort src_port;
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/* We have found a module input, now check all the sink modules of the net */
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for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
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ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
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if (module_id != sink_module) {
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continue;
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}
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/* Find the sink port and pin information */
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ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
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size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
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BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
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/* For the first module output, this is the source port, we do nothing and go to the next */
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if (true == first_port) {
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src_port = sink_port;
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/* Flip the flag */
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first_port = false;
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continue;
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}
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/* We need to print a wire connection here */
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print_verilog_wire_connection(fp, sink_port, src_port, false);
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}
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}
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/********************************************************************
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* Print a Verilog wire connection
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* We search all the sources of the net,
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* if we find a module input, we try to find a module output
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* among the sinks of the net
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* If we find such a pair, we print a wire connection
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*******************************************************************/
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static
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void print_verilog_module_local_short_connection(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id,
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const ModuleNetId& module_net) {
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/* Ensure a valid file stream */
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VTR_ASSERT(true == valid_file_stream(fp));
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for (ModuleNetSrcId net_src : module_manager.module_net_sources(module_id, module_net)) {
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ModuleId src_module = module_manager.net_source_modules(module_id, module_net)[net_src];
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if (module_id != src_module) {
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continue;
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}
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/* Find the source port and pin information */
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print_verilog_comment(fp, std::string("----- Net source id " + std::to_string(size_t(net_src)) + " -----"));
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ModulePortId src_port_id = module_manager.net_source_ports(module_id, module_net)[net_src];
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size_t src_pin = module_manager.net_source_pins(module_id, module_net)[net_src];
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BasicPort src_port(module_manager.module_port(module_id, src_port_id).get_name(), src_pin, src_pin);
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/* We have found a module input, now check all the sink modules of the net */
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for (ModuleNetSinkId net_sink : module_manager.module_net_sinks(module_id, module_net)) {
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ModuleId sink_module = module_manager.net_sink_modules(module_id, module_net)[net_sink];
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if (module_id != sink_module) {
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continue;
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}
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/* Find the sink port and pin information */
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print_verilog_comment(fp, std::string("----- Net sink id " + std::to_string(size_t(net_sink)) + " -----"));
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ModulePortId sink_port_id = module_manager.net_sink_ports(module_id, module_net)[net_sink];
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size_t sink_pin = module_manager.net_sink_pins(module_id, module_net)[net_sink];
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BasicPort sink_port(module_manager.module_port(module_id, sink_port_id).get_name(), sink_pin, sink_pin);
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/* We need to print a wire connection here */
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print_verilog_wire_connection(fp, sink_port, src_port, false);
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}
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}
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}
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/********************************************************************
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* Print short connections inside a Verilog module
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* The short connection is defined as the direct connection
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* between an input port of the module and an output port of the module
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* This type of connection is not covered when printing Verilog instances
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* Therefore, they are covered in this function
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*
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* module
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* +-----------------------------+
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* | |
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* inputA--->|---------------------------->|--->outputB
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* | |
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* | |
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* | |
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* +-----------------------------+
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*******************************************************************/
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static
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void print_verilog_module_local_short_connections(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id) {
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/* Local wires come from the child modules */
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for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
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/* We only care the nets that indicate short connections */
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if (false == module_net_include_local_short_connection(module_manager, module_id, module_net)) {
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continue;
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}
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print_verilog_comment(fp, std::string("----- Local connection due to Wire " + std::to_string(size_t(module_net)) + " -----"));
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print_verilog_module_local_short_connection(fp, module_manager, module_id, module_net);
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}
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}
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/********************************************************************
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* Print output short connections inside a Verilog module
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* The output short connection is defined as the direct connection
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* between two output ports of the module
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* This type of connection is not covered when printing Verilog instances
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* Therefore, they are covered in this function
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*
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* module
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* +-----------------------------+
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* |
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* src------>+--------------->|--->outputA
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* | |
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* | |
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* +--------------->|--->outputB
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* +-----------------------------+
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*******************************************************************/
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static
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void print_verilog_module_output_short_connections(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& module_id) {
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/* Local wires come from the child modules */
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for (ModuleNetId module_net : module_manager.module_nets(module_id)) {
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/* We only care the nets that indicate short connections */
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if (false == module_net_include_output_short_connection(module_manager, module_id, module_net)) {
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continue;
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}
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print_verilog_module_output_short_connection(fp, module_manager, module_id, module_net);
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}
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}
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/********************************************************************
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* Write a Verilog instance to a file
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* This function will name the input and output connections to
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* the inputs/output or local wires available in the parent module
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*
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* Parent_module
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* +-----------------------------+
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* | |
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* | +--------------+ |
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* | | | |
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* | | child_module | |
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* | | [instance] | |
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* | +--------------+ |
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* | |
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* +-----------------------------+
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*
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*******************************************************************/
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static
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void write_verilog_instance_to_file(std::fstream& fp,
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const ModuleManager& module_manager,
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const ModuleId& parent_module,
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const ModuleId& child_module,
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const size_t& instance_id,
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const bool& use_explicit_port_map) {
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/* Ensure a valid file stream */
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VTR_ASSERT(true == valid_file_stream(fp));
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/* Print module name */
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fp << "\t" << module_manager.module_name(child_module) << " ";
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/* Print instance name:
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* if we have an instance name, use it;
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* if not, we use a default name <name>_<num_instance_in_parent_module>
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*/
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if (true == module_manager.instance_name(parent_module, child_module, instance_id).empty()) {
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fp << module_manager.module_name(child_module) << "_" << instance_id << "_" << " (" << std::endl;
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} else {
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fp << module_manager.instance_name(parent_module, child_module, instance_id) << " (" << std::endl;
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}
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/* Print each port with/without explicit port map */
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/* port type2type mapping */
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std::map<ModuleManager::e_module_port_type, enum e_dump_verilog_port_type> port_type2type_map;
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port_type2type_map[ModuleManager::MODULE_GLOBAL_PORT] = VERILOG_PORT_CONKT;
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port_type2type_map[ModuleManager::MODULE_GPIO_PORT] = VERILOG_PORT_CONKT;
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port_type2type_map[ModuleManager::MODULE_INOUT_PORT] = VERILOG_PORT_CONKT;
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port_type2type_map[ModuleManager::MODULE_INPUT_PORT] = VERILOG_PORT_CONKT;
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port_type2type_map[ModuleManager::MODULE_OUTPUT_PORT] = VERILOG_PORT_CONKT;
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port_type2type_map[ModuleManager::MODULE_CLOCK_PORT] = VERILOG_PORT_CONKT;
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/* Port sequence: global, inout, input, output and clock ports, */
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size_t port_cnt = 0;
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for (const auto& kv : port_type2type_map) {
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for (const ModulePortId& child_port_id : module_manager.module_port_ids_by_type(child_module, kv.first)) {
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BasicPort child_port = module_manager.module_port(child_module, child_port_id);
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if (0 != port_cnt) {
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/* Do not dump a comma for the first port */
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fp << "," << std::endl;
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}
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/* Print port */
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fp << "\t\t";
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/* if explicit port map is required, output the port name */
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if (true == use_explicit_port_map) {
|
||||
fp << "." << child_port.get_name() << "(";
|
||||
}
|
||||
|
||||
/* Create the port name and width to be used by the instance */
|
||||
std::vector<BasicPort> instance_ports;
|
||||
for (size_t child_pin : child_port.pins()) {
|
||||
/* Find the net linked to the pin */
|
||||
ModuleNetId net = module_manager.module_instance_port_net(parent_module, child_module, instance_id,
|
||||
child_port_id, child_pin);
|
||||
BasicPort instance_port;
|
||||
if (ModuleNetId::INVALID() == net) {
|
||||
/* We give the same port name as child module, this case happens to global ports */
|
||||
instance_port.set_name(generate_verilog_undriven_local_wire_name(module_manager, child_module, child_port_id));
|
||||
instance_port.set_width(child_pin, child_pin);
|
||||
} else {
|
||||
/* Find the name for this child port */
|
||||
instance_port = generate_verilog_port_for_module_net(module_manager, parent_module, net);
|
||||
}
|
||||
/* Create the port information for the net */
|
||||
instance_ports.push_back(instance_port);
|
||||
}
|
||||
/* Try to merge the ports */
|
||||
std::vector<BasicPort> merged_ports = combine_verilog_ports(instance_ports);
|
||||
|
||||
/* Print a verilog port by combining the instance ports */
|
||||
fp << generate_verilog_ports(merged_ports);
|
||||
|
||||
/* if explicit port map is required, output the pair of branket */
|
||||
if (true == use_explicit_port_map) {
|
||||
fp << ")";
|
||||
}
|
||||
port_cnt++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Print an end to the instance */
|
||||
fp << ");" << std::endl;
|
||||
}
|
||||
|
||||
/********************************************************************
|
||||
* Write a Verilog module to a file
|
||||
* This is a key function, maybe most frequently called in our Verilog writer
|
||||
* Note that file stream must be valid
|
||||
*******************************************************************/
|
||||
void write_verilog_module_to_file(std::fstream& fp,
|
||||
const ModuleManager& module_manager,
|
||||
const ModuleId& module_id,
|
||||
const bool& use_explicit_port_map) {
|
||||
|
||||
VTR_ASSERT(true == valid_file_stream(fp));
|
||||
|
||||
/* Ensure we have a valid module_id */
|
||||
VTR_ASSERT(module_manager.valid_module_id(module_id));
|
||||
|
||||
/* Print module declaration */
|
||||
print_verilog_module_declaration(fp, module_manager, module_id);
|
||||
|
||||
/* Print an empty line as splitter */
|
||||
fp << std::endl;
|
||||
|
||||
/* Print internal wires */
|
||||
std::map<std::string, std::vector<BasicPort>> local_wires = find_verilog_module_local_wires(module_manager, module_id);
|
||||
for (std::pair<std::string, std::vector<BasicPort>> port_group : local_wires) {
|
||||
for (const BasicPort& local_wire : port_group.second) {
|
||||
fp << generate_verilog_port(VERILOG_PORT_WIRE, local_wire) << ";" << std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
/* Print an empty line as splitter */
|
||||
fp << std::endl;
|
||||
|
||||
/* Print local connection (from module inputs to output! */
|
||||
print_verilog_comment(fp, std::string("----- BEGIN Local short connections -----"));
|
||||
print_verilog_module_local_short_connections(fp, module_manager, module_id);
|
||||
print_verilog_comment(fp, std::string("----- END Local short connections -----"));
|
||||
|
||||
print_verilog_comment(fp, std::string("----- BEGIN Local output short connections -----"));
|
||||
print_verilog_module_output_short_connections(fp, module_manager, module_id);
|
||||
|
||||
print_verilog_comment(fp, std::string("----- END Local output short connections -----"));
|
||||
/* Print an empty line as splitter */
|
||||
fp << std::endl;
|
||||
|
||||
/* Print instances */
|
||||
for (ModuleId child_module : module_manager.child_modules(module_id)) {
|
||||
for (size_t instance : module_manager.child_module_instances(module_id, child_module)) {
|
||||
/* Print an instance */
|
||||
write_verilog_instance_to_file(fp, module_manager, module_id, child_module, instance, use_explicit_port_map);
|
||||
/* Print an empty line as splitter */
|
||||
fp << std::endl;
|
||||
}
|
||||
}
|
||||
|
||||
/* Print an end for the module */
|
||||
print_verilog_module_end(fp, module_manager.module_name(module_id));
|
||||
|
||||
/* Print an empty line as splitter */
|
||||
fp << std::endl;
|
||||
}
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
#ifndef VERILOG_MODULE_WRITER_H
|
||||
#define VERILOG_MODULE_WRITER_H
|
||||
|
||||
/********************************************************************
|
||||
* Include header files that are required by function declaration
|
||||
*******************************************************************/
|
||||
#include <fstream>
|
||||
#include "module_manager.h"
|
||||
|
||||
/********************************************************************
|
||||
* Function declaration
|
||||
*******************************************************************/
|
||||
|
||||
/* begin namespace openfpga */
|
||||
namespace openfpga {
|
||||
|
||||
void write_verilog_module_to_file(std::fstream& fp,
|
||||
const ModuleManager& module_manager,
|
||||
const ModuleId& module_id,
|
||||
const bool& use_explicit_port_map);
|
||||
|
||||
} /* end namespace openfpga */
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue