bring FPGA top module verilog writer online. Fabric Verilog generator done

openfpga/src/fpga_verilog/verilog_api.cpp

@@ -18,7 +18,7 @@
 #include "verilog_submodule.h"
 #include "verilog_routing.h"
 #include "verilog_grid.h"
-//#include "verilog_top_module.h"
+#include "verilog_top_module.h"
 
 /* Header file for this source file */
 #include "verilog_api.h"
@@ -111,14 +111,13 @@ void fpga_fabric_verilog(ModuleManager& module_manager,
                       options.verbose_output());
 
   /* Generate FPGA fabric */
-  //print_verilog_top_module(module_manager, 
-  //                         std::string(vpr_setup.FileNameOpts.ArchFile), 
-  //                         src_dir_path,
-  //                         dump_explicit_verilog);
+  print_verilog_top_module(const_cast<const ModuleManager&>(module_manager), 
+                           src_dir_path,
+                           options.explicit_port_mapping());
 
   /* Given a brief stats on how many Verilog modules have been written to files */
   VTR_LOGV(options.verbose_output(), 
-           "Outputted %lu Verilog modules in total\n", 
+           "Written %lu Verilog modules in total\n", 
            module_manager.num_modules());  
 }
 

openfpga/src/fpga_verilog/verilog_top_module.cpp

@@ -0,0 +1,75 @@
+/********************************************************************
+ * This file includes functions that are used to print the top-level
+ * module for the FPGA fabric in Verilog format
+ *******************************************************************/
+#include <fstream>
+#include <map>
+#include <algorithm>
+
+/* Headers from vtrutil library */
+#include "vtr_assert.h"
+#include "vtr_log.h"
+
+/* Headers from openfpgautil library */
+#include "openfpga_digest.h"
+
+#include "openfpga_naming.h"
+
+#include "verilog_constants.h"
+#include "verilog_writer_utils.h"
+#include "verilog_module_writer.h"
+#include "verilog_top_module.h"
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+/********************************************************************
+ * Print the top-level module for the FPGA fabric in Verilog format
+ * This function will 
+ * 1. name the top-level module
+ * 2. include dependent netlists 
+ *    - User defined netlists
+ *    - Auto-generated netlists
+ * 3. Add the submodules to the top-level graph
+ * 4. Add module nets to connect datapath ports
+ * 5. Add module nets/submodules to connect configuration ports
+ *******************************************************************/
+void print_verilog_top_module(const ModuleManager& module_manager,
+                              const std::string& verilog_dir,
+                              const bool& use_explicit_mapping) {
+  /* Create a module as the top-level fabric, and add it to the module manager */
+  std::string top_module_name = generate_fpga_top_module_name();
+  ModuleId top_module = module_manager.find_module(top_module_name);
+  VTR_ASSERT(true == module_manager.valid_module_id(top_module));
+
+  /* Start printing out Verilog netlists */
+  /* Create the file name for Verilog netlist */
+  std::string verilog_fname(verilog_dir + generate_fpga_top_netlist_name(std::string(VERILOG_NETLIST_FILE_POSTFIX)));
+
+  VTR_LOG("Writing Verilog netlist for top-level module of FPGA fabric '%s'...",
+          verilog_fname.c_str());
+
+  /* Create the file stream */
+  std::fstream fp;
+  fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
+
+  check_file_stream(verilog_fname.c_str(), fp);
+
+  print_verilog_file_header(fp, std::string("Top-level Verilog module for FPGA")); 
+
+  /* Print preprocessing flags */
+  print_verilog_include_defines_preproc_file(fp, verilog_dir);
+
+  /* Write the module content in Verilog format */
+  write_verilog_module_to_file(fp, module_manager, top_module, use_explicit_mapping);
+
+  /* Add an empty line as a splitter */
+  fp << std::endl;
+
+  /* Close file handler */
+  fp.close();
+
+  VTR_LOG("Done\n");
+}
+
+} /* end namespace openfpga */

openfpga/src/fpga_verilog/verilog_top_module.h

@@ -0,0 +1,23 @@
+#ifndef VERILOG_TOP_MODULE_H
+#define VERILOG_TOP_MODULE_H
+
+/********************************************************************
+ * Include header files that are required by function declaration
+ *******************************************************************/
+#include <string>
+#include "module_manager.h"
+
+/********************************************************************
+ * Function declaration
+ *******************************************************************/
+
+/* begin namespace openfpga */
+namespace openfpga {
+
+void print_verilog_top_module(const ModuleManager& module_manager,
+                              const std::string& verilog_dir,
+                              const bool& use_explicit_mapping);
+
+} /* end namespace openfpga */
+
+#endif

openfpga/src/fpga_verilog/verilog_writer_utils.cpp

@@ -1377,9 +1377,6 @@ void print_verilog_netlist_include_header_file(const std::vector<std::string>& n
 
   std::string verilog_fname(std::string(subckt_dir) + std::string(header_file_name));
 
-  VTR_LOG("Writing header file for primitive modules '%s' ...",
-          verilog_fname.c_str());
-
   /* Create the file stream */
   std::fstream fp;
   fp.open(verilog_fname, std::fstream::out | std::fstream::trunc);
@@ -1396,8 +1393,6 @@ void print_verilog_netlist_include_header_file(const std::vector<std::string>& n
 
   /* close file stream */
   fp.close();
-
-  VTR_LOG("Done\n");
 }
 
 } /* end namespace openfpga */