add lut physical truth table to physical pb

openfpga/src/repack/physical_pb.cpp

@@ -50,6 +50,7 @@ PhysicalPbId PhysicalPb::child(const PhysicalPbId& pb,
 
 std::vector<AtomBlockId> PhysicalPb::atom_blocks(const PhysicalPbId& pb) const {
   VTR_ASSERT(true == valid_pb_id(pb));
+  
   return atom_blocks_[pb];
 }
 
@@ -64,6 +65,11 @@ AtomNetId PhysicalPb::pb_graph_pin_atom_net(const PhysicalPbId& pb,
   return AtomNetId::INVALID();
 }
 
+AtomNetlist::TruthTable PhysicalPb::truth_table(const PhysicalPbId& pb) const {
+  VTR_ASSERT(true == valid_pb_id(pb));
+  return truth_tables_[pb];
+}
+
 std::vector<size_t> PhysicalPb::mode_bits(const PhysicalPbId& pb) const {
   VTR_ASSERT(true == valid_pb_id(pb));
   return mode_bits_[pb];
@@ -118,6 +124,13 @@ void PhysicalPb::add_child(const PhysicalPbId& parent,
   parent_pbs_[child] = parent;
 }
 
+void PhysicalPb::set_truth_table(const PhysicalPbId& pb,
+                                 const AtomNetlist::TruthTable& truth_table) {
+  VTR_ASSERT(true == valid_pb_id(pb)); 
+   
+  truth_tables_[pb] = truth_table;
+}
+
 void PhysicalPb::set_mode_bits(const PhysicalPbId& pb,
                                const std::vector<size_t>& mode_bits) {
   VTR_ASSERT(true == valid_pb_id(pb)); 
@@ -128,7 +141,7 @@ void PhysicalPb::set_mode_bits(const PhysicalPbId& pb,
 void PhysicalPb::add_atom_block(const PhysicalPbId& pb,
                                 const AtomBlockId& atom_block) {
   VTR_ASSERT(true == valid_pb_id(pb)); 
-   
+  
   atom_blocks_[pb].push_back(atom_block);
 }
 

openfpga/src/repack/physical_pb.h

@@ -12,7 +12,7 @@
 #include "physical_types.h"
 
 /* Headers from vpr library */
-#include "atom_netlist_fwd.h"
+#include "atom_netlist.h"
 
 #include "physical_pb_fwd.h"
 
@@ -48,6 +48,7 @@ class PhysicalPb {
     std::vector<AtomBlockId> atom_blocks(const PhysicalPbId& pb) const;
     AtomNetId pb_graph_pin_atom_net(const PhysicalPbId& pb,
                                     const t_pb_graph_pin* pb_graph_pin) const;
+    AtomNetlist::TruthTable truth_table(const PhysicalPbId& pb) const;
     std::vector<size_t> mode_bits(const PhysicalPbId& pb) const;
   public: /* Public mutators */
     PhysicalPbId create_pb(const t_pb_graph_node* pb_graph_node);
@@ -56,6 +57,8 @@ class PhysicalPb {
                    const t_pb_type* child_type);
     void add_atom_block(const PhysicalPbId& pb,
                         const AtomBlockId& atom_block);
+    void set_truth_table(const PhysicalPbId& pb,
+                         const AtomNetlist::TruthTable& truth_table);
     void set_mode_bits(const PhysicalPbId& pb,
                        const std::vector<size_t>& mode_bits);
     void set_pb_graph_pin_atom_net(const PhysicalPbId& pb,
@@ -75,6 +78,11 @@ class PhysicalPb {
     vtr::vector<PhysicalPbId, std::map<const t_pb_type*, std::vector<PhysicalPbId>>> child_pbs_;
     vtr::vector<PhysicalPbId, PhysicalPbId> parent_pbs_;
 
+    /* configuration bits 
+     * Truth tables and mode selection
+     */
+    vtr::vector<PhysicalPbId, AtomNetlist::TruthTable> truth_tables_;
+
     vtr::vector<PhysicalPbId, std::vector<size_t>> mode_bits_;
 
     /* Fast lookup */

openfpga/src/utils/lut_utils.cpp

@@ -446,12 +446,12 @@ std::vector<bool> build_single_output_lut_bitstream(const AtomNetlist::TruthTabl
 std::vector<bool> build_frac_lut_bitstream(const CircuitLibrary& circuit_lib,
                                            const MuxGraph& lut_mux_graph, 
                                            const VprDeviceAnnotation& device_annotation, 
-                                           const std::map<t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
+                                           const std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
                                            const size_t& default_sram_bit_value) {
   /* Initialization */
   std::vector<bool> lut_bitstream(lut_mux_graph.num_inputs(), default_sram_bit_value);
 
-  for (const std::pair<t_pb_graph_pin*, AtomNetlist::TruthTable>& element : truth_tables) {
+  for (const std::pair<const t_pb_graph_pin*, AtomNetlist::TruthTable>& element : truth_tables) {
     /* Find the corresponding circuit model output port and assoicated lut_output_mask */
     CircuitPortId lut_model_output_port = device_annotation.pb_circuit_port(element.first->port);
     size_t lut_frac_level = circuit_lib.port_lut_frac_level(lut_model_output_port);

openfpga/src/utils/lut_utils.h

@@ -36,7 +36,7 @@ bool lut_truth_table_use_on_set(const AtomNetlist::TruthTable& truth_table);
 std::vector<bool> build_frac_lut_bitstream(const CircuitLibrary& circuit_lib,
                                            const MuxGraph& lut_mux_graph, 
                                            const VprDeviceAnnotation& device_annotation, 
-                                           const std::map<t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
+                                           const std::map<const t_pb_graph_pin*, AtomNetlist::TruthTable>& truth_tables,
                                            const size_t& default_sram_bit_value);
 
 } /* end namespace openfpga */

openfpga/src/utils/physical_pb_utils.cpp

@@ -244,7 +244,7 @@ void rec_update_physical_pb_from_operating_pb(PhysicalPb& phy_pb,
 
     phy_pb.add_atom_block(physical_pb, atom_blk);
 
-    /* TODO: Iterate over ports and annotate the atom pins */
+    /* Iterate over ports and annotate the atom pins */
     synchronize_primitive_physical_pb_atom_nets(phy_pb, physical_pb,
                                                 pb_graph_node, 
                                                 pb_route,