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use constant module manager as much as possible in Verilog writer

This commit is contained in:
tangxifan 2020-02-16 16:35:26 -07:00
parent 11775c370b
commit 60f40a9657
11 changed files with 28 additions and 23 deletions
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4
openfpga/src/fpga_verilog/verilog_decoders.cpp
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@ -44,7 +44,7 @@ namespace openfpga {
***************************************************************************************/
static
void print_verilog_mux_local_decoder_module(std::fstream& fp,
ModuleManager& module_manager,
const ModuleManager& module_manager,
const DecoderLibrary& decoder_lib,
const DecoderId& decoder) {
/* Get the number of inputs */
@ -161,7 +161,7 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp,
* before running the back-end flow for FPGA fabric
* See more details in the function print_verilog_mux_local_decoder() for more details
***************************************************************************************/
void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,

2
openfpga/src/fpga_verilog/verilog_decoders.h
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@ -20,7 +20,7 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,

8
openfpga/src/fpga_verilog/verilog_essential_gates.cpp
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@ -142,7 +142,7 @@ void print_verilog_invbuf_body(std::fstream& fp,
* or tapered buffer to a file
***********************************************/
static
void print_verilog_invbuf_module(ModuleManager& module_manager,
void print_verilog_invbuf_module(const ModuleManager& module_manager,
std::fstream& fp,
const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
@ -226,7 +226,7 @@ void print_verilog_invbuf_module(ModuleManager& module_manager,
* either transmission-gate or pass-transistor
***********************************************/
static
void print_verilog_passgate_module(ModuleManager& module_manager,
void print_verilog_passgate_module(const ModuleManager& module_manager,
std::fstream& fp,
const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
@ -438,7 +438,7 @@ void print_verilog_mux2_gate_body(std::fstream& fp,
* 3. 2-input MUX
***********************************************/
static
void print_verilog_gate_module(ModuleManager& module_manager,
void print_verilog_gate_module(const ModuleManager& module_manager,
std::fstream& fp,
const CircuitLibrary& circuit_lib,
const CircuitModelId& circuit_model) {
@ -525,7 +525,7 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager
* include inverters, buffers, transmission-gates,
* etc.
***********************************************/
void print_verilog_submodule_essentials(ModuleManager& module_manager,
void print_verilog_submodule_essentials(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const std::string& verilog_dir,
const std::string& submodule_dir,

2
openfpga/src/fpga_verilog/verilog_essential_gates.h
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@ -14,7 +14,7 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_submodule_essentials(ModuleManager& module_manager,
void print_verilog_submodule_essentials(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const std::string& verilog_dir,
const std::string& submodule_dir,

2
openfpga/src/fpga_verilog/verilog_lut.cpp
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@ -29,7 +29,7 @@ namespace openfpga {
* Print Verilog modules for the Look-Up Tables (LUTs)
* in the circuit library
********************************************************************/
void print_verilog_submodule_luts(ModuleManager& module_manager,
void print_verilog_submodule_luts(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,

2
openfpga/src/fpga_verilog/verilog_lut.h
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@ -17,7 +17,7 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_submodule_luts(ModuleManager& module_manager,
void print_verilog_submodule_luts(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,

4
openfpga/src/fpga_verilog/verilog_memory.cpp
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@ -42,7 +42,7 @@ namespace openfpga {
* +---------------------+
********************************************************************/
static
void print_verilog_mux_memory_module(ModuleManager& module_manager,
void print_verilog_mux_memory_module(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
std::fstream& fp,
const CircuitModelId& mux_model,
@ -96,7 +96,7 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager,
* Take another example, the memory circuit can implement the scan-chain or
* memory-bank organization for the memories.
********************************************************************/
void print_verilog_submodule_memories(ModuleManager& module_manager,
void print_verilog_submodule_memories(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,

2
openfpga/src/fpga_verilog/verilog_memory.h
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@ -18,7 +18,7 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_submodule_memories(ModuleManager& module_manager,
void print_verilog_submodule_memories(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const MuxLibrary& mux_lib,
const CircuitLibrary& circuit_lib,

19
openfpga/src/fpga_verilog/verilog_submodule.cpp
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@ -42,13 +42,13 @@ void print_verilog_submodule(ModuleManager& module_manager,
* This should be done prior to other steps in this function,
* because they will be instanciated by other primitive modules
*/
add_user_defined_verilog_modules(module_manager, circuit_lib);
//add_user_defined_verilog_modules(module_manager, circuit_lib);
/* Create a vector to contain all the Verilog netlist names that have been generated in this function */
std::vector<std::string> netlist_names;
print_verilog_submodule_essentials(module_manager,
print_verilog_submodule_essentials(const_cast<const ModuleManager&>(module_manager),
netlist_names,
verilog_dir,
submodule_dir,
@ -58,7 +58,8 @@ void print_verilog_submodule(ModuleManager& module_manager,
/* NOTE: local decoders generation must go before the MUX generation!!!
* because local decoders modules will be instanciated in the MUX modules
*/
print_verilog_submodule_mux_local_decoders(module_manager, netlist_names,
print_verilog_submodule_mux_local_decoders(const_cast<const ModuleManager&>(module_manager),
netlist_names,
mux_lib, circuit_lib,
verilog_dir, submodule_dir);
print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, circuit_lib,
@ -67,23 +68,27 @@ void print_verilog_submodule(ModuleManager& module_manager,
/* LUTes */
print_verilog_submodule_luts(module_manager, netlist_names, circuit_lib,
print_verilog_submodule_luts(const_cast<const ModuleManager&>(module_manager),
netlist_names, circuit_lib,
verilog_dir, submodule_dir,
fpga_verilog_opts.explicit_port_mapping());
/* Hard wires */
print_verilog_submodule_wires(module_manager, netlist_names, circuit_lib,
print_verilog_submodule_wires(const_cast<const ModuleManager&>(module_manager),
netlist_names, circuit_lib,
verilog_dir, submodule_dir);
/* 4. Memories */
print_verilog_submodule_memories(module_manager, netlist_names,
print_verilog_submodule_memories(const_cast<const ModuleManager&>(module_manager),
netlist_names,
mux_lib, circuit_lib,
verilog_dir, submodule_dir,
fpga_verilog_opts.explicit_port_mapping());
/* 5. Dump template for all the modules */
if (true == fpga_verilog_opts.print_user_defined_template()) {
print_verilog_submodule_templates(module_manager, circuit_lib,
print_verilog_submodule_templates(const_cast<const ModuleManager&>(module_manager),
circuit_lib,
verilog_dir, submodule_dir);
}

4
openfpga/src/fpga_verilog/verilog_wire.cpp
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@ -35,7 +35,7 @@ namespace openfpga {
*
*******************************************************************/
static
void print_verilog_wire_module(ModuleManager& module_manager,
void print_verilog_wire_module(const ModuleManager& module_manager,
const CircuitLibrary& circuit_lib,
std::fstream& fp,
const CircuitModelId& wire_model) {
@ -92,7 +92,7 @@ void print_verilog_wire_module(ModuleManager& module_manager,
/********************************************************************
* Top-level function to print wire modules
*******************************************************************/
void print_verilog_submodule_wires(ModuleManager& module_manager,
void print_verilog_submodule_wires(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,

2
openfpga/src/fpga_verilog/verilog_wire.h
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@ -17,7 +17,7 @@
/* begin namespace openfpga */
namespace openfpga {
void print_verilog_submodule_wires(ModuleManager& module_manager,
void print_verilog_submodule_wires(const ModuleManager& module_manager,
std::vector<std::string>& netlist_names,
const CircuitLibrary& circuit_lib,
const std::string& verilog_dir,