From 60f40a965783f2846fd1bb168c8a46522688f788 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 16 Feb 2020 16:35:26 -0700 Subject: [PATCH] use constant module manager as much as possible in Verilog writer --- .../src/fpga_verilog/verilog_decoders.cpp | 4 ++-- openfpga/src/fpga_verilog/verilog_decoders.h | 2 +- .../fpga_verilog/verilog_essential_gates.cpp | 8 ++++---- .../fpga_verilog/verilog_essential_gates.h | 2 +- openfpga/src/fpga_verilog/verilog_lut.cpp | 2 +- openfpga/src/fpga_verilog/verilog_lut.h | 2 +- openfpga/src/fpga_verilog/verilog_memory.cpp | 4 ++-- openfpga/src/fpga_verilog/verilog_memory.h | 2 +- .../src/fpga_verilog/verilog_submodule.cpp | 19 ++++++++++++------- openfpga/src/fpga_verilog/verilog_wire.cpp | 4 ++-- openfpga/src/fpga_verilog/verilog_wire.h | 2 +- 11 files changed, 28 insertions(+), 23 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_decoders.cpp b/openfpga/src/fpga_verilog/verilog_decoders.cpp index 7689d3ed6..e9b9f6d02 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.cpp +++ b/openfpga/src/fpga_verilog/verilog_decoders.cpp @@ -44,7 +44,7 @@ namespace openfpga { ***************************************************************************************/ static void print_verilog_mux_local_decoder_module(std::fstream& fp, - ModuleManager& module_manager, + const ModuleManager& module_manager, const DecoderLibrary& decoder_lib, const DecoderId& decoder) { /* Get the number of inputs */ @@ -161,7 +161,7 @@ void print_verilog_mux_local_decoder_module(std::fstream& fp, * before running the back-end flow for FPGA fabric * See more details in the function print_verilog_mux_local_decoder() for more details ***************************************************************************************/ -void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, +void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager, std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, diff --git a/openfpga/src/fpga_verilog/verilog_decoders.h b/openfpga/src/fpga_verilog/verilog_decoders.h index 41f932932..271e7aa5c 100644 --- a/openfpga/src/fpga_verilog/verilog_decoders.h +++ b/openfpga/src/fpga_verilog/verilog_decoders.h @@ -20,7 +20,7 @@ /* begin namespace openfpga */ namespace openfpga { -void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager, +void print_verilog_submodule_mux_local_decoders(const ModuleManager& module_manager, std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp index c18bece61..a84d02bdf 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.cpp +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.cpp @@ -142,7 +142,7 @@ void print_verilog_invbuf_body(std::fstream& fp, * or tapered buffer to a file ***********************************************/ static -void print_verilog_invbuf_module(ModuleManager& module_manager, +void print_verilog_invbuf_module(const ModuleManager& module_manager, std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { @@ -226,7 +226,7 @@ void print_verilog_invbuf_module(ModuleManager& module_manager, * either transmission-gate or pass-transistor ***********************************************/ static -void print_verilog_passgate_module(ModuleManager& module_manager, +void print_verilog_passgate_module(const ModuleManager& module_manager, std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { @@ -438,7 +438,7 @@ void print_verilog_mux2_gate_body(std::fstream& fp, * 3. 2-input MUX ***********************************************/ static -void print_verilog_gate_module(ModuleManager& module_manager, +void print_verilog_gate_module(const ModuleManager& module_manager, std::fstream& fp, const CircuitLibrary& circuit_lib, const CircuitModelId& circuit_model) { @@ -525,7 +525,7 @@ void print_verilog_constant_generator_module(const ModuleManager& module_manager * include inverters, buffers, transmission-gates, * etc. ***********************************************/ -void print_verilog_submodule_essentials(ModuleManager& module_manager, +void print_verilog_submodule_essentials(const ModuleManager& module_manager, std::vector& netlist_names, const std::string& verilog_dir, const std::string& submodule_dir, diff --git a/openfpga/src/fpga_verilog/verilog_essential_gates.h b/openfpga/src/fpga_verilog/verilog_essential_gates.h index 33ce49c6c..b7f9b519a 100644 --- a/openfpga/src/fpga_verilog/verilog_essential_gates.h +++ b/openfpga/src/fpga_verilog/verilog_essential_gates.h @@ -14,7 +14,7 @@ /* begin namespace openfpga */ namespace openfpga { -void print_verilog_submodule_essentials(ModuleManager& module_manager, +void print_verilog_submodule_essentials(const ModuleManager& module_manager, std::vector& netlist_names, const std::string& verilog_dir, const std::string& submodule_dir, diff --git a/openfpga/src/fpga_verilog/verilog_lut.cpp b/openfpga/src/fpga_verilog/verilog_lut.cpp index 900ef3073..a849c5827 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.cpp +++ b/openfpga/src/fpga_verilog/verilog_lut.cpp @@ -29,7 +29,7 @@ namespace openfpga { * Print Verilog modules for the Look-Up Tables (LUTs) * in the circuit library ********************************************************************/ -void print_verilog_submodule_luts(ModuleManager& module_manager, +void print_verilog_submodule_luts(const ModuleManager& module_manager, std::vector& netlist_names, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, diff --git a/openfpga/src/fpga_verilog/verilog_lut.h b/openfpga/src/fpga_verilog/verilog_lut.h index f5d1345dc..7c8b85b79 100644 --- a/openfpga/src/fpga_verilog/verilog_lut.h +++ b/openfpga/src/fpga_verilog/verilog_lut.h @@ -17,7 +17,7 @@ /* begin namespace openfpga */ namespace openfpga { -void print_verilog_submodule_luts(ModuleManager& module_manager, +void print_verilog_submodule_luts(const ModuleManager& module_manager, std::vector& netlist_names, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, diff --git a/openfpga/src/fpga_verilog/verilog_memory.cpp b/openfpga/src/fpga_verilog/verilog_memory.cpp index 743647d44..de0418481 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.cpp +++ b/openfpga/src/fpga_verilog/verilog_memory.cpp @@ -42,7 +42,7 @@ namespace openfpga { * +---------------------+ ********************************************************************/ static -void print_verilog_mux_memory_module(ModuleManager& module_manager, +void print_verilog_mux_memory_module(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, std::fstream& fp, const CircuitModelId& mux_model, @@ -96,7 +96,7 @@ void print_verilog_mux_memory_module(ModuleManager& module_manager, * Take another example, the memory circuit can implement the scan-chain or * memory-bank organization for the memories. ********************************************************************/ -void print_verilog_submodule_memories(ModuleManager& module_manager, +void print_verilog_submodule_memories(const ModuleManager& module_manager, std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, diff --git a/openfpga/src/fpga_verilog/verilog_memory.h b/openfpga/src/fpga_verilog/verilog_memory.h index 774e6feb9..9d29eb15f 100644 --- a/openfpga/src/fpga_verilog/verilog_memory.h +++ b/openfpga/src/fpga_verilog/verilog_memory.h @@ -18,7 +18,7 @@ /* begin namespace openfpga */ namespace openfpga { -void print_verilog_submodule_memories(ModuleManager& module_manager, +void print_verilog_submodule_memories(const ModuleManager& module_manager, std::vector& netlist_names, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, diff --git a/openfpga/src/fpga_verilog/verilog_submodule.cpp b/openfpga/src/fpga_verilog/verilog_submodule.cpp index c52fc2262..099118e5f 100644 --- a/openfpga/src/fpga_verilog/verilog_submodule.cpp +++ b/openfpga/src/fpga_verilog/verilog_submodule.cpp @@ -42,13 +42,13 @@ void print_verilog_submodule(ModuleManager& module_manager, * This should be done prior to other steps in this function, * because they will be instanciated by other primitive modules */ - add_user_defined_verilog_modules(module_manager, circuit_lib); + //add_user_defined_verilog_modules(module_manager, circuit_lib); /* Create a vector to contain all the Verilog netlist names that have been generated in this function */ std::vector netlist_names; - print_verilog_submodule_essentials(module_manager, + print_verilog_submodule_essentials(const_cast(module_manager), netlist_names, verilog_dir, submodule_dir, @@ -58,7 +58,8 @@ void print_verilog_submodule(ModuleManager& module_manager, /* NOTE: local decoders generation must go before the MUX generation!!! * because local decoders modules will be instanciated in the MUX modules */ - print_verilog_submodule_mux_local_decoders(module_manager, netlist_names, + print_verilog_submodule_mux_local_decoders(const_cast(module_manager), + netlist_names, mux_lib, circuit_lib, verilog_dir, submodule_dir); print_verilog_submodule_muxes(module_manager, netlist_names, mux_lib, circuit_lib, @@ -67,23 +68,27 @@ void print_verilog_submodule(ModuleManager& module_manager, /* LUTes */ - print_verilog_submodule_luts(module_manager, netlist_names, circuit_lib, + print_verilog_submodule_luts(const_cast(module_manager), + netlist_names, circuit_lib, verilog_dir, submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* Hard wires */ - print_verilog_submodule_wires(module_manager, netlist_names, circuit_lib, + print_verilog_submodule_wires(const_cast(module_manager), + netlist_names, circuit_lib, verilog_dir, submodule_dir); /* 4. Memories */ - print_verilog_submodule_memories(module_manager, netlist_names, + print_verilog_submodule_memories(const_cast(module_manager), + netlist_names, mux_lib, circuit_lib, verilog_dir, submodule_dir, fpga_verilog_opts.explicit_port_mapping()); /* 5. Dump template for all the modules */ if (true == fpga_verilog_opts.print_user_defined_template()) { - print_verilog_submodule_templates(module_manager, circuit_lib, + print_verilog_submodule_templates(const_cast(module_manager), + circuit_lib, verilog_dir, submodule_dir); } diff --git a/openfpga/src/fpga_verilog/verilog_wire.cpp b/openfpga/src/fpga_verilog/verilog_wire.cpp index 2ac9e7ffa..4f084fad9 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.cpp +++ b/openfpga/src/fpga_verilog/verilog_wire.cpp @@ -35,7 +35,7 @@ namespace openfpga { * *******************************************************************/ static -void print_verilog_wire_module(ModuleManager& module_manager, +void print_verilog_wire_module(const ModuleManager& module_manager, const CircuitLibrary& circuit_lib, std::fstream& fp, const CircuitModelId& wire_model) { @@ -92,7 +92,7 @@ void print_verilog_wire_module(ModuleManager& module_manager, /******************************************************************** * Top-level function to print wire modules *******************************************************************/ -void print_verilog_submodule_wires(ModuleManager& module_manager, +void print_verilog_submodule_wires(const ModuleManager& module_manager, std::vector& netlist_names, const CircuitLibrary& circuit_lib, const std::string& verilog_dir, diff --git a/openfpga/src/fpga_verilog/verilog_wire.h b/openfpga/src/fpga_verilog/verilog_wire.h index 7d22ae4c8..55c39fb30 100644 --- a/openfpga/src/fpga_verilog/verilog_wire.h +++ b/openfpga/src/fpga_verilog/verilog_wire.h @@ -17,7 +17,7 @@ /* begin namespace openfpga */ namespace openfpga { -void print_verilog_submodule_wires(ModuleManager& module_manager, +void print_verilog_submodule_wires(const ModuleManager& module_manager, std::vector& netlist_names, const CircuitLibrary& circuit_lib, const std::string& verilog_dir,