ea8c36ce6e
upgrade Verilog SB generator using the RRSwitchBlock
2019-05-23 17:37:39 -06:00
4aab93b729
update class rr_switch_block and be ready for updating the downstream verilog generator
2019-05-22 22:04:31 -06:00
502344b13a
add missing files
2019-05-22 12:35:12 -06:00
efbc454cdd
Add Class for RRSwtichBlock and plug-in to replace the old t_sb
2019-05-22 12:34:06 -06:00
ec3b4c86c4
update file organization and be ready for SB/CB class
2019-05-21 12:15:38 -06:00
8186d6dd11
reorganize files and clean some warnings
2019-05-21 10:17:54 -06:00
b185a17359
add routing_channel unique module generation
2019-05-20 22:33:17 -06:00
ceee28226e
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-20 16:47:07 -06:00
8b520349e7
fixed a bug for rram based fpga when using explicit verilog port mapping
2019-05-20 16:44:47 -06:00
4f921b03da
Add travis full path to avoid missing sources
2019-05-16 15:51:10 -06:00
f31339bb5c
Correctly instantiate script variables
2019-05-16 14:30:16 -06:00
57d75520a6
Verilog verification with Travis
2019-05-15 15:57:05 -06:00
e44e228153
Force graphics to false
2019-05-15 15:01:54 -06:00
f940c4fd59
Third try to fix issues with graphics on mac
2019-05-15 13:22:14 -06:00
a55886a4d9
Second try to fix travis autotest adding x11 in macos packages
2019-05-15 09:28:29 -06:00
1961b18d14
Fix CMakeList to avoid MacOS build failure
2019-05-14 18:15:13 -06:00
99beeb48cc
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-13 16:42:27 -06:00
a3656dde45
Add missing Verilog source, Archictecture folder and Testbenches correction
2019-05-13 16:41:35 -06:00
b48a27acf0
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-13 14:45:57 -06:00
2019840d7c
cleaned unused variables
2019-05-13 14:45:02 -06:00
3313eac23b
add rr_chan obj
2019-05-10 22:50:08 -06:00
9c05a4fb0a
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-10 14:09:23 -06:00
ff9b84d800
Bug fix in Icarus requirement
2019-05-10 14:07:32 -06:00
be4643b8a6
updated Verilog generator to use compact CBs and SBs. SPICE generator to be updated
2019-05-10 10:21:06 -06:00
5c646f5de7
fix bugs in routing identification
2019-05-09 21:40:06 -06:00
a9df922412
finish the identification on mirror switch and connection blocks
...
Verilog generator to be updated
2019-05-09 21:31:39 -06:00
a3c3f2b892
developing compact routing hierarchy
2019-05-08 20:49:21 -06:00
4c6639218e
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-08 14:30:33 -06:00
e305e60ee4
minor fix on the shell interface of VPR
2019-05-08 14:29:58 -06:00
4f386de2ef
gen_xxx functions create mem-leaks because the mem is dynamically allocated inside and not freed. TBD later everywhere
2019-05-06 17:25:29 -06:00
7ddfe60721
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-06 16:12:52 -06:00
3b62f8e024
Conversion from s to ns for the loop breaking delays
2019-05-06 16:12:30 -06:00
cd4dc8b2e8
Delete read_xml_arch_file.c
...
Already present in SRC
2019-05-06 12:55:18 -06:00
a5a1a376ab
Modified code for cleaner delay naming convention
2019-05-06 12:52:49 -06:00
e7b1d89985
Change syntax name for loop_breaker_delay_before/after which is more explicit
2019-05-06 12:25:26 -06:00
7c257ebda7
Fix on the makefile which was not targetting the right folder
2019-05-06 12:21:53 -06:00
6e6ae1cc3d
fixed bugs in CMakeLists.txt and Makefile
2019-05-03 23:03:04 -06:00
4e3487b691
Add latest abc and update ace dependence
2019-05-03 18:56:03 -06:00
70b66e0799
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-03 14:22:20 -06:00
7860042276
added before after loop breaker constraining
2019-05-03 14:00:06 -06:00
11cf30b239
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-03 11:54:35 -06:00
5a97e3e602
update Makefile t
2019-05-03 11:48:41 -06:00
4e330ee463
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-05-03 10:43:22 -06:00
921b694400
Bug fix sdc breaking loop of edges outside current interconnect
2019-05-03 10:42:35 -06:00
42f20eda60
Add the user matching for internal register in formal verification script generation
2019-05-03 10:24:02 -06:00
974af5a2ae
Merge branch 'multimode_clb' of https://github.com/LNIS-Projects/OpenFPGA into multimode_clb
2019-04-30 14:30:38 -06:00
42daadee2f
critical bug fixing
2019-04-30 14:30:17 -06:00
1ab4688339
Create no segment constraint in loop_breaker if none is given by user
2019-04-30 12:30:07 -06:00
c46c0fc97d
bug fixing for SDC generator
2019-04-26 14:07:44 -06:00
46d44fa42a
Update VPR7 X2P with new engine
2019-04-26 12:23:47 -06:00
8eeb144f32
Streamline Makefile and Travis for Mac OS
2019-04-10 15:22:20 +08:00
c4b42726c4
fixes easing thehandling by the user.
2019-03-31 07:55:05 -06:00
b06df18a89
Update rr_graph_area.c
2019-03-11 21:46:42 +08:00
213f94ddee
Correct preconfiguration
2019-01-31 16:43:47 -07:00
5e36aa82c5
fixa bug in determining mux structure
2019-01-22 13:54:50 -07:00
f3e7ae0823
Hot fix
2019-01-10 17:37:15 -07:00
b8187bbca5
fix a bug for supporting default circuit_model of LUTs and FFs
2019-01-10 15:10:05 -07:00
4ae3aa517c
go.sh replaces the paths now
2019-01-09 23:16:43 -07:00
510c27f816
Removed commercial scripts, replaced by academia ones
2019-01-09 11:56:07 -07:00
3b4fc16c60
Adding help message on the go.sh
2019-01-09 11:54:28 -07:00
66701838ff
update relative path in ARCH XML
2019-01-08 11:41:24 -07:00
b80e435548
Correct manual testbench generation bug
2019-01-07 18:03:56 -07:00
7ff245448b
Add new benchmark and modify go.sh to use it
2018-12-26 04:24:26 -07:00
21dc8a006f
Change simulator script generation (waves)
2018-12-14 14:40:04 -07:00
ee6b1d6cd6
adapt arch xml and act for demo
2018-12-13 22:46:40 -07:00
3d9e913e4e
add a benchmark fifo
2018-12-12 16:45:33 -07:00
cc5a01d476
Fix waveform generation + add benchmark and update go.sh
2018-12-11 22:21:39 -07:00
a70b0ac9ac
Correct go.sh
2018-12-11 15:51:21 -07:00
317c3b59c9
Update go.sh and upload pip_add.v
2018-12-11 15:47:05 -07:00
fb0992bd85
Update go.sh and Makefile
2018-12-11 15:31:32 -07:00
c2c4e78639
Add pip_add benchmark
2018-12-11 15:29:48 -07:00
f5ea3ff233
Add an autochecked configuration free testbench
2018-12-11 14:44:13 -07:00
72fbd8d6a8
update blif reader to identify clock signals
2018-12-10 13:28:44 -07:00
a69c2e1882
Add security in checking to avoid simulation glitch error
2018-12-10 09:46:16 -07:00
7020d9b4b6
Edit waveform generator + fix clock mapping in autochecked testbench
2018-12-09 15:48:59 -07:00
5e94b7093d
Add scan-chain and timed architecture + update simulation script script (add script for autochecked testbench)
2018-12-08 22:57:54 -07:00
10866d1852
Correct verilog syntax error in autocheck testbench
2018-12-08 17:40:23 -07:00
d716b67e23
Correct syntax error in autocheck testbench
2018-12-08 17:29:56 -07:00
0580d8243f
Add Autochek testbench option
2018-12-08 17:19:12 -07:00
79930982cf
Changed for the naming
2018-12-08 16:19:38 -07:00
4440066565
added the script to launch vpr with picorv
2018-12-08 16:01:58 -07:00
c130404158
add a section for picorv generation through the flow
2018-12-08 11:33:14 -07:00
4cc875a5a5
fix a bug in wired LUT
2018-12-06 18:00:17 -07:00
b3c1018e28
fixed a bug in wired LUT
2018-12-06 16:50:30 -07:00
eebdf7cb10
Add possibility to choose default value for initialization
2018-12-06 15:34:14 -07:00
b6bb419e1d
add a ModelSim option
2018-12-06 14:13:37 -07:00
fe47b3d21f
Changing arch from memory dec to scff. Get the bitstream from go.sh
2018-12-06 14:03:17 -07:00
8281b7346b
Edit auto-generated modelsim script
2018-12-05 16:15:29 -07:00
44b7f7f3d4
Correct sub_modules.v generation to include decoders.v when necessary
2018-12-05 13:52:25 -07:00
dc4accedd9
Add forgottent files + add parameter transmission from verilog_api.c
2018-12-05 11:33:14 -07:00
9a8c7b391a
Add process for modelsim script autogeneration
2018-12-05 09:20:47 -07:00
75d64db0f9
Add verilog header sub_module.v file generation
2018-12-04 18:42:47 -07:00
8ac566ecc0
Add timing and initialization for simulation
2018-12-04 17:32:09 -07:00
70751551b5
fix a bug in wired LUT support
2018-11-30 21:33:31 -07:00
e223868df8
fix bugs for wired LUTs
2018-11-27 12:46:30 -07:00
de2bc18bbb
bugs fixed for shift register benchmark
2018-11-26 16:58:45 -07:00
9611576d6a
Update on the examples to respect the new syntax
2018-11-19 15:50:29 -07:00
861c449606
support wired LUT in FPGA-SPICE and FPGA-Verilog
2018-11-15 15:57:49 -07:00
f7d7a056da
Modification of the fpga_spice_utils
2018-11-15 14:11:55 -07:00
c81d00bb51
Correction of the double free bug
2018-11-15 13:55:16 -07:00
e0c2fc2c8a
Documentation_code&example_update
2018-10-12 15:50:09 -06:00
c67ba5f58a
clean up codes
2018-09-27 14:26:08 -06:00
31c3eba111
ReadMe modifications to add the beginning of the FPGA-SPICE tutorial
...
Modifications on the addresses aswell and the different commands when they were not working.
To do still:
-create a script to change the addresses when needed
-continue the tutorial
2018-09-27 09:33:39 -06:00
681cca99a4
fix a bug in tapbuf
2018-09-21 19:00:22 -06:00
d683134b12
rename customized vpr7 to vpr7 XML to Production
2018-09-17 23:10:45 -06:00
tangxifan
giacomin
AurelienUoU
Baudouin Chauviere
BaudouinChauviere
Baudouin Chauviere
Aurelien Alacchi