Eddie Hung
b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass
...
add a command to read/modify scratchpad contents
2019-12-18 13:55:44 -05:00
Marcin Kościelnicki
f382164d6e
tests/xilinx: fix flaky mux test
2019-12-18 15:53:29 +01:00
Marcin Kościelnicki
a235250403
xilinx: Add xilinx_dffopt pass ( #1557 )
2019-12-18 13:43:43 +01:00
Marcin Kościelnicki
aff6ad1ce0
xilinx: Improve flip-flop handling.
...
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
2019-12-18 13:43:43 +01:00
Eddie Hung
a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
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xilinx: add LUTRAM rules for RAM32M, RAM64M
2019-12-16 21:48:21 -08:00
Eddie Hung
aed67dd020
abc9 needs a clean afterwards
2019-12-16 18:42:23 -08:00
Eddie Hung
378d9e6e0c
Add another test
2019-12-16 13:57:55 -08:00
Eddie Hung
db0003410f
Accidentally commented out tests
2019-12-16 13:31:47 -08:00
Eddie Hung
5a00d5578c
Add unconditional match blocks for force RAM
2019-12-16 13:31:15 -08:00
Eddie Hung
e990c013c5
Merge blockram tests
2019-12-16 13:01:51 -08:00
Diego H
87e21b0122
Fixing compiler warning/issues. Moving test script to the correct place
2019-12-16 10:23:45 -06:00
N. Engelhardt
abcd82daca
add assert option to scratchpad command
2019-12-16 14:00:21 +01:00
Diego H
f3f59910eb
Removing fixed attribute value to !ramstyle rules
2019-12-15 23:51:58 -06:00
Diego H
b35559fc33
Merging attribute rules into a single match block; Adding tests
2019-12-15 23:33:09 -06:00
Eddie Hung
a5764a1236
Disable RAM16X1D test
2019-12-13 10:28:13 -08:00
Eddie Hung
d86d073ad6
Add testcase
2019-12-13 10:26:30 -08:00
Diego H
1c96345587
Renaming BRAM memory tests for the sake of uniformity
2019-12-13 09:33:18 -06:00
Eddie Hung
d0ee4cd88f
Remove extraneous synth_xilinx call
2019-12-12 19:00:26 -08:00
Eddie Hung
01116f0f0a
Add tests for these new models
2019-12-12 18:52:48 -08:00
Eddie Hung
037d1a03df
Add #1460 testcase
2019-12-12 17:49:55 -08:00
Eddie Hung
caab66111e
Rename memory tests to lutram, add more xilinx tests
2019-12-12 17:44:37 -08:00
Diego H
751a18d7e9
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
2019-12-12 17:32:58 -06:00
Eddie Hung
bea15b537b
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-12 14:57:17 -08:00
Eddie Hung
47ac1b01e6
Add test
2019-12-12 14:43:13 -08:00
Diego H
e33f407655
Adding a note (TODO) in the memory_params.ys check file
2019-12-12 16:06:46 -06:00
N. Engelhardt
1187e91c2f
add test and make help message more verbose
2019-12-12 20:51:59 +01:00
Diego H
937ec1ee78
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
2019-12-12 13:50:36 -06:00
Eddie Hung
23fcfd0adb
Make SV2017 compliant courtesy of @wsnyder
2019-12-12 07:34:07 -08:00
Eddie Hung
4a80510877
Even more obvious testcase
2019-12-11 23:52:05 -08:00
Eddie Hung
61a1f3f49b
Make testcase clearer with \o having its own init
2019-12-11 23:48:09 -08:00
Eddie Hung
151f7533e8
Add testcase
2019-12-11 16:52:37 -08:00
Eddie Hung
e75ca29b19
Add test: 'Warning: ignoring initial value on non-register: \o'
2019-12-11 11:26:54 -08:00
Eddie Hung
7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
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Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
2019-12-09 17:38:48 -08:00
Eddie Hung
eff858cd33
unmap $__ICE40_CARRY_WRAPPER in test
2019-12-09 14:20:35 -08:00
Eddie Hung
e05372778a
ice40_wrapcarry to really preserve attributes via -unwrap option
2019-12-09 11:48:28 -08:00
Miodrag Milanovic
49c9b63e0f
Fix for non-deterministic test
2019-12-07 11:09:25 +01:00
Eddie Hung
a46a7e8a67
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-12-06 23:22:52 -08:00
Eddie Hung
946d5854c0
Drop keep=0 attributes on SB_CARRY
2019-12-06 17:27:47 -08:00
Jan Kowalewski
dcb30b5f4a
tests: arch: xilinx: Change order of arguments in macc.sh
2019-12-06 09:15:49 +01:00
Eddie Hung
d8fbf88980
Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER
2019-12-05 07:01:02 -08:00
Eddie Hung
19bc429482
abc9_map.v to transform INIT=1 to INIT=0
2019-12-04 21:36:41 -08:00
Marcin Kościelnicki
2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. ( #1527 )
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The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
2019-12-04 08:44:08 +01:00
Eddie Hung
67f1ce2d43
Check SB_CARRY name also preserved
2019-12-03 14:51:39 -08:00
Eddie Hung
8de17877d4
Add testcase
2019-12-03 14:48:00 -08:00
Clifford Wolf
2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit
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Gowin: add and test DFF init values
2019-12-03 08:43:18 -08:00
Pepijn de Vos
a7d34a7cb5
update test
2019-12-03 16:56:15 +01:00
Pepijn de Vos
a3b25b4af8
Use -match-init to not synth contradicting init values
2019-12-03 15:12:25 +01:00
David Shah
e9ce4e658b
abc9: Fix breaking of SCCs
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Signed-off-by: David Shah <dave@ds0.me>
2019-12-01 20:44:56 +00:00
Eddie Hung
c61186dd9d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 13:24:03 -08:00
Eddie Hung
ff1e357682
Add multiple driver testcase
2019-11-27 13:22:26 -08:00
Eddie Hung
4bac6b13be
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-27 10:17:10 -08:00
Eddie Hung
6464dc35ec
Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladd
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xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
2019-11-27 08:00:22 -08:00
Clifford Wolf
f43c0bd8ba
Merge pull request #1534 from YosysHQ/mwk/opt_share-fix
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opt_share: Fix handling of fine cells.
2019-11-27 11:23:16 +01:00
Eddie Hung
f6c0ec1d09
Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff
2019-11-27 01:03:33 -08:00
Eddie Hung
6338615aa1
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-27 01:02:16 -08:00
Eddie Hung
8c813632b6
Revert "submod to bitty rather bussy, for bussy wires used as input and output"
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This reverts commit cba3073026
.
2019-11-27 00:48:22 -08:00
Eddie Hung
6318e3ce6d
Fix wire width
2019-11-26 23:38:49 -08:00
Eddie Hung
de3476cc23
No need for -abc9
2019-11-26 23:08:14 -08:00
Marcin Kościelnicki
fdcbda195b
opt_share: Fix handling of fine cells.
...
Fixes #1525 .
2019-11-27 08:01:07 +01:00
Eddie Hung
4a0198128e
Add citation
2019-11-26 22:51:16 -08:00
Eddie Hung
15042eaf57
Remove notes
2019-11-26 22:41:35 -08:00
Eddie Hung
222e199b73
Add testcase derived from fastfir_dynamictaps benchmark
2019-11-26 21:26:30 -08:00
Eddie Hung
dd317c9280
Add testcase where \init is copied
2019-11-25 16:07:35 -08:00
Eddie Hung
d087024caf
Merge remote-tracking branch 'origin/master' into xaig_dff
2019-11-25 12:42:09 -08:00
Marcin Kościelnicki
6cdea425b8
clkbufmap: Add support for inverters in clock path.
2019-11-25 20:40:39 +01:00
Marcin Kościelnicki
7562e7304e
xilinx: Use INV instead of LUT1 when applicable
2019-11-25 20:40:39 +01:00
Pepijn de Vos
72d03dc910
attempt to fix formatting
2019-11-25 14:50:34 +01:00
Pepijn de Vos
6c79abbf5a
gowin: add and test dff init values
2019-11-25 14:33:21 +01:00
Eddie Hung
b46e636c91
Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff
2019-11-23 08:38:48 -08:00
Eddie Hung
d223e11a72
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 22:28:35 -08:00
Eddie Hung
5cd3d3db0a
Remove redundant flatten
2019-11-22 22:28:10 -08:00
Eddie Hung
08f85e6438
Stray dump
2019-11-22 20:53:48 -08:00
Eddie Hung
2c5dfd802d
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 17:24:45 -08:00
Eddie Hung
4fdcf8f7d7
Add another test with constant driver
2019-11-22 17:23:34 -08:00
Eddie Hung
74ea438136
Add testcase for signal used as part input part output
2019-11-22 16:52:55 -08:00
Eddie Hung
0806b8e398
Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff
2019-11-22 16:50:56 -08:00
Eddie Hung
8779faf789
Cleanup spacing
2019-11-22 16:50:09 -08:00
Eddie Hung
2ef2e2c040
Add testcase
2019-11-22 16:48:11 -08:00
Eddie Hung
bd56161775
Merge branch 'eddie/clkpart' into xaig_dff
2019-11-22 15:38:48 -08:00
Eddie Hung
c761fa49b7
Missing endmodule
2019-11-22 12:37:57 -08:00
Clifford Wolf
72d2ef6fd0
Merge pull request #1511 from YosysHQ/dave/always
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sv: Error checking for always_comb, always_latch and always_ff
2019-11-22 15:32:29 +01:00
Marcin Kościelnicki
e110df9c48
gowin: Remove show command from tests.
2019-11-22 14:49:35 +01:00
Eddie Hung
6841e3b1c2
Another sloppy mistake!
2019-11-21 16:33:20 -08:00
Eddie Hung
fe36275234
Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff
2019-11-21 16:32:52 -08:00
Eddie Hung
39fdcb892b
async2sync -> clk2fflogic
2019-11-21 16:27:34 -08:00
Eddie Hung
5a30e3ac3b
Merge branch 'eddie/xaig_dff_adff' into xaig_dff
2019-11-21 16:15:25 -08:00
Eddie Hung
911a152b39
Add test
2019-11-21 16:13:28 -08:00
David Shah
49b670ca38
sv: Add tests for SV always types
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Signed-off-by: David Shah <dave@ds0.me>
2019-11-21 21:06:28 +00:00
Eddie Hung
cd9e830b67
Add multi clock test
2019-11-20 13:28:55 -08:00
Eddie Hung
1cc106452f
Add a equiv test too
2019-11-19 17:05:14 -08:00
Eddie Hung
90c5ca330c
Add two tests
2019-11-19 16:57:58 -08:00
Clifford Wolf
7ea0a5937b
Merge pull request #1449 from pepijndevos/gowin
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Improvements for gowin support
2019-11-19 17:29:27 +01:00
Marcin Kościelnicki
15232a48af
Fix #1462 , #1480 .
2019-11-19 08:57:39 +01:00
Marcin Kościelnicki
38e72d6e13
Fix #1496 .
2019-11-18 04:16:48 +01:00
Pepijn de Vos
32f0296df1
Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin
2019-11-16 12:43:17 +01:00
Pepijn de Vos
ab8c521030
fix fsm test with proper clock enable polarity
2019-11-11 17:51:26 +01:00
Miodrag Milanovic
3e0ffe05a7
Fixed tests
2019-11-11 15:41:33 +01:00
Pepijn de Vos
0e5dbc4abc
fix wide luts
2019-11-06 19:48:18 +01:00
Pepijn de Vos
df8390f5df
don't cound exact luts in big muxes; futile and fragile
2019-10-30 14:58:25 +01:00
Pepijn de Vos
903f997391
add tristate buffer and test
2019-10-28 15:18:01 +01:00
Pepijn de Vos
9517525224
do not use wide luts in testcase
2019-10-28 14:40:12 +01:00
Pepijn de Vos
8226f2db0b
ALU sim tweaks
2019-10-24 13:39:43 +02:00
Pepijn de Vos
83fbfe0964
Add some tests
...
Copied from Efinix.
* fsm is broken
* latch and tribuf are not implemented yet
* memory maps to dram
2019-10-21 16:25:15 +02:00
Miodrag Milanovic
190b40341a
fixed error
2019-10-18 13:15:36 +02:00
Miodrag Milanovic
9bd9db56c8
Unify verilog style
2019-10-18 12:50:24 +02:00
Miodrag Milanovic
12383f37b2
Common memory test now shared
2019-10-18 12:33:35 +02:00
Miodrag Milanovic
477702b8c9
Remove not needed tests
2019-10-18 12:20:35 +02:00
Miodrag Milanovic
5603595e5c
Share common tests
2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf
fix yosys path
2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675
Fix path to yosys
2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00
Miodrag Milanovic
3c41599ee1
Add async2sync
2019-10-18 11:00:27 +02:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix
2019-10-18 10:54:28 +02:00
Miodrag Milanović
66fca65b58
Merge branch 'master' into mmicko/anlogic
2019-10-18 10:53:56 +02:00
Miodrag Milanović
0b0b0cc0d9
Merge branch 'master' into eddie/pr1352
2019-10-18 10:52:50 +02:00
Miodrag Milanovic
b659082e4a
hierarchy - proc reorder
2019-10-18 09:13:06 +02:00
Miodrag Milanovic
46af9a0ff7
hierarchy - proc reorder
2019-10-18 09:06:43 +02:00
Miodrag Milanovic
0d60902fd9
hierarchy - proc reorder
2019-10-18 09:04:02 +02:00
Miodrag Milanovic
e6ad714d20
hierarchy - proc reorder
2019-10-18 08:06:57 +02:00
Miodrag Milanovic
980df499ab
Make equivalence work with latest master
2019-10-17 17:24:53 +02:00
Miodrag Milanovic
b2f0d75807
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
1a399c6456
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
a198bcdd4f
split muxes synth per type
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
36af102801
Test dffs separetely
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
487b38b124
Split latches into separete tests
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
fba6229718
Fix formatting
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
53bc499a90
Clean verilog code from not used define block
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
d37cd267a5
Removed alu and div_mod test as agreed, ignore generated files
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
a7fbc8c3fe
Test per flip-flop type
2019-10-17 17:10:42 +02:00
Eddie Hung
3b44084320
Add -assert
2019-10-17 17:10:42 +02:00
Eddie Hung
8422ad3e3a
Use built-in async2sync call as per #1417
2019-10-17 17:10:42 +02:00
Eddie Hung
5b7bc3ab85
Update mul test to DSP48E1
2019-10-17 17:10:02 +02:00
Eddie Hung
08bd1816e3
Update area for div_mod
2019-10-17 17:10:02 +02:00
Eddie Hung
a12801843b
Add comment for lack of tristate logic pointing to #1225
2019-10-17 17:10:02 +02:00
Eddie Hung
eded90b6b4
Move $x to end as 7f0eec8
2019-10-17 17:10:02 +02:00
SergeyDegtyar
305672170b
adffs test update (equiv_opt -multiclock)
2019-10-17 17:10:02 +02:00
Sergey
bb70eb977d
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
68f9239c57
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
df6d0b95da
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
c340d54657
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
205f52ffe5
Fix div_mod test
2019-10-17 17:10:02 +02:00
Sergey
df7fe40529
Fix div_mod test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
7bc8f0c2e2
Add comment with expected behavior for latches,tribuf tests;Update adffs test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
489444bcba
Fix latches.ys test
2019-10-17 17:10:02 +02:00
SergeyDegtyar
6331fa5b02
Remove xilinx_ug901 tests (will be moved to yosys-tests)
2019-10-17 17:10:02 +02:00
SergeyDegtyar
757c476f62
Add smoke tests to tests/xilinx
2019-10-17 17:10:02 +02:00
SergeyDegtyar
ca7a58bcc8
Add comments for unproven cells.
2019-10-17 17:08:38 +02:00
SergeyDegtyar
2ae7dec530
Add tests for Xilinx UG901 examples
2019-10-17 17:08:38 +02:00
Clifford Wolf
e84cedfae4
Use "(id)" instead of "id" for types as temporary hack
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-14 05:24:31 +02:00
Eddie Hung
3fb604c75d
Revert "Add test that is expecting to fail"
...
This reverts commit c28d4b8047
.
2019-10-08 12:41:26 -07:00