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1005 Commits

Author SHA1 Message Date
Eddie Hung 03ce2c72bb Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-15 16:42:16 -08:00
Eddie Hung 5918ede9bd abc9: aAdd test to check $_NOT_s are absorbed 2020-01-15 14:36:05 -08:00
Eddie Hung e30b6bbbf8 clk2fflogic: work for bit-level $_DFF_* and $_DFFSR_* 2020-01-15 09:51:31 -08:00
Eddie Hung 53a99ade9c Merge remote-tracking branch 'origin/master' into eddie/abc9_refactor 2020-01-14 11:46:56 -08:00
Eddie Hung 61ffd2d199
Merge pull request #1633 from YosysHQ/eddie/fix_autoname 
autoname: do not rename ports
 2020-01-14 11:40:54 -08:00
Eddie Hung 9fa0e03cc9
Merge pull request #1632 from YosysHQ/eddie/fix1630 
read_aiger: uniquify wires with $aiger<autoidx> prefix
 2020-01-14 11:40:40 -08:00
Miodrag Milanović 9fbeb57bbd
Merge pull request #1623 from YosysHQ/mmicko/edif_attr 
Export wire properties in EDIF
 2020-01-14 19:19:32 +01:00
Eddie Hung 00964e999d autoname: add testcase with $-prefix-ed port 2020-01-14 10:13:03 -08:00
Eddie Hung 565d349dc9 Add #1630 testcase 2020-01-13 21:27:53 -08:00
Eddie Hung a6d4ea7463 abc9: respect (* keep *) on cells 2020-01-13 19:21:11 -08:00
Eddie Hung 9ec948f396 write_xaiger: add support and test for (* keep *) on wires 2020-01-13 19:07:55 -08:00
Eddie Hung ca2f3db53f
Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad 
abc9: add some scripts/options into "scratchpad"
 2020-01-13 09:04:20 -08:00
Eddie Hung ae619ba87a Add #1626 testcase 2020-01-12 15:21:26 -08:00
Eddie Hung c063436eea Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad 2020-01-11 17:02:20 -08:00
Miodrag Milanovic ccfe1e5909 this one is fine 2020-01-10 15:20:50 +01:00
Miodrag Milanovic af852a0ea8 Fix tests 2020-01-10 14:48:01 +01:00
Eddie Hung a10016ccc5 Add abc9 sanity test 2020-01-09 18:17:06 -08:00
Eddie Hung 94ab3791ce Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs 2020-01-07 15:44:18 -08:00
Eddie Hung 0d3f10d3cc Add testcases 2020-01-07 11:44:20 -08:00
Eddie Hung 7c878bf397 tests/aiger: write Yosys output 2020-01-07 11:44:03 -08:00
Eddie Hung 3df869cc7c Add testcase from #1459 2020-01-06 16:22:22 -08:00
Eddie Hung 6e866030c2 Combine tests to check multiple clock domains 2020-01-02 14:38:59 -08:00
Eddie Hung b454735bea Merge remote-tracking branch 'origin/master' into xaig_dff 2020-01-02 12:44:06 -08:00
Eddie Hung 9e5ff30d05
Merge pull request #1606 from YosysHQ/eddie/improve_tests 
Fix a few issues in tests/arch/*
 2020-01-01 13:31:46 -08:00
Eddie Hung 52fe1e0c44 Revert insertion of 'reg', leave note behind 2020-01-01 09:05:46 -08:00
Miodrag Milanovic a1344ec06e Added a test case 2020-01-01 16:24:30 +01:00
Eddie Hung 713484fa66 Do not do call equiv_opt when no sim model exists 2019-12-31 18:40:30 -08:00
Eddie Hung a59016b146 Fix warnings 2019-12-31 18:40:11 -08:00
Eddie Hung c082329af3 Call equiv_opt with -multiclock and -assert 2019-12-31 18:39:32 -08:00
Eddie Hung ccc0a740d2 Add some abc9 dff tests 2019-12-31 16:16:05 -08:00
Eddie Hung 0c4be94a02 Add -D DFF_MODE to abc9_map test 2019-12-30 20:13:25 -08:00
Eddie Hung fc4b8b8991 Remove submod changes 2019-12-30 14:56:14 -08:00
Eddie Hung 405e974fe5 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-30 14:31:42 -08:00
Miodrag Milanović c0a17c2457
Merge pull request #1589 from YosysHQ/iopad_default 
Make iopad option default for all xilinx flows
 2019-12-30 20:34:31 +01:00
Eddie Hung c2c74f9bb0
Merge pull request #1599 from YosysHQ/eddie/retry_1588 
Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
 2019-12-30 10:01:02 -08:00
Miodrag Milanovic f9749c202c Fix new tests 2019-12-28 16:43:19 +01:00
Miodrag Milanovic 8c3de1d4bd Merge remote-tracking branch 'origin/master' into iopad_default 2019-12-28 16:23:31 +01:00
Miodrag Milanovic a82c701668 Make test without iopads 2019-12-28 16:22:24 +01:00
Miodrag Milanovic 509da7ed1a Revert "Fix xilinx tests, when iopads are default" 
This reverts commit 477e43d921.
 2019-12-28 16:12:45 +01:00
Eddie Hung 011f749ecf Update resource count 2019-12-28 02:15:11 -08:00
Eddie Hung d45869855c Add #1598 testcase 2019-12-27 16:44:57 -08:00
Marcin Kościelnicki a24596def3 iopadmap: Emit tristate buffers with const OE for some edge cases. 2019-12-25 17:37:58 +01:00
Eddie Hung 2e21aa59a2 Add DSP cascade tests 2019-12-23 14:58:06 -08:00
Marcin Kościelnicki 666c6128a9 xilinx_dsp: Initial DSP48A/DSP48A1 support. 2019-12-22 20:51:14 +01:00
Miodrag Milanovic 436fea9e69 Addressed review comments 2019-12-21 20:23:23 +01:00
Miodrag Milanovic 477e43d921 Fix xilinx tests, when iopads are default 2019-12-21 13:18:44 +01:00
Eddie Hung 1ea1e8e54f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-20 13:56:13 -08:00
Eddie Hung 94f15f023c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-19 10:29:40 -08:00
Eddie Hung d406f2ffd7
Merge pull request #1569 from YosysHQ/eddie/fix_1531 
verilog: preserve size of $genval$-s in for loops
 2019-12-19 12:21:33 -05:00
Eddie Hung d675f22f4e
Merge pull request #1571 from YosysHQ/eddie/fix_1570 
mem_arst.v: do not redeclare ANSI port
 2019-12-19 12:21:22 -05:00
Eddie Hung b2a42e1fac
Merge pull request #1572 from nakengelhardt/scratchpad_pass 
add a command to read/modify scratchpad contents
 2019-12-18 13:55:44 -05:00
Marcin Kościelnicki f382164d6e tests/xilinx: fix flaky mux test 2019-12-18 15:53:29 +01:00
Marcin Kościelnicki a235250403 xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
Marcin Kościelnicki aff6ad1ce0 xilinx: Improve flip-flop handling. 
This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
 2019-12-18 13:43:43 +01:00
Eddie Hung a73f96594f
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram 
xilinx: add LUTRAM rules for RAM32M, RAM64M
 2019-12-16 21:48:21 -08:00
Eddie Hung aed67dd020 abc9 needs a clean afterwards 2019-12-16 18:42:23 -08:00
Eddie Hung 378d9e6e0c Add another test 2019-12-16 13:57:55 -08:00
Eddie Hung db0003410f Accidentally commented out tests 2019-12-16 13:31:47 -08:00
Eddie Hung 5a00d5578c Add unconditional match blocks for force RAM 2019-12-16 13:31:15 -08:00
Eddie Hung e990c013c5 Merge blockram tests 2019-12-16 13:01:51 -08:00
Diego H 87e21b0122 Fixing compiler warning/issues. Moving test script to the correct place 2019-12-16 10:23:45 -06:00
N. Engelhardt abcd82daca add assert option to scratchpad command 2019-12-16 14:00:21 +01:00
Diego H f3f59910eb Removing fixed attribute value to !ramstyle rules 2019-12-15 23:51:58 -06:00
Diego H b35559fc33 Merging attribute rules into a single match block; Adding tests 2019-12-15 23:33:09 -06:00
Eddie Hung a5764a1236 Disable RAM16X1D test 2019-12-13 10:28:13 -08:00
Eddie Hung d86d073ad6 Add testcase 2019-12-13 10:26:30 -08:00
Diego H 1c96345587 Renaming BRAM memory tests for the sake of uniformity 2019-12-13 09:33:18 -06:00
Eddie Hung d0ee4cd88f Remove extraneous synth_xilinx call 2019-12-12 19:00:26 -08:00
Eddie Hung 01116f0f0a Add tests for these new models 2019-12-12 18:52:48 -08:00
Eddie Hung 037d1a03df Add #1460 testcase 2019-12-12 17:49:55 -08:00
Eddie Hung caab66111e Rename memory tests to lutram, add more xilinx tests 2019-12-12 17:44:37 -08:00
Diego H 751a18d7e9 Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test. 2019-12-12 17:32:58 -06:00
Eddie Hung bea15b537b Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-12 14:57:17 -08:00
Eddie Hung 47ac1b01e6 Add test 2019-12-12 14:43:13 -08:00
Diego H e33f407655 Adding a note (TODO) in the memory_params.ys check file 2019-12-12 16:06:46 -06:00
N. Engelhardt 1187e91c2f add test and make help message more verbose 2019-12-12 20:51:59 +01:00
Diego H 937ec1ee78 Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1 2019-12-12 13:50:36 -06:00
Eddie Hung 23fcfd0adb Make SV2017 compliant courtesy of @wsnyder 2019-12-12 07:34:07 -08:00
Eddie Hung 4a80510877 Even more obvious testcase 2019-12-11 23:52:05 -08:00
Eddie Hung 61a1f3f49b Make testcase clearer with \o having its own init 2019-12-11 23:48:09 -08:00
Eddie Hung 151f7533e8 Add testcase 2019-12-11 16:52:37 -08:00
Eddie Hung e75ca29b19 Add test: 'Warning: ignoring initial value on non-register: \o' 2019-12-11 11:26:54 -08:00
Eddie Hung 7e5602ad17
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr 
Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
 2019-12-09 17:38:48 -08:00
Eddie Hung eff858cd33 unmap $__ICE40_CARRY_WRAPPER in test 2019-12-09 14:20:35 -08:00
Eddie Hung e05372778a ice40_wrapcarry to really preserve attributes via -unwrap option 2019-12-09 11:48:28 -08:00
Miodrag Milanovic 49c9b63e0f Fix for non-deterministic test 2019-12-07 11:09:25 +01:00
Eddie Hung a46a7e8a67 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-12-06 23:22:52 -08:00
Eddie Hung 946d5854c0 Drop keep=0 attributes on SB_CARRY 2019-12-06 17:27:47 -08:00
Jan Kowalewski dcb30b5f4a tests: arch: xilinx: Change order of arguments in macc.sh 2019-12-06 09:15:49 +01:00
Eddie Hung d8fbf88980 Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER 2019-12-05 07:01:02 -08:00
Eddie Hung 19bc429482 abc9_map.v to transform INIT=1 to INIT=0 2019-12-04 21:36:41 -08:00
Marcin Kościelnicki 2abe38e73e
iopadmap: Refactor and fix tristate buffer mapping. (#1527) 
The previous code for rerouting wires when inserting tristate buffers
was overcomplicated and didn't handle all cases correctly (in
particular, only cell connections were rewired — internal connections
were not).
 2019-12-04 08:44:08 +01:00
Eddie Hung 67f1ce2d43 Check SB_CARRY name also preserved 2019-12-03 14:51:39 -08:00
Eddie Hung 8de17877d4 Add testcase 2019-12-03 14:48:00 -08:00
Clifford Wolf 2ec6d832dc
Merge pull request #1524 from pepijndevos/gowindffinit 
Gowin: add and test DFF init values
 2019-12-03 08:43:18 -08:00
Pepijn de Vos a7d34a7cb5 update test 2019-12-03 16:56:15 +01:00
Pepijn de Vos a3b25b4af8 Use -match-init to not synth contradicting init values 2019-12-03 15:12:25 +01:00
David Shah e9ce4e658b abc9: Fix breaking of SCCs 
Signed-off-by: David Shah <dave@ds0.me>
 2019-12-01 20:44:56 +00:00
Eddie Hung c61186dd9d Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff 2019-11-27 13:24:03 -08:00
Eddie Hung ff1e357682 Add multiple driver testcase 2019-11-27 13:22:26 -08:00