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1273 Commits

Author SHA1 Message Date
Clifford Wolf a5bfeb9e07 Add optimization of (a && 1'b1) and (a || 1'b0) 2017-02-11 10:05:00 +01:00
C-Elegans 94b272077d Fix issue #306, "Bug in opt -full" 
Add check for whether the high bit in the constant expression is greater
than the width of the variable, and optimizes that to a constant 1 or
0
 2017-02-10 10:38:02 -05:00
Clifford Wolf e6cc67b46f Fix handling of init attributes with strange width 2017-02-09 16:06:58 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf 8927e19b13 Update ABC scripts to use "&nf" instead of "map" 2017-02-01 11:15:20 +01:00
Clifford Wolf ffbe8d41f3 Fix indenting and log messages in code merged from opt_compare_pr 2017-01-31 16:20:56 +01:00
Clifford Wolf 19a980277f Merge branch 'opt_compare_pr' of https://github.com/C-Elegans/yosys into C-Elegans-opt_compare_pr 2017-01-31 15:54:41 +01:00
Clifford Wolf 7481ba4750 Improve opt_rmdff support for $dlatch cells 2017-01-31 10:15:04 +01:00
C-Elegans a94c3694d7 Refactor and generalize the comparision optimization 
Generalizes the optimization to:
a < C,
a >= C,
C > a,
C <= a
 2017-01-30 17:52:16 -05:00
Clifford Wolf fe29869ec5 Add $ff and $_FF_ support to equiv_simple 2017-01-30 10:50:38 +01:00
Clifford Wolf 45e10c1c89 Be more conservative with merging large cells into FSMs 2017-01-26 09:19:28 +01:00
Clifford Wolf 49b8160488 Add warnings for quickly growing FSM table size in fsm_expand 2017-01-26 09:05:59 +01:00
C-Elegans 2fa0fd4a37 Do not use b.as_int() in calculation of bit set 2017-01-21 12:58:26 -05:00
C-Elegans 84f9cd0025 Optimize compares to powers of 2 
Remove opt_compare and put comparison pass in opt_expr

assuming a [7:0] is unsigned
a >= (1<<x) becomes |a[7:x]
a <  (1<<x) becomes !a[7:x]

Additionally:
a >= 0 becomes constant true,
a < 0 becomes constant false

delete opt_compare.cc
revert opt.cc to commit b7cfb7dbd (remove opt_compare step)
 2017-01-16 13:45:50 -05:00
Austin Seipp 6781543244 passes/hierarchy: delete some dead code 
Signed-off-by: Austin Seipp <aseipp@pobox.com>
 2017-01-15 16:39:12 -06:00
C-Elegans 943389cdd5 Fix issue #269, optimize signed compare with 0 
add opt_compare pass and add it to opt
for a < 0:
    if a is signed, replace with a[max_bit-1]
for a >= 0:
    if a is signed, replace with ~a[max_bit-1]
 2017-01-15 13:38:29 -05:00
Clifford Wolf 0cac95ea94 Added "check -initdrv" 2017-01-04 18:12:41 +01:00
Clifford Wolf f0df7dd796 Added cell port resizing to hierarchy pass 2017-01-01 23:03:44 +01:00
Clifford Wolf b1cdf772eb Added "design -reset-vlog" 2016-11-30 11:25:55 +01:00
Clifford Wolf ac7a175a3c Improved equiv_purge log output 2016-11-29 13:30:35 +01:00
Clifford Wolf e444e59963 Added wire start_offset and upto handling to splitnets cmd 2016-11-23 13:54:33 +01:00
Clifford Wolf 55785a96eb Improved ABC default scripts 2016-11-19 18:20:54 +01:00
Clifford Wolf 70d7a02cae Added support for hierarchical defparams 2016-11-15 13:35:19 +01:00
Clifford Wolf 1827a48964 Minor bugfix in submod 2016-11-09 13:13:26 +01:00
Clifford Wolf 97ac77513f Bugfix in "setundef" pass 2016-11-08 18:53:36 +01:00
Clifford Wolf ef603c6fe1 Implemented "scc -set_attr" 2016-11-06 00:04:10 +01:00
Clifford Wolf 914aa8a5d3 Bugfix in "scc" command 2016-11-06 00:03:35 +01:00
Clifford Wolf 308a4b4a1b Bugfix in "hierarchy -check" 2016-11-02 20:09:57 +01:00
Clifford Wolf b63cace90f Added support for fsm_encoding="user" 2016-11-02 13:15:49 +01:00
Clifford Wolf 0c8e973d32 Added "fsm_expand -full" 2016-11-02 09:31:39 +01:00
Clifford Wolf d9d38eeedb Bugfix in fsm_map for FSMs without reset state 2016-10-25 23:21:37 +02:00
Clifford Wolf aa72262330 Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
Clifford Wolf 3655d7fea7 Added "setparam -type" 2016-10-19 13:54:04 +02:00
Clifford Wolf 15fb56697a Bugfix in "miter -assert" handling of assumptions 2016-10-17 14:56:58 +02:00
Clifford Wolf 6425d34e73 Added clk2fflogic support for $dffsr and $dlatch 2016-10-17 13:28:55 +02:00
Clifford Wolf 3a09d6bb65 Improvements and bugfixes in clk2fflogic 2016-10-16 23:03:29 +02:00
Clifford Wolf 74702b04c2 Build fixes for VS 2015 2016-10-16 20:37:02 +02:00
Clifford Wolf fa535c0b00 Some minor build fixes for Visual C 2016-10-14 18:36:02 +02:00
Clifford Wolf e4c5ee9b89 Avoid using strcasecmp() 2016-10-14 18:20:36 +02:00
Clifford Wolf 2733994aeb Added clk2fflogic 2016-10-14 14:55:07 +02:00
Clifford Wolf 2ef454c3f5 Added opt_rmdff support for $ff cells 2016-10-14 13:02:36 +02:00
Clifford Wolf 53655d173b Added $global_clock verilog syntax support for creating $ff cells 2016-10-14 12:33:56 +02:00
Clifford Wolf ffbb4e992e Added MEMID handling to "flatten" pass 2016-10-14 10:36:37 +02:00
Clifford Wolf ee91350add Added "zinit" pass 2016-10-12 12:05:19 +02:00
Clifford Wolf 8ebba8a35f Added $ff and $_FF_ cell types 2016-10-12 01:18:39 +02:00
Clifford Wolf ed519f578e Added "opt_rmdff -keepdc" 2016-09-30 17:02:38 +02:00
Clifford Wolf e788ad4885 Cosmetic fix in test_autotb.cc 2016-09-19 20:43:43 +02:00
Clifford Wolf 5e155aa121 Avoid creating very long strings in test_autotb 2016-09-19 10:20:20 +02:00
Clifford Wolf d8ad889594 Bugfix in techmap parameter handling 2016-09-14 20:46:54 +02:00
Kaj Tuomi df4ab169a7 Typo fix. 2016-09-08 10:57:16 +03:00
Clifford Wolf cb7dbf4070 Improvements in assertpmux 2016-09-07 12:42:16 +02:00
Clifford Wolf ab18e9df7c Added assertpmux 2016-09-07 00:28:01 +02:00
Clifford Wolf f3f5a02045 Added "tee +INT -INT" 2016-09-06 17:43:24 +02:00
Clifford Wolf fc5281b3f7 Run log_flush() before solving in sat command 2016-09-06 17:35:25 +02:00
Clifford Wolf 4ea7054b56 Improved init spec handling in opt_rmdff, modernized the code a bit 2016-08-30 01:34:04 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 66582964bc Improved "show" help message 2016-08-28 12:34:36 +02:00
Clifford Wolf 23afeadb5e Fixed handling of transparent bram rd ports on ROMs 2016-08-27 17:06:22 +02:00
Clifford Wolf cad40fc874 Fixed bug in memory_share for memory ports with different ABITS 2016-08-22 14:26:33 +02:00
Clifford Wolf d77a914683 Added "wreduce -memx" 2016-08-20 12:52:50 +02:00
Clifford Wolf 15ef608453 Added memory_memx pass, "memory -memx", and "prep -memx" 2016-08-19 19:48:26 +02:00
Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end 2016-08-19 18:38:25 +02:00
Clifford Wolf b3a01451a5 Bugfix in test_autotb 2016-08-18 13:43:12 +02:00
Clifford Wolf 00f29d5e5c Fixed use-after-free dict<> usage pattern in hierarchy.cc 2016-08-16 09:07:13 +02:00
Clifford Wolf 321e15b0bf Minor fixes in show command 2016-08-16 00:36:24 +02:00
Clifford Wolf 73b7232ec8 Fixed some compiler warnings in attrmap command 2016-08-10 13:44:08 +02:00
Clifford Wolf b0aab4e304 Added "attrmap" command 2016-08-09 19:56:55 +02:00
Clifford Wolf 3c6d31fd06 Added "attrmvcp" pass 2016-08-09 11:18:48 +02:00
Clifford Wolf 9d15529214 Undo "preserve wire attributes in iopadmap" change (it was OK before) 2016-08-08 11:47:35 +02:00
Clifford Wolf 88a67afa7d Added "test_autotb -seed" (and "autotest.sh -S") 2016-08-06 13:32:29 +02:00
Clifford Wolf 90c17aad56 preserve wire attributes in iopadmap 2016-08-06 13:24:59 +02:00
Clifford Wolf 5d6765a9d2 Added "insbuf" command 2016-08-02 10:37:19 +02:00
Clifford Wolf 8537c4d206 Renamed AbstractCellEdgesDatabase::add_cell() to add_edges_from_cell() 2016-07-25 16:39:25 +02:00
Clifford Wolf b1c432af56 Improvements in CellEdgesDatabase 2016-07-24 17:21:53 +02:00
Clifford Wolf f162b858f2 Added CellEdgesDatabase API 2016-07-24 13:59:57 +02:00
Clifford Wolf 54966679df Moved SatHelper::setup_init() code to SatHelper::setup() 2016-07-24 12:18:39 +02:00
Clifford Wolf 34e833103b Added $initstate support to "sat" command 2016-07-23 17:01:03 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf e92998a79c Minor bugfix in FSM reset state detection 2016-07-12 09:46:15 +02:00
Clifford Wolf b5a9fba0db Further improved fsm_detect output, attempt to detect self-resetting circuits 2016-07-09 14:02:49 +02:00
Clifford Wolf d63ffabacb Added printing of some warning messages to fsm_detect 2016-07-09 13:23:06 +02:00
Clifford Wolf 6ed6b3cb6d Replaced "select -assert-limit" with -assert-max and -assert-min 2016-07-01 12:24:13 +02:00
eshellko 9a742f4069 Added 'assert-limit' option for 'select' command 
For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
 2016-07-01 10:24:22 +04:00
Clifford Wolf 541083cf32 Bugfix in "abc -script" handling 2016-06-19 22:19:19 +02:00
Clifford Wolf ca91bccb6b Added "deminout" 2016-06-19 13:08:16 +02:00
Clifford Wolf 3380281e15 Added "dc2" to default ABC scripts 2016-06-17 20:15:35 +02:00
Clifford Wolf f498204ae4 Added "abc -I <num> -P <num>" 2016-06-17 19:39:35 +02:00
Clifford Wolf 95757efb25 Improved support for $sop cells 2016-06-17 16:31:16 +02:00
Clifford Wolf 52bb1b968d Added $sop cell type and "abc -sop" 2016-06-17 13:50:09 +02:00
Clifford Wolf c3365034e9 Updated ABC to hg rev b5df6e2b76f0 2016-06-17 11:16:31 +02:00
Clifford Wolf 99edf24966 Added "nlutmap -assert" 2016-06-09 11:47:41 +02:00
Clifford Wolf 2032e6d8e4 Added "proc_mux -ifx" 2016-06-06 17:15:50 +02:00
Clifford Wolf dcf576641b Added "setundef -init" 2016-06-03 11:38:31 +02:00
Clifford Wolf d2695e2bfa Fix all undef-muxes in dlatch input cone 2016-06-02 14:37:07 +02:00
Clifford Wolf adfc80727c Avoid creating undef-muxes when inferring latches in proc_dlatch 2016-06-01 13:25:06 +02:00
Clifford Wolf 11f7b8a2a1 Added opt_expr support for div/mod by power-of-two 2016-05-29 12:17:36 +02:00
Clifford Wolf 611f121cb9 Fixed "scc" for cells that have feedback singals _and_ are part of a larger loop 2016-05-27 16:33:13 +02:00
Marcus Comstedt e22e4d59b8 Made the expansion order of hierarchy deterministic 2016-05-22 16:41:26 +02:00
Clifford Wolf 1e227caf72 Improvements and fixes in autotest.sh script and test_autotb 2016-05-20 16:58:02 +02:00
Kaj Tuomi 8c3bc2ac0d Close opened dump file. 2016-05-19 11:53:29 +03:00
Kaj Tuomi f6221ade95 Fix for Modelsim transcript line warp issue #164 2016-05-19 11:34:38 +03:00
Clifford Wolf ffcdc53a18 Don't sign-extend memory bram initialization data 2016-05-15 00:05:30 +02:00
Clifford Wolf c3f6e0ea85 Added support for "keep" attribute to shregmap 2016-05-07 09:33:16 +02:00
Clifford Wolf aadca148da Fixed preservation of important attributes in techmap 2016-05-06 13:59:30 +02:00
Andrew Zonenberg 3486637b19 Changed port names in greenpak shregmap 2016-05-04 17:04:50 -07:00
Clifford Wolf 9647dc3c07 Added tristate buffer support to iopadmap 2016-05-04 22:48:02 +02:00
Clifford Wolf 658f93663b Fixed iopadmap attribute handling 2016-05-04 10:48:23 +02:00
Clifford Wolf e01464e2ac Added "qwp -v" 2016-04-28 23:17:30 +02:00
Clifford Wolf 0d2923cccd Connections between inputs and inouts are driven by the input 2016-04-26 19:49:05 +02:00
Clifford Wolf 958fb29c76 Fixed test_autotb for modules with many cell ports 2016-04-25 16:37:11 +02:00
Clifford Wolf 93e107e455 Fixed proc_mux performance bug 2016-04-25 10:43:04 +02:00
Clifford Wolf b1d6f05fa2 Fixed performance bug in proc_dlatch 2016-04-24 19:29:56 +02:00
Clifford Wolf 096c25d29d Improvements in greenpak4 shreg mapping 2016-04-23 23:10:13 +02:00
Andrew Zonenberg 7f16784f3c Merge https://github.com/cliffordwolf/yosys 2016-04-23 12:22:08 -07:00
Clifford Wolf e13c66122e Added "shregmap -zinit" for greenpak4 tech 2016-04-23 20:20:21 +02:00
Andrew Zonenberg 2849fd486e Fixed typo in help text 2016-04-22 23:01:39 -07:00
Clifford Wolf 7311be4028 Added "shregmap -tech greenpak4" 2016-04-22 19:42:08 +02:00
Clifford Wolf 965b0d59b5 More flexible handling of initialization values 2016-04-22 12:13:06 +02:00
Clifford Wolf 0bc95f1e04 Added "yosys -D" feature 2016-04-21 23:28:37 +02:00
Clifford Wolf 1565d1af69 Fixed performance bug in "share" pass 2016-04-21 19:47:25 +02:00
Clifford Wolf f38ca3e18f Improvements in opt_expr 2016-04-21 14:23:04 +02:00
Clifford Wolf 1761d08dd2 Bugfix and improvements in memory_share 2016-04-21 14:22:58 +02:00
Clifford Wolf f1fa757d0e Added "shregmap -params" 2016-04-18 11:58:21 +02:00
Clifford Wolf 525651c8f6 Added "shregmap -zinit" and "shregmap -init" 2016-04-18 11:44:10 +02:00
Clifford Wolf ce7c980ec7 Improvements in "shregmap" 2016-04-17 15:37:22 +02:00
Clifford Wolf de647a390c Added "shregmap" pass 2016-04-16 23:20:49 +02:00
Clifford Wolf fbdb8e7b3e Fixed copy&paste error in log message in lut2mux 2016-04-16 23:20:34 +02:00
Clifford Wolf 6041f780c3 Prefer noninverting FFs in dfflibmap 2016-04-05 12:51:04 +02:00
Clifford Wolf eaac5bfbc7 Improved formatting of "sat" output tables 2016-04-05 08:26:10 +02:00
Clifford Wolf 6cafd08ac1 Improved opt_merge support for $pmux cells 2016-03-31 09:58:55 +02:00
Clifford Wolf e5dd5c0bcc Preserve empty $pmux default cases 2016-03-31 09:57:23 +02:00
Clifford Wolf e2f6d61c00 Typo fixes in opt_expr and opt_merge 2016-03-31 09:56:56 +02:00
Clifford Wolf ec93680bd5 Renamed opt_share to opt_merge 2016-03-31 08:52:49 +02:00
Clifford Wolf 1d0f0d668a Renamed opt_const to opt_expr 2016-03-31 08:46:56 +02:00
Andrew Zonenberg 984561c034 Renamed counters pass to greenpak4_counters 2016-03-30 22:52:01 -07:00
Andrew Zonenberg 1ae33344f4 Added initial implementation of "counters" pass to synth_greenpak4. Can only infer non-resettable down counters for now. 2016-03-30 22:40:14 -07:00
Andrew Zonenberg 1b42e0c471 Reduced log verbosity 2016-03-30 22:03:50 -07:00
Andrew Zonenberg ad19e0c64a Continued work on counter extraction. Can recognize compatible RTL counters but not replace with hard macros. 2016-03-30 21:54:23 -07:00
Andrew Zonenberg d16d05e415 Merge https://github.com/cliffordwolf/yosys 2016-03-30 20:38:18 -07:00
Andrew Zonenberg dd7204c0bd Fixed typo in log message 2016-03-30 20:30:03 -07:00
Andrew Zonenberg 489caf32c5 Initial work on greenpak4 counter extraction. Doesn't work but a decent start 2016-03-30 01:07:20 -07:00
Clifford Wolf a47f69536a Added support for installed plugins 2016-03-30 10:02:03 +02:00
Clifford Wolf 9717495401 Fixed handling of inverters (aka 1-input luts) in nlutmap 2016-03-23 08:56:08 +01:00
Clifford Wolf 043fa0fad0 Cleanup abstract modules at end of "hierarchy -top" 2016-03-21 16:37:35 +01:00
Clifford Wolf 2c7e107d7a Support for abstract modules in chparam 2016-03-21 16:37:35 +01:00
Clifford Wolf bb9374b67c Improvements in ABCEXTERNAL handling 2016-03-19 20:02:40 +01:00
Sergey Kvachonok 2656b2c55a Support calling out to an external ABC. 
$ make ABCEXTERNAL=my-abc && make ABCEXTERNAL=my-abc install

configures yosys to use an external ABC executable instead of
building and installing the in-tree ABC copy (yosys-abc).
 2016-03-19 18:36:18 +03:00
Clifford Wolf c4aaed099f Using "mfs" and "lutpack" in ABC lut mapping 2016-03-07 11:14:11 +01:00
Clifford Wolf bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf 0d7fd2585e Added "int ceil_log2(int)" function 2016-02-13 16:52:16 +01:00
Clifford Wolf 825b99efc1 Added "stat -liberty" for calculating chip area 2016-02-04 12:26:13 +01:00
Clifford Wolf 801c022457 Improved dffsr2dff pass 2016-02-02 19:42:49 +01:00
Clifford Wolf d69395ca08 Added dffsr2dff 2016-02-02 17:19:01 +01:00
Clifford Wolf d6592d5b99 Use alphanumerical order instead of idstring idx in opt_clean compare_signals() 2016-02-02 09:16:18 +01:00
Clifford Wolf 17372d8abd Added "abc -luts" option, Improved Xilinx logic mapping 2016-02-01 12:40:32 +01:00
Clifford Wolf 9251553592 Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs) 2016-02-01 11:49:11 +01:00
Clifford Wolf 71f418c468 More clang sanitizer stuff 2016-01-31 19:55:48 +01:00
Clifford Wolf 8b3f8cd220 Added "equiv_struct -fwonly" 2016-01-08 10:59:16 +01:00
Clifford Wolf f5008f4f8a Bugfixes in equiv_struct 2016-01-08 09:57:28 +01:00
Clifford Wolf d00c63c927 Added "submod -copy" 2016-01-08 09:08:12 +01:00
Clifford Wolf c3fd03d722 Added "equiv_struct -maxiter <N>" 2016-01-06 13:54:54 +01:00
Clifford Wolf 1f8c47fb47 Added "equiv_add -try" mode 2016-01-06 13:54:00 +01:00
Clifford Wolf 1d62f8710f Fixed "splitnets -ports" for hierarchical designs 2015-12-22 13:25:00 +01:00
Clifford Wolf ab0c44d3ed Added %R select expression 2015-12-20 13:35:58 +01:00
Clifford Wolf 1ea6db3db8 Improved proc_mux performance for huge always blocks 2015-12-02 22:02:20 +01:00
Clifford Wolf e61c7f887a Added torder command 2015-11-19 15:34:32 +01:00
Clifford Wolf d98d99aec6 Added "abc -g" 2015-11-10 11:10:11 +01:00
Marcus Comstedt 8c2bdef36d Fix a segfault in dffinit when the value has too few bits 
The code was already trying to add the required number of bits, but
fell one short of the mark.
 2015-11-08 19:16:56 +01:00
Clifford Wolf 1ec6429bad Added "singleton" pass 2015-11-07 19:10:43 +01:00
Clifford Wolf f401eeb0cf Bugfix in mapping $tribuf to $_TBUF_ 2015-11-05 12:37:43 +01:00
Clifford Wolf ddf3e2dc65 Bugfix in memory_dff 2015-10-31 22:01:41 +01:00
Clifford Wolf ccdbf41be6 Improvements in wreduce 2015-10-31 13:39:30 +01:00
Clifford Wolf 0c202a2549 Use mfp<> in equiv_mark 2015-10-27 19:15:35 +01:00
Clifford Wolf 27714acd8a Improvements in equiv_struct 2015-10-25 22:04:20 +01:00
Clifford Wolf d014ba2d0e Major refactoring of equiv_struct 2015-10-25 19:31:29 +01:00
Clifford Wolf 207736b4ee Import more std:: stuff into Yosys namespace 2015-10-25 19:30:49 +01:00
Clifford Wolf da923c198e Added "equiv_add -cell" 2015-10-25 14:35:40 +01:00
Clifford Wolf 83bd27bf6e equiv_struct now creates equiv_merged attributes 2015-10-25 02:15:20 +02:00
Clifford Wolf 453736d918 Improvements in equiv_struct 2015-10-24 23:04:17 +02:00
Clifford Wolf 7f110e7018 renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit() 2015-10-24 22:56:40 +02:00
Clifford Wolf 6af8076967 improvement in "stat" 2015-10-24 21:56:53 +02:00
Clifford Wolf 6fe48cf41e equiv_purge bugfix, using SigChunk in Yosys namespace 2015-10-24 19:09:45 +02:00
Clifford Wolf 2a0f577f83 Fixed handling of driver-driver conflicts in wreduce 2015-10-24 13:44:35 +02:00
Clifford Wolf 4cec1c058d Added equiv_mark command 2015-10-23 23:56:58 +02:00
Clifford Wolf c35db8c19e Disabled "Skipping blackbox module" msg in show command 2015-10-23 20:11:05 +02:00
Clifford Wolf 15a67392f1 Also merge $equiv cells in equiv_struct 2015-10-23 15:26:58 +02:00
Clifford Wolf d19069b0fb Improvements in equiv_struct 2015-10-23 15:11:57 +02:00
Clifford Wolf 84a07ffb8a Added equiv_purge 2015-10-22 15:40:27 +02:00
Clifford Wolf 00e05b1310 Added equiv_struct command 2015-10-21 17:12:35 +02:00
Clifford Wolf 6416dfee93 Improved inout handling in equiv_make 2015-10-21 15:42:50 +02:00
Clifford Wolf 1d83854d84 Bugfixes in handling of "keep" attribute on wires 2015-10-15 14:57:28 +02:00
Clifford Wolf eb1e3caae7 Fixed "flatten" for unconnected inout ports 2015-10-13 10:30:23 +02:00
Clifford Wolf c58bd5dc30 Added edgetypes command 2015-09-27 11:53:20 +02:00
Clifford Wolf 281c1f4029 Some cleanups in qwp 2015-09-26 10:42:27 +02:00
Clifford Wolf ddcfc99f8c Added "test_cell -noeval" 2015-09-25 17:27:18 +02:00
Clifford Wolf 82028c42e0 Added wreduce $mul support and fixed signed $mul opt_const bug 2015-09-25 17:27:06 +02:00
Clifford Wolf 4864736167 Bugfix in bram read-enable code 2015-09-25 14:22:33 +02:00
Clifford Wolf 924d9d6e86 Added read-enable to memory model 2015-09-25 12:23:11 +02:00
Clifford Wolf ec92c89659 Added pivoting to qwp solver 2015-09-24 22:16:37 +02:00