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1044 Commits

Author SHA1 Message Date
Eddie Hung 1851f4b488 Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 23:01:18 -08:00
Eddie Hung 900c806d4e Move clkpart into passes/hierarchy 2019-11-22 17:25:53 -08:00
Eddie Hung bf7d36627e Merge remote-tracking branch 'origin/eddie/clkpart' into xaig_dff 2019-11-22 17:00:35 -08:00
Eddie Hung 95af8f56e4 Only action if there is more than one clock domain 2019-11-22 17:00:11 -08:00
Eddie Hung 00d76f6cc4 Replace TODO 2019-11-22 16:58:08 -08:00
Eddie Hung 698854955c Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:41:48 -08:00
Eddie Hung 84153288bb Brackets 2019-11-22 15:41:34 -08:00
Eddie Hung 3df191cec5 Entry in Makefile.inc 2019-11-22 15:41:23 -08:00
Eddie Hung bd56161775 Merge branch 'eddie/clkpart' into xaig_dff 2019-11-22 15:38:48 -08:00
Eddie Hung 856a3dc98d New 'clkpart' to {,un}partition design according to clock/enable 2019-11-22 15:35:51 -08:00
Eddie Hung c4ec42ac38 When expanding upwards, do not capture $__ABC9_{FF,ASYNC}_ 
Since they should be captured downwards from the owning flop
 2019-11-21 16:17:03 -08:00
Eddie Hung 729c6b93e8 endomain -> ctrldomain 2019-11-20 14:32:01 -08:00
Eddie Hung 09ee96e8c2 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-11-19 15:40:39 -08:00
Marcin Kościelnicki 38e72d6e13 Fix #1496. 2019-11-18 04:16:48 +01:00
whitequark c68722818a flowmap: when doing mincut, ensure source is always in X, not X̅. 
Fixes #1475.
 2019-11-12 00:15:43 +00:00
whitequark eef32195bd flowmap: don't break if that creates a k+2 (and larger) LUT either. 
Fixes #1405.
 2019-11-11 23:13:00 +00:00
Eddie Hung 2cb2116b4c Use "abc9_period" attribute for delay target 2019-10-07 15:03:44 -07:00
Eddie Hung 3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung a5ac33f230 Merge branch 'master' into eddie/abc_to_abc9 2019-10-04 17:53:20 -07:00
Eddie Hung f0cadb0de8 Fix from merge 2019-10-04 17:52:19 -07:00
Eddie Hung bbc0e06af3 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-04 17:39:08 -07:00
Eddie Hung 0acc51c3d8 Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` 2019-10-04 17:35:43 -07:00
Eddie Hung 7959e9d6b2 Fix merge issues 2019-10-04 17:21:14 -07:00
Eddie Hung 7a45cd5856 Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff 2019-10-04 16:58:55 -07:00
Eddie Hung aae2b9fd9c Rename abc_* names/attributes to more precisely be abc9_* 2019-10-04 11:04:10 -07:00
Eddie Hung 549d6ea467 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-03 10:55:23 -07:00
Clifford Wolf 0e05424885
Merge pull request #1422 from YosysHQ/eddie/aigmap_select 
Add -select option to aigmap
 2019-10-03 11:54:04 +02:00
Eddie Hung 265a655ef9 Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf 2019-10-02 12:43:35 -07:00
Eddie Hung edc3780723 techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias 2019-09-30 17:20:12 -07:00
Eddie Hung 1b96d29174 No need to punch ports at all 2019-09-30 17:02:20 -07:00
Eddie Hung 390b960c8c Resolve FIXME on calling proc just once 2019-09-30 16:37:29 -07:00
Eddie Hung e529872b01 Remove need for $currQ port connection 2019-09-30 16:33:40 -07:00
Eddie Hung f2f19df2d4 Add -select option to aigmap 2019-09-30 15:26:29 -07:00
Eddie Hung e0aa772663 Add comment 2019-09-30 15:19:02 -07:00
Eddie Hung a6994c5f16 scc call on active module module only, plus cleanup 2019-09-30 12:57:19 -07:00
Eddie Hung 8684b58bed Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-30 12:29:35 -07:00
Miodrag Milanović 0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in 
Open aig frontend as binary file
 2019-09-30 17:49:23 +02:00
Eddie Hung 1123c09588 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-29 19:39:12 -07:00
Eddie Hung 8474c5b366
Merge pull request #1359 from YosysHQ/xc7dsp 
DSP inference for Xilinx (improved for ice40, initial support for ecp5)
 2019-09-29 11:26:22 -07:00
Eddie Hung 5a4011e8c9 Fix "scc" call inside abc9 to consider all wires 2019-09-29 09:58:00 -07:00
Miodrag Milanovic 3f70c1fd26 Open aig frontend as binary file 2019-09-29 13:22:11 +02:00
Eddie Hung 79b6edb639 Big rework; flop info now mostly in cells_sim.v 2019-09-28 23:48:17 -07:00
Eddie Hung 313d2478e9 Split ABC9 based on clocking only, add "abc_mergeability" attr for en 2019-09-27 18:41:04 -07:00
Eddie Hung fe722b737c Add -select option to aigmap 2019-09-27 17:44:01 -07:00
Eddie Hung 8f5710c464 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-09-27 15:14:31 -07:00
Marcin Kościelnicki fd0e3a2c43 Fix _TECHMAP_REMOVEINIT_ handling. 
Previously, this wire was handled in the code that populated the "do or
do not" techmap cache, resulting in init value removal being performed
only for the first use of a given template.

Fixes the problem identified in #1396.
 2019-09-27 18:34:12 +02:00
Eddie Hung 44374b1b2b "abc_padding" attr for blackbox outputs that were padded, remove them later 2019-09-23 21:58:40 -07:00
Eddie Hung ec08a031b5 Revert abc9.cc 2019-09-20 17:52:23 -07:00
Eddie Hung 72ce06909e Trim mismatched connection to be same (smallest) size 2019-09-20 17:51:36 -07:00
Eddie Hung 567e5f0aa7 Fix first testcase in #1391 2019-09-20 17:51:27 -07:00
Clifford Wolf b76fac3ac3 Add techmap_autopurge attribute, fixes #1381 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-19 20:00:52 +02:00
Marcin Kościelnicki c9f9518de4 Added extractinv pass 2019-09-19 04:02:48 +02:00
Eddie Hung 9a73adde50 Explicitly order function arguments 2019-09-13 16:18:05 -07:00
Marcin Kościelnicki f72765090c Add -match-init option to dff2dffs. 2019-09-11 19:38:20 +02:00
Marcin Kościelnicki a82e8df7d3 techmap: Add support for extracting init values of ports 2019-09-07 16:30:43 +02:00
Eddie Hung 903cd58acf
Merge pull request #1312 from YosysHQ/xaig_arrival 
Allow arrival times of sequential outputs to be specified to abc9
 2019-09-05 12:00:23 -07:00
Clifford Wolf 30f1ac7ce9 Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes #1220 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-05 13:51:53 +02:00
Clifford Wolf 694a8f75cf Add flatten handling of pre-existing wires as created by interfaces, fixes #1145 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-05 13:30:58 +02:00
Eddie Hung c7f1ccbcb0 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 12:28:35 -07:00
Eddie Hung 999fb33fd0
Merge pull request #1340 from YosysHQ/eddie/abc_no_clean 
abc9 to not call "clean" at end of run (often called outside)
 2019-08-30 12:27:09 -07:00
Eddie Hung f0fef90e9d Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-30 10:30:46 -07:00
Eddie Hung 6e475484b2 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-30 09:37:32 -07:00
Eddie Hung 18cabe9370 Output has priority over input when stitching in abc9 2019-08-29 17:24:03 -07:00
Eddie Hung 3e0f73c3df abc9 to not call "clean" at end of run (often called outside) 2019-08-29 12:12:59 -07:00
Eddie Hung 1467761060 Fix typo that's gone unnoticed for 5 months!?! 2019-08-29 10:33:28 -07:00
Eddie Hung c4e5310823 Use a dummy box file if none specified 2019-08-28 20:58:55 -07:00
Eddie Hung 1b08f861b6 Merge branch 'eddie/xilinx_srl' into xaig_arrival 2019-08-28 15:31:48 -07:00
Eddie Hung 8d820a9884 Merge remote-tracking branch 'origin/master' into xaig_arrival 2019-08-28 15:19:10 -07:00
Eddie Hung ba5d81c7f1 Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl 2019-08-28 09:21:03 -07:00
Clifford Wolf 47ffbf554e Fix typo 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:06:42 +02:00
Clifford Wolf 0fda0e821c Add "paramap" pass 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-28 10:03:27 +02:00
Marcin Kościelnicki 5fb4b12cb5 improve clkbuf_inhibit propagation upwards through hierarchy 2019-08-27 17:26:47 +02:00
Eddie Hung 48c424e45b Cleanup 2019-08-23 13:46:05 -07:00
Eddie Hung 619f2414e5 clkbufmap to only check clkbuf_inhibit if no selection given 2019-08-23 11:14:42 -07:00
Eddie Hung 4d89c3f468 Review comment from @cliffordwolf 2019-08-23 10:03:41 -07:00
Eddie Hung 6872805a3e Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-23 10:00:50 -07:00
Eddie Hung 53fed4f7e9 Actually, there might not be any harm in updating sigmap... 2019-08-22 16:16:56 -07:00
Eddie Hung cfafd360d5 Add comment as per @cliffordwolf 2019-08-22 16:16:56 -07:00
Eddie Hung 8691596d19 Revert "Try way that doesn't involve creating a new wire" 
This reverts commit 2f427acc9e.
 2019-08-22 16:16:34 -07:00
Eddie Hung 5ff75b1cdc Try way that doesn't involve creating a new wire 2019-08-22 16:16:34 -07:00
Eddie Hung e1fff34dde If d_bit already in sigbit_chain_next, create extra wire 2019-08-22 16:16:34 -07:00
Eddie Hung 36d94caec1 Remove `shregmap -tech xilinx` additions 2019-08-22 11:22:09 -07:00
Eddie Hung affe9c9c1a Merge branch 'eddie/fix_techmap' into xaig_arrival 2019-08-20 20:06:47 -07:00
Eddie Hung fe61dcce8b Grammar 2019-08-20 20:05:51 -07:00
Eddie Hung 193eae0c84 techmap -max_iter to apply to each module individually 2019-08-20 19:50:20 -07:00
Eddie Hung 57493e328a techmap -max_iter to apply to each module individually 2019-08-20 19:48:16 -07:00
Eddie Hung f1a206ba03 Revert "Remove sequential extension" 
This reverts commit 091bf4a18b.
 2019-08-20 18:17:14 -07:00
Eddie Hung 091bf4a18b Remove sequential extension 2019-08-20 18:16:37 -07:00
Eddie Hung fad15d276d retime_mode -> dff_mode 2019-08-20 18:08:58 -07:00
Eddie Hung 505d062daf Fix use of {CLK,EN}_POLARITY, also add a FIXME 2019-08-20 13:33:31 -07:00
Eddie Hung c4d4c6db3f Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-20 12:00:12 -07:00
Eddie Hung 14c03861b6
Merge pull request #1304 from YosysHQ/eddie/abc9_refactor 
Refactor abc9 to use port attributes, not module attributes
 2019-08-20 11:59:31 -07:00
Eddie Hung 1f03154a0c Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 15:19:32 -07:00
Eddie Hung e29df7d5fa Remove debug 2019-08-19 12:44:43 -07:00
Eddie Hung 91687d3fea Add (* abc_arrival *) attribute 2019-08-19 12:33:24 -07:00
Eddie Hung ba2261e21a Move from cell attr to module attr 2019-08-19 11:18:33 -07:00
Eddie Hung 7e010834eb Fix typo 2019-08-19 10:41:18 -07:00
Eddie Hung 2f4e0a5388 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-08-19 10:07:27 -07:00
Eddie Hung d81a090d89 Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro 2019-08-19 09:56:17 -07:00
Eddie Hung e301440a0b Use attributes instead of params 2019-08-19 09:51:49 -07:00
Eddie Hung 9bfe924e17 Set abc_flop and use it in toposort 2019-08-19 09:40:01 -07:00
Clifford Wolf 2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255 
Fix various NDEBUG compiler warnings
 2019-08-17 15:07:16 +02:00
Clifford Wolf 8915f496d9
Merge pull request #1300 from YosysHQ/eddie/cleanup2 
Use ID::{A,B,Y,keep,blackbox,whitebox} instead of ID()
 2019-08-17 15:01:31 +02:00
Eddie Hung 24c934f1af Merge branch 'eddie/abc9_refactor' into xaig_dff 2019-08-16 16:51:22 -07:00
Eddie Hung 5abe133323 Use ID() 2019-08-16 16:38:49 -07:00
Eddie Hung 4fe307f1bc Compute abc_scc_break and move CI/CO outside of each abc9 2019-08-16 15:41:17 -07:00
Eddie Hung 6b51c154c6 Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap 2019-08-16 13:38:47 -07:00
Clifford Wolf 958be89c47
Merge pull request #1302 from mmicko/dfflibmap_regression 
DFFLIBMAP pass regression fix
 2019-08-16 14:26:58 +02:00
Miodrag Milanovic 72eacdb9f8 Regression in abc9 2019-08-16 13:21:11 +02:00
Miodrag Milanovic bb79e050a5 Just needed IDs to be IdString 2019-08-16 11:50:34 +02:00
Clifford Wolf bb37a20e8d Add missing NMUX to "abc -g" handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-16 10:36:11 +02:00
Eddie Hung eae5a6b12c Use ID::keep more liberally too 2019-08-15 14:51:12 -07:00
Eddie Hung 52355f5185 Use more ID::{A,B,Y,blackbox,whitebox} 2019-08-15 14:50:10 -07:00
Clifford Wolf 49301b733e
Merge branch 'master' into clifford/fix1255 2019-08-15 22:44:38 +02:00
Eddie Hung 02dead2e60 ID(\\.*) -> ID(.*) 2019-08-15 10:25:54 -07:00
Eddie Hung 78ba8b8574 Transform all "\\*" identifiers into ID() 2019-08-15 10:19:29 -07:00
Eddie Hung 9f98241010 Transform "$.*" to ID("$.*") in passes/techmap 2019-08-15 10:05:08 -07:00
Eddie Hung 4cfefae21e More use of IdString::in() 2019-08-15 09:23:57 -07:00
Eddie Hung 1551e14d2d AND with an inverted input, causes X{,N}OR output to be inverted too 2019-08-14 16:26:24 -07:00
Eddie Hung 1e47e81869 Revert "Only sort leaves on non-ANDNOT/ORNOT cells" 
This reverts commit 5ec5f6dec7.
 2019-08-14 15:23:25 -07:00
Eddie Hung 5ec5f6dec7 Only sort leaves on non-ANDNOT/ORNOT cells 2019-08-14 11:25:56 -07:00
Eddie Hung 0e128510c0
Revert "Since $_ANDNOT_ is not symmetric, do not sort leaves" 2019-08-14 10:40:53 -07:00
Marcin Kościelnicki 3c75a72feb move attributes to wires 2019-08-13 19:36:59 +00:00
Clifford Wolf 0c5db07cd6 Fix various NDEBUG compiler warnings, closes #1255 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-13 13:29:03 +02:00
Marcin Kościelnicki c6d5b97b98 review fixes 2019-08-13 00:35:54 +00:00
Marcin Kościelnicki f4c62f33ac Add clock buffer insertion pass, improve iopadmap. 
A few new attributes are defined for use in cell libraries:

- iopad_external_pin: marks PAD cell's external-facing pin.  Pad
  insertion will be skipped for ports that are already connected
  to such a pin.
- clkbuf_sink: marks an input pin as a clock pin, requesting clock
  buffer insertion.
- clkbuf_driver: marks an output pin as a clock buffer output pin.
  Clock buffer insertion will be skipped for nets that are already
  driven by such a pin.

All three are module attributes that should be set to a comma-separeted
list of pin names.

Clock buffer insertion itself works as follows:

1. All cell ports, starting from bottom up, can be marked as clock sinks
   (requesting clock buffer insertion) or as clock buffer outputs.
2. If a wire in a given module is driven by a cell port that is a clock
   buffer output, it is in turn also considered a clock buffer output.
3. If an input port in a non-top module is connected to a clock sink in a
   contained cell, it is also in turn considered a clock sink.
4. If a wire in a module is driven by a non-clock-buffer cell, and is
   also connected to a clock sink port in a contained cell, a clock
   buffer is inserted in this module.
5. For the top module, a clock buffer is also inserted on input ports
   connected to clock sinks, optionally with a special kind of input
   PAD (such as IBUFG for Xilinx).
6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit
   attribute is set on it.
 2019-08-13 00:16:38 +02:00
Eddie Hung e4a0971581 Since $_ANDNOT_ is not symmetric, do not sort leaves 2019-08-12 11:17:15 -07:00
Clifford Wolf f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup 
Cleanup a few barnacles across codebase
 2019-08-10 09:52:14 +02:00
Clifford Wolf 6d0be8d206 Disable NMUX, AOI3, OAI3, AOI4, OAI4 in ABC default gate lib, add "abc -g all", fixes #1273 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-09 19:17:59 +02:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung 7164996921 RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
Eddie Hung e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Eddie Hung 48d0f99406 stoi -> atoi 2019-08-07 11:09:17 -07:00
Eddie Hung 58e512ab70 Add comment 2019-08-07 09:54:27 -07:00
Eddie Hung f20acbc813 Revert "Add TODO" 
This reverts commit 6068a6bf0d91e3ab9a5eaa33894a816f1560f99a.
 2019-08-07 09:54:27 -07:00
Eddie Hung 789585a744 Add TODO 2019-08-07 09:54:27 -07:00
Eddie Hung 8a8c1d7857 Compute box_lookup just once 2019-08-07 09:54:27 -07:00
Eddie Hung c11ad24fd7 Use std::stoi instead of atoi(<str>.c_str()) 2019-08-06 16:45:48 -07:00
Eddie Hung 046e1a5214 Use State::S{0,1} 2019-08-06 16:22:47 -07:00
Eddie Hung 3486235338 Make liberal use of IdString.in() 2019-08-06 16:18:18 -07:00
Clifford Wolf 100c377451 Redesign of cell cost API 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-07 01:12:14 +02:00
Clifford Wolf 023086bd46 Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 04:47:55 +02:00
Clifford Wolf 0917a5cf72
Merge pull request #1238 from mmicko/vsbuild_fix 
Visual Studio build fix
 2019-08-02 17:07:39 +02:00
Miodrag Milanovic 28b7053a01 Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
Miodrag Milanovic 35d28de478 Visual Studio build fix 2019-07-31 09:10:24 +02:00
Eddie Hung 5939b5d636
Merge pull request #1188 from YosysHQ/eddie/abc9_push_inverters 
abc9: push inverters driving box inputs (comb outputs) through $lut soft logic
 2019-07-16 08:53:47 -07:00
Eddie Hung ba8ccbdea8
Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix 
abc9/ice40: encapsulate SB_CARRY+SB_LUT4 into one box
 2019-07-16 08:52:14 -07:00
Miodrag Milanovic 2b469e82a7 Fix check logic in extract_fa 2019-07-16 10:35:18 +02:00
Eddie Hung 9b91d815b5 If ConstEval fails do not log_abort() but return gracefully 2019-07-13 04:13:57 -07:00
Eddie Hung fb062c3426 Add comment 2019-07-13 00:52:21 -07:00
Eddie Hung e9bdc86c0e duplicate -> clone 2019-07-12 19:33:02 -07:00
Eddie Hung be0cb7f4b8 More cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 7d583f9e57 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 83f23a24a8 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 1adbfb5533 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 39a7c7c54c More cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 91c07be196 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 399e1ec870 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 58dbb28fd3 Cleanup 2019-07-12 19:30:18 -07:00
Eddie Hung 7dc15bdd2d Do not double count cells in abc 2019-07-12 08:22:26 -07:00
Eddie Hung 237d8651a5 Error out if abc9 not called with -lut or -luts 2019-07-11 09:58:00 -07:00
Eddie Hung 0c3ed73dad Count $_NOT_ cells turned into $luts 2019-07-11 09:55:14 -07:00
Eddie Hung 33862d0445 WIP for fixing partitioning, temporarily do not partition 2019-07-11 09:22:52 -07:00
Eddie Hung c0abd18799 Enable &mfs for abc9, even if it only currently works for ice40 2019-07-11 08:49:06 -07:00
Eddie Hung 9f608d6be3 write_verilog with *.v extension 2019-07-10 20:25:59 -07:00
Eddie Hung 71acd3ddcf Remove -retime from abc9, revert to abc behav with separate clock/en domains 2019-07-10 18:57:44 -07:00
Eddie Hung 052060f109 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-10 16:05:41 -07:00
whitequark ea447220da attrmap: also consider process, switch and case attributes. 2019-07-10 12:30:53 +00:00
Eddie Hung c2db70f41e Increment _TECHMAP_BITS_CONNMAP_ by one since counting from zero 2019-07-09 12:14:00 -07:00
Eddie Hung b5072256f2 Update muxcover doc as per @ZirconiumX 2019-07-08 12:50:59 -07:00
Eddie Hung 3681162c8d atoi -> stoi 2019-07-08 11:00:06 -07:00
Eddie Hung a34c5612e7 Add muxcover -mux2=cost option 2019-07-08 10:59:12 -07:00
Eddie Hung ef757002db Also remove $__ABC_FF_ 2019-07-01 10:55:24 -07:00
Eddie Hung 699d8e3939 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-07-01 10:44:42 -07:00
Gabriel L. Somlo 8cb3655ecd Make abc9 pass aware of optional ABCEXTERNAL override 
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
 2019-06-28 14:56:16 -04:00
Eddie Hung 4a2a93aa06 Fix spacing 2019-06-28 11:10:36 -07:00
Eddie Hung a625854ac5 Do not use Module::remove() iterator version 2019-06-27 15:29:20 -07:00
Eddie Hung 137c91d9a9 Remove &retime when abc9 -fast 2019-06-27 15:17:39 -07:00
Eddie Hung 6bf73e3546 Cleanup abc9.cc 2019-06-27 15:15:56 -07:00
Eddie Hung 6c256b8cda Merge origin/master 2019-06-27 11:20:15 -07:00
Eddie Hung c226af3f56 Fix spacing 2019-06-26 20:03:34 -07:00
Eddie Hung 26efd6f0a9 Support more than one port in the abc_scc_break attr 2019-06-26 19:57:54 -07:00
Eddie Hung d2fed0a7f1 nullptr check 2019-06-25 06:06:32 -07:00
Eddie Hung a19226c174 Fix for abc_scc_break is bus 2019-06-24 22:16:56 -07:00
Eddie Hung 5605002d8a More meaningful error message 2019-06-24 22:12:55 -07:00
Eddie Hung babadf5938 Do not use log_id as it strips \\, also fix scc for |wire| > 1 2019-06-24 22:04:22 -07:00
Eddie Hung 49a762ba46 Fix abc9's scc breaker, also break on abc_scc_break attr 2019-06-24 21:53:18 -07:00
Eddie Hung 1abe93e48d Merge remote-tracking branch 'origin/master' into xaig 2019-06-21 17:43:29 -07:00
Eddie Hung ad296d77ab Do not rename non LUT cells in abc9 2019-06-21 17:18:04 -07:00
Eddie Hung e01bab6c64
Merge pull request #1108 from YosysHQ/clifford/fix1091 
Add support for partial matches to muxcover
 2019-06-21 17:13:41 -07:00
Clifford Wolf ec979475e7 Replace "muxcover -freedecode" with "muxcover -dmux=cost" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 19:24:41 +02:00
Eddie Hung 6d74cf0d2b
Merge pull request #1085 from YosysHQ/eddie/shregmap_improve 
Improve shregmap to handle case where first flop is common to two chains
 2019-06-21 08:56:56 -07:00
Clifford Wolf 9286b6f013 Add "muxcover -freedecode" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-21 10:02:10 +02:00
Eddie Hung 54f3237720 Fix gcc warning of potentially uninitialised 2019-06-20 22:10:43 -07:00
Clifford Wolf 891ea6512e Improvements in muxcover 
- Slightly under-estimate cost of decoder muxes
- Prefer larger muxes at tree root at same cost
- Don't double-count input cost for partial muxes
- Add debug log output
 2019-06-20 19:47:59 -07:00
Clifford Wolf 40188457d1 Add support for partial matches to muxcover, fixes #1091 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 19:47:59 -07:00
Eddie Hung 0e97e6a00d Fix simple_abc9/generate test with 1'bx at MSB 2019-06-20 19:41:27 -07:00
Eddie Hung e612dade12 Merge remote-tracking branch 'origin/master' into xaig 2019-06-20 19:00:36 -07:00
Eddie Hung 3f34779d64 Do not call "setundef -zero" in abc9 2019-06-20 17:38:04 -07:00
Eddie Hung e63324f5ef Actually, there might not be any harm in updating sigmap... 2019-06-20 17:03:05 -07:00
Eddie Hung 9c61fb0e0c Add comment as per @cliffordwolf 2019-06-20 16:57:54 -07:00
Clifford Wolf 06eb87bcb7 Improve shregmap help message, fixes #1113 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-06-20 15:23:55 +02:00
Eddie Hung 96ade54993 Fix bug in #1078, add entry to CHANGELOG 2019-06-19 09:51:11 -07:00
Eddie Hung d80678e581 Cleanup 2019-06-17 15:10:33 -07:00
Eddie Hung 3ebba74461 Merge branch 'xaig' into xaig_dff 2019-06-17 13:51:53 -07:00
Eddie Hung 4d6d593fe3 &scorr before &sweep, remove &retime as recommended 2019-06-17 13:32:08 -07:00
Eddie Hung a474fe937b Merge branch 'xaig' into xaig_dff 2019-06-17 13:20:19 -07:00
Eddie Hung 63fc879a5f Copy not move parameters/attributes 2019-06-17 13:19:45 -07:00
Eddie Hung 7dd3a7f161 Merge branch 'xaig' into xaig_dff 2019-06-17 12:58:41 -07:00
Eddie Hung b45d06d7a3 Fix leak removing cells during ABC integration; also preserve attr 2019-06-17 12:54:24 -07:00
Eddie Hung 5ce672d1c5 Merge remote-tracking branch 'origin/xaig' into xaig_dff 2019-06-17 12:14:55 -07:00
Eddie Hung 7250c57c5a Re-enable &dc2 2019-06-17 10:28:51 -07:00
Eddie Hung fb90d8c18c Cleanup 2019-06-16 09:34:26 -07:00
Eddie Hung 3ed95dae8d Cleanup 2019-06-15 22:48:16 -07:00
Eddie Hung 416312b9ed abc9 to recover_init by default 2019-06-15 22:44:45 -07:00
Eddie Hung 2309459605 Do not treat $__ABC_FF_ as a user cell 2019-06-15 19:36:55 -07:00
Eddie Hung cdfb634977 Cleanup 2019-06-15 18:18:56 -07:00
Eddie Hung c2f3f116d0 Use $__ABC_FF_ instead of $_FF_ 2019-06-15 18:16:14 -07:00
Eddie Hung a76c8a7ffd Fix initialisation of flops 2019-06-15 09:46:35 -07:00
Eddie Hung ac18a76beb Map to $_FF_ instead of $_DFF_P_ to prevent recursion issues 2019-06-15 09:34:48 -07:00
Eddie Hung da487c4f31 For now, short $_DFF_[NP]_ from ff_map.v at re-integration 2019-06-15 09:08:18 -07:00
Eddie Hung 2d85725604 Get rid of compiler warnings 2019-06-14 13:07:56 -07:00
Eddie Hung a632799d5b Update abc9 -D doc 2019-06-14 12:29:46 -07:00
Eddie Hung e391fc8e7b Enable "abc9 -D <num>" for timing-driven synthesis 2019-06-14 12:28:01 -07:00
Eddie Hung a48b5bfaa5 Further cleanup based on @daveshah1 2019-06-14 12:25:06 -07:00
Eddie Hung 751e640c1d Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig 2019-06-14 10:29:16 -07:00
Eddie Hung a5425a2f7e Remove extra semicolon 2019-06-14 10:11:34 -07:00
David Shah 9566573054 ecp5: Add abc9 option 
Signed-off-by: David Shah <dave@ds0.me>
 2019-06-14 17:15:02 +01:00
Eddie Hung 2c40b66785 Rip out all non FPGA stuff from abc9 2019-06-12 16:53:12 -07:00
Eddie Hung f81a189fb8 Fix spelling 2019-06-12 16:52:09 -07:00
Eddie Hung b3faf0246d Be more precise when connecting during ABC9 re-integration 2019-06-12 16:04:33 -07:00
Eddie Hung 2e7e73f483 Remove hacky wideports_split from abc9 2019-06-12 15:52:49 -07:00
Eddie Hung d9974b85e7 Fix compile errors when #if 1 for debug 2019-06-12 15:47:39 -07:00
Eddie Hung 8bb67fa67c Do not call abc9 if no outputs 2019-06-12 10:18:44 -07:00
Eddie Hung 14e870d4c4 More write_xaiger cleanup 2019-06-12 10:00:57 -07:00
Eddie Hung b21d29598a Consistency 2019-06-12 09:40:51 -07:00
Eddie Hung b2c72f74f0 Merge branch 'xc7mux' into xaig 2019-06-12 09:14:27 -07:00
Eddie Hung afd620fd5f Typo: wire delay is -W argument 2019-06-12 09:13:53 -07:00
Eddie Hung 2cbcd6224c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" 
This reverts commit a138381ac3, reversing
changes made to b77c5da769.
 2019-06-12 09:05:02 -07:00
Eddie Hung 1e838a8913 Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx" 2019-06-12 08:49:15 -07:00
Eddie Hung 4c9fde87d1 Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" 
This reverts commit 2dffa4685b.
 2019-06-12 08:48:45 -07:00
Eddie Hung 2dffa4685b Add "-W' wire delay arg to abc9, use from synth_xilinx 2019-06-11 17:10:47 -07:00
Eddie Hung 6cdea93724 Revert "Try way that doesn't involve creating a new wire" 
This reverts commit 2f427acc9e.
 2019-06-11 16:05:42 -07:00
Eddie Hung d26646051c Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux" 
This reverts commit 5174082208, reversing
changes made to 54379f9872.
 2019-06-11 16:05:27 -07:00
Eddie Hung 5174082208 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-11 15:48:41 -07:00
Eddie Hung 2f427acc9e Try way that doesn't involve creating a new wire 2019-06-11 15:48:20 -07:00
Eddie Hung a138381ac3 Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux 2019-06-10 16:21:43 -07:00
Eddie Hung f19aa8d989 If d_bit already in sigbit_chain_next, create extra wire 2019-06-10 16:16:40 -07:00
Eddie Hung a1d4ae78a0 Revert "Rename shregmap -tech xilinx -> xilinx_dynamic" 
This reverts commit 94a5f4e609.
 2019-06-10 14:34:43 -07:00
Eddie Hung 7d27e1e431 Revert "shregmap -tech xilinx_dynamic to work -params and -enpol" 
This reverts commit 45d1bdf83a.
 2019-06-10 14:34:16 -07:00
Eddie Hung 3579d68193 Revert "Refactor to ShregmapTechXilinx7Static" 
This reverts commit e1e37db860.
 2019-06-10 14:34:15 -07:00
Eddie Hung b6a39351f4 Revert "Add -tech xilinx_static" 
This reverts commit dfe9d95579.
 2019-06-10 14:34:14 -07:00
Eddie Hung e1dbeb3004 Revert "Continue support for ShregmapTechXilinx7Static" 
This reverts commit 72eda94a66.
 2019-06-10 14:34:14 -07:00
Eddie Hung 9d8563178e Revert "shregmap -tech xilinx_static to handle INIT" 
This reverts commit 935df3569b.
 2019-06-10 14:34:12 -07:00
Eddie Hung 5a46a0b385 Fine tune aigerparse 2019-06-07 16:57:32 -07:00
Eddie Hung 30abdaf3b2 Allow muxcover costs to be changed 2019-06-07 08:34:11 -07:00
Eddie Hung fe4394fb9a Allow muxcover costs to be changed 2019-06-07 08:30:39 -07:00
Eddie Hung eaee250a6e Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux 2019-06-06 14:06:59 -07:00
Eddie Hung 83450a9489 Move muxpack from passes/techmap to passes/opt 2019-06-06 12:15:13 -07:00
Eddie Hung 3dd0682f29 Update doc 2019-06-06 12:11:59 -07:00
Eddie Hung 3e76e3a6fa Add tests, fix for != 2019-06-06 11:54:38 -07:00
Eddie Hung 543dd11c7e Missing file 2019-06-06 11:03:45 -07:00
Eddie Hung 7bd1c664a6 Initial adaptation of muxpack from shregmap 2019-06-06 10:51:02 -07:00
Eddie Hung fd8ef128bf Missing doc for -tech xilinx in shregmap 2019-06-05 14:21:44 -07:00
Eddie Hung 935df3569b shregmap -tech xilinx_static to handle INIT 2019-06-05 12:55:59 -07:00
Eddie Hung 72eda94a66 Continue support for ShregmapTechXilinx7Static 2019-06-05 12:33:55 -07:00
Eddie Hung dfe9d95579 Add -tech xilinx_static 2019-06-05 11:14:14 -07:00
Eddie Hung e1e37db860 Refactor to ShregmapTechXilinx7Static 2019-06-05 11:08:08 -07:00
Eddie Hung 45d1bdf83a shregmap -tech xilinx_dynamic to work -params and -enpol 2019-06-05 10:21:57 -07:00
Eddie Hung 94a5f4e609 Rename shregmap -tech xilinx -> xilinx_dynamic 2019-06-04 14:34:36 -07:00
Eddie Hung 295bd8d0bf Remove dupe 2019-06-03 12:32:20 -07:00
Eddie Hung eb08e71bd1 Merge branch 'xaig' into xc7mux 2019-05-31 13:03:03 -07:00
Eddie Hung a379234f56 Throw out unused code inherited from abc 2019-05-31 12:50:11 -07:00
Eddie Hung 4a6b9af227 Fix spelling 2019-05-30 15:50:47 -07:00
Eddie Hung a44fe3a632 Revert "Re-enable &dc2" 
This reverts commit 8c58c728a7.
 2019-05-30 11:41:50 -07:00
Eddie Hung 0800846e73 Do not double count LUT1s 2019-05-30 11:32:14 -07:00
Eddie Hung 8c58c728a7 Re-enable &dc2 2019-05-30 00:42:41 -07:00
Eddie Hung 2560f92f29 Reduce -W to 160 2019-05-29 23:01:46 -07:00
Eddie Hung 854557814e Erase all boxes before stitching 2019-05-29 19:17:36 -07:00
Eddie Hung b955344ecd Call &if with -W 250 2019-05-29 16:34:52 -07:00
Eddie Hung ecaa7856e9 Add some debug to abc9 2019-05-29 15:21:41 -07:00
Eddie Hung 4a76b425cc Misspell 2019-05-28 08:44:59 -07:00
Eddie Hung 89bd6b8504 If driver not found, use LUT2 2019-05-27 23:12:21 -07:00
Eddie Hung 4df37c77fd Disconnect all ABC boxes too 2019-05-27 19:40:27 -07:00
Eddie Hung 75bd41eaeb Parse without wideports 2019-05-27 12:22:05 -07:00
Eddie Hung bf3b8d5e45 Remove mapped_mod when done 2019-05-27 12:19:21 -07:00
Eddie Hung 234156c01a Instantiate cell type (from sym file) otherwise 'clean' warnings 2019-05-27 12:16:10 -07:00
Eddie Hung 03b289a851 Add 'cinput' and 'coutput' to symbols file for boxes 2019-05-27 11:38:52 -07:00
Eddie Hung 3981eba999 ABC9 to call &sweep 2019-05-26 11:31:35 -07:00
Eddie Hung 086b6560b4 Typo 2019-05-26 03:17:20 -07:00
Eddie Hung 823153e418 Combine ABC_COMMAND_LUT 2019-05-26 02:47:06 -07:00
Eddie Hung 32a4c10c0d Fix "a" extension 2019-05-26 02:44:36 -07:00
Eddie Hung 6ad09bfcea Add &fraig and &mfs back 2019-05-24 15:10:18 -07:00
Eddie Hung fb09c6219b Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-21 14:21:00 -07:00
Henner Zeller 5e443a5d0d Fix two instances of integer-assignment to string. 
o In cover.cc, the int-result of mkstemps() was assigned to a string
  and silently interpreted as a single-character filename with a funny
  value. Fix with the intent: assign the filename.
o in libparse.cc, an int was assigned to a string, but depending on
  visible constructors, this is ambiguous. Explicitly cast this to
  a char.
 2019-05-14 22:01:15 -07:00
Makai Mann 2f5cfa014b Zinit option '-singleton' -> '-all' 2019-05-10 10:23:14 -07:00
Clifford Wolf 3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings 
Fix all warnings that occurred when compiling with gcc9
 2019-05-08 11:25:22 +02:00
Kristoffer Ellersgaard Koch 30c762d3a1 Fix all warnings that occurred when compiling with gcc9 2019-05-08 10:27:14 +02:00
David Shah a84256aa36 abc: Fix handling of postfixed names (e.g. for retiming) 
Signed-off-by: David Shah <dave@ds0.me>
 2019-05-04 17:23:44 +01:00
David Shah 5ce9113eda abc: Improve name recovery 
Signed-off-by: David Shah <dave@ds0.me>
 2019-05-04 16:53:25 +01:00