afd5366fc2
extract_rdff: Add initvals parameter.
...
This is not used yet, but will be needed when read port reset/initial
value support lands.
2021-05-23 22:05:26 +02:00
1eea06bcc0
Add new helper class for merging FFs into cells, use for memory_dff.
...
Fixes #1854 .
2021-05-23 14:46:59 +02:00
c4cc888b2c
kernel/rtlil: Extract some helpers for checking memory cell types.
...
There will soon be more (versioned) memory cells, so handle passes that
only care if a cell is memory-related by a simple helper call instead of
a hardcoded list.
2021-05-22 21:43:00 +02:00
c7076495f1
kernel/mem: Add a check() function.
2021-05-22 21:42:53 +02:00
ff9e0394b8
kernel/mem: defer port removal to emit()
2021-05-22 21:42:53 +02:00
d6d5c2ef34
rtlil: add const accessors for modules, wires, and cells
2021-03-25 10:44:08 -04:00
d9ec35a526
split CodingReadme into multiple files
2021-03-22 19:16:25 +01:00
6a0d1e117d
Merge pull request #2681 from msinger/fix-issue2606
...
Fix check for bad std::regex
2021-03-19 08:47:07 +01:00
3aa10e90ba
modtools: fix use-after-free of cell pointers in ModWalker
...
cell_inputs and cell_outputs retain cell pointers as their keys across
invocations of setup(), which may however be invalidated in the meantime
(as happens in e.g. passes/opt/share.cc:1432). A later rehash of the
dicts (caused by inserting in ModWalker::add_wire()) will cause them to
be dereferenced.
2021-03-18 13:50:13 +01:00
d05d47cc04
Fix check for bad std::regex ( fixes #2606 )
2021-03-17 23:35:26 +01:00
dd6d34f461
blackbox: Include whiteboxed modules
...
Signed-off-by: gatecat <gatecat@ds0.me>
2021-03-17 13:58:04 +00:00
937392ad33
Replace assert in get_reference with more useful error message
2021-03-17 09:32:13 +01:00
f965b3fa54
rtlil: Disallow 0-width chunks in SigSpec.
...
Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.
Also fix another minor issue with possible non-canonical SigSpec.
Fixes #2623 .
2021-03-15 17:16:24 +01:00
4e03865d5b
Add support for memory writes in processes.
2021-03-08 20:16:29 +01:00
3d2aef0bde
Remove a few functions that, in fact, did not exist in the first place.
2021-03-06 01:19:49 +01:00
55e5bd4213
Replace assert in addModule with more useful error message
2021-03-06 00:10:28 +01:00
90b40aa51f
clk2fflogic: nice names for autogenerated signals
2021-03-02 18:28:56 -05:00
5e439b6e3f
Fix double-free on unmatched logger error pattern
...
When an expected logger error pattern is unmatched, the logger raises
another (hidden) error. Because of the previous ordering of actions,
`logv_error_with_prefix()` would inadvertently invoke `yosys_atexit()`
twice, causing a double-free.
2021-02-23 20:49:21 -05:00
4b31223e60
int -> bool
2021-02-23 17:52:43 +01:00
7c50b89b24
Adds is_wire to SigBit and SigChunk
...
Useful for PYOSYS because Python can't easily check wire against NULL.
2021-02-23 17:52:43 +01:00
fe74b0cd95
verilog: significant block scoping improvements
...
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.
Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.
1. Unlabled generate blocks are now implicitly named according to the LRM in
`label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
synthetic unnamed generate block to avoid creating extra hierarchy levels
where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
of the topmost scope, which is necessary because such wires and cells often
appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
scope, completely deferring the inspection and elaboration of nested scopes;
names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
in largely the same manner as other blocks
before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode
Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
16c4182c74
kernel/yosys.h: undef CONST on WIN32
2020-12-28 02:21:19 +01:00
ac988cfac5
kernel: undef Tcl macros interfering with cxxrtl.
2020-12-22 03:48:09 +00:00
ab9e2f4fda
Merge pull request #2487 from whitequark/cxxrtl-outlining
...
CXXRTL: implement zero-cost full coverage debug information through the magic✨ of outlining🪄 🎀 🧹
2020-12-19 04:14:31 +00:00
de99197738
timinginfo: Error instead of segfault on const signals.
...
Reported by @Ravenslofty
2020-12-15 00:51:16 +01:00
080f311040
kernel: make IdString::isPublic() const.
2020-12-12 20:50:44 +00:00
1838edf35c
bugpoint: add -wires option.
2020-12-07 09:24:35 +00:00
cc0d7244b8
tcl -h message only if YOSYS_ENABLE_TCL defined.
2020-11-23 21:48:44 -05:00
829b5cca60
Expose abc and data paths as globals
2020-11-06 14:17:15 +01:00
8720482ebd
Add new helper structures to represent memories.
2020-10-21 17:51:20 +02:00
4af04be0b7
add IdString::isPublic()
2020-09-03 17:37:58 +02:00
00e7dec7f5
Replace "ILANG" with "RTLIL" everywhere.
...
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
2020-08-26 17:29:32 +00:00
916028906a
Ensure \A_SIGNED is never used with $shiftx
...
It has no effect on the output ($shiftx doesn't perform any sign
extension whatsoever), so an attempt to use it should be caught early.
2020-08-18 19:36:24 +02:00
928fd40c2e
Respect \A_SIGNED for $shift
...
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
2020-08-18 19:36:24 +02:00
4a05cad7f8
async2sync: Support all FF types.
2020-07-30 20:22:03 +02:00
773b056ffb
ffinit: Fortify the code a bit.
...
This fixes handling of messy cases involving repeatedly setting and
removing the same init bit.
2020-07-28 17:21:15 +02:00
0c6d0d4b5d
satgen: Add support for dffe, sdff, sdffe, sdffce cells.
2020-07-24 03:19:21 +02:00
dafe04d559
Add utility module for representing flip-flops.
2020-07-23 23:39:46 +02:00
022af4f0ca
Add utility module for dealing with init attributes.
2020-07-23 20:49:48 +02:00
dc07ae9677
techmap: Add _TECHMAP_CELLNAME_ special parameter.
...
This parameter will resolve to the name of the cell being mapped. The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
2020-07-21 15:00:54 +02:00
3cb401db8c
celltypes: Fix EN port name for some FF types.
2020-07-20 23:04:10 +02:00
85a1bb17ed
satgen: Move importCell out of the header.
...
This function has no hope of ever getting inlined anyway, and it speeds
up yosys compile time by 7%.
2020-07-19 00:17:02 +02:00
d9f680b236
verilog_backend: add `-sv` option, make `-o <filename>.sv` work.
...
See #2271 .
2020-07-16 10:44:08 +00:00
c7d71f436d
Merge pull request #2168 from whitequark/assert-unused-exprs
...
Use (and ignore) the expression provided to log_assert in NDEBUG builds
2020-06-25 18:21:51 +02:00
21209d632e
Merge pull request #2135 from boqwxp/qbfsat-timeinfo
...
log and qbfsat: Also include child process usage in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver
2020-06-25 18:18:09 +02:00
e71d827590
Add add* functions for the new FF types
2020-06-23 15:40:02 +02:00
b0bee396a8
Add new builtin FF types
...
The new types include:
- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)
The new FF types are not actually used anywhere yet (this is left
for future commits).
2020-06-23 15:40:02 +02:00
28c2dd470b
log: Remove unused `_POSIX_TIMERS` branch in `PerformanceTimer::query()`.
2020-06-21 02:16:52 +00:00
a564cc806f
log, qbfsat: Include child process time in `PerformanceTimer::query()` and report the time for each call to the QBF-SAT solver.
2020-06-21 02:16:52 +00:00
08cede4669
qbfsat: Simplify solution format and replace `SigBit::str()` with `log_signal()`.
...
Co-Authored-By: Claire Wolf <claire@symbioticeda.com>
2020-06-21 02:16:11 +00:00
a3d1f8637a
qbfsat: Use bit precise mapping for hole value wires and a more robust hole spec for writing to and specializing from a solution file.
2020-06-21 02:16:11 +00:00
992d694d39
Merge pull request #2177 from boqwxp/dict-iterator-jump
...
hashlib, rtlil: Add `operator+()` and `operator+=()` to `dict` iterators
2020-06-21 02:05:12 +00:00
d71a9badda
dict: Remove guard for past-the-end iterators that might mask problems in static analysis.
...
Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-06-19 21:04:29 +00:00
3ccdab940c
rtlil: Add `Design::select()` for selecting whole modules.
2020-06-19 18:16:33 +00:00
e5a2d17b5d
hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and `dict<>::const_iterator` and add `operator+()` and `operator+=()` to `ObjIterator`.
2020-06-19 17:44:29 +00:00
c8c3c7af87
Use [[maybe_unused]] instead of YS_ATTRIBUTE(unused).
...
[[maybe_unused]] is available since C++17, so this commit adds
a polyfill YS_MAYBE_UNUSED. Once we require C++17 we can drop it.
2020-06-19 15:48:58 +00:00
118e4caa37
Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().
2020-06-19 15:48:58 +00:00
21692c4a2e
Use (and ignore) the expression provided to log_debug in NDEBUG builds.
2020-06-19 15:48:58 +00:00
2ffdb74fb1
Use (and ignore) the expression provided to log_assert in NDEBUG builds.
...
This avoids warnings in NDEBUG builds emitted when a variable is only
used in log_assert, but is always defined.
2020-06-19 15:48:58 +00:00
817411044a
Add missing [[noreturn]] to log_file_error()
...
Previously this was tagged only with YS_ATTRIBUTE(noreturn), but not
YS_NORETURN, so it got lost in #2173 , resulting in warnings in
frontends/ast/simplify.cc:
frontends/ast/simplify.cc:267:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
frontends/ast/simplify.cc:379:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
2020-06-19 11:46:06 +02:00
60478a8e3a
Use C++11 [[noreturn]] attribute.
2020-06-19 01:06:48 +00:00
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
c9c13c29df
MSVC defines TRANSPARENT too
2020-06-17 15:10:08 +02:00
7137f99658
kernel: guard include of signal.h more precisely.
...
Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM
does not have signals. (Arguably Yosys was broken even before, it was
just broken silently.)
2020-06-13 22:37:04 +00:00
483a1081e7
RTLIL: add Module::addProcess, use it in Module::cloneInto. NFC.
2020-06-09 09:55:48 +00:00
fbb346ea91
flatten: preserve original object names via hdlname attribute.
2020-06-08 20:19:41 +00:00
e558905598
RTLIL: use {get,set}_string_attribute in {get,set}_strpool_attribute.
...
The only difference in behavior is that this removes the attribute
when the pool becomes empty.
2020-06-08 20:19:41 +00:00
369dcb4e82
Merge pull request #2085 from rswarbrick/select
...
Silence warning in select.cc and pass some more args by ref
2020-06-08 15:55:52 +02:00
fbd0d8d5f0
Merge pull request #2105 from whitequark/split-flatten-off-techmap
...
Split `flatten` from `techmap` and simplify it
2020-06-08 15:27:15 +02:00
3bffd09d64
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
...
Preserve 'signed'-ness of a verilog wire through RTLIL
2020-06-04 11:23:06 +00:00
44f1e65155
Merge pull request #2070 from hackfin/master
...
Pyosys API: idict type handling
2020-06-04 11:17:08 +02:00
9338ff66b9
RTLIL: factor out RTLIL::Module::addMemory. NFC.
2020-06-04 00:02:12 +00:00
ff785cdb46
Merge pull request #1862 from boqwxp/cleanup_techmap
...
Clean up `passes/techmap/techmap.cc`
2020-05-31 20:40:48 +02:00
94c1035389
Merge pull request #1885 from Xiretza/mod-rem-cells
...
Fix modulo/remainder semantics
2020-05-29 16:37:23 +02:00
af36afe722
Merge pull request #2092 from whitequark/rtlil-no-space-control
...
Restrict RTLIL::IdString to not contain whitespace or control chars
2020-05-29 16:31:44 +02:00
efa7424fb9
Restrict RTLIL::IdString to not contain whitespace or control chars.
...
This is an existing invariant (most backends can't cope with these)
but one that was not checked or documented.
2020-05-29 06:43:18 +00:00
7c89738382
Add comments for mod/div semantics to rtlil.h
2020-05-28 22:59:04 +02:00
edd8ff2c07
Add flooring division operator
...
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.
This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
17163cf43a
Add flooring modulo operator
...
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).
This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
02bb52eef1
Merge pull request #2088 from rswarbrick/count-at
...
Minor optimisation in Module::wire() and Module::cell()
2020-05-28 09:41:17 +00:00
8a44a46806
Merge pull request #2086 from rswarbrick/sigbit
...
Use default copy constructor for RTLIL::SigBit
2020-05-28 09:40:49 +00:00
d681c9df85
Pass some more args by reference in select.cc
...
Before this patch, the code passed around std::string objects by
value. It's probably not a hot-spot, but it can't hurt to avoid the
copying.
Removing the copy and clean-up code means the resulting code is ~6.1kb
smaller when compiled with GCC 9.3 and standard settings.
2020-05-27 09:42:23 +01:00
7ff306ccdb
Minor optimisation in Module::wire() and Module::cell()
...
The existing code does a search to figure out whether id is in the
dict (with the call to count()), and then looks it up again to get the
result (with the call to at()). This version calls find() instead,
avoiding the double lookup.
Code size increases slightly (6kb). I think this is because the
contents of find() are getting inlined, and then inlined into lots of
the callsites for cell() and wire().
Looking at the compiled code before this patch, you just get
a (non-inlined) call to count() followed by a call to at(). After the
patch, the contents of find() have been inlined (so you see do_hash,
then do_lookup). The result for each function is about 30 bytes / 40%
bigger, which presumably also enlarges call-sites that inline it.
2020-05-26 16:07:36 +01:00
17b5f23f20
Use default copy constructor for RTLIL::SigBit
...
There was a handwritten copy constructor, which I'm not sure was
actually legal C++ (it unconditionally read from the 'data' member of
a union, which wouldn't have been written if wire was true). It was
also a bit less efficient than the constructor you get from the
compiler by default (which is allowed to just copy the memory).
This gives a marginal (~0.25%) decrease in code size when compiled
with GCC 9.3.
2020-05-26 13:18:01 +01:00
8f87ccec9b
Use c_str(), not str() for IdString/std::string == and != operators
...
These operators work by fetching the string from the global string
table and then comparing with the std::string that was passed in as
rhs.
Using str() means that we create a std::string (strlen; malloc;
memcpy), compare for equality (another memcmp if they have the same
length) and then finally free the string.
Using c_str() means that we pass the const char* straight to
std::string's equality operator. This ends up as a call to
std::string::compare (the const char* flavour), which is essentially
strcmp.
2020-05-26 12:27:15 +01:00
637650597b
Merge pull request #2059 from boqwxp/logger-vector-to-dict
...
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-21 15:36:30 +02:00
026fed3135
Merge pull request #2046 from PeterCrozier/trap
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Extend YS_DEBUGTRAP to MacOS.
2020-05-20 10:12:24 +02:00
6eea4b3d79
kernel: Try an order-independent approach to hashing `dict`.
...
Co-Authored-By: David Shah <dave@ds0.me>
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-19 23:32:53 +00:00
43c34a7828
idict handling in wrapper
...
- Also, re-applied no-line-break workaround to rtlil.h to make parser
catch all methods.
2020-05-19 11:13:49 +02:00
aee439360b
Add force_downto and force_upto wire attributes.
...
Fixes #2058 .
2020-05-19 01:42:40 +02:00
8297afe925
log: Use `dict` instead of `std::vector<std::pair>` for `log_expect_{error, warning, log}` to better express the intent that each element is unique.
2020-05-15 00:55:32 +00:00
67fc0c3698
abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
...
instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
976edb7597
kernel: Ensure `dict` always hashes to the same value given the same contents.
2020-05-14 20:06:55 +00:00
35b94d1f66
kernel: Re-implement `dict` hash code as a `dict` member function instead of a specialized template for `hash_ops`.
2020-05-14 20:06:55 +00:00
dabeb1e8a1
techmap: prefix special wires with backslash for use as IdString
2020-05-14 20:06:55 +00:00
2fb4931e5b
Add specialized `hash()` for type `dict` and use a `dict` instead of a `std::map` for `techmap_cache` and `techmap_do_cache`.
2020-05-14 20:06:53 +00:00
7146c0339e
timinginfo: ignore $specify2 cells if EN is false
2020-05-14 10:33:56 -07:00
b3e2538a14
abc9_ops: fix bypass boxes using (* abc9_bypass *)
2020-05-14 10:33:56 -07:00
7812a2959b
kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
2020-05-14 10:33:56 -07:00
b66904e9cd
Revert "Merge branch 'eddie/kernel_makeblackbox' into eddie/abc9_auto_dff"
...
This reverts commit e08497c7c9d8a6f7a3eccddf2149c45d9ecff207, reversing
changes made to e366fd55122236a21c6daee6765724add840a1f9.
2020-05-14 10:33:56 -07:00
039c3a5982
kernel: Module::makeblackbox() to clear connections + delete wires last
2020-05-14 10:33:56 -07:00
495dcfc812
Consolidate Linux and Mac version of YS_DEBUGTRAP_IF_DEBUGGING.
2020-05-13 14:17:00 +01:00
3988f935b8
Extend YS_DEBUGTRAP to MacOS.
2020-05-13 13:11:49 +01:00
8ec3b6db1c
Fix clang compiler warning
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-08 10:13:39 +02:00
ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
...
Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
...
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
...
C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
d1c8837572
Merge pull request #2000 from whitequark/log_error-trap
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kernel: Trap in `log_error()` when a debugger is attached
2020-05-03 16:19:42 +00:00
e9f2d3f009
kernel: Trap in `log_error()` when a debugger is attached.
...
The workflow of debugging fatal pass errors in Yosys is flawed in
three ways:
1. Running Yosys under a debugger is sufficient for the debugger
to catch some fatal errors (segfaults, aborts, STL exceptions)
but not others (`log_error()`, `log_cmd_error()`). This is
neither obvious nor easy to remember.
2. To catch Yosys-specific fatal errors, it is necessary to set
a breakpoint at `logv_error_with_prefix()`, or at least,
`logv_error()`. This is neither obvious nor easy to remember,
and GDB's autocomplete takes many seconds to suggest function
names due to the large amount of symbols in Yosys.
3. If a breakpoint is not set and Yosys encounters with such
a fatal error, the process terminates. When debugging a crash
that takes a long time to reproduce (or a nondeterministic crash)
this can waste a significant amount of time.
To solve this problem, add a macro `YS_DEBUGTRAP` that acts as a hard
breakpoint (if available), and a macro `YS_DEBUGTRAP_IF_DEBUGGING`
that acts as a hard breakpoint only if debugger is present.
Then, use `YS_DEBUGTRAP_IF_DEBUGGING` in `logv_error_with_prefix()`
to obviate the need for a breakpoint on nearly every platform.
Co-Authored-By: Alberto Gonzalez <boqwxp@airmail.cc>
2020-05-03 12:02:34 +00:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
b43c282e4e
Add WASI platform support.
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This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
eabc00de8b
Merge pull request #1992 from YosysHQ/eddie/bugpoint_help
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bugpoint: improve help text
2020-04-27 11:12:17 -07:00
5f9cd2e2f6
Preserve 'signed'-ness of a verilog wire through RTLIL
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As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987 , now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
e602184856
bugpoint: (* keep *) to (* bugpoint_keep *); also apply to modules/cells
2020-04-24 13:26:04 -07:00
d3555c667c
verific: do not assert if wire not found; warn instead
2020-04-23 16:28:11 -07:00
86ab7d3a6e
kernel: Cell::getParam() to throw exception again if not found
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As it did before #1945
2020-04-22 16:25:23 -07:00
bf22cda912
Merge pull request #1969 from boqwxp/pool_emplace
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kernel: Add `pool` support for rvalue references and C++11 move semantics.
2020-04-22 12:10:42 -07:00
a7c66fdc61
pool: add emplace() function
2020-04-22 08:14:07 -07:00
746c29b171
kernel: Rename arguments to rvalue-reference-accepting functions.
2020-04-21 17:17:47 +00:00
b4d76309e1
Use default parameter value in getParam
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Fixes #1822 .
2020-04-21 19:09:00 +02:00
06a344efcb
ilang, ast: Store parameter order and default value information.
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Fixes #1819 , #1820 .
2020-04-21 19:09:00 +02:00
79efaa65ad
idict: Make iterator go forward.
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Previously, iterating over an idict returned its contents in reverse.
2020-04-21 19:09:00 +02:00
ecaa892e35
Add rvalue-reference-accepting `entry_t` constructor for `pool`.
2020-04-20 05:37:10 +00:00
95b94ad19b
In `pool`, construct `entry_t`s in-place and add an rvalue-accepting-and-forwarding `insert()` method.
2020-04-20 02:18:30 +00:00
b6f624b56b
rtlil: add AttrObject::has_attribute.
2020-04-16 21:49:49 +00:00
ff7a1a1568
rtlil: add AttrObject::{get,set}_string_attribute.
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And make {get,set}_src_attribute use those functions.
2020-04-16 21:45:29 +00:00
c2804a68c2
Merge pull request #1896 from boqwxp/read_stdin_repl
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Frontend: allow reading file input from stdin, like a REPL heredoc mode
2020-04-16 17:18:29 +00:00
aa552cefa3
Merge pull request #1927 from YosysHQ/eddie/design_remove_assert
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kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
2020-04-16 08:06:12 -07:00
90a1c6b6a4
Merge pull request #1915 from boqwxp/dict_move_semantics
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kernel: Add `dict` support for rvalue references and C++11 move semantics.
2020-04-16 13:29:13 +00:00
5eb1f83d2d
Rename overloaded `insert()` to `emplace()` and add overloaded versions for all possible lvalue/rvalue combinationsfor its arguments.
2020-04-16 03:54:33 +00:00
76c9e1c265
Use script-style heredoc syntax for REPL heredocs.
2020-04-15 16:15:51 +00:00
b5ecbbef94
Allow reading file input from stdin, improving REPL experience.
2020-04-15 16:15:50 +00:00
3c4758c60e
Merge pull request #1894 from YosysHQ/mingw_fix
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Fix compile for mingw
2020-04-15 17:43:31 +02:00
dc3d432aaa
Merge pull request #1916 from YosysHQ/eddie/kernel_makeblackbox
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kernel: Module::makeblackbox() to clear connections too
2020-04-15 08:42:39 -07:00
0b7a5879e5
Merge pull request #1830 from boqwxp/qbfsat
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Add `qbfsat` command to integrate exists-forall solving and specialization
2020-04-15 17:33:50 +02:00
bc21e58bb5
Fix compile for mingw
2020-04-15 16:38:09 +02:00
635b2b8939
kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
2020-04-14 09:31:06 -07:00
9547d8c13e
kernel: Module::makeblackbox() to clear connections too
2020-04-13 20:37:22 -07:00
c479fdeb85
Add `dict` support for rvalue references and C++11 move semantics.
2020-04-13 23:52:16 +00:00
0d789c5a3b
Support custom PROGRAM_PREFIX
2020-04-10 10:38:40 +02:00
7c06cb6157
Merge pull request #1562 from whitequark/write_cxxrtl
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write_cxxrtl: new backend
2020-04-10 01:24:31 +00:00
371af7da38
Merge pull request #1858 from YosysHQ/eddie/fix1856
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kernel: include "kernel/constids.inc"
2020-04-09 14:23:47 -07:00
60ffc21e64
kernel: include "kernel/constids.inc" instead of "constids.inc"
2020-04-09 09:14:03 -07:00
516857f3ba
[NFCI] Deduplicate builtin FF cell types list
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A few passes included the same list of FF cell types. Make it a global
const instead.
The zinit pass also seems to include a list like that, but given that
it seems to be completely broken at the time (see #1568 discussion),
I'm going to pretend I didn't see that.
2020-04-09 18:05:06 +02:00
d20e971725
write_cxxrtl: new backend.
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This commit adds a basic implementation that isn't very performant
but implements most of the planned features.
2020-04-09 04:08:36 +00:00
a4598d64ef
Hole value recovery and specialization implementation for `qbfsat` command.
2020-04-04 22:13:25 +00:00
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
2d86563bb2
kernel: IdString::in(const IdString &) as per @Tjoppen
2020-04-02 07:14:08 -07:00
18d85b88ae
kernel: fix formatting (thanks @boqwxp)
2020-04-02 07:14:08 -07:00
7bcbf0c9d1
kernel: use C++11 fold hack to prevent recursion
2020-04-02 07:14:08 -07:00
ba13a40ef4
Revert "kernel: IdString:in() to use perfect forwarding"
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This reverts commit 7b2a85aedf24affc2e1202c78e70e6a317f5bf29.
2020-04-02 07:14:08 -07:00
6d4f01c3fa
kernel: separate IdString::put_reference() out to help inlining
2020-04-02 07:14:08 -07:00
4a8cecf03e
kernel: IdString:in() to use perfect forwarding
2020-04-02 07:14:08 -07:00
164dd0f6b2
kernel: Use constids.inc for global/constant IdStrings
2020-04-02 07:14:08 -07:00
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
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kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
c90324662c
Merge pull request #1828 from YosysHQ/eddie/celltypes_speedup
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kernel: share a single CellTypes within a pass
2020-04-01 14:17:45 -07:00
ae05795f54
Clean up pseudo-private member usage in `kernel/yosys.cc`.
2020-04-01 02:53:56 +00:00
348e892314
kernel: pass-by-value into Design::scratchpad_set_string() too
2020-03-27 12:21:09 -07:00
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
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This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
6ca7844cec
kernel: const Wire* overload -> Wire* !!!
2020-03-26 16:21:30 -07:00
f97b90e40b
kernel: Cell::set{Port,Param}() to pass by value, but use std::move
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Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
2020-03-26 14:33:06 -07:00
7ad7f41bc5
kernel: share a single CellTypes within a pass
2020-03-18 12:21:40 -07:00
940640ac44
kernel: SigSpec copies to not trigger pack()
2020-03-18 11:51:00 -07:00
4555b5b819
kernel: more pass by const ref, more speedups
2020-03-18 11:21:53 -07:00
8b12e97153
kernel: speedup
2020-03-18 08:48:36 -07:00
8c45ea9f0e
kernel: use const reference for SigSet too
2020-03-17 10:22:33 -07:00
bc51e609cb
kernel: fix DeleteWireWorker
2020-03-17 10:22:16 -07:00
ed4fa19ba2
Update Copyright
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-03-16 16:28:25 +01:00
418c069561
License: bump year and add title
2020-03-14 16:46:07 +00:00
395daf6ced
exclude clang from checking
2020-03-13 17:23:27 +01:00
8f221118d2
Add YS_ prefix to macros, add explanation and apply to older version as well
2020-03-13 17:19:54 +01:00
432a09af80
kernel: SigSpec use more const& + overloads to prevent implicit SigSpec
2020-03-13 08:17:39 -07:00
7c54e61979
Use boost xpressive for gcc 4.8
2020-03-13 14:58:35 +01:00
b567f03c26
kernel: optimise Module::remove(const pool<RTLIL::Wire*>()
2020-03-12 16:00:34 -07:00
a076052fe4
kernel: SigPool to use const& + overloads to prevent implicit SigSpec
2020-03-12 16:00:34 -07:00
7b679eecb3
Fix compilation for emcc
2020-03-11 22:09:24 +08:00
b8abf14376
Add ScriptPass::run_nocheck and use for abc9
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Signed-off-by: David Shah <dave@ds0.me>
2020-03-09 14:34:22 +00:00
b597f85b13
Merge pull request #1718 from boqwxp/precise_locations
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Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-03-03 08:38:32 -08:00
0f4c1906bb
Small fixes
2020-02-27 10:29:53 -08:00
78929e8c3d
Fixes for older compilers
2020-02-27 10:17:29 -08:00
6bb3d9f9c0
Make TimingInfo::TimingInfo(SigBit) constructor explicit
2020-02-27 10:17:29 -08:00
9dcf204dec
TimingInfo: index by (port_name,offset)
2020-02-27 10:17:29 -08:00
7c3b4b80ea
Fix spacing
2020-02-27 10:17:29 -08:00
1ef1ca812b
Get rid of (* abc9_{arrival,required} *) entirely
2020-02-27 10:17:29 -08:00
a6fec9fe60
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
3ea5506f81
abc9_ops: use TimingInfo for -prep_{lut,box} too
2020-02-27 10:17:29 -08:00
cda4acb544
abc9_ops: add and use new TimingInfo struct
2020-02-27 10:17:29 -08:00
036c46de1e
Merge pull request #1705 from YosysHQ/logger_pass
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Logger pass
2020-02-26 13:32:49 +01:00
1c569fe06a
Remove duplicate warning detection
2020-02-23 10:56:27 +01:00
f0afd65035
Closes #1717 . Add more precise Verilog source location information to AST and RTLIL nodes.
2020-02-23 07:22:26 +00:00
d079ab9d19
Handle expect no warnings together with expected
2020-02-22 10:52:46 +01:00
70db8e9200
Prevent double error message
2020-02-17 16:46:34 +01:00
5641b0248f
Option to expect no warnings
2020-02-17 15:36:06 +01:00
be977cf7eb
No new error if already failing
2020-02-17 12:54:36 +01:00
6b396e6455
remove whitespace
2020-02-14 13:12:05 +01:00
31b7a9c312
Add expect option to logger command
2020-02-14 12:21:16 +01:00
b523ecf2f4
specify: system timing checks to accept min:typ:max triple
2020-02-13 12:42:15 -08:00
5f53ea2b5b
Merge pull request #1659 from YosysHQ/clifford/experimental
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Add log_experimental() and experimental() API and "yosys -x"
2020-01-29 15:25:03 +01:00
6d27d43727
Add and use SigSpec::reverse()
2020-01-28 10:37:16 -08:00
5c2508cef8
Improve logging use of experimental features
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-28 17:51:50 +01:00
cef607c8b7
Add log_experimental() and experimental() API and "yosys -x"
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Signed-off-by: Claire Wolf <clifford@clifford.at>
2020-01-27 18:27:47 +01:00
de6006fbc8
Merge pull request #1613 from porglezomp-misc/version-flag-alias
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Add --version and -version as aliases for -V
2020-01-27 12:59:27 +01:00
ade57058f7
As before, only display MEM if Linux or FreeBSD
2020-01-14 11:38:48 -08:00
a901a5fb44
print_stats footer to return peak memory, option for including children
2020-01-14 11:25:23 -08:00
67c9c41f7e
Move abc9.* constpad entries to Abc9Pass::on_register()
2020-01-09 17:10:54 -08:00
dd718838bb
Merge remote-tracking branch 'origin/clifford/onpassreg' into eddie/abc9_scratchpad
2020-01-09 17:06:13 -08:00
cd92a974f4
Add Pass::on_register() and Pass::on_shutdown()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-09 21:36:34 +01:00
fbd9636e08
Add abc9.if.script.flow{,2} to constpad
2020-01-08 12:15:01 -08:00
a63e2508fc
Add RTLIL::constpad, init by yosys_setup(); use for abc9
2020-01-08 10:52:08 -08:00
b76b023584
Add --version and -version as aliases for -V
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The flag --version is commonly accepted by command line tools.
The code for the version flags added here matches the pattern used for
the help flag aliases, for consistency.
Fixes #1612
2020-01-05 03:19:02 -05:00
3edb2e708b
Always create $shl, $shr, $sshl, $sshr cells with unsigned B inputs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2020-01-02 18:58:45 +01:00
e97e33d00d
kernel: require \B_SIGNED=0 on $shl, $sshl, $shr, $sshr.
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Before this commit, these cells would accept any \B_SIGNED and in
case of \B_SIGNED=1, would still treat the \B input as unsigned.
Also fix the Verilog frontend to never emit such constructs.
2019-12-04 11:59:36 +00:00
6bf7114bbd
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
2019-10-04 16:45:36 -07:00
279fd22ddf
Add Const::{begin,end,empty}()
2019-10-04 15:00:57 -07:00
62c66406ad
log_dump() to support State enum
2019-10-02 17:49:07 -07:00
d963e8c2c6
Fix typo
2019-09-30 15:18:40 -07:00
0d27ffd4e6
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
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Open aig frontend as binary file
2019-09-30 17:49:23 +02:00
d5f0794a53
Merge pull request #1414 from hzeller/improve-replace-with-empty-map
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Avoid work in replace() if rules empty.
2019-09-29 19:35:23 -07:00
3f70c1fd26
Open aig frontend as binary file
2019-09-29 13:22:11 +02:00
8c2b4f0a50
Avoid work in replace() if rules empty.
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This speeds up processing when number of bits are large but there
is actually nothing to replace. Adresses part of #1382 .
Signed-off-by: Henner Zeller <h.zeller@acm.org>
2019-09-29 00:17:40 -07:00
d0493925ec
Support binary files for backends, fixes #1407
2019-09-28 09:36:18 +02:00
435300f930
Make read/write gzip files on macos works, fixes #1357
2019-09-26 19:35:12 +02:00
9a84e4711c
Spacing
2019-09-13 16:30:44 -07:00
5473e597bf
Use template specialisation
2019-09-13 11:13:57 -07:00
95e80809a5
Revert "SigSet<Cell*> to use stable compare class"
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This reverts commit 4ea34aaacd
2019-09-13 09:49:15 -07:00
c487a8ff25
Grammar
2019-09-12 12:00:34 -07:00
c05a403dd1
static_assert to enforce this going forward
2019-09-12 11:45:17 -07:00
4ea34aaacd
SigSet<Cell*> to use stable compare class
2019-09-12 11:45:02 -07:00
e9f3eb9760
Bump year in copyright notice
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-22 18:43:16 +02:00
2a78a1fd00
Merge pull request #1283 from YosysHQ/clifford/fix1255
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Fix various NDEBUG compiler warnings
2019-08-17 15:07:16 +02:00
3b19c3657c
Move namespace alias
2019-08-16 19:37:11 +00:00
0b9ee4fbbf
Try this for gcc-4.8?
2019-08-15 16:20:54 -07:00
453a9429b6
Fix spacing
2019-08-15 14:54:41 -07:00
52355f5185
Use more ID::{A,B,Y,blackbox,whitebox}
2019-08-15 14:50:10 -07:00
49301b733e
Merge branch 'master' into clifford/fix1255
2019-08-15 22:44:38 +02:00
4cfefae21e
More use of IdString::in()
2019-08-15 09:23:57 -07:00
0c5db07cd6
Fix various NDEBUG compiler warnings, closes #1255
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-13 13:29:03 +02:00
b25cf36856
Add YOSYS_NO_IDS_REFCNT configuration macro
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 12:23:16 +02:00
390bf459fb
Use ID() in kernel/*, add simple ID:: hack (to be improved upon later)
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
8222c5735e
More improvements and cleanups in IdString subsystem
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- better use of "inline" keyword
- deprecate "sticky" IDs feature
- improve handling of empty ID
- add move constructor
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
b5534b66c8
Improve API of ID() macro
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-11 11:39:46 +02:00
f54bf1631f
Merge pull request #1258 from YosysHQ/eddie/cleanup
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Cleanup a few barnacles across codebase
2019-08-10 09:52:14 +02:00
6d77236f38
substr() -> compare()
2019-08-07 12:20:08 -07:00
71eff6f0de
RTLIL::S{0,1} -> State::S{0,1} for headers
2019-08-07 11:14:03 -07:00
7164996921
RTLIL::S{0,1} -> State::S{0,1}
2019-08-07 11:12:38 -07:00
e6d5147214
Merge remote-tracking branch 'origin/master' into eddie/cleanup
2019-08-07 11:11:50 -07:00
48d0f99406
stoi -> atoi
2019-08-07 11:09:17 -07:00
9260e97aa2
Automatically prune init attributes in verific front-end, fixes #1237
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 15:31:49 +02:00
e9a756aa7a
Merge pull request #1213 from YosysHQ/eddie/wreduce_add
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wreduce/opt_expr: improve width reduction for $add and $sub cells
2019-08-07 14:27:35 +02:00
c5d56fbe2d
Merge pull request #1253 from YosysHQ/clifford/check
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Be less aggressive with running design->check()
2019-08-07 12:14:41 +02:00
338f6765eb
Tweak default gate costs, cleanup "stat -tech cmos"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 10:25:51 +02:00
234fcf1724
Fix typos
2019-08-06 19:07:45 -07:00
c11ad24fd7
Use std::stoi instead of atoi(<str>.c_str())
2019-08-06 16:45:48 -07:00
e38f40af5b
Use IdString::begins_with()
2019-08-06 16:42:25 -07:00
3486235338
Make liberal use of IdString.in()
2019-08-06 16:18:18 -07:00
100c377451
Redesign of cell cost API
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-07 01:12:14 +02:00
84f52aee0d
Add SigSpec::extract_end() convenience function
2019-08-06 15:25:11 -07:00
0b56be8c56
Restore original SigSpec::extract()
2019-08-06 15:24:55 -07:00
26cb3e7afc
Merge remote-tracking branch 'origin/master' into eddie/wreduce_add
2019-08-06 14:50:00 -07:00
95a6582f34
Be less aggressive with running design->check()
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 19:21:37 +02:00
27360ceda6
Add support for writing gzip-compressed files
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Signed-off-by: David Shah <dave@ds0.me>
2019-08-06 17:43:04 +01:00
023086bd46
Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-08-06 04:47:55 +02:00
f767179c75
New mxe hacks needed to support 2ca237e
2019-08-01 17:28:07 +02:00
3e4307c104
Fix case when file does not exist
2019-07-29 12:29:13 +02:00
6538671c84
Merge pull request #1226 from YosysHQ/dave/gzip
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Add support for gzip'd input files
2019-07-27 07:40:38 +01:00
da6701c4cd
Fix frontend auto-detection for gzipped input
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:29:05 +01:00
933db0410e
Add support for reading gzip'd input files
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Signed-off-by: David Shah <dave@ds0.me>
2019-07-26 10:23:58 +01:00
70882a8070
replaced std::iterator with using statements
2019-07-25 09:51:09 +02:00
25685a9a5b
made ObjectIterator extend std::iterator
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this makes it possible to use std algorithms on them
2019-07-24 16:35:40 +02:00
54708dfbd7
Add an SigSpec::at(offset, defval) convenience method
2019-07-19 13:54:57 -07:00
25ff27e37f
SigSpec::extract to take negative lengths
2019-07-19 12:34:04 -07:00
06f94c92d4
Revert "Add log_checkpoint function and use it in opt_muxtree"
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This reverts commit 0e6c83027f
2019-07-15 08:35:48 -07:00
44fd459c79
Redesign log_id_cache so that it doesn't keep IdString instances referenced, fixes #1178
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-15 17:10:42 +02:00
0e6c83027f
Add log_checkpoint function and use it in opt_muxtree
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-07-15 12:12:21 +02:00
ef07a313b4
Merge pull request #1162 from whitequark/rtlil-case-attrs
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Allow attributes on individual switch cases in RTLIL
2019-07-09 16:56:29 +02:00
41d7d9d24b
Clarify script -scriptwire doc
2019-07-08 19:21:21 -07:00
93bc5affd3
Allow attributes on individual switch cases in RTLIL.
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The parser changes are slightly awkward. Consider the following IL:
process $0
<point 1>
switch \foo
<point 2>
case 1'1
assign \bar \baz
<point 3>
...
case
end
end
Before this commit, attributes are valid in <point 1>, and <point 3>
iff it is immediately followed by a `switch`. (They are essentially
attached to the switch.) But, after this commit, and because switch
cases do not have an ending delimiter, <point 3> becomes ambiguous:
the attribute could attach to either the following `case`, or to
the following `switch`. This isn't expressible in LALR(1) and results
in a reduce/reduce conflict.
To address this, attributes inside processes are now valid anywhere
inside the process: in <point 1> and <point 3> a part of case body,
and in <point 2> as a separate rule. As a consequence, attributes
can now precede `assign`s, which is made illegal in the same way it
is illegal to attach attributes to `connect`.
Attributes are tracked separately from the parser state, so this
does not affect collection of attributes at all, other than allowing
them on `case`s. The grammar change serves purely to allow attributes
in more syntactic places.
2019-07-08 11:34:58 +00:00
f1504696e5
Use Pass::call_on_module() as per @cliffordwolf comments
2019-07-02 08:20:37 -07:00
02ba85b133
script -select -> script -scriptwire
2019-07-02 08:17:26 -07:00
06971385fa
Support ability for "script -select" to take commands from wires
2019-06-28 13:36:33 -07:00
da5f830395
Merge pull request #1098 from YosysHQ/xaig
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"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
2019-06-28 10:59:03 -07:00
fb30fcb7c5
Undo iterator based Module::remove() for cells, as containers will not
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invalidate
2019-06-27 15:03:21 -07:00
0f32cb4e0a
Merge remote-tracking branch 'upstream/master'
2019-06-27 12:11:47 +02:00
1abe93e48d
Merge remote-tracking branch 'origin/master' into xaig
2019-06-21 17:43:29 -07:00
e612dade12
Merge remote-tracking branch 'origin/master' into xaig
2019-06-20 19:00:36 -07:00
8767ec3fbd
Add a few more filename rewrites
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This now allows a full pipeline to work, something such as:
yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v"
Otherwise, you will get something along the lines of:
ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-20 10:27:59 -07:00
73bd1d59a7
Merge branch 'master' of https://github.com/bogdanvuk/yosys into clifford/ext1046
2019-06-20 13:04:04 +02:00
b3441935b1
Merge pull request #1100 from bwidawsk/home
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Support ~ in filename parsing
2019-06-19 10:52:59 +02:00
df6576edc8
In RTLIL::Module::check(), check process invariants.
2019-06-19 05:22:13 +00:00
468c41d997
Support ~ for home directory
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This is tested on Linux only
v2:
Wrap functioanlity in ifndef _WIN32 (eddiehung)
Find '~/' instead of '~' (cliffordwolf)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-06-18 14:38:40 -07:00
b45d06d7a3
Fix leak removing cells during ABC integration; also preserve attr
2019-06-17 12:54:24 -07:00
a48b5bfaa5
Further cleanup based on @daveshah1
2019-06-14 12:25:06 -07:00
8451cbea89
Move netlist helper module to passes/opt for the time being
2019-06-14 12:14:02 +02:00
fe651922cb
Merge remote-tracking branch 'upstream/master'
2019-06-14 12:06:57 +02:00
53695e6729
Prepare for situation when port of the signal cannot be found
2019-06-14 11:39:24 +02:00
d09d4e0706
Move ConstEvalAig to aigerparse.cc
2019-06-13 16:28:11 -07:00
63e2f83632
More slimming
2019-06-13 13:29:03 -07:00
d39a5a77a9
Add ConstEvalAig specialised for AIGs
2019-06-13 13:13:48 -07:00
8665f48879
Implement disconnection of constant register bits
2019-06-13 19:35:37 +02:00
4912567cbf
Pass SigBit by value to Netlist algorithms
2019-06-13 15:42:45 +02:00
d69989b8d2
Rename satgen_algo.h -> algo.h, code cleanup and refactoring
2019-06-12 19:35:05 +02:00
f7a9769c14
Merge remote-tracking branch 'origin/master' into xaig
2019-06-12 08:50:39 -07:00
9892df17ef
Generate satgen instance instead of calling sat pass
2019-06-11 11:47:13 +02:00
d097f423d1
Refactor driver map generation
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- Implement iterators over the driver map that enumerate signals and cells
within the cones of the signal
2019-06-10 21:42:35 +02:00
211d85cfcc
Fixes and cleanups in AST_TECALL handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-06-07 12:41:09 +02:00
a3bbc5365b
Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into clifford/pr983
2019-06-07 12:08:42 +02:00
ba2185ead8
Refactor hierarchy wand/wor handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-28 16:43:25 +02:00
0971f772d7
Fix handling of warning and error messages within log_make_debug-blocks
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-22 13:46:38 +02:00
287de4b848
Add rewrite_sigspecs2, Improve remove() wires
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-15 16:01:00 +02:00
3870e7cf29
Merge pull request #991 from kristofferkoch/gcc9-warnings
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Fix all warnings that occurred when compiling with gcc9
2019-05-08 11:25:22 +02:00
30c762d3a1
Fix all warnings that occurred when compiling with gcc9
2019-05-08 10:27:14 +02:00
c582a25bdb
Merge pull request #998 from mdaiter/get_bool_attribute_opts
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Minor optimization to get_attribute_bool
2019-05-08 08:34:35 +02:00
6e629d2895
Minor optimization to get_attribute_bool
2019-05-07 22:04:28 -05:00
bafbb9ee90
Optimize ceil_log2 function
2019-05-07 12:17:56 -05:00
87426f5a06
Improve write_verilog specify support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:46:24 +02:00
d9c4644e88
Merge remote-tracking branch 'origin/master' into clifford/specify
2019-05-03 15:05:57 -07:00
ac10e7d96d
Initial implementation of elaboration system tasks
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(IEEE1800-2017 section 20.11)
This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block.
This is very useful to stop a synthesis of a parametrized block when an
illegal combination of parameters is chosen.
2019-05-03 03:10:43 +03:00
9268cd1613
Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:19:10 +02:00
4f15e7f00f
fix codestyle formatting
2019-04-29 19:20:33 +09:00
e531fb203a
escape spaces with backslash when writing dep file
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filenames are sparated by spaces in the dep file. if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.
2019-04-29 16:13:34 +09:00
64925b4e8f
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:57:10 +02:00
4575e4ad86
Improve $specrule interface
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 22:18:04 +02:00
71c38d9de5
Add $specrule cells for $setup/$hold/$skew specify rules
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
e807e88b60
Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
aec2475a9d
Add CellTypes support for $specify2 and $specify3
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
e1d73e03d3
Add InternalCellChecker support for $specify2 and $specify3
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
3cc95fb4be
Add specify parser
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 21:36:59 +02:00
742c2f245d
Fixes for OAI4 cell implementation
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Fixes #955 and the underlying issue in #954
Signed-off-by: David Shah <dave@ds0.me>
2019-04-23 17:54:00 +01:00
2c6358ea25
Remove kernel/cost.cc since master has refactored it
2019-04-22 11:21:17 -07:00
4883391b63
Merge remote-tracking branch 'origin/master' into xaig
2019-04-22 11:19:52 -07:00
e158ea2097
Add log_debug() framework
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-22 17:25:52 +02:00
99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings
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Feature/python bindings
2019-04-22 14:47:52 +02:00
caec7f9d2c
Merge remote-tracking branch 'origin/master' into xaig
2019-04-20 12:23:49 -07:00
5b915f0153
Add "wbflip" command
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 11:04:46 +02:00
290a798cec
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:32:00 -07:00
c997a77014
Ignore 'whitebox' attr in flatten with "-wb" option
2019-04-18 10:19:45 -07:00
8fe0a961b3
Merge remote-tracking branch 'origin/clifford/whitebox' into xaig
2019-04-18 09:00:06 -07:00
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
bca3cf6843
Merge branch 'master' into xaig
2019-04-08 16:31:59 -07:00
dfb242c905
Add "read_ilang -lib"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-05 17:31:49 +02:00
827a96d3a3
Global lists in rtlil.cc are now static objects
2019-04-03 14:27:39 +02:00
0774a500d4
Added support for changing Yosys namespace
2019-04-03 12:21:21 +02:00
072c939380
Fixed identation
2019-04-01 13:36:01 +02:00
03d1606b42
Merge remote-tracking branch 'origin/master' into feature/python_bindings
2019-03-28 12:16:39 +01:00
3b796c033c
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-23 14:38:48 +01:00
370db33a4c
Add fmcombine pass
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-15 20:46:17 +01:00
76c9c350e7
Add hashlib "<container>::element(int n)" methods
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-14 22:04:42 +01:00
1cd04a6838
Fix a bug in handling quotes in multi-cmd lines in Yosys scripts
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-12 21:15:11 +01:00
20c6a8c9b0
Improve determinism of IdString DB for similar scripts
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-11 20:12:28 +01:00
Marcelina Kościelnicka
Zachary Snow
N. Engelhardt
Miodrag Milanović
Xiretza
Michael Singer
gatecat
Lofty
Noah Moroze
Robert Baruch
umarcor
whitequark
nitz
N. Engelhardt
clairexen
Alberto Gonzalez
Anonymous Maarten
Rupert Swarbrick
Martin
Eddie Hung
Peter Crozier
Claire Wolf
Vamsi K Vytla
Rupert Swarbrick
Waldir Pimenta
jiegec
David Shah
Cassie Jones
Henner Zeller
Jakob Wenzel
Bogdan Vukobratovic
Ben Widawsky
Kristoffer Ellersgaard Koch
Matthew Daiter
Udi Finkelstein
Oleg Endo
Benedikt Tutzer
Benedikt Tutzer