timinginfo: Error instead of segfault on const signals.

Reported by @Ravenslofty
This commit is contained in:
Marcelina Kościelnicka 2020-12-14 18:14:42 +01:00
parent 5a881497e1
commit de99197738
1 changed files with 2 additions and 2 deletions

View File

@ -88,10 +88,10 @@ struct TimingInfo
auto src = cell->getPort(ID::SRC);
auto dst = cell->getPort(ID::DST);
for (const auto &c : src.chunks())
if (!c.wire->port_input)
if (!c.wire || !c.wire->port_input)
log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
for (const auto &c : dst.chunks())
if (!c.wire->port_output)
if (!c.wire || !c.wire->port_output)
log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();