mirror of https://github.com/YosysHQ/yosys.git
timinginfo: Error instead of segfault on const signals.
Reported by @Ravenslofty
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parent
5a881497e1
commit
de99197738
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@ -88,10 +88,10 @@ struct TimingInfo
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auto src = cell->getPort(ID::SRC);
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auto dst = cell->getPort(ID::DST);
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for (const auto &c : src.chunks())
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if (!c.wire->port_input)
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if (!c.wire || !c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where SRC '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(src));
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for (const auto &c : dst.chunks())
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if (!c.wire->port_output)
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if (!c.wire || !c.wire->port_output)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module output.\n", log_id(module), log_id(cell), log_signal(dst));
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int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
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int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
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