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Adds is_wire to SigBit and SigChunk 

Useful for PYOSYS because Python can't easily check wire against NULL.
This commit is contained in:
Robert Baruch 2021-02-20 11:46:30 -08:00 committed by Marcelina Kościelnicka
parent ae07298a6b
commit 7c50b89b24
1 changed files with 3 additions and 0 deletions
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3
kernel/rtlil.h
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@ -735,6 +735,7 @@ struct RTLIL::SigChunk
RTLIL::SigChunk extract(int offset, int length) const;
inline int size() const { return width; }
inline int is_wire() const { return wire != NULL; }
bool operator <(const RTLIL::SigChunk &other) const;
bool operator ==(const RTLIL::SigChunk &other) const;
@ -760,6 +761,8 @@ struct RTLIL::SigBit
SigBit(const RTLIL::SigBit &sigbit) = default;
RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default;
inline int is_wire() const { return wire != NULL; }
bool operator <(const RTLIL::SigBit &other) const;
bool operator ==(const RTLIL::SigBit &other) const;
bool operator !=(const RTLIL::SigBit &other) const;