From 7c50b89b244ed23d42f95c3d08efde40ec7ddd82 Mon Sep 17 00:00:00 2001 From: Robert Baruch Date: Sat, 20 Feb 2021 11:46:30 -0800 Subject: [PATCH] Adds is_wire to SigBit and SigChunk Useful for PYOSYS because Python can't easily check wire against NULL. --- kernel/rtlil.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 4dad3c428..a5f170085 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -735,6 +735,7 @@ struct RTLIL::SigChunk RTLIL::SigChunk extract(int offset, int length) const; inline int size() const { return width; } + inline int is_wire() const { return wire != NULL; } bool operator <(const RTLIL::SigChunk &other) const; bool operator ==(const RTLIL::SigChunk &other) const; @@ -760,6 +761,8 @@ struct RTLIL::SigBit SigBit(const RTLIL::SigBit &sigbit) = default; RTLIL::SigBit &operator =(const RTLIL::SigBit &other) = default; + inline int is_wire() const { return wire != NULL; } + bool operator <(const RTLIL::SigBit &other) const; bool operator ==(const RTLIL::SigBit &other) const; bool operator !=(const RTLIL::SigBit &other) const;