mirror of https://github.com/YosysHQ/yosys.git
kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
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4cec21b93e
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@ -128,11 +128,9 @@ struct TimingInfo
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int rise_max = cell->getParam(ID::T_RISE_MAX).as_int();
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int fall_max = cell->getParam(ID::T_FALL_MAX).as_int();
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int max = std::max(rise_max,fall_max);
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if (max < 0)
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log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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if (max <= 0) {
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log_debug("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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continue;
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if (max < 0) {
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log_warning("Module '%s' contains specify cell '%s' with T_{RISE,FALL}_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
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max = 0;
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}
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for (const auto &d : dst) {
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auto &v = t.arrival[NameBit(d)];
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@ -152,11 +150,9 @@ struct TimingInfo
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if (!c.wire->port_input)
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log_error("Module '%s' contains specify cell '%s' where DST '%s' is not a module input.\n", log_id(module), log_id(cell), log_signal(dst));
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int max = cell->getParam(ID::T_LIMIT_MAX).as_int();
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if (max < 0)
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log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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if (max <= 0) {
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log_debug("Module '%s' contains specify cell '%s' with T_LIMIT_MAX <= 0 which is currently unsupported. Ignoring.\n", log_id(module), log_id(cell));
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continue;
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if (max < 0) {
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log_warning("Module '%s' contains specify cell '%s' with T_LIMIT_MAX < 0 which is currently unsupported. Clamping to 0.\n", log_id(module), log_id(cell));
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max = 0;
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}
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for (const auto &s : src) {
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auto &v = t.required[NameBit(s)];
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