mirror of https://github.com/YosysHQ/yosys.git
ffinit: Fortify the code a bit.
This fixes handling of messy cases involving repeatedly setting and removing the same init bit.
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@ -83,22 +83,24 @@ struct FfInitVals
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void set_init(RTLIL::SigBit bit, RTLIL::State val)
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{
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bit = (*sigmap)(bit);
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auto it = initbits.find(bit);
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if (it != initbits.end()) {
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auto it2 = it->second.second.wire->attributes.find(ID::init);
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it2->second[it->second.second.offset] = val;
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} else {
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log_assert(bit.wire);
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initbits[bit] = std::make_pair(val,bit);
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auto it2 = bit.wire->attributes.find(ID::init);
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if (it2 != bit.wire->attributes.end()) {
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it2->second[bit.offset] = val;
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} else {
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Const cval(State::Sx, GetSize(bit.wire));
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cval[bit.offset] = val;
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bit.wire->attributes[ID::init] = cval;
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}
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SigBit mbit = (*sigmap)(bit);
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SigBit abit = bit;
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auto it = initbits.find(mbit);
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if (it != initbits.end())
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abit = it->second.second;
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else if (val == State::Sx)
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return;
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log_assert(abit.wire);
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initbits[mbit] = std::make_pair(val,abit);
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auto it2 = abit.wire->attributes.find(ID::init);
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if (it2 != abit.wire->attributes.end()) {
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it2->second[abit.offset] = val;
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if (it2->second.is_fully_undef())
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abit.wire->attributes.erase(it2);
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} else if (val != State::Sx) {
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Const cval(State::Sx, GetSize(abit.wire));
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cval[abit.offset] = val;
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abit.wire->attributes[ID::init] = cval;
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}
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}
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@ -111,14 +113,7 @@ struct FfInitVals
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void remove_init(RTLIL::SigBit bit)
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{
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auto it = initbits.find((*sigmap)(bit));
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if (it != initbits.end()) {
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auto it2 = it->second.second.wire->attributes.find(ID::init);
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it2->second[it->second.second.offset] = State::Sx;
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if (it2->second.is_fully_undef())
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it->second.second.wire->attributes.erase(it2);
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initbits.erase(it);
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}
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set_init(bit, State::Sx);
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}
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void remove_init(const RTLIL::SigSpec &sig)
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