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ql_ap3_arch_eval

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1.0.0

Mono Color

• 8d5036f108 commented/corrected failing benchmarks Tarachand Pagarani 2020-12-17 05:46:30 -0800
• a4461bd152 Merge branch 'ql_ap3_arch_eval' of https://github.com/lnis-uofu/SOFA into ql_ap3_arch_eval Merging changes. Lalit Sharma 2020-12-17 03:05:37 -0800
• c84c04c4b8 Increasing IO capacity to 32 Lalit Sharma 2020-12-17 03:04:50 -0800
• c264ee0ddd add more benchmark tests Tarachand Pagarani 2020-12-17 02:17:20 -0800
• cfdaedcdd0 added script with random key generation example Tarachand Pagarani 2020-12-17 01:42:19 -0800
• b556cf452c add tasks for 32x32 configuration Tarachand Pagarani 2020-12-17 01:40:19 -0800
• 8502502b43 add 32x32 layout Tarachand Pagarani 2020-12-17 01:28:35 -0800
• 9c2764723f [HDL] Update caravel include netlist to use simulation without power pins tangxifan 2020-12-16 20:26:53 -0700
• 2d8b4b59db [Testbench] Add ccff_test for caravel tangxifan 2020-12-16 20:25:21 -0700
• 9a23f0b15e [Testbench] Bug fix tangxifan 2020-12-16 18:56:11 -0700
• c0e521ed85 [HDL] Update caravel integration netlist with mpw-b tagged version tangxifan 2020-12-16 16:41:18 -0700
• efe404e62b [Testbench] Remove unnecessary RTL netlist from synthesis tangxifan 2020-12-16 16:09:06 -0700
• df61359bb1
  Merge pull request #73 from lnis-uofu/ganesh_dev tangxifan 2020-12-16 15:47:46 -0700
• 5ffdce9ce0 [Testbench] Caravel SCFF testbench is working but see problems in verification tangxifan 2020-12-16 15:22:22 -0700
• d7f36a1f70 [SOFA-CHD] Updated SOFA-CHD - Updated cells - DRC Clean Ganesh Gore 2020-12-16 15:00:15 -0700
• f5d78fc0fa [Testbench] Start building caravel testbench tangxifan 2020-12-16 14:53:52 -0700
• e24d643cbd [Testbench] Move Caravel testbenches to a path that can be scripted to run tangxifan 2020-12-16 13:40:20 -0700
• 3897c18ebe [HDL] Bug fix in VSS port naming tangxifan 2020-12-16 13:40:09 -0700
• 3b56703c35 [HDL] Add VDD/VSS connects to wrapper netlists tangxifan 2020-12-16 11:44:40 -0700
• b5fa0733a2 [Testbench] Start build caravel scff test tangxifan 2020-12-16 11:43:02 -0700
• 682d15875b [HDL] Add user project wrapper for post-PnRed FPGA netlists so that we can plug in for Caravel RTL simulation tangxifan 2020-12-16 11:12:28 -0700
• 60850586d4 add testcases for ap3 arch evaluation Tarachand Pagarani 2020-12-16 07:05:53 -0800
• e8effb9357 [Ci] Skipped DRC, only merge online Ganesh Gore 2020-12-15 22:57:45 -0700
• edff7f3da0 [HDL] Patch the include netlist with missing HDL netlists from Caravel RTL tangxifan 2020-12-15 17:58:17 -0700
• d663d240cb [HDL] Add include netlist for Caravel RTL netlists tangxifan 2020-12-15 16:14:01 -0700
• 80d79a6eb1 [Testbench] Add testbenches for RTL and Gate-level netlists of Caravel tangxifan 2020-12-15 16:13:34 -0700
• 255b29b59d
  Merge pull request #72 from lnis-uofu/ganesh_dev tangxifan 2020-12-15 14:25:36 -0700
• d286166d57 [CI] Added submodule fetch Ganesh Gore 2020-12-15 13:48:49 -0700
• 29deb0feea [CI] Updated CI dependency file Ganesh Gore 2020-12-15 10:11:53 -0700
• 7150cc694b [QLSOFA_HD] Minor updates + Added labels for LVS Fix Ganesh Gore 2020-12-15 09:17:54 -0700
• 84ab1ac17f [SOFA_HD] Minor updates + Added labels for LVS Fix + One metal shape correction Ganesh Gore 2020-12-15 08:46:51 -0700
• e1b16ac7eb
  Merge pull request #71 from lnis-uofu/xt_dev tangxifan 2020-12-14 22:17:26 -0700
• 501c2799ed [Testbench] Rename testbench to be consistent with post-PnR netlist path change tangxifan 2020-12-14 20:27:22 -0700
• e200190568 [Actions] Still segfaults removing actions Ganesh Gore 2020-12-14 16:30:51 -0700
• acc577458d [Actions] Trying self-hosted runners Ganesh Gore 2020-12-14 16:27:20 -0700
• b5d99cae4b [Actions] Still memory error removing action Ganesh Gore 2020-12-14 16:01:49 -0700
• fc11e98efd [Actions] Testing docker run with memory option Ganesh Gore 2020-12-14 15:31:49 -0700
• 3f8a9ee1fe [Sync] Updated sync file list Ganesh Gore 2020-12-14 15:29:41 -0700
• f9868a77b1
  Merge pull request #69 from lnis-uofu/xt_dev tangxifan 2020-12-14 15:16:49 -0700
• 2a9ddcd9a2
  Merge pull request #70 from lnis-uofu/ganesh_dev tangxifan 2020-12-14 15:16:03 -0700
• 06e220d7e4 Merge remote-tracking branch 'origin/master' into ganesh_dev Ganesh Gore 2020-12-14 14:14:22 -0700
• e15f319103 [QLSOFA_HD] Updated QLSOFA_HD module files Ganesh Gore 2020-12-14 13:38:27 -0700
• 809b070ce2 [QLSOFA_HD] Updated QLSOFA_HD Verification results Ganesh Gore 2020-12-14 13:38:08 -0700
• ffa44ff099 [QLSOFA_HD] Updated QLSOFA_HD postPnr Netlist + Caravel DRC clean Ganesh Gore 2020-12-14 13:37:41 -0700
• 4c9a3de34a [QLSOFA_HD] Updated QLSOFA_HD netlist and task Ganesh Gore 2020-12-14 13:36:52 -0700
• e78b234e00 [Testbench] Bug fix for wrapper testbench include netlist tangxifan 2020-12-14 13:30:01 -0700
• 68c1e17a96 [Testbench] Add more testbenches for CHD post-pnr verification tangxifan 2020-12-14 13:26:04 -0700
• 7c0dc4c871 [Testbench] Restore post-Pnr testbenches for CHD version tangxifan 2020-12-14 13:17:37 -0700
• 62924d5464 [Git] Bug fix in lfs file tracking tangxifan 2020-12-14 13:11:20 -0700
• 3c174619b0 [Action] Updated action script for local run Ganesh Gore 2020-12-14 12:08:16 -0700
• 230b945e2d
  Merge pull request #68 from lnis-uofu/xt_dev tangxifan 2020-12-14 11:26:13 -0700
• d6dc543870
  Merge pull request #67 from lnis-uofu/ganesh_dev tangxifan 2020-12-14 11:10:04 -0700
• 61ab543e2a [Doc] Update sphinx bibtex version requirement to avoid imcompatible versions tangxifan 2020-12-14 10:57:59 -0700
• 13fc082cb3 [SOFA_HD] Updated verification script Ganesh Gore 2020-12-14 01:16:30 -0700
• 5c12369380 [SOFA_HD] Updated netlist + Caravel precheck passed Ganesh Gore 2020-12-14 01:16:00 -0700
• 967905e046 [SOFA_HD] Updated netlist and task Ganesh Gore 2020-12-14 01:14:14 -0700
• fa87753d62 [Cleanup] Renamed projects to SOFA-HD and QLSOFA-HD Ganesh Gore 2020-12-14 00:45:11 -0700
• 9f9897c5e2 [SOFA-CHD] Updated design with mux-primitive bug fixed - Calibre DRC pending Ganesh Gore 2020-12-14 00:34:42 -0700
• 0672f01e3a [Cleanup] Removed unused SDCs Ganesh Gore 2020-12-14 00:31:03 -0700
• 8def618a52
  Merge pull request #66 from lnis-uofu/xt_dev tangxifan 2020-12-11 18:08:18 -0700
• b38a948a56 [Doc] Add testing waveform example to documentation tangxifan 2020-12-11 17:24:28 -0700
• 63bc60ccdd [Git] Relax the LFS application to get rid of small files tangxifan 2020-12-11 16:25:23 -0700
• 1e490c1714 [HDL] Add digital I/O self testing testbench tangxifan 2020-12-11 16:11:12 -0700
• 52d98eb7ca [HDL] Revert I/O cell back to the current design in GDS tangxifan 2020-12-11 11:26:46 -0700
• 88f522026a [Doc] Update I/O schematic to be consistent with HDL netlist tangxifan 2020-12-11 11:25:28 -0700
• 9dc1b6efa7 [Doc] Fine tune documentation on I/O design tangxifan 2020-12-11 11:25:07 -0700
• c1cdca61b5 [HDL] Critical Patch on the digital I/O cell which now outputs 'Z' when input mode is selected tangxifan 2020-12-11 10:59:28 -0700
• 00b1740b44
  Merge pull request #65 from lnis-uofu/xt_dev tangxifan 2020-12-11 10:12:53 -0700
• 9c80a1b1a7 [HDL] Bug fix in the custom cell code generator tangxifan 2020-12-10 15:45:20 -0700
• 3ccb0e2931
  Merge pull request #64 from lnis-uofu/xt_dev tangxifan 2020-12-09 20:55:06 -0700
• b1a606443f [Doc] Add motiviation figure and reworked introduction part tangxifan 2020-12-09 20:12:09 -0700
• abd51929f9 [Doc] Add MUX design information to documentation tangxifan 2020-12-09 17:51:15 -0700
• 9f82ac7636 [Doc] Add SOFA CHD to documentation. Clean up redundant document between HD FPGA IPs tangxifan 2020-12-09 16:18:04 -0700
• d9e965cf3b [Testbench] Add post-PnR testbenches for SOFA-CHD tangxifan 2020-12-09 14:55:27 -0700
• 5a567644db
  Merge pull request #63 from lnis-uofu/xt_dev tangxifan 2020-12-09 14:05:20 -0700
• e7fd8e7d92 [Arch] Fine-tune architecture file to be consistent in port naming as post-PnR netlist tangxifan 2020-12-09 12:12:40 -0700
• 73622b1df5 [TESTBENCH] Add more cells that are used by post-PNR CHD FPGA tangxifan 2020-12-09 12:12:14 -0700
• 0c761ebc05
  Merge pull request #61 from lnis-uofu/ganesh_dev tangxifan 2020-12-09 10:41:29 -0700
• 0180a5146f
  Merge pull request #62 from lnis-uofu/xt_dev tangxifan 2020-12-09 09:53:45 -0700
• d9b945ab6f [Actions] Temporarily disable deployment + Magic DRC check fails on CI machine + Not enough RAM + Will perform test locally and upload Ganesh Gore 2020-12-09 01:04:26 -0700
• 77bb6d4eae [SOFA_CHD] Added Verification results Ganesh Gore 2020-12-09 00:55:27 -0700
• 45ff6d2dfe [SOFA_CHD] Added post-pnr netlist, Verified CCFF/SCFF Ganesh Gore 2020-12-09 00:54:03 -0700
• 1a2e6de718 [SOFA_CHD] Removed large testbench file Ganesh Gore 2020-12-09 00:51:30 -0700
• 9284bbf8fa [SOFA_CHD] Added OpenFPGA taks and verilog netlist Ganesh Gore 2020-12-09 00:49:00 -0700
• def270a94b [Actions] Launched checker in correct directory Ganesh Gore 2020-12-08 21:50:18 -0700
• 3c9017b2f8 [CI] Bug fix tangxifan 2020-12-08 16:41:22 -0700
• 80937ca769 [CI] Update dependency to sync with OpenFPGA tangxifan 2020-12-08 16:36:02 -0700
• ed92cba451 [HDL] Add netlist for simulation with Caravel + FPGA tangxifan 2020-12-08 15:35:38 -0700
• 3ecd96596f [Actions] Merged Caravel with Klayout Ganesh Gore 2020-12-08 13:32:26 -0700
• 06ea86c0b0
  Merge pull request #60 from lnis-uofu/xt_dev Laboratory for Nano Integrated Systems (LNIS) 2020-12-08 13:30:40 -0700
• 44a68c888d remove dedicated VCC/GND tiles and pb_type tpagarani_dev Tarachand Pagarani 2020-12-08 11:17:31 -0800
• 2f2b301395 [Action] Updated repo destination Ganesh Gore 2020-12-08 11:31:04 -0700
• 9efe8a7935 [Actions] Added correct repository Ganesh Gore 2020-12-08 10:24:54 -0700
• 3cc54ccb59 [MSIM] Bug fix tangxifan 2020-12-08 10:15:39 -0700
• 4247819ccb Merge branch 'xt_dev' of https://github.com/LNIS-Projects/skywater-openfpga into xt_dev tangxifan 2020-12-08 10:13:33 -0700
• 55ff90905f [DC] Add scripts to automate the synthesis for local encoders tangxifan 2020-12-08 10:12:57 -0700
• 9fc40cd919 correct PDK path Tarachand Pagarani 2020-12-08 07:21:41 -0800
• 053afc7c45 correct the VPR binding for netlist generation Tarachand Pagarani 2020-12-08 07:12:13 -0800
• 3d2f792fa5
  Merge pull request #59 from lnis-uofu/xt_dev tangxifan 2020-12-07 18:53:42 -0700
• 77dfb469b5
  Update MSIM/common/run_post_pnr_msim_task.py tangxifan 2020-12-07 17:41:22 -0700