mirror of https://github.com/lnis-uofu/SOFA.git
[Testbench] Add ccff_test for caravel
This commit is contained in:
tangxifan
parent
9a23f0b15e
commit
2d8b4b59db
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@ -0,0 +1,30 @@
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FIRMWARE_PATH = ../common
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GCC_PATH?=/var/tmp/xtang/riscv32i/bin
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GCC_PREFIX?=riscv32-unknown-elf
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.SUFFIXES:
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PATTERN = ccff_test_caravel
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all: ${PATTERN:=.hex}
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hex: ${PATTERN:=.hex}
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%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
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${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -mabi=ilp32 -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
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%.hex: %.elf
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${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
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# to fix flash base address
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sed -i 's/@10000000/@00000000/g' $@
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%.bin: %.elf
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${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
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# ---- Clean ----
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clean:
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rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
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.PHONY: clean hex all
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#include "../common/defs.h"
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/*
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* Scan-chain Test:
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* - Configures directions for control ports
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* +==========+===============+===========+
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* | GPIO | Functionality | Direction |
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* +==========+===============+===========+
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* | GPIO[0] | TEST_EN | input |
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* +----------+---------------+-----------+
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* | GPIO[1] | IO_ISOL_N | input |
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* +----------+---------------+-----------+
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* | GPIO[2] | RESET | input |
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* +----------+---------------+-----------+
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* | GPIO[3] | PROG_RESET | input |
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* +----------+---------------+-----------+
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* | GPIO[11] | SC_TAIL | output |
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* +----------+---------------+-----------+
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* | GPIO[12] | CCFF_HEAD | input |
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* +----------+---------------+-----------+
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* | GPIO[25] | MODE_SWITCH) | input |
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* +----------+---------------+-----------+
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* | GPIO[26] | SC_HEAD | input |
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* +----------+---------------+-----------+
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* | GPIO[35] | CCFF_TAIL | output |
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* +----------+---------------+-----------+
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* | GPIO[36] | CLK | input |
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* +----------+---------------+-----------+
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* | GPIO[37] | PROG_CLK | input |
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* +----------+---------------+-----------+
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*
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* - Configure FPGA data I/Os to be input
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*/
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void main() {
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/*
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IO Control Registers
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| 3-bits | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit | 1-bit |
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Output: 0000_0110_0000_1110 (0x1808) = GPIO_MODE_USER_STD_OUTPUT
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| 110 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 |
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Input: 0000_0001_0000_1111 (0x0402) = GPIO_MODE_USER_STD_INPUT_NOPULL
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| DM | VTRIP | SLOW | AN_POL | AN_SEL | AN_EN | MOD_SEL | INP_DIS | HOLDH | OEB_N | MGMT_EN |
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| 001 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
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*/
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// By default all the I/Os are in input mode
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reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_2 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_3 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_4 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_6 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_7 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_8 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_9 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_10 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_12 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_13 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_14 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_15 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_16 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_17 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_18 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_19 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_20 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_21 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_22 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_23 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_24 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_25 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_26 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_27 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_28 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_29 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_30 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_31 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_32 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_33 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_34 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_36 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_37 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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// Only specify those should be in output mode
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reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_35 = GPIO_MODE_USER_STD_OUTPUT;
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/* Apply configuration */
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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}
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@ -0,0 +1,58 @@
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@00000000
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93 00 00 00 93 01 00 00 13 02 00 00 93 02 00 00
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13 03 00 00 93 03 00 00 13 04 00 00 93 04 00 00
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13 05 00 00 93 05 00 00 13 06 00 00 93 06 00 00
|
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13 07 00 00 93 07 00 00 13 08 00 00 93 08 00 00
|
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13 09 00 00 93 09 00 00 13 0A 00 00 93 0A 00 00
|
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13 0B 00 00 93 0B 00 00 13 0C 00 00 93 0C 00 00
|
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13 0D 00 00 93 0D 00 00 13 0E 00 00 93 0E 00 00
|
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13 0F 00 00 93 0F 00 00 17 05 00 00 13 05 05 31
|
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93 05 00 00 13 06 00 00 63 D8 C5 00 14 41 94 C1
|
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11 05 91 05 E3 CC C5 FE 13 05 00 00 93 05 00 00
|
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63 57 B5 00 23 20 05 00 11 05 E3 4D B5 FE 71 28
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01 A0 01 00 B7 02 00 28 13 03 00 12 23 90 62 00
|
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A3 81 02 00 05 C6 21 4F 93 73 F6 0F 93 DE 73 00
|
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23 80 D2 01 93 EE 0E 01 23 80 D2 01 86 03 93 F3
|
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F3 0F 7D 1F E3 14 0F FE 23 80 62 00 A1 C9 13 0F
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00 02 83 23 05 00 A1 4F 93 DE F3 01 23 80 D2 01
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93 EE 0E 01 23 80 D2 01 83 CE 02 00 93 FE 2E 00
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93 DE 1E 00 86 03 B3 E3 D3 01 7D 1F 63 17 0F 00
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23 20 75 00 11 05 83 23 05 00 FD 1F E3 96 0F FC
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FD 15 F1 F1 63 04 0F 00 23 20 75 00 13 03 00 08
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A3 81 62 00 82 80 01 00 00 00 41 11 22 C6 00 08
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B7 07 00 26 93 87 07 02 13 07 20 40 98 C3 B7 07
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00 26 93 87 47 02 13 07 20 40 98 C3 B7 07 00 26
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93 87 87 02 13 07 20 40 98 C3 B7 07 00 26 93 87
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C7 02 13 07 20 40 98 C3 B7 07 00 26 93 87 07 03
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13 07 20 40 98 C3 B7 07 00 26 93 87 47 03 13 07
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20 40 98 C3 B7 07 00 26 93 87 87 03 13 07 20 40
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98 C3 B7 07 00 26 93 87 C7 03 13 07 20 40 98 C3
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B7 07 00 26 93 87 07 04 13 07 20 40 98 C3 B7 07
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00 26 93 87 47 04 13 07 20 40 98 C3 B7 07 00 26
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93 87 87 04 13 07 20 40 98 C3 B7 07 00 26 93 87
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07 05 13 07 20 40 98 C3 B7 07 00 26 93 87 47 05
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13 07 20 40 98 C3 B7 07 00 26 93 87 87 05 13 07
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20 40 98 C3 B7 07 00 26 93 87 C7 05 13 07 20 40
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98 C3 B7 07 00 26 93 87 07 06 13 07 20 40 98 C3
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B7 07 00 26 93 87 47 06 13 07 20 40 98 C3 B7 07
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00 26 93 87 87 06 13 07 20 40 98 C3 B7 07 00 26
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93 87 C7 06 13 07 20 40 98 C3 B7 07 00 26 93 87
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07 07 13 07 20 40 98 C3 B7 07 00 26 93 87 47 07
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13 07 20 40 98 C3 B7 07 00 26 93 87 87 07 13 07
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20 40 98 C3 B7 07 00 26 93 87 C7 07 13 07 20 40
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98 C3 B7 07 00 26 93 87 07 08 13 07 20 40 98 C3
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B7 07 00 26 93 87 47 08 13 07 20 40 98 C3 B7 07
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00 26 93 87 87 08 13 07 20 40 98 C3 B7 07 00 26
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93 87 C7 08 13 07 20 40 98 C3 B7 07 00 26 93 87
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07 09 13 07 20 40 98 C3 B7 07 00 26 93 87 47 09
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13 07 20 40 98 C3 B7 07 00 26 93 87 87 09 13 07
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20 40 98 C3 B7 07 00 26 93 87 C7 09 13 07 20 40
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98 C3 B7 07 00 26 93 87 07 0A 13 07 20 40 98 C3
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B7 07 00 26 93 87 47 0A 13 07 20 40 98 C3 B7 07
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00 26 93 87 87 0A 13 07 20 40 98 C3 B7 07 00 26
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93 87 07 0B 13 07 20 40 98 C3 B7 07 00 26 93 87
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47 0B 13 07 20 40 98 C3 B7 07 00 26 93 87 C7 04
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09 67 13 07 87 80 98 C3 B7 07 00 26 93 87 C7 0A
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09 67 13 07 87 80 98 C3 B7 07 00 26 05 47 98 C3
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01 00 B7 07 00 26 98 43 85 47 E3 0C F7 FE 01 00
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32 44 41 01 82 80 00 00
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@ -0,0 +1,250 @@
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`timescale 1 ns / 1 ps
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`define POWER_UP_TIME_PERIOD 200
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`define SOC_SETUP_TIME_PERIOD 2000
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`define SOC_CLOCK_PERIOD 12.5
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`define FPGA_PROG_CLOCK_PERIOD 12.5
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`define FPGA_CLOCK_PERIOD 12.5
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module ccff_test_caravel;
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reg clock;
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reg RSTB;
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reg power1, power2;
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reg power3, power4;
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wire gpio;
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wire [37:0] mprj_io;
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// ----- Local wires for control ports of FPGA fabric -----
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wire [0:0] pReset;
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reg [0:0] prog_clock_reg;
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wire [0:0] prog_clk;
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wire [0:0] prog_clock;
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wire [0:0] Test_en;
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wire [0:0] Reset;
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reg [0:0] op_clock_reg;
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wire [0:0] op_clk;
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wire [0:0] op_clock;
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reg [0:0] prog_reset;
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reg [0:0] greset;
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// ---- Configuration-chain head -----
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reg [0:0] ccff_head;
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// ---- Configuration-chain tail -----
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wire [0:0] ccff_tail;
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// ---- Scan-chain head -----
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wire [0:0] sc_head;
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// ---- Scan-chain tail -----
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wire [0:0] sc_tail;
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wire [0:0] IO_ISOL_N;
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// ----- Counters for error checking -----
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integer num_prog_cycles = 0;
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integer num_errors = 0;
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integer num_checked_points = 0;
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// Indicate when SoC setup phase should be finished
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reg soc_setup_done = 0;
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// Indicate when configuration should be finished
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reg config_done = 0;
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initial
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begin
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config_done = 1'b0;
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soc_setup_done = 1'b0;
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end
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// ----- Begin raw programming clock signal generation -----
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initial
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begin
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prog_clock_reg[0] = 1'b0;
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end
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always
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begin
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#(`FPGA_PROG_CLOCK_PERIOD) prog_clock_reg[0] = ~prog_clock_reg[0];
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end
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// ----- End raw programming clock signal generation -----
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// ----- Begin raw operating clock signal generation -----
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initial
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begin
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op_clock_reg[0] = 1'b0;
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end
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// ----- End raw operating clock signal generation -----
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// ----- Actual operating clock is triggered only when config_done is enabled -----
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assign prog_clock[0] = prog_clock_reg[0] & (~prog_reset[0]);
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assign op_clock[0] = op_clock_reg[0];
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// ----- Begin programming reset signal generation -----
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initial
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begin
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prog_reset[0] = 1'b1;
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#(`SOC_SETUP_TIME_PERIOD + 2 * `FPGA_PROG_CLOCK_PERIOD) prog_reset[0] = 1'b0;
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end
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// ----- End programming reset signal generation -----
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// ----- Begin operating reset signal generation -----
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// ----- Reset signal is disabled always -----
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initial
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begin
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greset[0] = 1'b1;
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end
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// ----- End operating reset signal generation -----
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// ----- Begin connecting global ports of FPGA fabric to stimuli -----
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assign op_clk[0] = op_clock[0];
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assign prog_clk[0] = prog_clock[0];
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assign pReset[0] = ~prog_reset[0];
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assign Reset[0] = ~greset[0];
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assign Test_en[0] = 1'b0;
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assign sc_head[0] = 1'b0;
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assign IO_ISOL_N[0] = ~greset;
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// ----- End connecting global ports of FPGA fabric to stimuli -----
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assign mprj_io[0] = Test_en;
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assign mprj_io[1] = IO_ISOL_N;
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assign mprj_io[2] = Reset;
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assign mprj_io[3] = pReset;
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assign mprj_io[12] = ccff_head;
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assign mprj_io[25] = 1'b0; // Set FPGA to interface logic analyzer by default
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assign mprj_io[26] = sc_head;
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assign mprj_io[36] = op_clk;
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assign mprj_io[37] = prog_clk;
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assign sc_tail = mprj_io[11];
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assign ccff_tail = mprj_io[35];
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assign mprj_io[10:4] = {7{1'b0}};
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assign mprj_io[24:13] = {12{1'b0}};
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assign mprj_io[34:27] = {8{1'b0}};
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// Generate a pulse after programming reset is disabled (in the 2nd clock
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// cycle). Then the head of configuration chain should be always zero
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always @(negedge prog_clock[0]) begin
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ccff_head = 1'b1;
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if (0 != num_prog_cycles) begin
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ccff_head = 1'b0;
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end
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end
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// ----- Count the number of programming cycles -------
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always @(posedge prog_clock[0]) begin
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num_prog_cycles = num_prog_cycles + 1;
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// Indicate when configuration is suppose to end
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if (`FPGA_BITSTREAM_SIZE + 1 == num_prog_cycles) begin
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config_done = 1'b1;
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end
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// Check the ccff_tail when configuration is done
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if (1'b1 == config_done) begin
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// The tail should spit a pulse after configuration is done
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// So it should be at logic '1' and then pulled down to logic '0'
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if (0 == num_checked_points) begin
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if (ccff_tail !== 1'b1) begin
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$display("Error: ccff_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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end
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if (1 <= num_checked_points) begin
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if (ccff_tail !== 1'b0) begin
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$display("Error: ccff_tail = %b", sc_tail);
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num_errors = num_errors + 1;
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end
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end
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num_checked_points = num_checked_points + 1;
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end
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if (2 < num_checked_points) begin
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$display("Simulation finish with %d errors", num_errors);
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// End simulation
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$finish;
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end
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end
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// External clock is used by default. Make this artificially fast for the
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// simulation. Normally this would be a slow clock and the digital PLL
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// would be the fast clock.
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always #(`SOC_CLOCK_PERIOD) clock <= (clock === 1'b0);
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initial begin
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clock = 0;
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end
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initial begin
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RSTB <= 1'b0;
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soc_setup_done <= 1'b1;
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#(`SOC_SETUP_TIME_PERIOD);
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RSTB <= 1'b1; // Release reset
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soc_setup_done <= 1'b1; // We can start scff test
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end
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initial begin // Power-up sequence
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power1 <= 1'b0;
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power2 <= 1'b0;
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power3 <= 1'b0;
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power4 <= 1'b0;
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#(`POWER_UP_TIME_PERIOD);
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power1 <= 1'b1;
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#(`POWER_UP_TIME_PERIOD);
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power2 <= 1'b1;
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#(`POWER_UP_TIME_PERIOD);
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power3 <= 1'b1;
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#(`POWER_UP_TIME_PERIOD);
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power4 <= 1'b1;
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end
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wire flash_csb;
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wire flash_clk;
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wire flash_io0;
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wire flash_io1;
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|
||||
wire VDD3V3 = power1;
|
||||
wire VDD1V8 = power2;
|
||||
wire USER_VDD3V3 = power3;
|
||||
wire USER_VDD1V8 = power4;
|
||||
wire VSS = 1'b0;
|
||||
|
||||
caravel uut (
|
||||
.vddio (VDD3V3),
|
||||
.vssio (VSS),
|
||||
.vdda (VDD3V3),
|
||||
.vssa (VSS),
|
||||
.vccd (VDD1V8),
|
||||
.vssd (VSS),
|
||||
.vdda1 (USER_VDD3V3),
|
||||
.vdda2 (USER_VDD3V3),
|
||||
.vssa1 (VSS),
|
||||
.vssa2 (VSS),
|
||||
.vccd1 (USER_VDD1V8),
|
||||
.vccd2 (USER_VDD1V8),
|
||||
.vssd1 (VSS),
|
||||
.vssd2 (VSS),
|
||||
.clock (clock),
|
||||
.gpio (gpio),
|
||||
.mprj_io (mprj_io),
|
||||
.flash_csb(flash_csb),
|
||||
.flash_clk(flash_clk),
|
||||
.flash_io0(flash_io0),
|
||||
.flash_io1(flash_io1),
|
||||
.resetb (RSTB)
|
||||
);
|
||||
|
||||
spiflash #(
|
||||
.FILENAME("/research/ece/lnis/USERS/tang/github/skywater-openfpga/TESTBENCH/caravel_dv/scff_test/scff_test_caravel.hex")
|
||||
) spiflash (
|
||||
.csb(flash_csb),
|
||||
.clk(flash_clk),
|
||||
.io0(flash_io0),
|
||||
.io1(flash_io1),
|
||||
.io2(), // not used
|
||||
.io3() // not used
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue