mirror of https://github.com/lnis-uofu/SOFA.git
[QLSOFA_HD] Updated QLSOFA_HD module files
This commit is contained in:
Ganesh Gore
parent
809b070ce2
commit
e15f319103
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FPGA1212_QLSOFA_HD_PNR/modules/spef/cbx_1__0__icv_in_design.nominal_25.spef (Stored with Git LFS)
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@ -0,0 +1,504 @@
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//
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//
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//
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//
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//
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//
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module cbx_1__0_ ( pReset , chanx_left_in , chanx_right_in , ccff_head ,
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chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
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bottom_grid_pin_2_ , bottom_grid_pin_4_ , bottom_grid_pin_6_ ,
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bottom_grid_pin_8_ , bottom_grid_pin_10_ , bottom_grid_pin_12_ ,
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bottom_grid_pin_14_ , bottom_grid_pin_16_ , ccff_tail , IO_ISOL_N ,
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gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
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gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , top_width_0_height_0__pin_0_ ,
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top_width_0_height_0__pin_2_ , top_width_0_height_0__pin_4_ ,
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top_width_0_height_0__pin_6_ , top_width_0_height_0__pin_8_ ,
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top_width_0_height_0__pin_10_ , top_width_0_height_0__pin_12_ ,
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top_width_0_height_0__pin_14_ , top_width_0_height_0__pin_16_ ,
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top_width_0_height_0__pin_1_upper , top_width_0_height_0__pin_1_lower ,
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top_width_0_height_0__pin_3_upper , top_width_0_height_0__pin_3_lower ,
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top_width_0_height_0__pin_5_upper , top_width_0_height_0__pin_5_lower ,
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top_width_0_height_0__pin_7_upper , top_width_0_height_0__pin_7_lower ,
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top_width_0_height_0__pin_9_upper , top_width_0_height_0__pin_9_lower ,
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top_width_0_height_0__pin_11_upper , top_width_0_height_0__pin_11_lower ,
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top_width_0_height_0__pin_13_upper , top_width_0_height_0__pin_13_lower ,
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top_width_0_height_0__pin_15_upper , top_width_0_height_0__pin_15_lower ,
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top_width_0_height_0__pin_17_upper , top_width_0_height_0__pin_17_lower ,
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SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP , pReset_E_in ,
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pReset_W_in , pReset_W_out , pReset_E_out , prog_clk_0_N_in ,
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prog_clk_0_W_out ) ;
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input [0:0] pReset ;
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input [0:29] chanx_left_in ;
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input [0:29] chanx_right_in ;
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input [0:0] ccff_head ;
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output [0:29] chanx_left_out ;
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output [0:29] chanx_right_out ;
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output [0:0] bottom_grid_pin_0_ ;
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output [0:0] bottom_grid_pin_2_ ;
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output [0:0] bottom_grid_pin_4_ ;
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output [0:0] bottom_grid_pin_6_ ;
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output [0:0] bottom_grid_pin_8_ ;
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output [0:0] bottom_grid_pin_10_ ;
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output [0:0] bottom_grid_pin_12_ ;
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output [0:0] bottom_grid_pin_14_ ;
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output [0:0] bottom_grid_pin_16_ ;
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output [0:0] ccff_tail ;
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input [0:0] IO_ISOL_N ;
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input [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
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output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
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output [0:8] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
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input [0:0] top_width_0_height_0__pin_0_ ;
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input [0:0] top_width_0_height_0__pin_2_ ;
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input [0:0] top_width_0_height_0__pin_4_ ;
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input [0:0] top_width_0_height_0__pin_6_ ;
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input [0:0] top_width_0_height_0__pin_8_ ;
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input [0:0] top_width_0_height_0__pin_10_ ;
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input [0:0] top_width_0_height_0__pin_12_ ;
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input [0:0] top_width_0_height_0__pin_14_ ;
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input [0:0] top_width_0_height_0__pin_16_ ;
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output [0:0] top_width_0_height_0__pin_1_upper ;
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output [0:0] top_width_0_height_0__pin_1_lower ;
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output [0:0] top_width_0_height_0__pin_3_upper ;
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output [0:0] top_width_0_height_0__pin_3_lower ;
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output [0:0] top_width_0_height_0__pin_5_upper ;
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output [0:0] top_width_0_height_0__pin_5_lower ;
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output [0:0] top_width_0_height_0__pin_7_upper ;
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output [0:0] top_width_0_height_0__pin_7_lower ;
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output [0:0] top_width_0_height_0__pin_9_upper ;
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output [0:0] top_width_0_height_0__pin_9_lower ;
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output [0:0] top_width_0_height_0__pin_11_upper ;
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output [0:0] top_width_0_height_0__pin_11_lower ;
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output [0:0] top_width_0_height_0__pin_13_upper ;
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output [0:0] top_width_0_height_0__pin_13_lower ;
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output [0:0] top_width_0_height_0__pin_15_upper ;
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output [0:0] top_width_0_height_0__pin_15_lower ;
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output [0:0] top_width_0_height_0__pin_17_upper ;
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output [0:0] top_width_0_height_0__pin_17_lower ;
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input SC_IN_TOP ;
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output SC_OUT_BOT ;
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input SC_IN_BOT ;
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output SC_OUT_TOP ;
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input pReset_E_in ;
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input pReset_W_in ;
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output pReset_W_out ;
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output pReset_E_out ;
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input prog_clk_0_N_in ;
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output prog_clk_0_W_out ;
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wire [0:0] prog_clk ;
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wire prog_clk_0 ;
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wire [0:3] mux_tree_tapbuf_size12_0_sram ;
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wire [0:3] mux_tree_tapbuf_size12_1_sram ;
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wire [0:3] mux_tree_tapbuf_size12_2_sram ;
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wire [0:3] mux_tree_tapbuf_size12_3_sram ;
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wire [0:3] mux_tree_tapbuf_size12_4_sram ;
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wire [0:3] mux_tree_tapbuf_size12_5_sram ;
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wire [0:3] mux_tree_tapbuf_size12_6_sram ;
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wire [0:3] mux_tree_tapbuf_size12_7_sram ;
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wire [0:3] mux_tree_tapbuf_size12_8_sram ;
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wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
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wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
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wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
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wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
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wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
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wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
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wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
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wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
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wire [0:0] logical_tile_io_mode_io__0_ccff_tail ;
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wire [0:0] logical_tile_io_mode_io__1_ccff_tail ;
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wire [0:0] logical_tile_io_mode_io__2_ccff_tail ;
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wire [0:0] logical_tile_io_mode_io__3_ccff_tail ;
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wire [0:0] logical_tile_io_mode_io__4_ccff_tail ;
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wire [0:0] logical_tile_io_mode_io__5_ccff_tail ;
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wire [0:0] logical_tile_io_mode_io__6_ccff_tail ;
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wire [0:0] logical_tile_io_mode_io__7_ccff_tail ;
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assign pReset_W_in = pReset_E_in ;
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assign prog_clk_0 = prog_clk[0] ;
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cbx_1__0__mux_tree_tapbuf_size12_0 mux_top_ipin_0 (
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.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
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chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
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chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
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chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
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.sram ( mux_tree_tapbuf_size12_0_sram ) ,
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.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
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SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
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.out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ;
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cbx_1__0__mux_tree_tapbuf_size12_1 mux_top_ipin_1 (
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.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
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chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
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chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
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chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
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.sram ( mux_tree_tapbuf_size12_1_sram ) ,
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.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
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SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
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.out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_103 ) ) ;
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cbx_1__0__mux_tree_tapbuf_size12_2 mux_top_ipin_2 (
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.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
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chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
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chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
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chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
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.sram ( mux_tree_tapbuf_size12_2_sram ) ,
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.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
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SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
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.out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_103 ) ) ;
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cbx_1__0__mux_tree_tapbuf_size12_3 mux_top_ipin_3 (
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.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
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chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
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chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
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chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
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.sram ( mux_tree_tapbuf_size12_3_sram ) ,
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.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
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SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
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.out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_105 ) ) ;
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cbx_1__0__mux_tree_tapbuf_size12_4 mux_top_ipin_4 (
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.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
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chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
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chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
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chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) ,
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.sram ( mux_tree_tapbuf_size12_4_sram ) ,
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.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
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SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
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.out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_105 ) ) ;
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cbx_1__0__mux_tree_tapbuf_size12_5 mux_top_ipin_5 (
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.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
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chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
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chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] ,
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chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
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.sram ( mux_tree_tapbuf_size12_5_sram ) ,
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.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
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SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
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.out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ;
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cbx_1__0__mux_tree_tapbuf_size12_6 mux_top_ipin_6 (
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.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
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chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
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chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
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chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
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.sram ( mux_tree_tapbuf_size12_6_sram ) ,
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.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
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SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
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.out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_104 ) ) ;
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cbx_1__0__mux_tree_tapbuf_size12_7 mux_top_ipin_7 (
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.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
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chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
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chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
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chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
|
||||
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
|
||||
.out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_104 ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12 mux_top_ipin_8 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
|
||||
chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
|
||||
chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
|
||||
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( bottom_grid_pin_16_ ) , .p0 ( optlc_net_103 ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
|
||||
cbx_1__0__mux_tree_tapbuf_size12_mem mem_top_ipin_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( { ccff_tail_mid } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ;
|
||||
cbx_1__0__logical_tile_io_mode_io__0 logical_tile_io_mode_io__0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
|
||||
.io_outpad ( top_width_0_height_0__pin_0_ ) ,
|
||||
.ccff_head ( { ccff_tail_mid } ) ,
|
||||
.io_inpad ( top_width_0_height_0__pin_1_lower ) ,
|
||||
.ccff_tail ( logical_tile_io_mode_io__0_ccff_tail ) ) ;
|
||||
cbx_1__0__logical_tile_io_mode_io__1 logical_tile_io_mode_io__1 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[1] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[1] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[1] ) ,
|
||||
.io_outpad ( top_width_0_height_0__pin_2_ ) ,
|
||||
.ccff_head ( logical_tile_io_mode_io__0_ccff_tail ) ,
|
||||
.io_inpad ( top_width_0_height_0__pin_3_lower ) ,
|
||||
.ccff_tail ( logical_tile_io_mode_io__1_ccff_tail ) ) ;
|
||||
cbx_1__0__logical_tile_io_mode_io__2 logical_tile_io_mode_io__2 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[2] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[2] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[2] ) ,
|
||||
.io_outpad ( top_width_0_height_0__pin_4_ ) ,
|
||||
.ccff_head ( logical_tile_io_mode_io__1_ccff_tail ) ,
|
||||
.io_inpad ( top_width_0_height_0__pin_5_lower ) ,
|
||||
.ccff_tail ( logical_tile_io_mode_io__2_ccff_tail ) ) ;
|
||||
cbx_1__0__logical_tile_io_mode_io__3 logical_tile_io_mode_io__3 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[3] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[3] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[3] ) ,
|
||||
.io_outpad ( top_width_0_height_0__pin_6_ ) ,
|
||||
.ccff_head ( logical_tile_io_mode_io__2_ccff_tail ) ,
|
||||
.io_inpad ( top_width_0_height_0__pin_7_lower ) ,
|
||||
.ccff_tail ( logical_tile_io_mode_io__3_ccff_tail ) ) ;
|
||||
cbx_1__0__logical_tile_io_mode_io__4 logical_tile_io_mode_io__4 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[4] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[4] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[4] ) ,
|
||||
.io_outpad ( top_width_0_height_0__pin_8_ ) ,
|
||||
.ccff_head ( logical_tile_io_mode_io__3_ccff_tail ) ,
|
||||
.io_inpad ( top_width_0_height_0__pin_9_lower ) ,
|
||||
.ccff_tail ( logical_tile_io_mode_io__4_ccff_tail ) ) ;
|
||||
cbx_1__0__logical_tile_io_mode_io__5 logical_tile_io_mode_io__5 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[5] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[5] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_506_ } ) ,
|
||||
.io_outpad ( top_width_0_height_0__pin_10_ ) ,
|
||||
.ccff_head ( logical_tile_io_mode_io__4_ccff_tail ) ,
|
||||
.io_inpad ( top_width_0_height_0__pin_11_lower ) ,
|
||||
.ccff_tail ( logical_tile_io_mode_io__5_ccff_tail ) ,
|
||||
.ZBUF_217_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ;
|
||||
cbx_1__0__logical_tile_io_mode_io__6 logical_tile_io_mode_io__6 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[6] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[6] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[6] ) ,
|
||||
.io_outpad ( top_width_0_height_0__pin_12_ ) ,
|
||||
.ccff_head ( logical_tile_io_mode_io__5_ccff_tail ) ,
|
||||
.io_inpad ( top_width_0_height_0__pin_13_lower ) ,
|
||||
.ccff_tail ( logical_tile_io_mode_io__6_ccff_tail ) ) ;
|
||||
cbx_1__0__logical_tile_io_mode_io__7 logical_tile_io_mode_io__7 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[7] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[7] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_507_ } ) ,
|
||||
.io_outpad ( top_width_0_height_0__pin_14_ ) ,
|
||||
.ccff_head ( logical_tile_io_mode_io__6_ccff_tail ) ,
|
||||
.io_inpad ( top_width_0_height_0__pin_15_lower ) ,
|
||||
.ccff_tail ( logical_tile_io_mode_io__7_ccff_tail ) ,
|
||||
.ZBUF_208_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ;
|
||||
cbx_1__0__logical_tile_io_mode_io_ logical_tile_io_mode_io__8 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[8] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[8] ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( { aps_rename_508_ } ) ,
|
||||
.io_outpad ( top_width_0_height_0__pin_16_ ) ,
|
||||
.ccff_head ( logical_tile_io_mode_io__7_ccff_tail ) ,
|
||||
.io_inpad ( top_width_0_height_0__pin_17_lower ) ,
|
||||
.ccff_tail ( ccff_tail ) ,
|
||||
.ZBUF_898_f_0 ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_W_in ) ,
|
||||
.X ( aps_rename_509_ ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_W_in ) ,
|
||||
.X ( pReset_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
|
||||
.X ( ctsbuf_net_1106 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
|
||||
.X ( chanx_right_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
|
||||
.X ( chanx_right_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
|
||||
.X ( chanx_right_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
|
||||
.X ( chanx_right_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
|
||||
.X ( chanx_right_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
|
||||
.X ( chanx_right_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
|
||||
.X ( chanx_right_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
|
||||
.X ( chanx_right_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
|
||||
.X ( chanx_right_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
|
||||
.X ( chanx_right_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
|
||||
.X ( chanx_right_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
|
||||
.X ( chanx_right_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
|
||||
.X ( chanx_right_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
|
||||
.X ( chanx_right_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
|
||||
.X ( chanx_right_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
|
||||
.X ( chanx_right_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
|
||||
.X ( chanx_right_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
|
||||
.X ( chanx_right_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
|
||||
.X ( chanx_right_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
|
||||
.X ( chanx_right_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) ,
|
||||
.X ( chanx_right_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) ,
|
||||
.X ( chanx_right_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) ,
|
||||
.X ( chanx_right_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) ,
|
||||
.X ( chanx_right_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) ,
|
||||
.X ( chanx_right_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) ,
|
||||
.X ( chanx_right_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) ,
|
||||
.X ( chanx_right_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) ,
|
||||
.X ( chanx_right_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) ,
|
||||
.X ( chanx_right_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) ,
|
||||
.X ( chanx_right_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) ,
|
||||
.X ( chanx_left_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) ,
|
||||
.X ( chanx_left_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) ,
|
||||
.X ( chanx_left_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) ,
|
||||
.X ( chanx_left_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) ,
|
||||
.X ( chanx_left_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) ,
|
||||
.X ( chanx_left_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) ,
|
||||
.X ( chanx_left_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) ,
|
||||
.X ( chanx_left_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) ,
|
||||
.X ( chanx_left_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) ,
|
||||
.X ( chanx_left_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) ,
|
||||
.X ( chanx_left_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) ,
|
||||
.X ( chanx_left_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) ,
|
||||
.X ( chanx_left_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) ,
|
||||
.X ( chanx_left_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) ,
|
||||
.X ( chanx_left_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) ,
|
||||
.X ( chanx_left_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) ,
|
||||
.X ( chanx_left_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) ,
|
||||
.X ( chanx_left_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) ,
|
||||
.X ( chanx_left_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) ,
|
||||
.X ( chanx_left_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) ,
|
||||
.X ( chanx_left_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) ,
|
||||
.X ( chanx_left_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) ,
|
||||
.X ( chanx_left_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) ,
|
||||
.X ( chanx_left_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) ,
|
||||
.X ( chanx_left_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) ,
|
||||
.X ( chanx_left_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) ,
|
||||
.X ( chanx_left_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) ,
|
||||
.X ( chanx_left_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) ,
|
||||
.X ( chanx_left_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) ,
|
||||
.X ( chanx_left_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_79__78 (
|
||||
.A ( top_width_0_height_0__pin_1_lower[0] ) ,
|
||||
.X ( top_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_80__79 (
|
||||
.A ( top_width_0_height_0__pin_3_lower[0] ) ,
|
||||
.X ( top_width_0_height_0__pin_3_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_81__80 (
|
||||
.A ( top_width_0_height_0__pin_5_lower[0] ) ,
|
||||
.X ( top_width_0_height_0__pin_5_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_82__81 (
|
||||
.A ( top_width_0_height_0__pin_7_lower[0] ) ,
|
||||
.X ( top_width_0_height_0__pin_7_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_83__82 (
|
||||
.A ( top_width_0_height_0__pin_9_lower[0] ) ,
|
||||
.X ( top_width_0_height_0__pin_9_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_84__83 (
|
||||
.A ( top_width_0_height_0__pin_11_lower[0] ) ,
|
||||
.X ( top_width_0_height_0__pin_11_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_85__84 (
|
||||
.A ( top_width_0_height_0__pin_13_lower[0] ) ,
|
||||
.X ( top_width_0_height_0__pin_13_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_86__85 (
|
||||
.A ( top_width_0_height_0__pin_15_lower[0] ) ,
|
||||
.X ( top_width_0_height_0__pin_15_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_87__86 (
|
||||
.A ( top_width_0_height_0__pin_17_lower[0] ) ,
|
||||
.X ( top_width_0_height_0__pin_17_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_88__87 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_89__88 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_37 ) ,
|
||||
.HI ( optlc_net_103 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_38 ) ,
|
||||
.HI ( optlc_net_104 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_39 ) ,
|
||||
.HI ( optlc_net_105 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ZBUF_208_inst_110 ( .A ( aps_rename_507_ ) ,
|
||||
.X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_111 ( .A ( aps_rename_509_ ) ,
|
||||
.X ( pReset_W_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_217_inst_112 ( .A ( aps_rename_506_ ) ,
|
||||
.X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ZBUF_898_f_inst_113 ( .A ( aps_rename_508_ ) ,
|
||||
.X ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1106 ) ,
|
||||
.X ( prog_clk_0_W_out ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,538 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module cbx_1__1_ ( pReset , chanx_left_in , chanx_right_in , ccff_head ,
|
||||
chanx_left_out , chanx_right_out , bottom_grid_pin_0_ ,
|
||||
bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
|
||||
bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
|
||||
bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
|
||||
bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
|
||||
bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
|
||||
ccff_tail , SC_IN_TOP , SC_OUT_BOT , SC_IN_BOT , SC_OUT_TOP ,
|
||||
REGIN_FEEDTHROUGH , REGOUT_FEEDTHROUGH , CIN_FEEDTHROUGH ,
|
||||
COUT_FEEDTHROUGH , pReset_E_in , pReset_W_in , pReset_W_out ,
|
||||
pReset_S_out , pReset_E_out , prog_clk_0_N_in , prog_clk_0_W_out ,
|
||||
prog_clk_1_W_in , prog_clk_1_E_in , prog_clk_1_N_out , prog_clk_1_S_out ,
|
||||
prog_clk_2_E_in , prog_clk_2_W_in , prog_clk_2_W_out , prog_clk_2_E_out ,
|
||||
prog_clk_3_W_in , prog_clk_3_E_in , prog_clk_3_E_out , prog_clk_3_W_out ,
|
||||
clk_1_W_in , clk_1_E_in , clk_1_N_out , clk_1_S_out , clk_2_E_in ,
|
||||
clk_2_W_in , clk_2_W_out , clk_2_E_out , clk_3_W_in , clk_3_E_in ,
|
||||
clk_3_E_out , clk_3_W_out ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chanx_left_in ;
|
||||
input [0:29] chanx_right_in ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chanx_left_out ;
|
||||
output [0:29] chanx_right_out ;
|
||||
output [0:0] bottom_grid_pin_0_ ;
|
||||
output [0:0] bottom_grid_pin_1_ ;
|
||||
output [0:0] bottom_grid_pin_2_ ;
|
||||
output [0:0] bottom_grid_pin_3_ ;
|
||||
output [0:0] bottom_grid_pin_4_ ;
|
||||
output [0:0] bottom_grid_pin_5_ ;
|
||||
output [0:0] bottom_grid_pin_6_ ;
|
||||
output [0:0] bottom_grid_pin_7_ ;
|
||||
output [0:0] bottom_grid_pin_8_ ;
|
||||
output [0:0] bottom_grid_pin_9_ ;
|
||||
output [0:0] bottom_grid_pin_10_ ;
|
||||
output [0:0] bottom_grid_pin_11_ ;
|
||||
output [0:0] bottom_grid_pin_12_ ;
|
||||
output [0:0] bottom_grid_pin_13_ ;
|
||||
output [0:0] bottom_grid_pin_14_ ;
|
||||
output [0:0] bottom_grid_pin_15_ ;
|
||||
output [0:0] ccff_tail ;
|
||||
input SC_IN_TOP ;
|
||||
output SC_OUT_BOT ;
|
||||
input SC_IN_BOT ;
|
||||
output SC_OUT_TOP ;
|
||||
input REGIN_FEEDTHROUGH ;
|
||||
output REGOUT_FEEDTHROUGH ;
|
||||
input CIN_FEEDTHROUGH ;
|
||||
output COUT_FEEDTHROUGH ;
|
||||
input pReset_E_in ;
|
||||
input pReset_W_in ;
|
||||
output pReset_W_out ;
|
||||
output pReset_S_out ;
|
||||
output pReset_E_out ;
|
||||
input prog_clk_0_N_in ;
|
||||
output prog_clk_0_W_out ;
|
||||
input prog_clk_1_W_in ;
|
||||
input prog_clk_1_E_in ;
|
||||
output prog_clk_1_N_out ;
|
||||
output prog_clk_1_S_out ;
|
||||
input prog_clk_2_E_in ;
|
||||
input prog_clk_2_W_in ;
|
||||
output prog_clk_2_W_out ;
|
||||
output prog_clk_2_E_out ;
|
||||
input prog_clk_3_W_in ;
|
||||
input prog_clk_3_E_in ;
|
||||
output prog_clk_3_E_out ;
|
||||
output prog_clk_3_W_out ;
|
||||
input clk_1_W_in ;
|
||||
input clk_1_E_in ;
|
||||
output clk_1_N_out ;
|
||||
output clk_1_S_out ;
|
||||
input clk_2_E_in ;
|
||||
input clk_2_W_in ;
|
||||
output clk_2_W_out ;
|
||||
output clk_2_E_out ;
|
||||
input clk_3_W_in ;
|
||||
input clk_3_E_in ;
|
||||
output clk_3_E_out ;
|
||||
output clk_3_W_out ;
|
||||
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_2_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_3_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_4_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_5_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_6_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_7_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
|
||||
|
||||
assign pReset_W_in = pReset_E_in ;
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
assign prog_clk_1_E_in = prog_clk_1_W_in ;
|
||||
assign prog_clk_2_W_in = prog_clk_2_E_in ;
|
||||
assign prog_clk_3_E_in = prog_clk_3_W_in ;
|
||||
assign clk_1_E_in = clk_1_W_in ;
|
||||
assign clk_2_W_in = clk_2_E_in ;
|
||||
assign clk_3_E_in = clk_3_W_in ;
|
||||
|
||||
cbx_1__1__mux_tree_tapbuf_size12_0 mux_top_ipin_0 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
|
||||
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
|
||||
chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
|
||||
.out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_1 mux_top_ipin_2 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
|
||||
chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
|
||||
chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
|
||||
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
|
||||
.out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_2 mux_top_ipin_4 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
|
||||
chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
|
||||
chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
|
||||
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_89 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_3 mux_top_ipin_6 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
|
||||
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
|
||||
chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
|
||||
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
|
||||
.out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_4 mux_top_ipin_8 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
|
||||
chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
|
||||
chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
|
||||
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
|
||||
.out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_89 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_5 mux_top_ipin_10 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
|
||||
chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
|
||||
chanx_left_out[22] , chanx_right_out[28] , chanx_left_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
|
||||
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_89 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_6 mux_top_ipin_12 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
|
||||
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
|
||||
chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
|
||||
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
|
||||
.out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12 mux_top_ipin_14 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
|
||||
chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[20] ,
|
||||
chanx_left_out[20] , chanx_right_out[26] , chanx_left_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
|
||||
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
|
||||
.out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_mem_0 mem_top_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_0 mux_top_ipin_1 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
|
||||
chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] ,
|
||||
chanx_left_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
|
||||
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_89 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
|
||||
chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] ,
|
||||
chanx_left_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
|
||||
SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
|
||||
.out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_2 mux_top_ipin_5 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
|
||||
chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] ,
|
||||
chanx_left_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
|
||||
SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
|
||||
.out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
|
||||
chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[22] ,
|
||||
chanx_left_out[22] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
|
||||
SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
|
||||
.out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_4 mux_top_ipin_9 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
|
||||
chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[24] ,
|
||||
chanx_left_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
|
||||
SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
|
||||
.out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
|
||||
chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] ,
|
||||
chanx_left_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
|
||||
SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
|
||||
.out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_90 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_6 mux_top_ipin_13 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[13] , chanx_left_out[13] ,
|
||||
chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] ,
|
||||
chanx_left_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
|
||||
SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
|
||||
.out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_90 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10 mux_top_ipin_15 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
|
||||
chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
|
||||
chanx_left_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
|
||||
SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
|
||||
.out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
|
||||
cbx_1__1__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( { copt_net_100 } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) ,
|
||||
.X ( pReset_W_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) ,
|
||||
.X ( pReset_S_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) ,
|
||||
.X ( pReset_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_2 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_N_in ) ,
|
||||
.X ( ctsbuf_net_193 ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 prog_clk_1_N_FTB01 ( .A ( prog_clk_1_E_in ) ,
|
||||
.X ( prog_clk_1_N_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 prog_clk_1_S_FTB01 ( .A ( prog_clk_1_E_in ) ,
|
||||
.X ( prog_clk_1_S_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 prog_clk_2_W_FTB01 ( .A ( prog_clk_2_W_in ) ,
|
||||
.X ( prog_clk_2_W_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 prog_clk_2_E_FTB01 ( .A ( prog_clk_2_W_in ) ,
|
||||
.X ( aps_rename_505_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 prog_clk_3_E_FTB01 ( .A ( prog_clk_3_E_in ) ,
|
||||
.X ( aps_rename_506_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 prog_clk_3_W_FTB01 ( .A ( prog_clk_3_E_in ) ,
|
||||
.X ( prog_clk_3_W_out ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 clk_1_N_FTB01 ( .A ( clk_1_E_in ) ,
|
||||
.X ( clk_1_N_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 clk_1_S_FTB01 ( .A ( clk_1_E_in ) ,
|
||||
.X ( clk_1_S_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 clk_2_W_FTB01 ( .A ( clk_2_W_in ) ,
|
||||
.X ( clk_2_W_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 clk_2_E_FTB01 ( .A ( clk_2_W_in ) ,
|
||||
.X ( aps_rename_507_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 clk_3_E_FTB01 ( .A ( clk_3_E_in ) ,
|
||||
.X ( aps_rename_508_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 clk_3_W_FTB01 ( .A ( clk_3_E_in ) ,
|
||||
.X ( clk_3_W_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chanx_left_in[0] ) ,
|
||||
.X ( chanx_right_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chanx_left_in[1] ) ,
|
||||
.X ( chanx_right_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[2] ) ,
|
||||
.X ( chanx_right_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[3] ) ,
|
||||
.X ( chanx_right_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[4] ) ,
|
||||
.X ( chanx_right_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[5] ) ,
|
||||
.X ( chanx_right_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[6] ) ,
|
||||
.X ( chanx_right_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[7] ) ,
|
||||
.X ( chanx_right_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[8] ) ,
|
||||
.X ( chanx_right_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[9] ) ,
|
||||
.X ( chanx_right_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[10] ) ,
|
||||
.X ( chanx_right_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[11] ) ,
|
||||
.X ( chanx_right_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[12] ) ,
|
||||
.X ( chanx_right_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[13] ) ,
|
||||
.X ( chanx_right_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[14] ) ,
|
||||
.X ( chanx_right_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[15] ) ,
|
||||
.X ( chanx_right_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[16] ) ,
|
||||
.X ( chanx_right_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[17] ) ,
|
||||
.X ( chanx_right_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[18] ) ,
|
||||
.X ( chanx_right_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[19] ) ,
|
||||
.X ( chanx_right_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[20] ) ,
|
||||
.X ( chanx_right_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[21] ) ,
|
||||
.X ( chanx_right_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[22] ) ,
|
||||
.X ( chanx_right_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_left_in[23] ) ,
|
||||
.X ( chanx_right_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[24] ) ,
|
||||
.X ( chanx_right_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[25] ) ,
|
||||
.X ( chanx_right_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[26] ) ,
|
||||
.X ( chanx_right_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[27] ) ,
|
||||
.X ( chanx_right_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[28] ) ,
|
||||
.X ( chanx_right_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[29] ) ,
|
||||
.X ( chanx_right_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[0] ) ,
|
||||
.X ( chanx_left_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[1] ) ,
|
||||
.X ( chanx_left_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[2] ) ,
|
||||
.X ( chanx_left_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[3] ) ,
|
||||
.X ( chanx_left_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[4] ) ,
|
||||
.X ( chanx_left_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[5] ) ,
|
||||
.X ( chanx_left_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) ,
|
||||
.X ( chanx_left_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) ,
|
||||
.X ( chanx_left_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) ,
|
||||
.X ( chanx_left_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[9] ) ,
|
||||
.X ( chanx_left_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[10] ) ,
|
||||
.X ( chanx_left_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[11] ) ,
|
||||
.X ( chanx_left_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[12] ) ,
|
||||
.X ( chanx_left_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[13] ) ,
|
||||
.X ( chanx_left_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[14] ) ,
|
||||
.X ( chanx_left_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[15] ) ,
|
||||
.X ( chanx_left_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[16] ) ,
|
||||
.X ( chanx_left_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[17] ) ,
|
||||
.X ( chanx_left_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[18] ) ,
|
||||
.X ( chanx_left_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[19] ) ,
|
||||
.X ( chanx_left_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[20] ) ,
|
||||
.X ( chanx_left_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[21] ) ,
|
||||
.X ( chanx_left_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[22] ) ,
|
||||
.X ( chanx_left_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_70__69 ( .A ( chanx_right_in[23] ) ,
|
||||
.X ( chanx_left_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[24] ) ,
|
||||
.X ( chanx_left_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[25] ) ,
|
||||
.X ( chanx_left_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[26] ) ,
|
||||
.X ( chanx_left_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[27] ) ,
|
||||
.X ( chanx_left_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[28] ) ,
|
||||
.X ( chanx_left_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[29] ) ,
|
||||
.X ( chanx_left_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_78__77 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_79__78 ( .A ( REGIN_FEEDTHROUGH ) ,
|
||||
.X ( REGOUT_FEEDTHROUGH ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( CIN_FEEDTHROUGH ) ,
|
||||
.X ( COUT_FEEDTHROUGH ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
|
||||
.HI ( optlc_net_89 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
|
||||
.HI ( optlc_net_90 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) ,
|
||||
.HI ( optlc_net_91 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) ,
|
||||
.HI ( optlc_net_92 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_602 ( .A ( aps_rename_507_ ) ,
|
||||
.X ( clk_2_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_603 ( .A ( aps_rename_505_ ) ,
|
||||
.X ( prog_clk_2_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_240_f_inst_604 ( .A ( aps_rename_508_ ) ,
|
||||
.X ( clk_3_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_39_inst_605 ( .A ( aps_rename_506_ ) ,
|
||||
.X ( prog_clk_3_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 copt_h_inst_1328 ( .A ( copt_net_102 ) ,
|
||||
.X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 cts_buf_3531229 ( .A ( ctsbuf_net_193 ) ,
|
||||
.X ( prog_clk_0_W_out ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1330 ( .A ( copt_net_100 ) ,
|
||||
.X ( copt_net_102 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,500 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module cbx_1__2_ ( pReset , chanx_left_in , chanx_right_in , ccff_head ,
|
||||
chanx_left_out , chanx_right_out , top_grid_pin_0_ , bottom_grid_pin_0_ ,
|
||||
bottom_grid_pin_1_ , bottom_grid_pin_2_ , bottom_grid_pin_3_ ,
|
||||
bottom_grid_pin_4_ , bottom_grid_pin_5_ , bottom_grid_pin_6_ ,
|
||||
bottom_grid_pin_7_ , bottom_grid_pin_8_ , bottom_grid_pin_9_ ,
|
||||
bottom_grid_pin_10_ , bottom_grid_pin_11_ , bottom_grid_pin_12_ ,
|
||||
bottom_grid_pin_13_ , bottom_grid_pin_14_ , bottom_grid_pin_15_ ,
|
||||
ccff_tail , IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
|
||||
bottom_width_0_height_0__pin_0_ , bottom_width_0_height_0__pin_1_upper ,
|
||||
bottom_width_0_height_0__pin_1_lower , SC_IN_TOP , SC_OUT_BOT ,
|
||||
SC_IN_BOT , SC_OUT_TOP , pReset_E_in , pReset_W_in , pReset_W_out ,
|
||||
pReset_S_out , pReset_E_out , prog_clk_0_S_in , prog_clk_0_W_out ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chanx_left_in ;
|
||||
input [0:29] chanx_right_in ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chanx_left_out ;
|
||||
output [0:29] chanx_right_out ;
|
||||
output [0:0] top_grid_pin_0_ ;
|
||||
output [0:0] bottom_grid_pin_0_ ;
|
||||
output [0:0] bottom_grid_pin_1_ ;
|
||||
output [0:0] bottom_grid_pin_2_ ;
|
||||
output [0:0] bottom_grid_pin_3_ ;
|
||||
output [0:0] bottom_grid_pin_4_ ;
|
||||
output [0:0] bottom_grid_pin_5_ ;
|
||||
output [0:0] bottom_grid_pin_6_ ;
|
||||
output [0:0] bottom_grid_pin_7_ ;
|
||||
output [0:0] bottom_grid_pin_8_ ;
|
||||
output [0:0] bottom_grid_pin_9_ ;
|
||||
output [0:0] bottom_grid_pin_10_ ;
|
||||
output [0:0] bottom_grid_pin_11_ ;
|
||||
output [0:0] bottom_grid_pin_12_ ;
|
||||
output [0:0] bottom_grid_pin_13_ ;
|
||||
output [0:0] bottom_grid_pin_14_ ;
|
||||
output [0:0] bottom_grid_pin_15_ ;
|
||||
output [0:0] ccff_tail ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] bottom_width_0_height_0__pin_0_ ;
|
||||
output [0:0] bottom_width_0_height_0__pin_1_upper ;
|
||||
output [0:0] bottom_width_0_height_0__pin_1_lower ;
|
||||
input SC_IN_TOP ;
|
||||
output SC_OUT_BOT ;
|
||||
input SC_IN_BOT ;
|
||||
output SC_OUT_TOP ;
|
||||
input pReset_E_in ;
|
||||
input pReset_W_in ;
|
||||
output pReset_W_out ;
|
||||
output pReset_S_out ;
|
||||
output pReset_E_out ;
|
||||
input prog_clk_0_S_in ;
|
||||
output prog_clk_0_W_out ;
|
||||
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_2_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_3_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_4_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_5_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_6_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_7_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_8_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ;
|
||||
|
||||
assign pReset_W_in = pReset_E_in ;
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
cbx_1__2__mux_tree_tapbuf_size12_0 mux_bottom_ipin_0 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
|
||||
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[18] ,
|
||||
chanx_left_out[18] , chanx_right_out[24] , chanx_left_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
|
||||
.out ( top_grid_pin_0_ ) , .p0 ( optlc_net_105 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_1 mux_top_ipin_0 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
|
||||
chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
|
||||
chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
|
||||
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
|
||||
.out ( bottom_grid_pin_0_ ) , .p0 ( optlc_net_102 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_2 mux_top_ipin_2 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
|
||||
chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
|
||||
chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
|
||||
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( bottom_grid_pin_2_ ) , .p0 ( optlc_net_101 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_3 mux_top_ipin_4 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
|
||||
chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] ,
|
||||
chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
|
||||
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
|
||||
.out ( bottom_grid_pin_4_ ) , .p0 ( optlc_net_101 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_4 mux_top_ipin_6 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
|
||||
chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
|
||||
chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
|
||||
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
|
||||
.out ( bottom_grid_pin_6_ ) , .p0 ( optlc_net_103 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_5 mux_top_ipin_8 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
|
||||
chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
|
||||
chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
|
||||
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( bottom_grid_pin_8_ ) , .p0 ( optlc_net_101 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_6 mux_top_ipin_10 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[11] , chanx_left_out[11] ,
|
||||
chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[23] ,
|
||||
chanx_left_out[23] , chanx_right_out[29] , chanx_left_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
|
||||
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
|
||||
.out ( bottom_grid_pin_10_ ) , .p0 ( optlc_net_103 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_7 mux_top_ipin_12 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
|
||||
chanx_right_out[13] , chanx_left_out[13] , chanx_right_out[19] ,
|
||||
chanx_left_out[19] , chanx_right_out[25] , chanx_left_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
|
||||
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
|
||||
.out ( bottom_grid_pin_12_ ) , .p0 ( optlc_net_103 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12 mux_top_ipin_14 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[9] , chanx_left_out[9] ,
|
||||
chanx_right_out[15] , chanx_left_out[15] , chanx_right_out[21] ,
|
||||
chanx_left_out[21] , chanx_right_out[27] , chanx_left_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
|
||||
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( bottom_grid_pin_14_ ) , .p0 ( optlc_net_105 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_mem_0 mem_bottom_ipin_0 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_mem_1 mem_top_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_mem_2 mem_top_ipin_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_mem_3 mem_top_ipin_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_mem_4 mem_top_ipin_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_mem_5 mem_top_ipin_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_mem_6 mem_top_ipin_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_mem_7 mem_top_ipin_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size12_mem mem_top_ipin_14 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_0 mux_top_ipin_1 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
|
||||
chanx_right_out[17] , chanx_left_out[17] , chanx_right_out[26] ,
|
||||
chanx_left_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
|
||||
SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
|
||||
.out ( bottom_grid_pin_1_ ) , .p0 ( optlc_net_101 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_1 mux_top_ipin_3 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
|
||||
chanx_right_out[19] , chanx_left_out[19] , chanx_right_out[28] ,
|
||||
chanx_left_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
|
||||
SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
|
||||
.out ( bottom_grid_pin_3_ ) , .p0 ( optlc_net_106 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_2 mux_top_ipin_5 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[6] , chanx_left_out[6] ,
|
||||
chanx_right_out[12] , chanx_left_out[12] , chanx_right_out[21] ,
|
||||
chanx_left_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
|
||||
SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
|
||||
.out ( bottom_grid_pin_5_ ) , .p0 ( optlc_net_104 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_3 mux_top_ipin_7 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[8] , chanx_left_out[8] ,
|
||||
chanx_right_out[14] , chanx_left_out[14] , chanx_right_out[23] ,
|
||||
chanx_left_out[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
|
||||
SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
|
||||
.out ( bottom_grid_pin_7_ ) , .p0 ( optlc_net_103 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_4 mux_top_ipin_9 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[10] , chanx_left_out[10] ,
|
||||
chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[25] ,
|
||||
chanx_left_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
|
||||
SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
|
||||
.out ( bottom_grid_pin_9_ ) , .p0 ( optlc_net_102 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_5 mux_top_ipin_11 (
|
||||
.in ( { chanx_right_out[0] , chanx_left_out[0] , chanx_right_out[3] ,
|
||||
chanx_left_out[3] , chanx_right_out[12] , chanx_left_out[12] ,
|
||||
chanx_right_out[18] , chanx_left_out[18] , chanx_right_out[27] ,
|
||||
chanx_left_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
|
||||
SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
|
||||
.out ( bottom_grid_pin_11_ ) , .p0 ( optlc_net_101 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_6 mux_top_ipin_13 (
|
||||
.in ( { chanx_right_out[2] , chanx_left_out[2] , chanx_right_out[5] ,
|
||||
chanx_left_out[5] , chanx_right_out[14] , chanx_left_out[14] ,
|
||||
chanx_right_out[20] , chanx_left_out[20] , chanx_right_out[29] ,
|
||||
chanx_left_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
|
||||
SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
|
||||
.out ( bottom_grid_pin_13_ ) , .p0 ( optlc_net_101 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10 mux_top_ipin_15 (
|
||||
.in ( { chanx_right_out[1] , chanx_left_out[1] , chanx_right_out[4] ,
|
||||
chanx_left_out[4] , chanx_right_out[7] , chanx_left_out[7] ,
|
||||
chanx_right_out[16] , chanx_left_out[16] , chanx_right_out[22] ,
|
||||
chanx_left_out[22] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
|
||||
SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
|
||||
.out ( bottom_grid_pin_15_ ) , .p0 ( optlc_net_103 ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_mem_0 mem_top_ipin_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_mem_1 mem_top_ipin_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_mem_2 mem_top_ipin_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_mem_3 mem_top_ipin_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_mem_4 mem_top_ipin_9 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_mem_5 mem_top_ipin_11 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_mem_6 mem_top_ipin_13 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
|
||||
cbx_1__2__mux_tree_tapbuf_size10_mem mem_top_ipin_15 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( { ccff_tail_mid } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
|
||||
cbx_1__2__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
|
||||
.io_outpad ( bottom_width_0_height_0__pin_0_ ) ,
|
||||
.ccff_head ( { ccff_tail_mid } ) ,
|
||||
.io_inpad ( bottom_width_0_height_0__pin_1_lower ) ,
|
||||
.ccff_tail ( ccff_tail ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_W_FTB01 ( .A ( pReset_W_in ) ,
|
||||
.X ( pReset_W_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_S_FTB01 ( .A ( pReset_W_in ) ,
|
||||
.X ( pReset_S_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_E_FTB01 ( .A ( pReset_W_in ) ,
|
||||
.X ( pReset_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_W_FTB01 ( .A ( prog_clk_0_S_in ) ,
|
||||
.X ( ctsbuf_net_1107 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chanx_left_in[0] ) ,
|
||||
.X ( chanx_right_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chanx_left_in[1] ) ,
|
||||
.X ( chanx_right_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chanx_left_in[2] ) ,
|
||||
.X ( chanx_right_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chanx_left_in[3] ) ,
|
||||
.X ( chanx_right_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chanx_left_in[4] ) ,
|
||||
.X ( chanx_right_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chanx_left_in[5] ) ,
|
||||
.X ( chanx_right_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chanx_left_in[6] ) ,
|
||||
.X ( chanx_right_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chanx_left_in[7] ) ,
|
||||
.X ( chanx_right_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chanx_left_in[8] ) ,
|
||||
.X ( chanx_right_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chanx_left_in[9] ) ,
|
||||
.X ( chanx_right_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chanx_left_in[10] ) ,
|
||||
.X ( chanx_right_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chanx_left_in[11] ) ,
|
||||
.X ( chanx_right_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chanx_left_in[12] ) ,
|
||||
.X ( chanx_right_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chanx_left_in[13] ) ,
|
||||
.X ( chanx_right_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chanx_left_in[14] ) ,
|
||||
.X ( chanx_right_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chanx_left_in[15] ) ,
|
||||
.X ( chanx_right_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chanx_left_in[16] ) ,
|
||||
.X ( chanx_right_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_left_in[17] ) ,
|
||||
.X ( chanx_right_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_left_in[18] ) ,
|
||||
.X ( chanx_right_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_left_in[19] ) ,
|
||||
.X ( chanx_right_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_left_in[20] ) ,
|
||||
.X ( chanx_right_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_left_in[21] ) ,
|
||||
.X ( chanx_right_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_left_in[22] ) ,
|
||||
.X ( chanx_right_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_left_in[23] ) ,
|
||||
.X ( chanx_right_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_left_in[24] ) ,
|
||||
.X ( chanx_right_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_left_in[25] ) ,
|
||||
.X ( chanx_right_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_left_in[26] ) ,
|
||||
.X ( chanx_right_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_left_in[27] ) ,
|
||||
.X ( chanx_right_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_left_in[28] ) ,
|
||||
.X ( chanx_right_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_left_in[29] ) ,
|
||||
.X ( chanx_right_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) ,
|
||||
.X ( chanx_left_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) ,
|
||||
.X ( chanx_left_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) ,
|
||||
.X ( chanx_left_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) ,
|
||||
.X ( chanx_left_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[4] ) ,
|
||||
.X ( chanx_left_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[5] ) ,
|
||||
.X ( chanx_left_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[6] ) ,
|
||||
.X ( chanx_left_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[7] ) ,
|
||||
.X ( chanx_left_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[8] ) ,
|
||||
.X ( chanx_left_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[9] ) ,
|
||||
.X ( chanx_left_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[10] ) ,
|
||||
.X ( chanx_left_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[11] ) ,
|
||||
.X ( chanx_left_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[12] ) ,
|
||||
.X ( chanx_left_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[13] ) ,
|
||||
.X ( chanx_left_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[14] ) ,
|
||||
.X ( chanx_left_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[15] ) ,
|
||||
.X ( chanx_left_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[16] ) ,
|
||||
.X ( chanx_left_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[17] ) ,
|
||||
.X ( chanx_left_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[18] ) ,
|
||||
.X ( chanx_left_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[19] ) ,
|
||||
.X ( chanx_left_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[20] ) ,
|
||||
.X ( chanx_left_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[21] ) ,
|
||||
.X ( chanx_left_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_right_in[22] ) ,
|
||||
.X ( chanx_left_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_right_in[23] ) ,
|
||||
.X ( chanx_left_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_right_in[24] ) ,
|
||||
.X ( chanx_left_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_right_in[25] ) ,
|
||||
.X ( chanx_left_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_right_in[26] ) ,
|
||||
.X ( chanx_left_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_right_in[27] ) ,
|
||||
.X ( chanx_left_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_right_in[28] ) ,
|
||||
.X ( chanx_left_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_right_in[29] ) ,
|
||||
.X ( chanx_left_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_79__78 (
|
||||
.A ( bottom_width_0_height_0__pin_1_lower[0] ) ,
|
||||
.X ( bottom_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_80__79 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_81__80 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_TOP ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
|
||||
.HI ( optlc_net_101 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
|
||||
.HI ( optlc_net_102 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_108 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) ,
|
||||
.HI ( optlc_net_103 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_110 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) ,
|
||||
.HI ( optlc_net_104 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_112 ( .LO ( SYNOPSYS_UNCONNECTED_73 ) ,
|
||||
.HI ( optlc_net_105 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_74 ) ,
|
||||
.HI ( optlc_net_106 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 cts_buf_3531241 ( .A ( ctsbuf_net_1107 ) ,
|
||||
.X ( prog_clk_0_W_out ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,441 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
|
||||
prog_clk , ccff_head , ccff_tail , mem_out ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] ccff_tail ;
|
||||
output [0:0] mem_out ;
|
||||
|
||||
wire copt_net_74 ;
|
||||
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) ,
|
||||
.X ( copt_net_73 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) ,
|
||||
.X ( mem_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) ,
|
||||
.X ( copt_net_75 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) ,
|
||||
.X ( copt_net_76 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) ,
|
||||
.X ( copt_net_77 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) ,
|
||||
.X ( copt_net_78 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
|
||||
FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
|
||||
input SOC_IN ;
|
||||
output SOC_OUT ;
|
||||
output SOC_DIR ;
|
||||
output FPGA_IN ;
|
||||
input FPGA_OUT ;
|
||||
input FPGA_DIR ;
|
||||
input IO_ISOL_N ;
|
||||
|
||||
sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
|
||||
.B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) ,
|
||||
.Y ( SOC_DIR_N ) ) ;
|
||||
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
|
||||
.TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
|
||||
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
|
||||
.TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ;
|
||||
sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) ,
|
||||
.Y ( BUF_net_65 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
|
||||
prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
|
||||
iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] iopad_outpad ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] iopad_inpad ;
|
||||
output [0:0] ccff_tail ;
|
||||
|
||||
wire [0:0] EMBEDDED_IO_HD_0_en ;
|
||||
|
||||
cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
|
||||
.SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
|
||||
.SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
|
||||
.SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
|
||||
.FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
|
||||
.FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
|
||||
cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
|
||||
ccff_tail ) ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] io_outpad ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] io_inpad ;
|
||||
output [0:0] ccff_tail ;
|
||||
|
||||
cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
|
||||
.iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
|
||||
.iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
|
||||
ccff_tail , mem_out ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] ccff_tail ;
|
||||
output [0:3] mem_out ;
|
||||
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) ,
|
||||
.X ( copt_net_67 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) ,
|
||||
.X ( copt_net_68 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) ,
|
||||
.X ( copt_net_69 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) ,
|
||||
.X ( copt_net_70 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) ,
|
||||
.X ( copt_net_71 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) ,
|
||||
.X ( copt_net_72 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__const1 ( const1 ) ;
|
||||
output [0:0] const1 ;
|
||||
|
||||
wire [0:0] const1_0 ;
|
||||
|
||||
assign const1_0[0] = 1'b1 ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
|
||||
input [0:11] in ;
|
||||
input [0:3] sram ;
|
||||
input [0:3] sram_inv ;
|
||||
output [0:0] out ;
|
||||
input p0 ;
|
||||
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
|
||||
|
||||
cby_0__1__const1 const1_0_ (
|
||||
.const1 ( { SYNOPSYS_UNCONNECTED_1 } ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
|
||||
.A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
|
||||
.S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
|
||||
chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail ,
|
||||
IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
|
||||
right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper ,
|
||||
right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_bottom_in ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_bottom_out ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:0] left_grid_pin_0_ ;
|
||||
output [0:0] ccff_tail ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] right_width_0_height_0__pin_0_ ;
|
||||
output [0:0] right_width_0_height_0__pin_1_upper ;
|
||||
output [0:0] right_width_0_height_0__pin_1_lower ;
|
||||
input pReset_N_in ;
|
||||
input prog_clk_0_E_in ;
|
||||
|
||||
wire ropt_net_120 ;
|
||||
wire ropt_net_118 ;
|
||||
wire ropt_net_136 ;
|
||||
wire ropt_net_117 ;
|
||||
wire ropt_net_121 ;
|
||||
wire ropt_net_125 ;
|
||||
wire ropt_net_124 ;
|
||||
wire ropt_net_122 ;
|
||||
wire ropt_net_115 ;
|
||||
wire ropt_net_116 ;
|
||||
wire ropt_net_126 ;
|
||||
wire ropt_net_119 ;
|
||||
wire ropt_net_123 ;
|
||||
wire ropt_net_114 ;
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
|
||||
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
|
||||
chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
|
||||
.out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ;
|
||||
cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( { ccff_tail_mid } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
|
||||
cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
|
||||
.io_outpad ( right_width_0_height_0__pin_0_ ) ,
|
||||
.ccff_head ( { ccff_tail_mid } ) ,
|
||||
.io_inpad ( right_width_0_height_0__pin_1_lower ) ,
|
||||
.ccff_tail ( ccff_tail ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( chany_top_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( ropt_net_120 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( chany_top_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( chany_top_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( ropt_net_118 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( chany_top_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( chany_top_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( ropt_net_136 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) ,
|
||||
.X ( ropt_net_117 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( chany_top_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( ropt_net_121 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) ,
|
||||
.X ( ropt_net_125 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) ,
|
||||
.X ( ropt_net_124 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) ,
|
||||
.X ( chany_top_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) ,
|
||||
.X ( chany_top_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) ,
|
||||
.X ( ropt_net_122 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) ,
|
||||
.X ( chany_top_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) ,
|
||||
.X ( chany_top_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) ,
|
||||
.X ( chany_top_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) ,
|
||||
.X ( ropt_net_115 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) ,
|
||||
.X ( chany_top_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) ,
|
||||
.X ( chany_top_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( chany_bottom_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( chany_bottom_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( chany_bottom_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( ropt_net_116 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( ropt_net_126 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) ,
|
||||
.X ( ropt_net_119 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) ,
|
||||
.X ( chany_bottom_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) ,
|
||||
.X ( ropt_net_123 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) ,
|
||||
.X ( chany_bottom_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) ,
|
||||
.X ( chany_bottom_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) ,
|
||||
.X ( chany_bottom_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) ,
|
||||
.X ( chany_bottom_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) ,
|
||||
.X ( chany_bottom_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) ,
|
||||
.X ( chany_bottom_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) ,
|
||||
.X ( chany_bottom_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) ,
|
||||
.X ( ropt_net_114 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) ,
|
||||
.X ( chany_bottom_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_63__62 (
|
||||
.A ( right_width_0_height_0__pin_1_lower[0] ) ,
|
||||
.X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
|
||||
.HI ( optlc_net_66 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) ,
|
||||
.X ( chany_bottom_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) ,
|
||||
.X ( chany_top_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) ,
|
||||
.X ( chany_bottom_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) ,
|
||||
.X ( chany_top_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) ,
|
||||
.X ( chany_bottom_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) ,
|
||||
.X ( chany_top_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) ,
|
||||
.X ( chany_bottom_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,486 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
|
||||
prog_clk , ccff_head , ccff_tail , mem_out , VDD , VSS ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] ccff_tail ;
|
||||
output [0:0] mem_out ;
|
||||
input VDD ;
|
||||
input VSS ;
|
||||
|
||||
wire copt_net_74 ;
|
||||
supply1 VDD ;
|
||||
supply0 VSS ;
|
||||
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) ,
|
||||
.X ( copt_net_73 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) ,
|
||||
.X ( mem_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) ,
|
||||
.X ( copt_net_75 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) ,
|
||||
.X ( copt_net_76 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) ,
|
||||
.X ( copt_net_77 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) ,
|
||||
.X ( copt_net_78 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
|
||||
FPGA_OUT , FPGA_DIR , IO_ISOL_N , VDD , VSS ) ;
|
||||
input SOC_IN ;
|
||||
output SOC_OUT ;
|
||||
output SOC_DIR ;
|
||||
output FPGA_IN ;
|
||||
input FPGA_OUT ;
|
||||
input FPGA_DIR ;
|
||||
input IO_ISOL_N ;
|
||||
input VDD ;
|
||||
input VSS ;
|
||||
|
||||
supply1 VDD ;
|
||||
supply0 VSS ;
|
||||
|
||||
sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
|
||||
.B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) , .VPWR ( VDD ) ,
|
||||
.VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) ,
|
||||
.Y ( SOC_DIR_N ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
|
||||
.TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
|
||||
.TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) ,
|
||||
.Y ( BUF_net_65 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
|
||||
prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
|
||||
iopad_outpad , ccff_head , iopad_inpad , ccff_tail , VDD , VSS ) ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] iopad_outpad ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] iopad_inpad ;
|
||||
output [0:0] ccff_tail ;
|
||||
input VDD ;
|
||||
input VSS ;
|
||||
|
||||
wire [0:0] EMBEDDED_IO_HD_0_en ;
|
||||
supply1 VDD ;
|
||||
supply0 VSS ;
|
||||
|
||||
cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
|
||||
.SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
|
||||
.SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
|
||||
.SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
|
||||
.FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
|
||||
.FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ,
|
||||
.VDD ( VDD ) , .VSS ( VSS ) ) ;
|
||||
cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ,
|
||||
.VDD ( VDD ) , .VSS ( VSS ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
|
||||
ccff_tail , VDD , VSS ) ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] io_outpad ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] io_inpad ;
|
||||
output [0:0] ccff_tail ;
|
||||
input VDD ;
|
||||
input VSS ;
|
||||
|
||||
supply1 VDD ;
|
||||
supply0 VSS ;
|
||||
|
||||
cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
|
||||
.iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
|
||||
.iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) , .VDD ( VDD ) ,
|
||||
.VSS ( VSS ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
|
||||
ccff_tail , mem_out , VDD , VSS ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] ccff_tail ;
|
||||
output [0:3] mem_out ;
|
||||
input VDD ;
|
||||
input VSS ;
|
||||
|
||||
supply1 VDD ;
|
||||
supply0 VSS ;
|
||||
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) ,
|
||||
.X ( copt_net_67 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) ,
|
||||
.X ( copt_net_68 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) ,
|
||||
.X ( copt_net_69 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) ,
|
||||
.X ( copt_net_70 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) ,
|
||||
.X ( copt_net_71 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) ,
|
||||
.X ( copt_net_72 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , VDD ,
|
||||
VSS , p0 ) ;
|
||||
input [0:11] in ;
|
||||
input [0:3] sram ;
|
||||
input [0:3] sram_inv ;
|
||||
output [0:0] out ;
|
||||
input VDD ;
|
||||
input VSS ;
|
||||
input p0 ;
|
||||
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
|
||||
supply1 VDD ;
|
||||
supply0 VSS ;
|
||||
|
||||
sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
|
||||
.A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) , .VPWR ( VDD ) ,
|
||||
.VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .VPWR ( VDD ) ,
|
||||
.VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) , .VPWR ( VDD ) ,
|
||||
.VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .VPWR ( VDD ) ,
|
||||
.VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) , .VPWR ( VDD ) ,
|
||||
.VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .VPWR ( VDD ) ,
|
||||
.VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
|
||||
.S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) , .VPWR ( VDD ) ,
|
||||
.VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
|
||||
chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail ,
|
||||
IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
|
||||
right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper ,
|
||||
right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ,
|
||||
VDD , VSS ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_bottom_in ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_bottom_out ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:0] left_grid_pin_0_ ;
|
||||
output [0:0] ccff_tail ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] right_width_0_height_0__pin_0_ ;
|
||||
output [0:0] right_width_0_height_0__pin_1_upper ;
|
||||
output [0:0] right_width_0_height_0__pin_1_lower ;
|
||||
input pReset_N_in ;
|
||||
input prog_clk_0_E_in ;
|
||||
input VDD ;
|
||||
input VSS ;
|
||||
|
||||
wire ropt_net_120 ;
|
||||
wire ropt_net_118 ;
|
||||
wire ropt_net_136 ;
|
||||
wire ropt_net_117 ;
|
||||
wire ropt_net_121 ;
|
||||
wire ropt_net_125 ;
|
||||
wire ropt_net_124 ;
|
||||
wire ropt_net_122 ;
|
||||
wire ropt_net_115 ;
|
||||
wire ropt_net_116 ;
|
||||
wire ropt_net_126 ;
|
||||
wire ropt_net_119 ;
|
||||
wire ropt_net_123 ;
|
||||
wire ropt_net_114 ;
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
|
||||
supply1 VDD ;
|
||||
supply0 VSS ;
|
||||
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
|
||||
chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
|
||||
.out ( left_grid_pin_0_ ) , .VDD ( VDD ) , .VSS ( VSS ) ,
|
||||
.p0 ( optlc_net_66 ) ) ;
|
||||
cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( { ccff_tail_mid } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_0_sram ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
|
||||
cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
|
||||
.io_outpad ( right_width_0_height_0__pin_0_ ) ,
|
||||
.ccff_head ( { ccff_tail_mid } ) ,
|
||||
.io_inpad ( right_width_0_height_0__pin_1_lower ) ,
|
||||
.ccff_tail ( ccff_tail ) , .VDD ( VDD ) , .VSS ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ,
|
||||
.VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
|
||||
.X ( prog_clk[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( chany_top_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( chany_top_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( ropt_net_120 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( chany_top_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( chany_top_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( ropt_net_118 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( chany_top_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( chany_top_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( ropt_net_136 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( chany_top_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) ,
|
||||
.X ( chany_top_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) ,
|
||||
.X ( chany_top_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( chany_top_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) ,
|
||||
.X ( ropt_net_117 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( chany_top_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( ropt_net_121 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) ,
|
||||
.X ( ropt_net_125 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( chany_top_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) ,
|
||||
.X ( chany_top_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( chany_top_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) ,
|
||||
.X ( ropt_net_124 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) ,
|
||||
.X ( chany_top_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) ,
|
||||
.X ( chany_top_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) ,
|
||||
.X ( ropt_net_122 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) ,
|
||||
.X ( chany_top_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) ,
|
||||
.X ( chany_top_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) ,
|
||||
.X ( chany_top_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) ,
|
||||
.X ( ropt_net_115 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) ,
|
||||
.X ( chany_top_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) ,
|
||||
.X ( chany_top_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( chany_bottom_out[0] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( chany_bottom_out[1] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( chany_bottom_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( chany_bottom_out[3] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( chany_bottom_out[4] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( chany_bottom_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( chany_bottom_out[6] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( chany_bottom_out[7] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( chany_bottom_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( chany_bottom_out[10] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( chany_bottom_out[11] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( chany_bottom_out[12] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( ropt_net_116 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( ropt_net_126 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( chany_bottom_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( chany_bottom_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) ,
|
||||
.X ( ropt_net_119 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) ,
|
||||
.X ( chany_bottom_out[18] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( chany_bottom_out[19] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) ,
|
||||
.X ( ropt_net_123 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) ,
|
||||
.X ( chany_bottom_out[21] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) ,
|
||||
.X ( chany_bottom_out[22] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) ,
|
||||
.X ( chany_bottom_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) ,
|
||||
.X ( chany_bottom_out[24] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) ,
|
||||
.X ( chany_bottom_out[25] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) ,
|
||||
.X ( chany_bottom_out[26] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) ,
|
||||
.X ( chany_bottom_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) ,
|
||||
.X ( ropt_net_114 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) ,
|
||||
.X ( chany_bottom_out[29] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_63__62 (
|
||||
.A ( right_width_0_height_0__pin_1_lower[0] ) ,
|
||||
.X ( right_width_0_height_0__pin_1_upper[0] ) , .VPWR ( VDD ) ,
|
||||
.VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
|
||||
.HI ( optlc_net_66 ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) ,
|
||||
.X ( chany_bottom_out[28] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) ,
|
||||
.X ( chany_top_out[27] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) ,
|
||||
.X ( chany_bottom_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) ,
|
||||
.X ( chany_top_out[13] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) ,
|
||||
.X ( chany_top_out[5] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) ,
|
||||
.X ( chany_bottom_out[17] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) ,
|
||||
.X ( chany_top_out[2] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) ,
|
||||
.X ( chany_top_out[15] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) ,
|
||||
.X ( chany_top_out[23] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) ,
|
||||
.X ( chany_bottom_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) ,
|
||||
.X ( chany_top_out[20] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) ,
|
||||
.X ( chany_top_out[16] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) ,
|
||||
.X ( chany_bottom_out[14] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) ,
|
||||
.X ( chany_top_out[8] ) , .VPWR ( VDD ) , .VGND ( VSS ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,430 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem ( pReset ,
|
||||
prog_clk , ccff_head , ccff_tail , mem_out ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] ccff_tail ;
|
||||
output [0:0] mem_out ;
|
||||
|
||||
wire copt_net_74 ;
|
||||
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( ccff_head[0] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( copt_net_74 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_2__1 ( .A ( mem_out[0] ) , .X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1217 ( .A ( copt_net_75 ) ,
|
||||
.X ( copt_net_73 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1218 ( .A ( copt_net_78 ) ,
|
||||
.X ( mem_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1219 ( .A ( copt_net_74 ) ,
|
||||
.X ( copt_net_75 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1220 ( .A ( copt_net_73 ) ,
|
||||
.X ( copt_net_76 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1221 ( .A ( copt_net_76 ) ,
|
||||
.X ( copt_net_77 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1222 ( .A ( copt_net_77 ) ,
|
||||
.X ( copt_net_78 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__EMBEDDED_IO_HD ( SOC_IN , SOC_OUT , SOC_DIR , FPGA_IN ,
|
||||
FPGA_OUT , FPGA_DIR , IO_ISOL_N ) ;
|
||||
input SOC_IN ;
|
||||
output SOC_OUT ;
|
||||
output SOC_DIR ;
|
||||
output FPGA_IN ;
|
||||
input FPGA_OUT ;
|
||||
input FPGA_DIR ;
|
||||
input IO_ISOL_N ;
|
||||
|
||||
sky130_fd_sc_hd__nand2b_1 ISOL_EN_GATE ( .A_N ( FPGA_DIR ) ,
|
||||
.B ( IO_ISOL_N ) , .Y ( aps_rename_505_ ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 INV_SOC_DIR ( .A ( aps_rename_505_ ) ,
|
||||
.Y ( SOC_DIR_N ) ) ;
|
||||
sky130_fd_sc_hd__ebufn_4 IN_PROTECT_GATE ( .A ( SOC_IN ) ,
|
||||
.TE_B ( SOC_DIR_N ) , .Z ( FPGA_IN ) ) ;
|
||||
sky130_fd_sc_hd__ebufn_4 OUT_PROTECT_GATE ( .A ( FPGA_OUT ) ,
|
||||
.TE_B ( BUF_net_63 ) , .Z ( SOC_OUT ) ) ;
|
||||
sky130_fd_sc_hd__inv_4 BINV_R_63 ( .A ( BUF_net_65 ) , .Y ( BUF_net_63 ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_64 ( .A ( BUF_net_65 ) , .Y ( SOC_DIR ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_65 ( .A ( aps_rename_505_ ) ,
|
||||
.Y ( BUF_net_65 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__logical_tile_io_mode_physical__iopad ( IO_ISOL_N , pReset ,
|
||||
prog_clk , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
|
||||
iopad_outpad , ccff_head , iopad_inpad , ccff_tail ) ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] iopad_outpad ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] iopad_inpad ;
|
||||
output [0:0] ccff_tail ;
|
||||
|
||||
wire [0:0] EMBEDDED_IO_HD_0_en ;
|
||||
|
||||
cby_0__1__EMBEDDED_IO_HD EMBEDDED_IO_HD_0_ (
|
||||
.SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN[0] ) ,
|
||||
.SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT[0] ) ,
|
||||
.SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR[0] ) ,
|
||||
.FPGA_IN ( iopad_inpad[0] ) , .FPGA_OUT ( iopad_outpad[0] ) ,
|
||||
.FPGA_DIR ( EMBEDDED_IO_HD_0_en[0] ) , .IO_ISOL_N ( IO_ISOL_N[0] ) ) ;
|
||||
cby_0__1__EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem EMBEDDED_IO_HD_sky130_fd_sc_hd__dfrtp_1_mem (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( EMBEDDED_IO_HD_0_en ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__logical_tile_io_mode_io_ ( IO_ISOL_N , pReset , prog_clk ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_IN , gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_DIR , io_outpad , ccff_head , io_inpad ,
|
||||
ccff_tail ) ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] io_outpad ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] io_inpad ;
|
||||
output [0:0] ccff_tail ;
|
||||
|
||||
cby_0__1__logical_tile_io_mode_physical__iopad logical_tile_io_mode_physical__iopad_0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
|
||||
.iopad_outpad ( io_outpad ) , .ccff_head ( ccff_head ) ,
|
||||
.iopad_inpad ( io_inpad ) , .ccff_tail ( ccff_tail ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__mux_tree_tapbuf_size12_mem ( pReset , prog_clk , ccff_head ,
|
||||
ccff_tail , mem_out ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:0] prog_clk ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:0] ccff_tail ;
|
||||
output [0:3] mem_out ;
|
||||
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_0_ ( .D ( copt_net_71 ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_1_ ( .D ( mem_out[0] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_2_ ( .D ( mem_out[1] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__dfrtp_1 sky130_fd_sc_hd__dfrtp_1_3_ ( .D ( mem_out[2] ) ,
|
||||
.CLK ( prog_clk[0] ) , .RESET_B ( pReset[0] ) , .Q ( mem_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 FTB_1__0 ( .A ( mem_out[3] ) , .X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1211 ( .A ( ccff_head[0] ) ,
|
||||
.X ( copt_net_67 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1212 ( .A ( copt_net_67 ) ,
|
||||
.X ( copt_net_68 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1213 ( .A ( copt_net_68 ) ,
|
||||
.X ( copt_net_69 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1214 ( .A ( copt_net_69 ) ,
|
||||
.X ( copt_net_70 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1215 ( .A ( copt_net_72 ) ,
|
||||
.X ( copt_net_71 ) ) ;
|
||||
sky130_fd_sc_hd__dlygate4sd3_1 copt_h_inst_1216 ( .A ( copt_net_70 ) ,
|
||||
.X ( copt_net_72 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1__mux_tree_tapbuf_size12 ( in , sram , sram_inv , out , p0 ) ;
|
||||
input [0:11] in ;
|
||||
input [0:3] sram ;
|
||||
input [0:3] sram_inv ;
|
||||
output [0:0] out ;
|
||||
input p0 ;
|
||||
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_0_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_10_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_11_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_1_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_2_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_3_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_4_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_5_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_6_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_7_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_8_X ;
|
||||
wire [0:0] sky130_fd_sc_hd__mux2_1_9_X ;
|
||||
|
||||
sky130_fd_sc_hd__buf_6 sky130_fd_sc_hd__buf_4_0_ (
|
||||
.A ( sky130_fd_sc_hd__mux2_1_11_X[0] ) , .X ( out[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_0_ ( .A0 ( in[1] ) , .A1 ( in[0] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_0_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_1_ ( .A0 ( in[3] ) , .A1 ( in[2] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_2_ ( .A0 ( in[5] ) , .A1 ( in[4] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_2_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_3_ ( .A0 ( in[7] ) , .A1 ( in[6] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l1_in_4_ ( .A0 ( in[9] ) , .A1 ( in[8] ) ,
|
||||
.S ( sram[0] ) , .X ( sky130_fd_sc_hd__mux2_1_4_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_0_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_1_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_0_X[0] ) , .S ( sram[1] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_5_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_1_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_3_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_2_X[0] ) , .S ( sram[1] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_2_ ( .A0 ( in[10] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_4_X[0] ) , .S ( sram[1] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_7_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l2_in_3_ ( .A0 ( p0 ) , .A1 ( in[11] ) ,
|
||||
.S ( sram[1] ) , .X ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l3_in_0_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_6_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_5_X[0] ) , .S ( sram[2] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_9_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l3_in_1_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_8_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_7_X[0] ) , .S ( sram[2] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ) ;
|
||||
sky130_fd_sc_hd__mux2_1 mux_l4_in_0_ (
|
||||
.A0 ( sky130_fd_sc_hd__mux2_1_10_X[0] ) ,
|
||||
.A1 ( sky130_fd_sc_hd__mux2_1_9_X[0] ) , .S ( sram[3] ) ,
|
||||
.X ( sky130_fd_sc_hd__mux2_1_11_X[0] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
|
||||
chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail ,
|
||||
IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
|
||||
right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper ,
|
||||
right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_bottom_in ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_bottom_out ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:0] left_grid_pin_0_ ;
|
||||
output [0:0] ccff_tail ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] right_width_0_height_0__pin_0_ ;
|
||||
output [0:0] right_width_0_height_0__pin_1_upper ;
|
||||
output [0:0] right_width_0_height_0__pin_1_lower ;
|
||||
input pReset_N_in ;
|
||||
input prog_clk_0_E_in ;
|
||||
|
||||
wire ropt_net_120 ;
|
||||
wire ropt_net_118 ;
|
||||
wire ropt_net_136 ;
|
||||
wire ropt_net_117 ;
|
||||
wire ropt_net_121 ;
|
||||
wire ropt_net_125 ;
|
||||
wire ropt_net_124 ;
|
||||
wire ropt_net_122 ;
|
||||
wire ropt_net_115 ;
|
||||
wire ropt_net_116 ;
|
||||
wire ropt_net_126 ;
|
||||
wire ropt_net_119 ;
|
||||
wire ropt_net_123 ;
|
||||
wire ropt_net_114 ;
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
|
||||
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
|
||||
chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
|
||||
.out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ;
|
||||
cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( { ccff_tail_mid } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
|
||||
cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
|
||||
.io_outpad ( right_width_0_height_0__pin_0_ ) ,
|
||||
.ccff_head ( { ccff_tail_mid } ) ,
|
||||
.io_inpad ( right_width_0_height_0__pin_1_lower ) ,
|
||||
.ccff_tail ( ccff_tail ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( chany_top_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( ropt_net_120 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( chany_top_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( chany_top_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( ropt_net_118 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( chany_top_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( chany_top_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( ropt_net_136 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) ,
|
||||
.X ( ropt_net_117 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( chany_top_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( ropt_net_121 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) ,
|
||||
.X ( ropt_net_125 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) ,
|
||||
.X ( ropt_net_124 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) ,
|
||||
.X ( chany_top_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) ,
|
||||
.X ( chany_top_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) ,
|
||||
.X ( ropt_net_122 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) ,
|
||||
.X ( chany_top_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) ,
|
||||
.X ( chany_top_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) ,
|
||||
.X ( chany_top_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) ,
|
||||
.X ( ropt_net_115 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) ,
|
||||
.X ( chany_top_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) ,
|
||||
.X ( chany_top_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( chany_bottom_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( chany_bottom_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( chany_bottom_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( ropt_net_116 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( ropt_net_126 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) ,
|
||||
.X ( ropt_net_119 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) ,
|
||||
.X ( chany_bottom_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) ,
|
||||
.X ( ropt_net_123 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) ,
|
||||
.X ( chany_bottom_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) ,
|
||||
.X ( chany_bottom_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) ,
|
||||
.X ( chany_bottom_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) ,
|
||||
.X ( chany_bottom_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) ,
|
||||
.X ( chany_bottom_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) ,
|
||||
.X ( chany_bottom_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) ,
|
||||
.X ( chany_bottom_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) ,
|
||||
.X ( ropt_net_114 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) ,
|
||||
.X ( chany_bottom_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_63__62 (
|
||||
.A ( right_width_0_height_0__pin_1_lower[0] ) ,
|
||||
.X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
|
||||
.HI ( optlc_net_66 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) ,
|
||||
.X ( chany_bottom_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) ,
|
||||
.X ( chany_top_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) ,
|
||||
.X ( chany_bottom_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) ,
|
||||
.X ( chany_top_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) ,
|
||||
.X ( chany_bottom_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) ,
|
||||
.X ( chany_top_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) ,
|
||||
.X ( chany_bottom_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module cby_0__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
|
||||
chany_bottom_out , chany_top_out , left_grid_pin_0_ , ccff_tail ,
|
||||
IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
|
||||
right_width_0_height_0__pin_0_ , right_width_0_height_0__pin_1_upper ,
|
||||
right_width_0_height_0__pin_1_lower , pReset_N_in , prog_clk_0_E_in ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_bottom_in ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_bottom_out ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:0] left_grid_pin_0_ ;
|
||||
output [0:0] ccff_tail ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] right_width_0_height_0__pin_0_ ;
|
||||
output [0:0] right_width_0_height_0__pin_1_upper ;
|
||||
output [0:0] right_width_0_height_0__pin_1_lower ;
|
||||
input pReset_N_in ;
|
||||
input prog_clk_0_E_in ;
|
||||
|
||||
wire ropt_net_120 ;
|
||||
wire ropt_net_118 ;
|
||||
wire ropt_net_136 ;
|
||||
wire ropt_net_117 ;
|
||||
wire ropt_net_121 ;
|
||||
wire ropt_net_125 ;
|
||||
wire ropt_net_124 ;
|
||||
wire ropt_net_122 ;
|
||||
wire ropt_net_115 ;
|
||||
wire ropt_net_116 ;
|
||||
wire ropt_net_126 ;
|
||||
wire ropt_net_119 ;
|
||||
wire ropt_net_123 ;
|
||||
wire ropt_net_114 ;
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
|
||||
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
cby_0__1__mux_tree_tapbuf_size12 mux_right_ipin_0 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
|
||||
chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
|
||||
.out ( left_grid_pin_0_ ) , .p0 ( optlc_net_66 ) ) ;
|
||||
cby_0__1__mux_tree_tapbuf_size12_mem mem_right_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( { ccff_tail_mid } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
|
||||
cby_0__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
|
||||
.io_outpad ( right_width_0_height_0__pin_0_ ) ,
|
||||
.ccff_head ( { ccff_tail_mid } ) ,
|
||||
.io_inpad ( right_width_0_height_0__pin_1_lower ) ,
|
||||
.ccff_tail ( ccff_tail ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 pReset_FTB00 ( .A ( pReset_N_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_3__2 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( chany_top_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_4__3 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_5__4 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( ropt_net_120 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_6__5 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( chany_top_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_7__6 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( chany_top_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_8__7 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( ropt_net_118 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_9__8 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( chany_top_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_10__9 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( chany_top_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_11__10 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( ropt_net_136 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_12__11 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_13__12 ( .A ( chany_bottom_in[10] ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_14__13 ( .A ( chany_bottom_in[11] ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_15__14 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_16__15 ( .A ( chany_bottom_in[13] ) ,
|
||||
.X ( ropt_net_117 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( chany_top_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_18__17 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( ropt_net_121 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_19__18 ( .A ( chany_bottom_in[16] ) ,
|
||||
.X ( ropt_net_125 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_20__19 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[18] ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_22__21 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_23__22 ( .A ( chany_bottom_in[20] ) ,
|
||||
.X ( ropt_net_124 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[21] ) ,
|
||||
.X ( chany_top_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[22] ) ,
|
||||
.X ( chany_top_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_26__25 ( .A ( chany_bottom_in[23] ) ,
|
||||
.X ( ropt_net_122 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[24] ) ,
|
||||
.X ( chany_top_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[25] ) ,
|
||||
.X ( chany_top_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_29__28 ( .A ( chany_bottom_in[26] ) ,
|
||||
.X ( chany_top_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_30__29 ( .A ( chany_bottom_in[27] ) ,
|
||||
.X ( ropt_net_115 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[28] ) ,
|
||||
.X ( chany_top_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_32__31 ( .A ( chany_bottom_in[29] ) ,
|
||||
.X ( chany_top_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( chany_bottom_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_34__33 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( chany_bottom_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( chany_bottom_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_44__43 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( ropt_net_116 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( ropt_net_126 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_50__49 ( .A ( chany_top_in[17] ) ,
|
||||
.X ( ropt_net_119 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[18] ) ,
|
||||
.X ( chany_bottom_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_52__51 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_53__52 ( .A ( chany_top_in[20] ) ,
|
||||
.X ( ropt_net_123 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[21] ) ,
|
||||
.X ( chany_bottom_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_55__54 ( .A ( chany_top_in[22] ) ,
|
||||
.X ( chany_bottom_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[23] ) ,
|
||||
.X ( chany_bottom_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[24] ) ,
|
||||
.X ( chany_bottom_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[25] ) ,
|
||||
.X ( chany_bottom_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chany_top_in[26] ) ,
|
||||
.X ( chany_bottom_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[27] ) ,
|
||||
.X ( chany_bottom_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( chany_top_in[28] ) ,
|
||||
.X ( ropt_net_114 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[29] ) ,
|
||||
.X ( chany_bottom_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_63__62 (
|
||||
.A ( right_width_0_height_0__pin_1_lower[0] ) ,
|
||||
.X ( right_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_67 ( .LO ( SYNOPSYS_UNCONNECTED_5 ) ,
|
||||
.HI ( optlc_net_66 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1258 ( .A ( ropt_net_114 ) ,
|
||||
.X ( chany_bottom_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1259 ( .A ( ropt_net_115 ) ,
|
||||
.X ( chany_top_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1260 ( .A ( ropt_net_116 ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1261 ( .A ( ropt_net_117 ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1262 ( .A ( ropt_net_118 ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1263 ( .A ( ropt_net_119 ) ,
|
||||
.X ( chany_bottom_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1264 ( .A ( ropt_net_120 ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1265 ( .A ( ropt_net_121 ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1266 ( .A ( ropt_net_122 ) ,
|
||||
.X ( chany_top_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1267 ( .A ( ropt_net_123 ) ,
|
||||
.X ( chany_bottom_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1268 ( .A ( ropt_net_124 ) ,
|
||||
.X ( chany_top_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1269 ( .A ( ropt_net_125 ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1270 ( .A ( ropt_net_126 ) ,
|
||||
.X ( chany_bottom_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1280 ( .A ( ropt_net_136 ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,538 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module cby_1__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
|
||||
chany_bottom_out , chany_top_out , left_grid_pin_16_ , left_grid_pin_17_ ,
|
||||
left_grid_pin_18_ , left_grid_pin_19_ , left_grid_pin_20_ ,
|
||||
left_grid_pin_21_ , left_grid_pin_22_ , left_grid_pin_23_ ,
|
||||
left_grid_pin_24_ , left_grid_pin_25_ , left_grid_pin_26_ ,
|
||||
left_grid_pin_27_ , left_grid_pin_28_ , left_grid_pin_29_ ,
|
||||
left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail , Test_en_S_in ,
|
||||
Test_en_E_in , Test_en_W_in , Test_en_N_out , Test_en_W_out ,
|
||||
Test_en_E_out , pReset_S_in , pReset_N_out , Reset_S_in , Reset_E_in ,
|
||||
Reset_W_in , Reset_N_out , Reset_W_out , Reset_E_out , prog_clk_0_W_in ,
|
||||
prog_clk_0_S_out , prog_clk_0_N_out , prog_clk_2_N_in , prog_clk_2_S_in ,
|
||||
prog_clk_2_S_out , prog_clk_2_N_out , prog_clk_3_S_in , prog_clk_3_N_in ,
|
||||
prog_clk_3_N_out , prog_clk_3_S_out , clk_2_N_in , clk_2_S_in ,
|
||||
clk_2_S_out , clk_2_N_out , clk_3_S_in , clk_3_N_in , clk_3_N_out ,
|
||||
clk_3_S_out ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_bottom_in ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_bottom_out ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:0] left_grid_pin_16_ ;
|
||||
output [0:0] left_grid_pin_17_ ;
|
||||
output [0:0] left_grid_pin_18_ ;
|
||||
output [0:0] left_grid_pin_19_ ;
|
||||
output [0:0] left_grid_pin_20_ ;
|
||||
output [0:0] left_grid_pin_21_ ;
|
||||
output [0:0] left_grid_pin_22_ ;
|
||||
output [0:0] left_grid_pin_23_ ;
|
||||
output [0:0] left_grid_pin_24_ ;
|
||||
output [0:0] left_grid_pin_25_ ;
|
||||
output [0:0] left_grid_pin_26_ ;
|
||||
output [0:0] left_grid_pin_27_ ;
|
||||
output [0:0] left_grid_pin_28_ ;
|
||||
output [0:0] left_grid_pin_29_ ;
|
||||
output [0:0] left_grid_pin_30_ ;
|
||||
output [0:0] left_grid_pin_31_ ;
|
||||
output [0:0] ccff_tail ;
|
||||
input Test_en_S_in ;
|
||||
input Test_en_E_in ;
|
||||
input Test_en_W_in ;
|
||||
output Test_en_N_out ;
|
||||
output Test_en_W_out ;
|
||||
output Test_en_E_out ;
|
||||
input pReset_S_in ;
|
||||
output pReset_N_out ;
|
||||
input Reset_S_in ;
|
||||
input Reset_E_in ;
|
||||
input Reset_W_in ;
|
||||
output Reset_N_out ;
|
||||
output Reset_W_out ;
|
||||
output Reset_E_out ;
|
||||
input prog_clk_0_W_in ;
|
||||
output prog_clk_0_S_out ;
|
||||
output prog_clk_0_N_out ;
|
||||
input prog_clk_2_N_in ;
|
||||
input prog_clk_2_S_in ;
|
||||
output prog_clk_2_S_out ;
|
||||
output prog_clk_2_N_out ;
|
||||
input prog_clk_3_S_in ;
|
||||
input prog_clk_3_N_in ;
|
||||
output prog_clk_3_N_out ;
|
||||
output prog_clk_3_S_out ;
|
||||
input clk_2_N_in ;
|
||||
input clk_2_S_in ;
|
||||
output clk_2_S_out ;
|
||||
output clk_2_N_out ;
|
||||
input clk_3_S_in ;
|
||||
input clk_3_N_in ;
|
||||
output clk_3_N_out ;
|
||||
output clk_3_S_out ;
|
||||
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_2_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_3_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_4_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_5_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_6_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_7_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
|
||||
|
||||
assign Test_en_E_in = Test_en_S_in ;
|
||||
assign Test_en_E_in = Test_en_W_in ;
|
||||
assign Reset_E_in = Reset_S_in ;
|
||||
assign Reset_E_in = Reset_W_in ;
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
assign prog_clk_2_S_in = prog_clk_2_N_in ;
|
||||
assign prog_clk_3_N_in = prog_clk_3_S_in ;
|
||||
assign clk_2_S_in = clk_2_N_in ;
|
||||
assign clk_3_N_in = clk_3_S_in ;
|
||||
|
||||
cby_1__1__mux_tree_tapbuf_size12_0 mux_right_ipin_0 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
|
||||
chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
|
||||
.out ( left_grid_pin_16_ ) , .p0 ( optlc_net_108 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_1 mux_right_ipin_2 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
|
||||
chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] ,
|
||||
chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
|
||||
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
|
||||
.out ( left_grid_pin_18_ ) , .p0 ( optlc_net_107 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_2 mux_right_ipin_4 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
|
||||
chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] ,
|
||||
chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
|
||||
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( left_grid_pin_20_ ) , .p0 ( optlc_net_105 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_3 mux_right_ipin_6 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
|
||||
chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
|
||||
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
|
||||
.out ( left_grid_pin_22_ ) , .p0 ( optlc_net_108 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_4 mux_right_ipin_8 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
|
||||
chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] ,
|
||||
chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
|
||||
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
|
||||
.out ( left_grid_pin_24_ ) , .p0 ( optlc_net_107 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_5 mux_right_ipin_10 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
|
||||
chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] ,
|
||||
chany_bottom_out[22] , chany_top_out[28] , chany_bottom_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
|
||||
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( left_grid_pin_26_ ) , .p0 ( optlc_net_108 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_6 mux_right_ipin_12 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
|
||||
chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
|
||||
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
|
||||
.out ( left_grid_pin_28_ ) , .p0 ( optlc_net_106 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12 mux_right_ipin_14 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
|
||||
chany_top_out[14] , chany_bottom_out[14] , chany_top_out[20] ,
|
||||
chany_bottom_out[20] , chany_top_out[26] , chany_bottom_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
|
||||
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
|
||||
.out ( left_grid_pin_30_ ) , .p0 ( optlc_net_107 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_mem_0 mem_right_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_10 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_12 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
|
||||
chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] ,
|
||||
chany_bottom_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
|
||||
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( left_grid_pin_17_ ) , .p0 ( optlc_net_106 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
|
||||
chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] ,
|
||||
chany_bottom_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
|
||||
SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
|
||||
.out ( left_grid_pin_19_ ) , .p0 ( optlc_net_108 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
|
||||
chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] ,
|
||||
chany_bottom_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
|
||||
SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
|
||||
.out ( left_grid_pin_21_ ) , .p0 ( optlc_net_108 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
|
||||
chany_top_out[13] , chany_bottom_out[13] , chany_top_out[22] ,
|
||||
chany_bottom_out[22] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
|
||||
SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
|
||||
.out ( left_grid_pin_23_ ) , .p0 ( optlc_net_105 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
|
||||
chany_top_out[15] , chany_bottom_out[15] , chany_top_out[24] ,
|
||||
chany_bottom_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
|
||||
SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
|
||||
.out ( left_grid_pin_25_ ) , .p0 ( optlc_net_105 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
|
||||
chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] ,
|
||||
chany_bottom_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
|
||||
SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
|
||||
.out ( left_grid_pin_27_ ) , .p0 ( optlc_net_105 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[13] , chany_bottom_out[13] ,
|
||||
chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] ,
|
||||
chany_bottom_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
|
||||
SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
|
||||
.out ( left_grid_pin_29_ ) , .p0 ( optlc_net_106 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
|
||||
chany_bottom_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
|
||||
SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
|
||||
.out ( left_grid_pin_31_ ) , .p0 ( optlc_net_106 ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
|
||||
cby_1__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 Test_en_N_FTB01 ( .A ( Test_en_E_in ) ,
|
||||
.X ( aps_rename_505_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 Test_en_W_FTB01 ( .A ( Test_en_E_in ) ,
|
||||
.X ( aps_rename_506_ ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 Test_en_E_FTB01 ( .A ( Test_en_E_in ) ,
|
||||
.X ( Test_en_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_107 ( .LO ( SYNOPSYS_UNCONNECTED_65 ) ,
|
||||
.HI ( optlc_net_105 ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 Reset_N_FTB01 ( .A ( Reset_E_in ) ,
|
||||
.X ( aps_rename_507_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 Reset_W_FTB01 ( .A ( Reset_E_in ) , .X ( net_net_94 ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 Reset_E_FTB01 ( .A ( Reset_E_in ) ,
|
||||
.X ( Reset_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
|
||||
.X ( ctsbuf_net_1109 ) ) ;
|
||||
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
|
||||
.X ( ctsbuf_net_2110 ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_2_S_FTB01 ( .A ( prog_clk_2_S_in ) ,
|
||||
.X ( aps_rename_508_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_4 prog_clk_2_N_FTB01 ( .A ( prog_clk_2_S_in ) ,
|
||||
.X ( ZBUF_4_f_0 ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_N_in ) ,
|
||||
.X ( aps_rename_509_ ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 prog_clk_3_S_FTB01 ( .A ( prog_clk_3_N_in ) ,
|
||||
.X ( prog_clk_3_S_out ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 clk_2_S_FTB01 ( .A ( clk_2_S_in ) ,
|
||||
.X ( clk_2_S_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 clk_2_N_FTB01 ( .A ( clk_2_S_in ) ,
|
||||
.X ( aps_rename_510_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_N_in ) ,
|
||||
.X ( aps_rename_511_ ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 clk_3_S_FTB01 ( .A ( clk_3_N_in ) ,
|
||||
.X ( clk_3_S_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_17__16 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( chany_top_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_18__17 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( chany_top_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( chany_top_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( chany_top_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( chany_top_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[10] ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[11] ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[13] ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( chany_top_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[16] ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[18] ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[20] ) ,
|
||||
.X ( chany_top_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[21] ) ,
|
||||
.X ( chany_top_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[22] ) ,
|
||||
.X ( chany_top_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[23] ) ,
|
||||
.X ( chany_top_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[24] ) ,
|
||||
.X ( chany_top_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[25] ) ,
|
||||
.X ( chany_top_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[26] ) ,
|
||||
.X ( chany_top_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[27] ) ,
|
||||
.X ( chany_top_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[28] ) ,
|
||||
.X ( chany_top_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[29] ) ,
|
||||
.X ( chany_top_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( chany_bottom_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( chany_bottom_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( chany_bottom_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( chany_bottom_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[17] ) ,
|
||||
.X ( chany_bottom_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[18] ) ,
|
||||
.X ( chany_bottom_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[20] ) ,
|
||||
.X ( chany_bottom_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[21] ) ,
|
||||
.X ( chany_bottom_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[22] ) ,
|
||||
.X ( chany_bottom_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[23] ) ,
|
||||
.X ( chany_bottom_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[24] ) ,
|
||||
.X ( chany_bottom_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[25] ) ,
|
||||
.X ( chany_bottom_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[26] ) ,
|
||||
.X ( chany_bottom_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[27] ) ,
|
||||
.X ( chany_bottom_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[28] ) ,
|
||||
.X ( chany_bottom_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[29] ) ,
|
||||
.X ( chany_bottom_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_88 ( .A ( BUF_net_89 ) , .Y ( Test_en_W_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_89 ( .A ( aps_rename_506_ ) ,
|
||||
.Y ( BUF_net_89 ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_90 ( .A ( BUF_net_91 ) , .Y ( pReset_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_91 ( .A ( pReset_S_in ) , .Y ( BUF_net_91 ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_92 ( .A ( BUF_net_93 ) , .Y ( Reset_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_93 ( .A ( aps_rename_507_ ) ,
|
||||
.Y ( BUF_net_93 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 BUFT_RR_94 ( .A ( net_net_94 ) , .X ( Reset_W_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_95 ( .A ( BUF_net_96 ) , .Y ( clk_2_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_96 ( .A ( aps_rename_510_ ) ,
|
||||
.Y ( BUF_net_96 ) ) ;
|
||||
sky130_fd_sc_hd__inv_6 BINV_R_97 ( .A ( BUF_net_98 ) , .Y ( clk_3_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_98 ( .A ( aps_rename_511_ ) ,
|
||||
.Y ( BUF_net_98 ) ) ;
|
||||
sky130_fd_sc_hd__inv_6 BINV_R_101 ( .A ( BUF_net_102 ) ,
|
||||
.Y ( prog_clk_3_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_102 ( .A ( aps_rename_509_ ) ,
|
||||
.Y ( BUF_net_102 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_109 ( .LO ( SYNOPSYS_UNCONNECTED_66 ) ,
|
||||
.HI ( optlc_net_106 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_111 ( .LO ( SYNOPSYS_UNCONNECTED_67 ) ,
|
||||
.HI ( optlc_net_107 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_113 ( .LO ( SYNOPSYS_UNCONNECTED_68 ) ,
|
||||
.HI ( optlc_net_108 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_114 ( .A ( aps_rename_505_ ) ,
|
||||
.X ( Test_en_N_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_115 ( .A ( aps_rename_508_ ) ,
|
||||
.X ( prog_clk_2_S_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_4_f_inst_1347 ( .A ( ZBUF_4_f_0 ) ,
|
||||
.X ( prog_clk_2_N_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 cts_buf_3591249 ( .A ( ctsbuf_net_1109 ) ,
|
||||
.X ( prog_clk_0_S_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 cts_buf_3641254 ( .A ( ctsbuf_net_2110 ) ,
|
||||
.X ( prog_clk_0_N_out ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,485 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module cby_2__1_ ( pReset , chany_bottom_in , chany_top_in , ccff_head ,
|
||||
chany_bottom_out , chany_top_out , right_grid_pin_0_ , left_grid_pin_16_ ,
|
||||
left_grid_pin_17_ , left_grid_pin_18_ , left_grid_pin_19_ ,
|
||||
left_grid_pin_20_ , left_grid_pin_21_ , left_grid_pin_22_ ,
|
||||
left_grid_pin_23_ , left_grid_pin_24_ , left_grid_pin_25_ ,
|
||||
left_grid_pin_26_ , left_grid_pin_27_ , left_grid_pin_28_ ,
|
||||
left_grid_pin_29_ , left_grid_pin_30_ , left_grid_pin_31_ , ccff_tail ,
|
||||
IO_ISOL_N , gfpga_pad_EMBEDDED_IO_HD_SOC_IN ,
|
||||
gfpga_pad_EMBEDDED_IO_HD_SOC_OUT , gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ,
|
||||
left_width_0_height_0__pin_0_ , left_width_0_height_0__pin_1_upper ,
|
||||
left_width_0_height_0__pin_1_lower , pReset_S_in , prog_clk_0_W_in ,
|
||||
prog_clk_0_S_out , prog_clk_0_N_out ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_bottom_in ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_bottom_out ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:0] right_grid_pin_0_ ;
|
||||
output [0:0] left_grid_pin_16_ ;
|
||||
output [0:0] left_grid_pin_17_ ;
|
||||
output [0:0] left_grid_pin_18_ ;
|
||||
output [0:0] left_grid_pin_19_ ;
|
||||
output [0:0] left_grid_pin_20_ ;
|
||||
output [0:0] left_grid_pin_21_ ;
|
||||
output [0:0] left_grid_pin_22_ ;
|
||||
output [0:0] left_grid_pin_23_ ;
|
||||
output [0:0] left_grid_pin_24_ ;
|
||||
output [0:0] left_grid_pin_25_ ;
|
||||
output [0:0] left_grid_pin_26_ ;
|
||||
output [0:0] left_grid_pin_27_ ;
|
||||
output [0:0] left_grid_pin_28_ ;
|
||||
output [0:0] left_grid_pin_29_ ;
|
||||
output [0:0] left_grid_pin_30_ ;
|
||||
output [0:0] left_grid_pin_31_ ;
|
||||
output [0:0] ccff_tail ;
|
||||
input [0:0] IO_ISOL_N ;
|
||||
input [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_IN ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ;
|
||||
output [0:0] gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ;
|
||||
input [0:0] left_width_0_height_0__pin_0_ ;
|
||||
output [0:0] left_width_0_height_0__pin_1_upper ;
|
||||
output [0:0] left_width_0_height_0__pin_1_lower ;
|
||||
input pReset_S_in ;
|
||||
input prog_clk_0_W_in ;
|
||||
output prog_clk_0_S_out ;
|
||||
output prog_clk_0_N_out ;
|
||||
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_2_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_3_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_4_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_5_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_6_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_7_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_6_ccff_tail ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_2_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_3_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_4_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_5_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_6_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_7_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size12_8_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size12_mem_8_ccff_tail ;
|
||||
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
cby_2__1__mux_tree_tapbuf_size12_0 mux_left_ipin_0 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[18] ,
|
||||
chany_bottom_out[18] , chany_top_out[24] , chany_bottom_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
|
||||
.out ( right_grid_pin_0_ ) , .p0 ( optlc_net_90 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_1 mux_right_ipin_0 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
|
||||
chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
|
||||
chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 ,
|
||||
SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
|
||||
.out ( left_grid_pin_16_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_2 mux_right_ipin_2 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
|
||||
chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
|
||||
chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 ,
|
||||
SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( left_grid_pin_18_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_3 mux_right_ipin_4 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
|
||||
chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] ,
|
||||
chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
|
||||
SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
|
||||
.out ( left_grid_pin_20_ ) , .p0 ( optlc_net_89 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_4 mux_right_ipin_6 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
|
||||
chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
|
||||
chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 ,
|
||||
SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
|
||||
.out ( left_grid_pin_22_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_5 mux_right_ipin_8 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
|
||||
chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
|
||||
chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 ,
|
||||
SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( left_grid_pin_24_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_6 mux_right_ipin_10 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[11] , chany_bottom_out[11] ,
|
||||
chany_top_out[17] , chany_bottom_out[17] , chany_top_out[23] ,
|
||||
chany_bottom_out[23] , chany_top_out[29] , chany_bottom_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
|
||||
SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
|
||||
.out ( left_grid_pin_26_ ) , .p0 ( optlc_net_89 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_7 mux_right_ipin_12 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
|
||||
chany_top_out[13] , chany_bottom_out[13] , chany_top_out[19] ,
|
||||
chany_bottom_out[19] , chany_top_out[25] , chany_bottom_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 ,
|
||||
SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
|
||||
.out ( left_grid_pin_28_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12 mux_right_ipin_14 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[9] , chany_bottom_out[9] ,
|
||||
chany_top_out[15] , chany_bottom_out[15] , chany_top_out[21] ,
|
||||
chany_bottom_out[21] , chany_top_out[27] , chany_bottom_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size12_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 ,
|
||||
SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( left_grid_pin_30_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_mem_0 mem_left_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_0_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_mem_1 mem_right_ipin_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_1_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_mem_2 mem_right_ipin_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_2_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_mem_3 mem_right_ipin_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_3_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_mem_4 mem_right_ipin_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_4_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_mem_5 mem_right_ipin_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_5_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_mem_6 mem_right_ipin_10 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_6_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_mem_7 mem_right_ipin_12 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_7_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size12_mem mem_right_ipin_14 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size12_8_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_0 mux_right_ipin_1 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
|
||||
chany_top_out[17] , chany_bottom_out[17] , chany_top_out[26] ,
|
||||
chany_bottom_out[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
|
||||
SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
|
||||
.out ( left_grid_pin_17_ ) , .p0 ( optlc_net_90 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_1 mux_right_ipin_3 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
|
||||
chany_top_out[19] , chany_bottom_out[19] , chany_top_out[28] ,
|
||||
chany_bottom_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 ,
|
||||
SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
|
||||
.out ( left_grid_pin_19_ ) , .p0 ( optlc_net_90 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_2 mux_right_ipin_5 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[6] , chany_bottom_out[6] ,
|
||||
chany_top_out[12] , chany_bottom_out[12] , chany_top_out[21] ,
|
||||
chany_bottom_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 ,
|
||||
SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
|
||||
.out ( left_grid_pin_21_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_3 mux_right_ipin_7 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[8] , chany_bottom_out[8] ,
|
||||
chany_top_out[14] , chany_bottom_out[14] , chany_top_out[23] ,
|
||||
chany_bottom_out[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
|
||||
SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
|
||||
.out ( left_grid_pin_23_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_4 mux_right_ipin_9 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[10] , chany_bottom_out[10] ,
|
||||
chany_top_out[16] , chany_bottom_out[16] , chany_top_out[25] ,
|
||||
chany_bottom_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
|
||||
SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
|
||||
.out ( left_grid_pin_25_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_5 mux_right_ipin_11 (
|
||||
.in ( { chany_top_out[0] , chany_bottom_out[0] , chany_top_out[3] ,
|
||||
chany_bottom_out[3] , chany_top_out[12] , chany_bottom_out[12] ,
|
||||
chany_top_out[18] , chany_bottom_out[18] , chany_top_out[27] ,
|
||||
chany_bottom_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 ,
|
||||
SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
|
||||
.out ( left_grid_pin_27_ ) , .p0 ( optlc_net_91 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_6 mux_right_ipin_13 (
|
||||
.in ( { chany_top_out[2] , chany_bottom_out[2] , chany_top_out[5] ,
|
||||
chany_bottom_out[5] , chany_top_out[14] , chany_bottom_out[14] ,
|
||||
chany_top_out[20] , chany_bottom_out[20] , chany_top_out[29] ,
|
||||
chany_bottom_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
|
||||
SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
|
||||
.out ( left_grid_pin_29_ ) , .p0 ( optlc_net_90 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10 mux_right_ipin_15 (
|
||||
.in ( { chany_top_out[1] , chany_bottom_out[1] , chany_top_out[4] ,
|
||||
chany_bottom_out[4] , chany_top_out[7] , chany_bottom_out[7] ,
|
||||
chany_top_out[16] , chany_bottom_out[16] , chany_top_out[22] ,
|
||||
chany_bottom_out[22] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
|
||||
SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
|
||||
.out ( left_grid_pin_31_ ) , .p0 ( optlc_net_92 ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_mem_0 mem_right_ipin_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_mem_1 mem_right_ipin_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_mem_2 mem_right_ipin_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_2_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_mem_3 mem_right_ipin_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_3_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_mem_4 mem_right_ipin_9 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_4_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_mem_5 mem_right_ipin_11 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_5_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_mem_6 mem_right_ipin_13 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_6_sram ) ) ;
|
||||
cby_2__1__mux_tree_tapbuf_size10_mem mem_right_ipin_15 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size12_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( { ccff_tail_mid } ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_7_sram ) ) ;
|
||||
cby_2__1__logical_tile_io_mode_io_ logical_tile_io_mode_io__0 (
|
||||
.IO_ISOL_N ( IO_ISOL_N ) , .pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_IN ( gfpga_pad_EMBEDDED_IO_HD_SOC_IN ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ( gfpga_pad_EMBEDDED_IO_HD_SOC_OUT ) ,
|
||||
.gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ( gfpga_pad_EMBEDDED_IO_HD_SOC_DIR ) ,
|
||||
.io_outpad ( left_width_0_height_0__pin_0_ ) ,
|
||||
.ccff_head ( { ccff_tail_mid } ) ,
|
||||
.io_inpad ( left_width_0_height_0__pin_1_lower ) ,
|
||||
.ccff_tail ( { ropt_net_108 } ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_S_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_W_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_S_FTB01 ( .A ( prog_clk_0_W_in ) ,
|
||||
.X ( ctsbuf_net_193 ) ) ;
|
||||
sky130_fd_sc_hd__clkbuf_1 prog_clk_0_N_FTB01 ( .A ( prog_clk_0_W_in ) ,
|
||||
.X ( ctsbuf_net_294 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_19__18 ( .A ( chany_bottom_in[0] ) ,
|
||||
.X ( chany_top_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_20__19 ( .A ( chany_bottom_in[1] ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_21__20 ( .A ( chany_bottom_in[2] ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_22__21 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( chany_top_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_23__22 ( .A ( chany_bottom_in[4] ) ,
|
||||
.X ( chany_top_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_24__23 ( .A ( chany_bottom_in[5] ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_25__24 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( chany_top_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_26__25 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( chany_top_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_27__26 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_28__27 ( .A ( chany_bottom_in[9] ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_29__28 ( .A ( chany_bottom_in[10] ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_30__29 ( .A ( chany_bottom_in[11] ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_31__30 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_32__31 ( .A ( chany_bottom_in[13] ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_33__32 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( chany_top_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_34__33 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_35__34 ( .A ( chany_bottom_in[16] ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chany_bottom_in[18] ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chany_bottom_in[20] ) ,
|
||||
.X ( chany_top_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chany_bottom_in[21] ) ,
|
||||
.X ( chany_top_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chany_bottom_in[22] ) ,
|
||||
.X ( chany_top_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chany_bottom_in[23] ) ,
|
||||
.X ( chany_top_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chany_bottom_in[24] ) ,
|
||||
.X ( chany_top_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chany_bottom_in[25] ) ,
|
||||
.X ( chany_top_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chany_bottom_in[26] ) ,
|
||||
.X ( chany_top_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chany_bottom_in[27] ) ,
|
||||
.X ( chany_top_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chany_bottom_in[28] ) ,
|
||||
.X ( chany_top_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chany_bottom_in[29] ) ,
|
||||
.X ( chany_top_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chany_top_in[0] ) ,
|
||||
.X ( chany_bottom_out[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chany_top_in[1] ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[2] ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( chany_bottom_out[3] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[4] ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[5] ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( chany_bottom_out[6] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[9] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[13] ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( chany_bottom_out[14] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[17] ) ,
|
||||
.X ( chany_bottom_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[18] ) ,
|
||||
.X ( chany_bottom_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[20] ) ,
|
||||
.X ( chany_bottom_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_top_in[21] ) ,
|
||||
.X ( chany_bottom_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_top_in[22] ) ,
|
||||
.X ( chany_bottom_out[22] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_top_in[23] ) ,
|
||||
.X ( chany_bottom_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_top_in[24] ) ,
|
||||
.X ( chany_bottom_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_top_in[25] ) ,
|
||||
.X ( chany_bottom_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_top_in[26] ) ,
|
||||
.X ( chany_bottom_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_top_in[27] ) ,
|
||||
.X ( chany_bottom_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_top_in[28] ) ,
|
||||
.X ( chany_bottom_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_top_in[29] ) ,
|
||||
.X ( chany_bottom_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_79__78 (
|
||||
.A ( left_width_0_height_0__pin_1_lower[0] ) ,
|
||||
.X ( left_width_0_height_0__pin_1_upper[0] ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_91 ( .LO ( SYNOPSYS_UNCONNECTED_69 ) ,
|
||||
.HI ( optlc_net_89 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_93 ( .LO ( SYNOPSYS_UNCONNECTED_70 ) ,
|
||||
.HI ( optlc_net_90 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_95 ( .LO ( SYNOPSYS_UNCONNECTED_71 ) ,
|
||||
.HI ( optlc_net_91 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_97 ( .LO ( SYNOPSYS_UNCONNECTED_72 ) ,
|
||||
.HI ( optlc_net_92 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1342 ( .A ( ropt_net_108 ) ,
|
||||
.X ( ccff_tail[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 cts_buf_3591231 ( .A ( ctsbuf_net_193 ) ,
|
||||
.X ( prog_clk_0_S_out ) ) ;
|
||||
sky130_fd_sc_hd__clkbuf_8 cts_buf_3641236 ( .A ( ctsbuf_net_294 ) ,
|
||||
.X ( prog_clk_0_N_out ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,548 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module sb_0__0_ ( pReset , chany_top_in , top_left_grid_pin_1_ ,
|
||||
chanx_right_in , right_bottom_grid_pin_1_ , right_bottom_grid_pin_3_ ,
|
||||
right_bottom_grid_pin_5_ , right_bottom_grid_pin_7_ ,
|
||||
right_bottom_grid_pin_9_ , right_bottom_grid_pin_11_ ,
|
||||
right_bottom_grid_pin_13_ , right_bottom_grid_pin_15_ ,
|
||||
right_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
|
||||
ccff_tail , pReset_E_in , prog_clk_0_E_in ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] top_left_grid_pin_1_ ;
|
||||
input [0:29] chanx_right_in ;
|
||||
input [0:0] right_bottom_grid_pin_1_ ;
|
||||
input [0:0] right_bottom_grid_pin_3_ ;
|
||||
input [0:0] right_bottom_grid_pin_5_ ;
|
||||
input [0:0] right_bottom_grid_pin_7_ ;
|
||||
input [0:0] right_bottom_grid_pin_9_ ;
|
||||
input [0:0] right_bottom_grid_pin_11_ ;
|
||||
input [0:0] right_bottom_grid_pin_13_ ;
|
||||
input [0:0] right_bottom_grid_pin_15_ ;
|
||||
input [0:0] right_bottom_grid_pin_17_ ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:29] chanx_right_out ;
|
||||
output [0:0] ccff_tail ;
|
||||
input pReset_E_in ;
|
||||
input prog_clk_0_E_in ;
|
||||
|
||||
wire ropt_net_141 ;
|
||||
wire ropt_net_133 ;
|
||||
wire ropt_net_134 ;
|
||||
wire ropt_net_135 ;
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_18_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_19_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_20_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_21_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_22_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_23_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_24_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_25_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
|
||||
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
sb_0__0__mux_tree_tapbuf_size2_0 mux_top_track_0 (
|
||||
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 } ) ,
|
||||
.out ( chany_top_out[0] ) , .p0 ( optlc_net_95 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_1 mux_top_track_6 (
|
||||
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_3 , SYNOPSYS_UNCONNECTED_4 } ) ,
|
||||
.out ( chany_top_out[3] ) , .p0 ( optlc_net_95 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_2 mux_top_track_12 (
|
||||
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[7] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_5 , SYNOPSYS_UNCONNECTED_6 } ) ,
|
||||
.out ( chany_top_out[6] ) , .p0 ( optlc_net_95 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_3 mux_top_track_28 (
|
||||
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[15] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 } ) ,
|
||||
.out ( chany_top_out[14] ) , .p0 ( optlc_net_95 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_4 mux_top_track_44 (
|
||||
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_9 , SYNOPSYS_UNCONNECTED_10 } ) ,
|
||||
.out ( chany_top_out[22] ) , .p0 ( optlc_net_95 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_5 mux_right_track_14 (
|
||||
.in ( { chany_top_in[6] , right_bottom_grid_pin_3_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_11 , SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( chanx_right_out[7] ) , .p0 ( optlc_net_95 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_6 mux_right_track_16 (
|
||||
.in ( { chany_top_in[7] , right_bottom_grid_pin_5_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 } ) ,
|
||||
.out ( chanx_right_out[8] ) , .p0 ( optlc_net_94 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_7 mux_right_track_18 (
|
||||
.in ( { chany_top_in[8] , right_bottom_grid_pin_7_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_15 , SYNOPSYS_UNCONNECTED_16 } ) ,
|
||||
.out ( chanx_right_out[9] ) , .p0 ( optlc_net_94 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_8 mux_right_track_20 (
|
||||
.in ( { chany_top_in[9] , right_bottom_grid_pin_9_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_17 , SYNOPSYS_UNCONNECTED_18 } ) ,
|
||||
.out ( chanx_right_out[10] ) , .p0 ( optlc_net_96 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_9 mux_right_track_22 (
|
||||
.in ( { chany_top_in[10] , right_bottom_grid_pin_11_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
|
||||
.out ( chanx_right_out[11] ) , .p0 ( optlc_net_96 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_10 mux_right_track_24 (
|
||||
.in ( { chany_top_in[11] , right_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_10_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
|
||||
.out ( chanx_right_out[12] ) , .p0 ( optlc_net_96 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_11 mux_right_track_26 (
|
||||
.in ( { chany_top_in[12] , right_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_11_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( chanx_right_out[13] ) , .p0 ( optlc_net_94 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_12 mux_right_track_30 (
|
||||
.in ( { chany_top_in[14] , right_bottom_grid_pin_3_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_12_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
|
||||
.out ( chanx_right_out[15] ) , .p0 ( optlc_net_98 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_13 mux_right_track_32 (
|
||||
.in ( { chany_top_in[15] , right_bottom_grid_pin_5_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_13_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
|
||||
.out ( chanx_right_out[16] ) , .p0 ( optlc_net_94 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_14 mux_right_track_34 (
|
||||
.in ( { chany_top_in[16] , right_bottom_grid_pin_7_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_14_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
|
||||
.out ( chanx_right_out[17] ) , .p0 ( optlc_net_96 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_15 mux_right_track_36 (
|
||||
.in ( { chany_top_in[17] , right_bottom_grid_pin_9_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_15_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
|
||||
.out ( chanx_right_out[18] ) , .p0 ( optlc_net_94 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_16 mux_right_track_38 (
|
||||
.in ( { chany_top_in[18] , right_bottom_grid_pin_11_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_16_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
|
||||
.out ( chanx_right_out[19] ) , .p0 ( optlc_net_94 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_17 mux_right_track_40 (
|
||||
.in ( { chany_top_in[19] , right_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_17_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( chanx_right_out[20] ) , .p0 ( optlc_net_96 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_18 mux_right_track_42 (
|
||||
.in ( { chany_top_in[20] , right_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_18_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
|
||||
.out ( chanx_right_out[21] ) , .p0 ( optlc_net_96 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_19 mux_right_track_46 (
|
||||
.in ( { chany_top_in[22] , right_bottom_grid_pin_3_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_19_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
|
||||
.out ( chanx_right_out[23] ) , .p0 ( optlc_net_95 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_20 mux_right_track_48 (
|
||||
.in ( { chany_top_in[23] , right_bottom_grid_pin_5_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_20_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
|
||||
.out ( chanx_right_out[24] ) , .p0 ( optlc_net_95 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_21 mux_right_track_50 (
|
||||
.in ( { chany_top_in[24] , right_bottom_grid_pin_7_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_21_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
|
||||
.out ( chanx_right_out[25] ) , .p0 ( optlc_net_95 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_22 mux_right_track_52 (
|
||||
.in ( { chany_top_in[25] , right_bottom_grid_pin_9_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_22_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
|
||||
.out ( chanx_right_out[26] ) , .p0 ( optlc_net_94 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_23 mux_right_track_54 (
|
||||
.in ( { chany_top_in[26] , right_bottom_grid_pin_11_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_23_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
|
||||
.out ( chanx_right_out[27] ) , .p0 ( optlc_net_94 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_24 mux_right_track_56 (
|
||||
.in ( { chany_top_in[27] , right_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_24_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
|
||||
.out ( chanx_right_out[28] ) , .p0 ( optlc_net_98 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2 mux_right_track_58 (
|
||||
.in ( { chany_top_in[28] , right_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_25_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
|
||||
.out ( chanx_right_out[29] ) , .p0 ( optlc_net_94 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_28 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_44 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_5 mem_right_track_14 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_6 mem_right_track_16 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_7 mem_right_track_18 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_8 mem_right_track_20 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_9 mem_right_track_22 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_10 mem_right_track_24 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_11 mem_right_track_26 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_12 mem_right_track_30 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_13 mem_right_track_32 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_14 mem_right_track_34 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_15 mem_right_track_36 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_16 mem_right_track_38 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_17 mem_right_track_40 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_18 mem_right_track_42 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_19 mem_right_track_46 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_20 mem_right_track_48 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_21 mem_right_track_50 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_22 mem_right_track_52 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_23 mem_right_track_54 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem_24 mem_right_track_56 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size2_mem mem_right_track_58 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_0 mux_right_track_0 (
|
||||
.in ( { chany_top_in[29] , right_bottom_grid_pin_1_[0] ,
|
||||
right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 ,
|
||||
SYNOPSYS_UNCONNECTED_55 } ) ,
|
||||
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_97 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_1 mux_right_track_2 (
|
||||
.in ( { chany_top_in[0] , right_bottom_grid_pin_3_[0] ,
|
||||
right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 ,
|
||||
SYNOPSYS_UNCONNECTED_58 } ) ,
|
||||
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_97 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_2 mux_right_track_4 (
|
||||
.in ( { chany_top_in[1] , right_bottom_grid_pin_5_[0] ,
|
||||
right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 ,
|
||||
SYNOPSYS_UNCONNECTED_61 } ) ,
|
||||
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_97 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_3 mux_right_track_6 (
|
||||
.in ( { chany_top_in[2] , right_bottom_grid_pin_1_[0] ,
|
||||
right_bottom_grid_pin_7_[0] , right_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 ,
|
||||
SYNOPSYS_UNCONNECTED_64 } ) ,
|
||||
.out ( chanx_right_out[3] ) , .p0 ( optlc_net_97 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_4 mux_right_track_8 (
|
||||
.in ( { chany_top_in[3] , right_bottom_grid_pin_3_[0] ,
|
||||
right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
|
||||
SYNOPSYS_UNCONNECTED_67 } ) ,
|
||||
.out ( chanx_right_out[4] ) , .p0 ( optlc_net_97 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4 mux_right_track_10 (
|
||||
.in ( { chany_top_in[4] , right_bottom_grid_pin_5_[0] ,
|
||||
right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 ,
|
||||
SYNOPSYS_UNCONNECTED_70 } ) ,
|
||||
.out ( chanx_right_out[5] ) , .p0 ( optlc_net_97 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size3_0 mux_right_track_12 (
|
||||
.in ( { chany_top_in[5] , right_bottom_grid_pin_1_[0] ,
|
||||
right_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
|
||||
.out ( chanx_right_out[6] ) , .p0 ( optlc_net_98 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size3_1 mux_right_track_28 (
|
||||
.in ( { chany_top_in[13] , right_bottom_grid_pin_1_[0] ,
|
||||
right_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
|
||||
.out ( chanx_right_out[14] ) , .p0 ( optlc_net_98 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size3 mux_right_track_44 (
|
||||
.in ( { chany_top_in[21] , right_bottom_grid_pin_1_[0] ,
|
||||
right_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
|
||||
.out ( chanx_right_out[22] ) , .p0 ( optlc_net_98 ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size3_mem_0 mem_right_track_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size3_mem_1 mem_right_track_28 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
|
||||
sb_0__0__mux_tree_tapbuf_size3_mem mem_right_track_44 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) ,
|
||||
.X ( chany_top_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_37__36 ( .A ( chanx_right_in[2] ) ,
|
||||
.X ( ropt_net_141 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[3] ) ,
|
||||
.X ( chany_top_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_39__38 ( .A ( chanx_right_in[5] ) ,
|
||||
.X ( ropt_net_133 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_40__39 ( .A ( chanx_right_in[6] ) ,
|
||||
.X ( chany_top_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[8] ) ,
|
||||
.X ( chany_top_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_42__41 ( .A ( chanx_right_in[9] ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_43__42 ( .A ( chanx_right_in[10] ) ,
|
||||
.X ( ropt_net_134 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[11] ) ,
|
||||
.X ( chany_top_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[12] ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_46__45 ( .A ( chanx_right_in[13] ) ,
|
||||
.X ( ropt_net_135 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_47__46 ( .A ( chanx_right_in[14] ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[16] ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[17] ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[18] ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[19] ) ,
|
||||
.X ( chany_top_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[20] ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[21] ) ,
|
||||
.X ( chany_top_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[22] ) ,
|
||||
.X ( chany_top_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[24] ) ,
|
||||
.X ( chany_top_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_56__55 ( .A ( chanx_right_in[25] ) ,
|
||||
.X ( chany_top_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[26] ) ,
|
||||
.X ( chany_top_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[27] ) ,
|
||||
.X ( chany_top_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[28] ) ,
|
||||
.X ( chany_top_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) ,
|
||||
.X ( chany_top_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) ,
|
||||
.HI ( optlc_net_94 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_99 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) ,
|
||||
.HI ( optlc_net_95 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_101 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) ,
|
||||
.HI ( optlc_net_96 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_103 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) ,
|
||||
.HI ( optlc_net_97 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_105 ( .LO ( SYNOPSYS_UNCONNECTED_81 ) ,
|
||||
.HI ( optlc_net_98 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1299 ( .A ( ropt_net_133 ) ,
|
||||
.X ( chany_top_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1300 ( .A ( ropt_net_134 ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1301 ( .A ( ropt_net_135 ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1307 ( .A ( ropt_net_141 ) ,
|
||||
.X ( chany_top_out[1] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,814 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module sb_0__1_ ( pReset , chany_top_in , top_left_grid_pin_1_ ,
|
||||
chanx_right_in , right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
|
||||
right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
|
||||
right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ ,
|
||||
right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in ,
|
||||
bottom_left_grid_pin_1_ , ccff_head , chany_top_out , chanx_right_out ,
|
||||
chany_bottom_out , ccff_tail , pReset_E_in , pReset_S_out ,
|
||||
prog_clk_0_E_in ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] top_left_grid_pin_1_ ;
|
||||
input [0:29] chanx_right_in ;
|
||||
input [0:0] right_bottom_grid_pin_36_ ;
|
||||
input [0:0] right_bottom_grid_pin_37_ ;
|
||||
input [0:0] right_bottom_grid_pin_38_ ;
|
||||
input [0:0] right_bottom_grid_pin_39_ ;
|
||||
input [0:0] right_bottom_grid_pin_40_ ;
|
||||
input [0:0] right_bottom_grid_pin_41_ ;
|
||||
input [0:0] right_bottom_grid_pin_42_ ;
|
||||
input [0:0] right_bottom_grid_pin_43_ ;
|
||||
input [0:29] chany_bottom_in ;
|
||||
input [0:0] bottom_left_grid_pin_1_ ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:29] chanx_right_out ;
|
||||
output [0:29] chany_bottom_out ;
|
||||
output [0:0] ccff_tail ;
|
||||
input pReset_E_in ;
|
||||
output pReset_S_out ;
|
||||
input prog_clk_0_E_in ;
|
||||
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_5_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_6_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_7_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_8_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_8_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_10_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_11_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_6_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_7_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_8_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_10_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_11_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_5_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_6_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_7_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_8_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_10_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_11_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_8_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_9_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_5_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_6_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_7_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_7_ccff_tail ;
|
||||
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
sb_0__1__mux_tree_tapbuf_size6_0 mux_top_track_0 (
|
||||
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[1] , chanx_right_in[12] ,
|
||||
chanx_right_in[23] , chany_top_out[4] , chany_top_out[20] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 } ) ,
|
||||
.out ( chany_top_out[0] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_1 mux_top_track_6 (
|
||||
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[4] , chanx_right_in[15] ,
|
||||
chanx_right_in[26] , chany_top_out[9] , chany_top_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
|
||||
SYNOPSYS_UNCONNECTED_6 } ) ,
|
||||
.out ( chany_top_out[3] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_2 mux_top_track_12 (
|
||||
.in ( { top_left_grid_pin_1_[0] , chanx_right_in[6] , chanx_right_in[17] ,
|
||||
chanx_right_in[28] , chany_top_out[12] , chany_top_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
|
||||
SYNOPSYS_UNCONNECTED_9 } ) ,
|
||||
.out ( chany_top_out[6] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_3 mux_right_track_2 (
|
||||
.in ( { chany_top_in[0] , chany_bottom_out[7] ,
|
||||
right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
|
||||
right_bottom_grid_pin_43_[0] , chany_top_out[7] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
|
||||
SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_4 mux_right_track_6 (
|
||||
.in ( { chany_top_in[2] , chany_bottom_out[9] ,
|
||||
right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
|
||||
right_bottom_grid_pin_42_[0] , chany_top_out[9] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
|
||||
SYNOPSYS_UNCONNECTED_15 } ) ,
|
||||
.out ( chanx_right_out[3] ) , .p0 ( optlc_net_144 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_5 mux_right_track_8 (
|
||||
.in ( { chany_top_in[4] , chany_bottom_out[11] ,
|
||||
right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
|
||||
right_bottom_grid_pin_43_[0] , chany_top_out[11] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
|
||||
SYNOPSYS_UNCONNECTED_18 } ) ,
|
||||
.out ( chanx_right_out[4] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_6 mux_bottom_track_7 (
|
||||
.in ( { chany_bottom_out[9] , chany_bottom_out[24] , chanx_right_in[6] ,
|
||||
chanx_right_in[17] , chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
|
||||
SYNOPSYS_UNCONNECTED_21 } ) ,
|
||||
.out ( chany_bottom_out[3] ) , .p0 ( optlc_net_145 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6 mux_bottom_track_13 (
|
||||
.in ( { chany_bottom_out[12] , chany_bottom_out[27] , chanx_right_in[4] ,
|
||||
chanx_right_in[15] , chanx_right_in[26] , bottom_left_grid_pin_1_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
|
||||
SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( chany_bottom_out[6] ) , .p0 ( optlc_net_145 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_mem_2 mem_top_track_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_mem_3 mem_right_track_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_mem_4 mem_right_track_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_4_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_mem_5 mem_right_track_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_5_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_mem_6 mem_bottom_track_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_6_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size6_mem mem_bottom_track_13 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_7_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_0 mux_top_track_2 (
|
||||
.in ( { chanx_right_in[2] , chanx_right_in[13] , chanx_right_in[24] ,
|
||||
chany_top_out[7] , chany_top_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
|
||||
SYNOPSYS_UNCONNECTED_27 } ) ,
|
||||
.out ( chany_top_out[1] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_1 mux_top_track_4 (
|
||||
.in ( { chanx_right_in[3] , chanx_right_in[14] , chanx_right_in[25] ,
|
||||
chany_top_out[8] , chany_top_out[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
|
||||
SYNOPSYS_UNCONNECTED_30 } ) ,
|
||||
.out ( chany_top_out[2] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_2 mux_top_track_10 (
|
||||
.in ( { chanx_right_in[5] , chanx_right_in[16] , chanx_right_in[27] ,
|
||||
chany_top_out[11] , chany_top_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 ,
|
||||
SYNOPSYS_UNCONNECTED_33 } ) ,
|
||||
.out ( chany_top_out[5] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_3 mux_top_track_20 (
|
||||
.in ( { chanx_right_in[7] , chanx_right_in[18] , chanx_right_in[29] ,
|
||||
chany_top_out[13] , chany_top_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 ,
|
||||
SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( chany_top_out[10] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_4 mux_right_track_0 (
|
||||
.in ( { chany_bottom_out[4] , right_bottom_grid_pin_36_[0] ,
|
||||
right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_42_[0] ,
|
||||
chany_top_out[4] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
|
||||
SYNOPSYS_UNCONNECTED_39 } ) ,
|
||||
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_5 mux_right_track_4 (
|
||||
.in ( { chany_top_in[1] , chany_bottom_out[8] ,
|
||||
right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] ,
|
||||
chany_top_out[8] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
|
||||
SYNOPSYS_UNCONNECTED_42 } ) ,
|
||||
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_144 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_6 mux_right_track_10 (
|
||||
.in ( { chany_top_in[5] , chany_bottom_out[12] ,
|
||||
right_bottom_grid_pin_38_[0] , right_bottom_grid_pin_41_[0] ,
|
||||
chany_top_out[12] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
|
||||
SYNOPSYS_UNCONNECTED_45 } ) ,
|
||||
.out ( chanx_right_out[5] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_7 mux_bottom_track_1 (
|
||||
.in ( { chany_bottom_out[4] , chany_bottom_out[20] , chanx_right_in[9] ,
|
||||
chanx_right_in[20] , bottom_left_grid_pin_1_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 ,
|
||||
SYNOPSYS_UNCONNECTED_48 } ) ,
|
||||
.out ( chany_bottom_out[0] ) , .p0 ( optlc_net_145 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_8 mux_bottom_track_5 (
|
||||
.in ( { chany_bottom_out[8] , chany_bottom_out[23] , chanx_right_in[7] ,
|
||||
chanx_right_in[18] , chanx_right_in[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
|
||||
SYNOPSYS_UNCONNECTED_51 } ) ,
|
||||
.out ( chany_bottom_out[2] ) , .p0 ( optlc_net_145 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_9 mux_bottom_track_11 (
|
||||
.in ( { chany_bottom_out[11] , chany_bottom_out[25] , chanx_right_in[5] ,
|
||||
chanx_right_in[16] , chanx_right_in[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 ,
|
||||
SYNOPSYS_UNCONNECTED_54 } ) ,
|
||||
.out ( chany_bottom_out[5] ) , .p0 ( optlc_net_145 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_10 mux_bottom_track_21 (
|
||||
.in ( { chany_bottom_out[13] , chany_bottom_out[28] , chanx_right_in[3] ,
|
||||
chanx_right_in[14] , chanx_right_in[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_10_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 ,
|
||||
SYNOPSYS_UNCONNECTED_57 } ) ,
|
||||
.out ( chany_bottom_out[10] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5 mux_bottom_track_29 (
|
||||
.in ( { chany_bottom_out[15] , chany_bottom_out[29] , chanx_right_in[2] ,
|
||||
chanx_right_in[13] , chanx_right_in[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_11_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 ,
|
||||
SYNOPSYS_UNCONNECTED_60 } ) ,
|
||||
.out ( chany_bottom_out[14] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_0 mem_top_track_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_1 mem_top_track_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_2 mem_top_track_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_3 mem_top_track_20 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_4 mem_right_track_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_5 mem_right_track_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_6 mem_right_track_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_6_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_7 mem_bottom_track_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_7_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_8 mem_bottom_track_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_8_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_9 mem_bottom_track_11 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_9_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_9_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem_10 mem_bottom_track_21 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_10_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size5_mem mem_bottom_track_29 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_10_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_11_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_0 mux_top_track_28 (
|
||||
.in ( { chanx_right_in[8] , chanx_right_in[19] , chany_top_out[15] ,
|
||||
chany_top_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
|
||||
SYNOPSYS_UNCONNECTED_63 } ) ,
|
||||
.out ( chany_top_out[14] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_1 mux_top_track_52 (
|
||||
.in ( { chanx_right_in[0] , chanx_right_in[11] , chanx_right_in[22] ,
|
||||
chany_top_out[19] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 ,
|
||||
SYNOPSYS_UNCONNECTED_66 } ) ,
|
||||
.out ( chany_top_out[26] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_2 mux_right_track_12 (
|
||||
.in ( { chany_top_in[9] , chany_bottom_out[13] ,
|
||||
right_bottom_grid_pin_36_[0] , chany_top_out[13] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 ,
|
||||
SYNOPSYS_UNCONNECTED_69 } ) ,
|
||||
.out ( chanx_right_out[6] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_3 mux_right_track_14 (
|
||||
.in ( { chany_top_in[13] , chany_bottom_out[15] ,
|
||||
right_bottom_grid_pin_37_[0] , chany_top_out[15] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 ,
|
||||
SYNOPSYS_UNCONNECTED_72 } ) ,
|
||||
.out ( chanx_right_out[7] ) , .p0 ( optlc_net_144 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_4 mux_right_track_16 (
|
||||
.in ( { chany_bottom_out[16] , chany_top_in[17] ,
|
||||
right_bottom_grid_pin_38_[0] , chany_top_out[16] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
|
||||
SYNOPSYS_UNCONNECTED_75 } ) ,
|
||||
.out ( chanx_right_out[8] ) , .p0 ( optlc_net_144 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_5 mux_right_track_18 (
|
||||
.in ( { chany_bottom_out[17] , chany_top_in[21] ,
|
||||
right_bottom_grid_pin_39_[0] , chany_top_out[17] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 ,
|
||||
SYNOPSYS_UNCONNECTED_78 } ) ,
|
||||
.out ( chanx_right_out[9] ) , .p0 ( optlc_net_144 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_6 mux_right_track_20 (
|
||||
.in ( { chany_bottom_out[19] , chany_top_in[25] ,
|
||||
right_bottom_grid_pin_40_[0] , chany_top_out[19] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 ,
|
||||
SYNOPSYS_UNCONNECTED_81 } ) ,
|
||||
.out ( chanx_right_out[10] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_7 mux_right_track_22 (
|
||||
.in ( { chany_bottom_out[20] , chany_top_in[29] ,
|
||||
right_bottom_grid_pin_41_[0] , chany_top_out[20] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 ,
|
||||
SYNOPSYS_UNCONNECTED_84 } ) ,
|
||||
.out ( chanx_right_out[11] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_8 mux_right_track_36 (
|
||||
.in ( { chany_bottom_out[29] , right_bottom_grid_pin_40_[0] ,
|
||||
chany_top_out[29] , chany_bottom_in[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 ,
|
||||
SYNOPSYS_UNCONNECTED_87 } ) ,
|
||||
.out ( chanx_right_out[18] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_9 mux_bottom_track_3 (
|
||||
.in ( { chany_bottom_out[7] , chany_bottom_out[21] , chanx_right_in[8] ,
|
||||
chanx_right_in[19] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 ,
|
||||
SYNOPSYS_UNCONNECTED_90 } ) ,
|
||||
.out ( chany_bottom_out[1] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_10 mux_bottom_track_37 (
|
||||
.in ( { chany_bottom_out[16] , chanx_right_in[1] , chanx_right_in[12] ,
|
||||
chanx_right_in[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_10_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 ,
|
||||
SYNOPSYS_UNCONNECTED_93 } ) ,
|
||||
.out ( chany_bottom_out[18] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4 mux_bottom_track_45 (
|
||||
.in ( { chany_bottom_out[17] , chanx_right_in[0] , chanx_right_in[11] ,
|
||||
chanx_right_in[22] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_11_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 ,
|
||||
SYNOPSYS_UNCONNECTED_96 } ) ,
|
||||
.out ( chany_bottom_out[22] ) , .p0 ( optlc_net_144 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_0 mem_top_track_28 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_1 mem_top_track_52 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_2 mem_right_track_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_3 mem_right_track_14 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_4 mem_right_track_16 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_5 mem_right_track_18 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_6 mem_right_track_20 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_7 mem_right_track_22 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_8 mem_right_track_36 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_9 mem_bottom_track_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem_10 mem_bottom_track_37 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_11_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size4_mem mem_bottom_track_45 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_0 mux_top_track_36 (
|
||||
.in ( { chanx_right_in[9] , chanx_right_in[20] , chany_top_out[16] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) ,
|
||||
.out ( chany_top_out[18] ) , .p0 ( optlc_net_144 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_1 mux_top_track_44 (
|
||||
.in ( { chanx_right_in[10] , chanx_right_in[21] , chany_top_out[17] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
|
||||
.out ( chany_top_out[22] ) , .p0 ( optlc_net_144 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_2 mux_right_track_24 (
|
||||
.in ( { chany_bottom_out[21] , right_bottom_grid_pin_42_[0] ,
|
||||
chany_top_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
|
||||
.out ( chanx_right_out[12] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_3 mux_right_track_26 (
|
||||
.in ( { chany_bottom_out[23] , right_bottom_grid_pin_43_[0] ,
|
||||
chany_top_out[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
|
||||
.out ( chanx_right_out[13] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_4 mux_right_track_28 (
|
||||
.in ( { chany_bottom_out[24] , right_bottom_grid_pin_36_[0] ,
|
||||
chany_top_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
|
||||
.out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_5 mux_right_track_30 (
|
||||
.in ( { chany_bottom_out[25] , right_bottom_grid_pin_37_[0] ,
|
||||
chany_top_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
|
||||
.out ( chanx_right_out[15] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_6 mux_right_track_32 (
|
||||
.in ( { chany_bottom_out[27] , right_bottom_grid_pin_38_[0] ,
|
||||
chany_top_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
|
||||
.out ( chanx_right_out[16] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_7 mux_right_track_34 (
|
||||
.in ( { chany_bottom_out[28] , right_bottom_grid_pin_39_[0] ,
|
||||
chany_top_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
|
||||
.out ( chanx_right_out[17] ) , .p0 ( optlc_net_144 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_8 mux_right_track_50 (
|
||||
.in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] ,
|
||||
chany_bottom_in[4] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
|
||||
.out ( chanx_right_out[25] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3 mux_bottom_track_53 (
|
||||
.in ( { chany_bottom_out[19] , chanx_right_in[10] , chanx_right_in[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
|
||||
.out ( chany_bottom_out[26] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem_0 mem_top_track_36 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem_2 mem_right_track_24 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem_3 mem_right_track_26 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem_4 mem_right_track_28 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem_5 mem_right_track_30 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_5_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem_6 mem_right_track_32 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_6_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem_7 mem_right_track_34 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_7_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem_8 mem_right_track_50 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_8_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size3_mem mem_bottom_track_53 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size3_9_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_0 mux_right_track_38 (
|
||||
.in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
|
||||
.out ( chanx_right_out[19] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_1 mux_right_track_40 (
|
||||
.in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
|
||||
.out ( chanx_right_out[20] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_2 mux_right_track_44 (
|
||||
.in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
|
||||
.out ( chanx_right_out[22] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_3 mux_right_track_46 (
|
||||
.in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[9] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
|
||||
.out ( chanx_right_out[23] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_4 mux_right_track_48 (
|
||||
.in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[5] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
|
||||
.out ( chanx_right_out[24] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_5 mux_right_track_52 (
|
||||
.in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[2] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
|
||||
.out ( chanx_right_out[26] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_6 mux_right_track_54 (
|
||||
.in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[1] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
|
||||
.out ( chanx_right_out[27] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2 mux_right_track_56 (
|
||||
.in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
|
||||
.out ( chanx_right_out[28] ) , .p0 ( optlc_net_143 ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_mem_0 mem_right_track_38 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_mem_1 mem_right_track_40 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_mem_2 mem_right_track_44 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_mem_3 mem_right_track_46 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_mem_4 mem_right_track_48 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_mem_5 mem_right_track_52 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_mem_6 mem_right_track_54 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
|
||||
sb_0__1__mux_tree_tapbuf_size2_mem mem_right_track_56 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 pReset_S_FTB01 ( .A ( pReset_E_in ) ,
|
||||
.X ( pReset_S_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chany_top_in[3] ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chany_top_in[6] ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chany_top_in[7] ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chany_top_in[8] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chany_top_in[10] ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chany_top_in[11] ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chany_top_in[12] ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chany_top_in[14] ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chany_top_in[15] ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chany_top_in[16] ) ,
|
||||
.X ( chany_bottom_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chany_top_in[18] ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chany_top_in[19] ) ,
|
||||
.X ( chany_bottom_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chany_top_in[20] ) ,
|
||||
.X ( chany_bottom_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chany_top_in[22] ) ,
|
||||
.X ( chany_bottom_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chany_top_in[23] ) ,
|
||||
.X ( chany_bottom_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chany_top_in[24] ) ,
|
||||
.X ( chany_bottom_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chany_top_in[26] ) ,
|
||||
.X ( chany_bottom_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chany_top_in[27] ) ,
|
||||
.X ( chany_bottom_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chany_top_in[28] ) ,
|
||||
.X ( chany_bottom_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chany_bottom_in[3] ) ,
|
||||
.X ( chany_top_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chany_bottom_in[6] ) ,
|
||||
.X ( chany_top_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chany_bottom_in[7] ) ,
|
||||
.X ( chany_top_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chany_bottom_in[8] ) ,
|
||||
.X ( chany_top_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chany_bottom_in[10] ) ,
|
||||
.X ( chany_top_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chany_bottom_in[11] ) ,
|
||||
.X ( chany_top_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chany_bottom_in[12] ) ,
|
||||
.X ( chany_top_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chany_bottom_in[14] ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chany_bottom_in[15] ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chany_bottom_in[16] ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chany_bottom_in[17] ) ,
|
||||
.X ( chanx_right_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chany_bottom_in[18] ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chany_bottom_in[19] ) ,
|
||||
.X ( chany_top_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chany_bottom_in[20] ) ,
|
||||
.X ( chany_top_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chany_bottom_in[22] ) ,
|
||||
.X ( chany_top_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chany_bottom_in[23] ) ,
|
||||
.X ( chany_top_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chany_bottom_in[24] ) ,
|
||||
.X ( chany_top_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chany_bottom_in[26] ) ,
|
||||
.X ( chany_top_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chany_bottom_in[27] ) ,
|
||||
.X ( chany_top_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chany_bottom_in[28] ) ,
|
||||
.X ( chany_top_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_146 ( .LO ( SYNOPSYS_UNCONNECTED_133 ) ,
|
||||
.HI ( optlc_net_143 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_134 ) ,
|
||||
.HI ( optlc_net_144 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_135 ) ,
|
||||
.HI ( optlc_net_145 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_154 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) ,
|
||||
.HI ( optlc_net_146 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_156 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) ,
|
||||
.HI ( optlc_net_147 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_158 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) ,
|
||||
.HI ( optlc_net_148 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,551 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module sb_0__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ ,
|
||||
right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
|
||||
right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
|
||||
right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ ,
|
||||
right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in ,
|
||||
bottom_left_grid_pin_1_ , ccff_head , chanx_right_out , chany_bottom_out ,
|
||||
ccff_tail , SC_IN_TOP , SC_OUT_BOT , pReset_E_in , pReset_S_out ,
|
||||
prog_clk_0_E_in ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chanx_right_in ;
|
||||
input [0:0] right_top_grid_pin_1_ ;
|
||||
input [0:0] right_bottom_grid_pin_36_ ;
|
||||
input [0:0] right_bottom_grid_pin_37_ ;
|
||||
input [0:0] right_bottom_grid_pin_38_ ;
|
||||
input [0:0] right_bottom_grid_pin_39_ ;
|
||||
input [0:0] right_bottom_grid_pin_40_ ;
|
||||
input [0:0] right_bottom_grid_pin_41_ ;
|
||||
input [0:0] right_bottom_grid_pin_42_ ;
|
||||
input [0:0] right_bottom_grid_pin_43_ ;
|
||||
input [0:29] chany_bottom_in ;
|
||||
input [0:0] bottom_left_grid_pin_1_ ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chanx_right_out ;
|
||||
output [0:29] chany_bottom_out ;
|
||||
output [0:0] ccff_tail ;
|
||||
input SC_IN_TOP ;
|
||||
output SC_OUT_BOT ;
|
||||
input pReset_E_in ;
|
||||
output pReset_S_out ;
|
||||
input prog_clk_0_E_in ;
|
||||
|
||||
wire ropt_net_129 ;
|
||||
wire ropt_net_130 ;
|
||||
wire ropt_net_131 ;
|
||||
wire ropt_net_128 ;
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_18_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_19_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_20_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_21_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_22_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_23_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_24_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_25_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_26_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
|
||||
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
sb_0__2__mux_tree_tapbuf_size4_0 mux_right_track_0 (
|
||||
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] ,
|
||||
right_bottom_grid_pin_41_[0] , chany_bottom_in[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 } ) ,
|
||||
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_1 mux_right_track_2 (
|
||||
.in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
|
||||
right_bottom_grid_pin_42_[0] , chany_bottom_in[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
|
||||
SYNOPSYS_UNCONNECTED_6 } ) ,
|
||||
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_2 mux_right_track_4 (
|
||||
.in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
|
||||
right_bottom_grid_pin_43_[0] , chany_bottom_in[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
|
||||
SYNOPSYS_UNCONNECTED_9 } ) ,
|
||||
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_3 mux_right_track_6 (
|
||||
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] ,
|
||||
right_bottom_grid_pin_41_[0] , chany_bottom_in[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
|
||||
SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( chanx_right_out[3] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_4 mux_right_track_8 (
|
||||
.in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
|
||||
right_bottom_grid_pin_42_[0] , chany_bottom_in[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
|
||||
SYNOPSYS_UNCONNECTED_15 } ) ,
|
||||
.out ( chanx_right_out[4] ) , .p0 ( optlc_net_91 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4 mux_right_track_10 (
|
||||
.in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
|
||||
right_bottom_grid_pin_43_[0] , chany_bottom_in[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
|
||||
SYNOPSYS_UNCONNECTED_18 } ) ,
|
||||
.out ( chanx_right_out[5] ) , .p0 ( optlc_net_91 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_mem_1 mem_right_track_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_mem_2 mem_right_track_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_mem_3 mem_right_track_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_mem_4 mem_right_track_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size4_mem mem_right_track_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_0 mux_right_track_12 (
|
||||
.in ( { right_top_grid_pin_1_[0] , chany_bottom_in[22] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 } ) ,
|
||||
.out ( chanx_right_out[6] ) , .p0 ( optlc_net_91 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_1 mux_right_track_14 (
|
||||
.in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_21 , SYNOPSYS_UNCONNECTED_22 } ) ,
|
||||
.out ( chanx_right_out[7] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_2 mux_right_track_16 (
|
||||
.in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[20] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_23 , SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( chanx_right_out[8] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_3 mux_right_track_18 (
|
||||
.in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[19] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 } ) ,
|
||||
.out ( chanx_right_out[9] ) , .p0 ( optlc_net_89 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_4 mux_right_track_20 (
|
||||
.in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[18] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_27 , SYNOPSYS_UNCONNECTED_28 } ) ,
|
||||
.out ( chanx_right_out[10] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_5 mux_right_track_22 (
|
||||
.in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[17] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_29 , SYNOPSYS_UNCONNECTED_30 } ) ,
|
||||
.out ( chanx_right_out[11] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_6 mux_right_track_24 (
|
||||
.in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[16] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 } ) ,
|
||||
.out ( chanx_right_out[12] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_7 mux_right_track_26 (
|
||||
.in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[15] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_33 , SYNOPSYS_UNCONNECTED_34 } ) ,
|
||||
.out ( chanx_right_out[13] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_8 mux_right_track_30 (
|
||||
.in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[13] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_35 , SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( chanx_right_out[15] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_9 mux_right_track_32 (
|
||||
.in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[12] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
|
||||
.out ( chanx_right_out[16] ) , .p0 ( optlc_net_89 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_10 mux_right_track_34 (
|
||||
.in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[11] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_10_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
|
||||
.out ( chanx_right_out[17] ) , .p0 ( optlc_net_89 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_11 mux_right_track_36 (
|
||||
.in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[10] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_11_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
|
||||
.out ( chanx_right_out[18] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_12 mux_right_track_38 (
|
||||
.in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[9] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_12_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
|
||||
.out ( chanx_right_out[19] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_13 mux_right_track_40 (
|
||||
.in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[8] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_13_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
|
||||
.out ( chanx_right_out[20] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_14 mux_right_track_42 (
|
||||
.in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[7] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_14_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
|
||||
.out ( chanx_right_out[21] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_15 mux_right_track_44 (
|
||||
.in ( { right_top_grid_pin_1_[0] , chany_bottom_in[6] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_15_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
|
||||
.out ( chanx_right_out[22] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_16 mux_right_track_46 (
|
||||
.in ( { right_bottom_grid_pin_36_[0] , chany_bottom_in[5] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_16_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
|
||||
.out ( chanx_right_out[23] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_17 mux_right_track_48 (
|
||||
.in ( { right_bottom_grid_pin_37_[0] , chany_bottom_in[4] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_17_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
|
||||
.out ( chanx_right_out[24] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_18 mux_right_track_50 (
|
||||
.in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[3] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_18_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
|
||||
.out ( chanx_right_out[25] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_19 mux_right_track_54 (
|
||||
.in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[1] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_19_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
|
||||
.out ( chanx_right_out[27] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_20 mux_right_track_56 (
|
||||
.in ( { right_bottom_grid_pin_41_[0] , chany_bottom_in[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_20_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
|
||||
.out ( chanx_right_out[28] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_21 mux_right_track_58 (
|
||||
.in ( { right_bottom_grid_pin_42_[0] , chany_bottom_in[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_21_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
|
||||
.out ( chanx_right_out[29] ) , .p0 ( optlc_net_88 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_22 mux_bottom_track_1 (
|
||||
.in ( { chanx_right_in[28] , bottom_left_grid_pin_1_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_22_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
|
||||
.out ( chany_bottom_out[0] ) , .p0 ( optlc_net_91 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_23 mux_bottom_track_7 (
|
||||
.in ( { chanx_right_in[25] , bottom_left_grid_pin_1_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_23_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
|
||||
.out ( chany_bottom_out[3] ) , .p0 ( optlc_net_91 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_24 mux_bottom_track_13 (
|
||||
.in ( { chanx_right_in[22] , bottom_left_grid_pin_1_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_24_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
|
||||
.out ( chany_bottom_out[6] ) , .p0 ( optlc_net_89 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_25 mux_bottom_track_29 (
|
||||
.in ( { chanx_right_in[14] , bottom_left_grid_pin_1_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_25_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
|
||||
.out ( chany_bottom_out[14] ) , .p0 ( optlc_net_89 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2 mux_bottom_track_45 (
|
||||
.in ( { chanx_right_in[6] , bottom_left_grid_pin_1_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_26_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
|
||||
.out ( chany_bottom_out[22] ) , .p0 ( optlc_net_89 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_0 mem_right_track_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_1 mem_right_track_14 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_2 mem_right_track_16 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_3 mem_right_track_18 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_4 mem_right_track_20 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_5 mem_right_track_22 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_6 mem_right_track_24 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_7 mem_right_track_26 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_8 mem_right_track_30 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_9 mem_right_track_32 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_10 mem_right_track_34 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_11 mem_right_track_36 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_12 mem_right_track_38 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_13 mem_right_track_40 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_14 mem_right_track_42 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_15 mem_right_track_44 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_16 mem_right_track_46 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_17 mem_right_track_48 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_18 mem_right_track_50 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_19 mem_right_track_54 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_20 mem_right_track_56 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_21 mem_right_track_58 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_22 mem_bottom_track_1 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_23 mem_bottom_track_7 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_24 mem_bottom_track_13 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem_25 mem_bottom_track_29 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size2_mem mem_bottom_track_45 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size3_0 mux_right_track_28 (
|
||||
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_43_[0] ,
|
||||
chany_bottom_in[14] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
|
||||
.out ( chanx_right_out[14] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size3 mux_right_track_52 (
|
||||
.in ( { right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_43_[0] ,
|
||||
chany_bottom_in[2] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
|
||||
.out ( chanx_right_out[26] ) , .p0 ( optlc_net_90 ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size3_mem_0 mem_right_track_28 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
|
||||
sb_0__2__mux_tree_tapbuf_size3_mem mem_right_track_52 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_90 ( .LO ( SYNOPSYS_UNCONNECTED_77 ) ,
|
||||
.HI ( optlc_net_88 ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_E_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_36__35 ( .A ( chanx_right_in[0] ) ,
|
||||
.X ( chany_bottom_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_37__36 ( .A ( chanx_right_in[1] ) ,
|
||||
.X ( chany_bottom_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_38__37 ( .A ( chanx_right_in[2] ) ,
|
||||
.X ( chany_bottom_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_39__38 ( .A ( chanx_right_in[3] ) ,
|
||||
.X ( chany_bottom_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_40__39 ( .A ( chanx_right_in[4] ) ,
|
||||
.X ( ropt_net_129 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_41__40 ( .A ( chanx_right_in[5] ) ,
|
||||
.X ( chany_bottom_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_42__41 ( .A ( chanx_right_in[7] ) ,
|
||||
.X ( chany_bottom_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_43__42 ( .A ( chanx_right_in[8] ) ,
|
||||
.X ( chany_bottom_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_44__43 ( .A ( chanx_right_in[9] ) ,
|
||||
.X ( chany_bottom_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_45__44 ( .A ( chanx_right_in[10] ) ,
|
||||
.X ( chany_bottom_out[18] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_46__45 ( .A ( chanx_right_in[11] ) ,
|
||||
.X ( chany_bottom_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_47__46 ( .A ( chanx_right_in[12] ) ,
|
||||
.X ( ropt_net_130 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_48__47 ( .A ( chanx_right_in[13] ) ,
|
||||
.X ( chany_bottom_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_49__48 ( .A ( chanx_right_in[15] ) ,
|
||||
.X ( ropt_net_131 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[16] ) ,
|
||||
.X ( chany_bottom_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[17] ) ,
|
||||
.X ( chany_bottom_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[18] ) ,
|
||||
.X ( chany_bottom_out[10] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[19] ) ,
|
||||
.X ( chany_bottom_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[20] ) ,
|
||||
.X ( chany_bottom_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[21] ) ,
|
||||
.X ( chany_bottom_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[23] ) ,
|
||||
.X ( chany_bottom_out[5] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_57__56 ( .A ( chanx_right_in[24] ) ,
|
||||
.X ( ropt_net_128 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[26] ) ,
|
||||
.X ( chany_bottom_out[2] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[27] ) ,
|
||||
.X ( chany_bottom_out[1] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[29] ) ,
|
||||
.X ( chany_bottom_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_61__60 ( .A ( SC_IN_TOP ) , .X ( SC_OUT_BOT ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 BUFT_RR_85 ( .A ( pReset_E_in ) , .X ( pReset_S_out ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_92 ( .LO ( SYNOPSYS_UNCONNECTED_78 ) ,
|
||||
.HI ( optlc_net_89 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_94 ( .LO ( SYNOPSYS_UNCONNECTED_79 ) ,
|
||||
.HI ( optlc_net_90 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_96 ( .LO ( SYNOPSYS_UNCONNECTED_80 ) ,
|
||||
.HI ( optlc_net_91 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1293 ( .A ( ropt_net_128 ) ,
|
||||
.X ( chany_bottom_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1294 ( .A ( ropt_net_129 ) ,
|
||||
.X ( chany_bottom_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1295 ( .A ( ropt_net_130 ) ,
|
||||
.X ( chany_bottom_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1296 ( .A ( ropt_net_131 ) ,
|
||||
.X ( chany_bottom_out[13] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,888 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module sb_1__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
|
||||
top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
|
||||
top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
|
||||
top_left_grid_pin_51_ , chanx_right_in , right_bottom_grid_pin_1_ ,
|
||||
right_bottom_grid_pin_3_ , right_bottom_grid_pin_5_ ,
|
||||
right_bottom_grid_pin_7_ , right_bottom_grid_pin_9_ ,
|
||||
right_bottom_grid_pin_11_ , right_bottom_grid_pin_13_ ,
|
||||
right_bottom_grid_pin_15_ , right_bottom_grid_pin_17_ , chanx_left_in ,
|
||||
left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
|
||||
left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
|
||||
left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
|
||||
left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
|
||||
left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_right_out ,
|
||||
chanx_left_out , ccff_tail , SC_IN_TOP , SC_OUT_TOP , Test_en_S_in ,
|
||||
Test_en_N_out , pReset_S_in , pReset_E_in , pReset_W_in , pReset_N_out ,
|
||||
pReset_W_out , pReset_E_out , Reset_S_in , Reset_N_out , prog_clk_0_N_in ,
|
||||
prog_clk_3_S_in , prog_clk_3_N_out , clk_3_S_in , clk_3_N_out ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] top_left_grid_pin_44_ ;
|
||||
input [0:0] top_left_grid_pin_45_ ;
|
||||
input [0:0] top_left_grid_pin_46_ ;
|
||||
input [0:0] top_left_grid_pin_47_ ;
|
||||
input [0:0] top_left_grid_pin_48_ ;
|
||||
input [0:0] top_left_grid_pin_49_ ;
|
||||
input [0:0] top_left_grid_pin_50_ ;
|
||||
input [0:0] top_left_grid_pin_51_ ;
|
||||
input [0:29] chanx_right_in ;
|
||||
input [0:0] right_bottom_grid_pin_1_ ;
|
||||
input [0:0] right_bottom_grid_pin_3_ ;
|
||||
input [0:0] right_bottom_grid_pin_5_ ;
|
||||
input [0:0] right_bottom_grid_pin_7_ ;
|
||||
input [0:0] right_bottom_grid_pin_9_ ;
|
||||
input [0:0] right_bottom_grid_pin_11_ ;
|
||||
input [0:0] right_bottom_grid_pin_13_ ;
|
||||
input [0:0] right_bottom_grid_pin_15_ ;
|
||||
input [0:0] right_bottom_grid_pin_17_ ;
|
||||
input [0:29] chanx_left_in ;
|
||||
input [0:0] left_bottom_grid_pin_1_ ;
|
||||
input [0:0] left_bottom_grid_pin_3_ ;
|
||||
input [0:0] left_bottom_grid_pin_5_ ;
|
||||
input [0:0] left_bottom_grid_pin_7_ ;
|
||||
input [0:0] left_bottom_grid_pin_9_ ;
|
||||
input [0:0] left_bottom_grid_pin_11_ ;
|
||||
input [0:0] left_bottom_grid_pin_13_ ;
|
||||
input [0:0] left_bottom_grid_pin_15_ ;
|
||||
input [0:0] left_bottom_grid_pin_17_ ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:29] chanx_right_out ;
|
||||
output [0:29] chanx_left_out ;
|
||||
output [0:0] ccff_tail ;
|
||||
input SC_IN_TOP ;
|
||||
output SC_OUT_TOP ;
|
||||
input Test_en_S_in ;
|
||||
output Test_en_N_out ;
|
||||
input pReset_S_in ;
|
||||
input pReset_E_in ;
|
||||
input pReset_W_in ;
|
||||
output pReset_N_out ;
|
||||
output pReset_W_out ;
|
||||
output pReset_E_out ;
|
||||
input Reset_S_in ;
|
||||
output Reset_N_out ;
|
||||
input prog_clk_0_N_in ;
|
||||
input prog_clk_3_S_in ;
|
||||
output prog_clk_3_N_out ;
|
||||
input clk_3_S_in ;
|
||||
output clk_3_N_out ;
|
||||
|
||||
wire ropt_net_176 ;
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_5_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_5_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_6_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_7_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_8_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_9_ccff_tail ;
|
||||
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
|
||||
wire [0:3] mux_tree_tapbuf_size9_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size9_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size9_2_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size9_mem_2_ccff_tail ;
|
||||
|
||||
assign pReset_E_in = pReset_S_in ;
|
||||
assign pReset_E_in = pReset_W_in ;
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
sb_1__0__mux_tree_tapbuf_size7_0 mux_top_track_0 (
|
||||
.in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
|
||||
top_left_grid_pin_50_[0] , chanx_right_in[1] , chanx_left_out[4] ,
|
||||
chanx_left_in[0] , chanx_right_out[4] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 } ) ,
|
||||
.out ( chany_top_out[0] ) , .p0 ( optlc_net_154 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_1 mux_right_track_0 (
|
||||
.in ( { chany_top_in[10] , chany_top_in[21] ,
|
||||
right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_7_[0] ,
|
||||
right_bottom_grid_pin_13_[0] , chanx_right_out[4] ,
|
||||
chanx_right_out[20] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
|
||||
SYNOPSYS_UNCONNECTED_6 } ) ,
|
||||
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_154 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_2 mux_right_track_12 (
|
||||
.in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] ,
|
||||
right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_13_[0] ,
|
||||
chanx_right_out[12] , chanx_right_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
|
||||
SYNOPSYS_UNCONNECTED_9 } ) ,
|
||||
.out ( chanx_right_out[6] ) , .p0 ( optlc_net_154 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_3 mux_right_track_20 (
|
||||
.in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] ,
|
||||
right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_15_[0] ,
|
||||
chanx_right_out[13] , chanx_right_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
|
||||
SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( chanx_right_out[10] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_4 mux_right_track_28 (
|
||||
.in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] ,
|
||||
right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_17_[0] ,
|
||||
chanx_right_out[15] , chanx_right_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
|
||||
SYNOPSYS_UNCONNECTED_15 } ) ,
|
||||
.out ( chanx_right_out[14] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_5 mux_left_track_3 (
|
||||
.in ( { chany_top_in[10] , chany_top_in[21] , chanx_left_out[7] ,
|
||||
chanx_left_out[21] , left_bottom_grid_pin_3_[0] ,
|
||||
left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
|
||||
SYNOPSYS_UNCONNECTED_18 } ) ,
|
||||
.out ( chanx_left_out[1] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_6 mux_left_track_5 (
|
||||
.in ( { chany_top_in[9] , chany_top_in[20] , chanx_left_out[8] ,
|
||||
chanx_left_out[23] , left_bottom_grid_pin_5_[0] ,
|
||||
left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
|
||||
SYNOPSYS_UNCONNECTED_21 } ) ,
|
||||
.out ( chanx_left_out[2] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_7 mux_left_track_13 (
|
||||
.in ( { chany_top_in[6] , chany_top_in[17] , chany_top_in[28] ,
|
||||
chanx_left_out[12] , chanx_left_out[27] , left_bottom_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
|
||||
SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_8 mux_left_track_21 (
|
||||
.in ( { chany_top_in[5] , chany_top_in[16] , chany_top_in[27] ,
|
||||
chanx_left_out[13] , chanx_left_out[28] , left_bottom_grid_pin_3_[0] ,
|
||||
left_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
|
||||
SYNOPSYS_UNCONNECTED_27 } ) ,
|
||||
.out ( chanx_left_out[10] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7 mux_left_track_29 (
|
||||
.in ( { chany_top_in[4] , chany_top_in[15] , chany_top_in[26] ,
|
||||
chanx_left_out[15] , chanx_left_out[29] , left_bottom_grid_pin_5_[0] ,
|
||||
left_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
|
||||
SYNOPSYS_UNCONNECTED_30 } ) ,
|
||||
.out ( chanx_left_out[14] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem_1 mem_right_track_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem_5 mem_left_track_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem_6 mem_left_track_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem_7 mem_left_track_13 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem_8 mem_left_track_21 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_9_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size6_0 mux_top_track_2 (
|
||||
.in ( { chany_top_out[19] , top_left_grid_pin_48_[0] ,
|
||||
top_left_grid_pin_51_[0] , chanx_right_in[2] , chanx_left_out[7] ,
|
||||
chanx_right_out[7] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 ,
|
||||
SYNOPSYS_UNCONNECTED_33 } ) ,
|
||||
.out ( chany_top_out[1] ) , .p0 ( optlc_net_152 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size6_1 mux_top_track_6 (
|
||||
.in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
|
||||
top_left_grid_pin_50_[0] , chanx_right_in[5] , chanx_left_out[9] ,
|
||||
chanx_right_out[9] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 ,
|
||||
SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( chany_top_out[3] ) , .p0 ( optlc_net_152 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size6 mux_top_track_8 (
|
||||
.in ( { chany_top_out[19] , top_left_grid_pin_48_[0] ,
|
||||
top_left_grid_pin_51_[0] , chanx_right_in[9] , chanx_left_out[11] ,
|
||||
chanx_right_out[11] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 ,
|
||||
SYNOPSYS_UNCONNECTED_39 } ) ,
|
||||
.out ( chany_top_out[4] ) , .p0 ( optlc_net_152 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size6_mem_0 mem_top_track_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size6_mem_1 mem_top_track_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size6_mem mem_top_track_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_0 mux_top_track_4 (
|
||||
.in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
|
||||
chanx_right_in[4] , chanx_left_out[8] , chanx_right_out[8] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
|
||||
SYNOPSYS_UNCONNECTED_42 } ) ,
|
||||
.out ( chany_top_out[2] ) , .p0 ( optlc_net_152 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_1 mux_top_track_10 (
|
||||
.in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
|
||||
chanx_left_out[12] , chanx_right_in[13] , chanx_right_out[12] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 ,
|
||||
SYNOPSYS_UNCONNECTED_45 } ) ,
|
||||
.out ( chany_top_out[5] ) , .p0 ( optlc_net_155 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_2 mux_right_track_36 (
|
||||
.in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] ,
|
||||
right_bottom_grid_pin_7_[0] , chanx_right_out[16] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 ,
|
||||
SYNOPSYS_UNCONNECTED_48 } ) ,
|
||||
.out ( chanx_right_out[18] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_3 mux_left_track_37 (
|
||||
.in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] ,
|
||||
chanx_left_out[16] , left_bottom_grid_pin_7_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 ,
|
||||
SYNOPSYS_UNCONNECTED_51 } ) ,
|
||||
.out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_4 mux_left_track_45 (
|
||||
.in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] ,
|
||||
chanx_left_out[17] , left_bottom_grid_pin_9_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 ,
|
||||
SYNOPSYS_UNCONNECTED_54 } ) ,
|
||||
.out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5 mux_left_track_53 (
|
||||
.in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] ,
|
||||
chanx_left_out[19] , left_bottom_grid_pin_11_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 ,
|
||||
SYNOPSYS_UNCONNECTED_57 } ) ,
|
||||
.out ( chanx_left_out[26] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_mem_0 mem_top_track_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_mem_1 mem_top_track_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_mem_2 mem_right_track_36 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_mem_3 mem_left_track_37 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_9_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_mem_4 mem_left_track_45 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size5_mem mem_left_track_53 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size5_5_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_0 mux_top_track_12 (
|
||||
.in ( { top_left_grid_pin_44_[0] , chanx_left_out[13] ,
|
||||
chanx_right_in[17] , chanx_right_out[13] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_58 , SYNOPSYS_UNCONNECTED_59 ,
|
||||
SYNOPSYS_UNCONNECTED_60 } ) ,
|
||||
.out ( chany_top_out[6] ) , .p0 ( optlc_net_152 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_1 mux_top_track_14 (
|
||||
.in ( { chany_top_out[19] , chanx_left_out[15] , chanx_right_in[21] ,
|
||||
chanx_right_out[15] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 ,
|
||||
SYNOPSYS_UNCONNECTED_63 } ) ,
|
||||
.out ( chany_top_out[7] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_2 mux_top_track_16 (
|
||||
.in ( { top_left_grid_pin_46_[0] , chanx_left_out[16] ,
|
||||
chanx_right_in[25] , chanx_right_out[16] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_64 , SYNOPSYS_UNCONNECTED_65 ,
|
||||
SYNOPSYS_UNCONNECTED_66 } ) ,
|
||||
.out ( chany_top_out[8] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_3 mux_top_track_18 (
|
||||
.in ( { top_left_grid_pin_47_[0] , chanx_left_out[17] ,
|
||||
chanx_right_in[29] , chanx_right_out[17] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 ,
|
||||
SYNOPSYS_UNCONNECTED_69 } ) ,
|
||||
.out ( chany_top_out[9] ) , .p0 ( optlc_net_155 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_4 mux_right_track_44 (
|
||||
.in ( { chany_top_in[8] , chany_top_in[19] , right_bottom_grid_pin_9_[0] ,
|
||||
chanx_right_out[17] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_70 , SYNOPSYS_UNCONNECTED_71 ,
|
||||
SYNOPSYS_UNCONNECTED_72 } ) ,
|
||||
.out ( chanx_right_out[22] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4 mux_right_track_52 (
|
||||
.in ( { chany_top_in[9] , chany_top_in[20] ,
|
||||
right_bottom_grid_pin_11_[0] , chanx_right_out[19] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 ,
|
||||
SYNOPSYS_UNCONNECTED_75 } ) ,
|
||||
.out ( chanx_right_out[26] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_14 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_16 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_18 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_mem_4 mem_right_track_44 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size4_mem mem_right_track_52 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3_0 mux_top_track_20 (
|
||||
.in ( { top_left_grid_pin_48_[0] , chanx_left_out[19] ,
|
||||
chanx_right_out[19] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_76 , SYNOPSYS_UNCONNECTED_77 } ) ,
|
||||
.out ( chany_top_out[10] ) , .p0 ( optlc_net_155 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3_1 mux_top_track_22 (
|
||||
.in ( { top_left_grid_pin_49_[0] , chanx_left_out[20] ,
|
||||
chanx_right_out[20] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_78 , SYNOPSYS_UNCONNECTED_79 } ) ,
|
||||
.out ( chany_top_out[11] ) , .p0 ( optlc_net_156 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3_2 mux_top_track_24 (
|
||||
.in ( { top_left_grid_pin_50_[0] , chanx_left_out[21] ,
|
||||
chanx_right_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 } ) ,
|
||||
.out ( chany_top_out[12] ) , .p0 ( optlc_net_155 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3_3 mux_top_track_26 (
|
||||
.in ( { top_left_grid_pin_51_[0] , chanx_left_out[23] ,
|
||||
chanx_right_out[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_82 , SYNOPSYS_UNCONNECTED_83 } ) ,
|
||||
.out ( chany_top_out[13] ) , .p0 ( optlc_net_155 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3 mux_top_track_36 (
|
||||
.in ( { top_left_grid_pin_44_[0] , chanx_left_out[29] ,
|
||||
chanx_right_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_84 , SYNOPSYS_UNCONNECTED_85 } ) ,
|
||||
.out ( chany_top_out[18] ) , .p0 ( optlc_net_156 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_20 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_22 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3_mem_2 mem_top_track_24 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3_mem_3 mem_top_track_26 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size3_mem mem_top_track_36 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_0 mux_top_track_28 (
|
||||
.in ( { chanx_left_out[24] , chanx_right_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 } ) ,
|
||||
.out ( chany_top_out[14] ) , .p0 ( optlc_net_155 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_1 mux_top_track_30 (
|
||||
.in ( { chanx_left_out[25] , chanx_right_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_88 , SYNOPSYS_UNCONNECTED_89 } ) ,
|
||||
.out ( chany_top_out[15] ) , .p0 ( optlc_net_152 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_2 mux_top_track_32 (
|
||||
.in ( { chanx_left_out[27] , chanx_right_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_90 , SYNOPSYS_UNCONNECTED_91 } ) ,
|
||||
.out ( chany_top_out[16] ) , .p0 ( optlc_net_155 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_3 mux_top_track_34 (
|
||||
.in ( { chanx_left_out[28] , chanx_right_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 } ) ,
|
||||
.out ( chany_top_out[17] ) , .p0 ( optlc_net_156 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_4 mux_top_track_40 (
|
||||
.in ( { top_left_grid_pin_46_[0] , chanx_left_in[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_94 , SYNOPSYS_UNCONNECTED_95 } ) ,
|
||||
.out ( chany_top_out[20] ) , .p0 ( optlc_net_156 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_5 mux_top_track_42 (
|
||||
.in ( { top_left_grid_pin_47_[0] , chanx_left_in[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_96 , SYNOPSYS_UNCONNECTED_97 } ) ,
|
||||
.out ( chany_top_out[21] ) , .p0 ( optlc_net_156 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_6 mux_top_track_44 (
|
||||
.in ( { top_left_grid_pin_48_[0] , chanx_left_in[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 } ) ,
|
||||
.out ( chany_top_out[22] ) , .p0 ( optlc_net_156 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_7 mux_top_track_46 (
|
||||
.in ( { top_left_grid_pin_49_[0] , chanx_left_in[17] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_100 , SYNOPSYS_UNCONNECTED_101 } ) ,
|
||||
.out ( chany_top_out[23] ) , .p0 ( optlc_net_156 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_8 mux_top_track_48 (
|
||||
.in ( { top_left_grid_pin_50_[0] , chanx_left_in[13] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_102 , SYNOPSYS_UNCONNECTED_103 } ) ,
|
||||
.out ( chany_top_out[24] ) , .p0 ( optlc_net_156 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_9 mux_top_track_50 (
|
||||
.in ( { top_left_grid_pin_51_[0] , chanx_left_in[9] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 } ) ,
|
||||
.out ( chany_top_out[25] ) , .p0 ( optlc_net_155 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2 mux_top_track_58 (
|
||||
.in ( { chanx_right_in[0] , chanx_left_in[1] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_10_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_106 , SYNOPSYS_UNCONNECTED_107 } ) ,
|
||||
.out ( chany_top_out[29] ) , .p0 ( optlc_net_154 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_28 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_30 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_32 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_34 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_40 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_42 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_44 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_46 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_48 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_50 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size2_mem mem_top_track_58 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size8_0 mux_right_track_2 (
|
||||
.in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] ,
|
||||
right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_9_[0] ,
|
||||
right_bottom_grid_pin_15_[0] , chanx_right_out[7] ,
|
||||
chanx_right_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size8_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_108 , SYNOPSYS_UNCONNECTED_109 ,
|
||||
SYNOPSYS_UNCONNECTED_110 , SYNOPSYS_UNCONNECTED_111 } ) ,
|
||||
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size8_1 mux_right_track_4 (
|
||||
.in ( { chany_top_in[1] , chany_top_in[12] , chany_top_in[23] ,
|
||||
right_bottom_grid_pin_5_[0] , right_bottom_grid_pin_11_[0] ,
|
||||
right_bottom_grid_pin_17_[0] , chanx_right_out[8] ,
|
||||
chanx_right_out[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size8_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_112 , SYNOPSYS_UNCONNECTED_113 ,
|
||||
SYNOPSYS_UNCONNECTED_114 , SYNOPSYS_UNCONNECTED_115 } ) ,
|
||||
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size8 mux_left_track_1 (
|
||||
.in ( { chany_top_in[0] , chany_top_in[11] , chany_top_in[22] ,
|
||||
chanx_left_out[4] , chanx_left_out[20] , left_bottom_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size8_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_116 , SYNOPSYS_UNCONNECTED_117 ,
|
||||
SYNOPSYS_UNCONNECTED_118 , SYNOPSYS_UNCONNECTED_119 } ) ,
|
||||
.out ( chanx_left_out[0] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size8_mem_0 mem_right_track_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size8_mem_1 mem_right_track_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size8_mem mem_left_track_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size10 mux_right_track_6 (
|
||||
.in ( { chany_top_in[2] , chany_top_in[13] , chany_top_in[24] ,
|
||||
right_bottom_grid_pin_1_[0] , right_bottom_grid_pin_5_[0] ,
|
||||
right_bottom_grid_pin_9_[0] , right_bottom_grid_pin_13_[0] ,
|
||||
right_bottom_grid_pin_17_[0] , chanx_right_out[9] ,
|
||||
chanx_right_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_120 , SYNOPSYS_UNCONNECTED_121 ,
|
||||
SYNOPSYS_UNCONNECTED_122 , SYNOPSYS_UNCONNECTED_123 } ) ,
|
||||
.out ( chanx_right_out[3] ) , .p0 ( optlc_net_153 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size10_mem mem_right_track_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size9_0 mux_right_track_10 (
|
||||
.in ( { chany_top_in[3] , chany_top_in[14] , chany_top_in[25] ,
|
||||
right_bottom_grid_pin_3_[0] , right_bottom_grid_pin_7_[0] ,
|
||||
right_bottom_grid_pin_11_[0] , right_bottom_grid_pin_15_[0] ,
|
||||
chanx_right_out[11] , chanx_right_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size9_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_124 , SYNOPSYS_UNCONNECTED_125 ,
|
||||
SYNOPSYS_UNCONNECTED_126 , SYNOPSYS_UNCONNECTED_127 } ) ,
|
||||
.out ( chanx_right_out[5] ) , .p0 ( optlc_net_153 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size9_1 mux_left_track_7 (
|
||||
.in ( { chany_top_in[8] , chany_top_in[19] , chanx_left_out[9] ,
|
||||
chanx_left_out[24] , left_bottom_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_5_[0] , left_bottom_grid_pin_9_[0] ,
|
||||
left_bottom_grid_pin_13_[0] , left_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size9_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_128 , SYNOPSYS_UNCONNECTED_129 ,
|
||||
SYNOPSYS_UNCONNECTED_130 , SYNOPSYS_UNCONNECTED_131 } ) ,
|
||||
.out ( chanx_left_out[3] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size9 mux_left_track_11 (
|
||||
.in ( { chany_top_in[7] , chany_top_in[18] , chany_top_in[29] ,
|
||||
chanx_left_out[11] , chanx_left_out[25] , left_bottom_grid_pin_3_[0] ,
|
||||
left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_11_[0] ,
|
||||
left_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size9_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_132 , SYNOPSYS_UNCONNECTED_133 ,
|
||||
SYNOPSYS_UNCONNECTED_134 , SYNOPSYS_UNCONNECTED_135 } ) ,
|
||||
.out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size9_mem_1 mem_left_track_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
|
||||
sb_1__0__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size9_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size9_2_sram ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_151 ( .LO ( SYNOPSYS_UNCONNECTED_136 ) ,
|
||||
.HI ( optlc_net_149 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 pReset_N_FTB01 ( .A ( pReset_E_in ) ,
|
||||
.X ( aps_rename_505_ ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 pReset_W_FTB01 ( .A ( pReset_E_in ) ,
|
||||
.X ( pReset_W_out ) ) ;
|
||||
sky130_fd_sc_hd__bufbuf_16 pReset_E_FTB01 ( .A ( pReset_E_in ) ,
|
||||
.X ( pReset_E_out ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_153 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) ,
|
||||
.HI ( optlc_net_150 ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_3_N_FTB01 ( .A ( prog_clk_3_S_in ) ,
|
||||
.X ( aps_rename_506_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 clk_3_N_FTB01 ( .A ( clk_3_S_in ) ,
|
||||
.X ( aps_rename_507_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( top_left_grid_pin_45_[0] ) ,
|
||||
.X ( chany_top_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_12 FTB_50__49 ( .A ( chanx_right_in[3] ) ,
|
||||
.X ( chanx_left_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[6] ) ,
|
||||
.X ( chanx_left_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[7] ) ,
|
||||
.X ( chanx_left_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[8] ) ,
|
||||
.X ( chanx_left_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[10] ) ,
|
||||
.X ( chanx_left_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[11] ) ,
|
||||
.X ( chanx_left_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[12] ) ,
|
||||
.X ( chanx_left_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[14] ) ,
|
||||
.X ( chanx_left_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[15] ) ,
|
||||
.X ( chanx_left_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[16] ) ,
|
||||
.X ( chanx_left_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[18] ) ,
|
||||
.X ( chanx_left_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[19] ) ,
|
||||
.X ( chanx_left_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[20] ) ,
|
||||
.X ( chanx_left_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[22] ) ,
|
||||
.X ( chanx_left_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[23] ) ,
|
||||
.X ( chanx_left_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[24] ) ,
|
||||
.X ( chanx_left_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[26] ) ,
|
||||
.X ( chanx_left_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[27] ) ,
|
||||
.X ( chanx_left_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[28] ) ,
|
||||
.X ( chanx_left_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_left_in[2] ) ,
|
||||
.X ( chany_top_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_left_in[3] ) ,
|
||||
.X ( chanx_right_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[4] ) ,
|
||||
.X ( chany_top_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[5] ) ,
|
||||
.X ( chany_top_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) ,
|
||||
.X ( chanx_right_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) ,
|
||||
.X ( chanx_right_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) ,
|
||||
.X ( chanx_right_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) ,
|
||||
.X ( chanx_right_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) ,
|
||||
.X ( chanx_right_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) ,
|
||||
.X ( chanx_right_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) ,
|
||||
.X ( chanx_right_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) ,
|
||||
.X ( chanx_right_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_81__80 ( .A ( chanx_left_in[16] ) ,
|
||||
.X ( chanx_right_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) ,
|
||||
.X ( chanx_right_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) ,
|
||||
.X ( chanx_right_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) ,
|
||||
.X ( chanx_right_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) ,
|
||||
.X ( chanx_right_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) ,
|
||||
.X ( chanx_right_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) ,
|
||||
.X ( chanx_right_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) ,
|
||||
.X ( chanx_right_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) ,
|
||||
.X ( chanx_right_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) ,
|
||||
.X ( chanx_right_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_91__90 ( .A ( SC_IN_TOP ) , .X ( ropt_net_176 ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_137 ( .A ( BUF_net_138 ) ,
|
||||
.Y ( Test_en_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_138 ( .A ( Test_en_S_in ) , .Y ( BUF_net_138 ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_139 ( .A ( BUF_net_140 ) , .Y ( pReset_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_140 ( .A ( aps_rename_505_ ) ,
|
||||
.Y ( BUF_net_140 ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_141 ( .A ( BUF_net_142 ) , .Y ( Reset_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_142 ( .A ( Reset_S_in ) , .Y ( BUF_net_142 ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_143 ( .A ( BUF_net_144 ) ,
|
||||
.Y ( prog_clk_3_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_144 ( .A ( aps_rename_506_ ) ,
|
||||
.Y ( BUF_net_144 ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_145 ( .A ( BUF_net_146 ) , .Y ( clk_3_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_146 ( .A ( aps_rename_507_ ) ,
|
||||
.Y ( BUF_net_146 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) ,
|
||||
.HI ( optlc_net_151 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) ,
|
||||
.HI ( optlc_net_152 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_162 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) ,
|
||||
.HI ( optlc_net_153 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_164 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) ,
|
||||
.HI ( optlc_net_154 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_166 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) ,
|
||||
.HI ( optlc_net_155 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_168 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) ,
|
||||
.HI ( optlc_net_156 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1359 ( .A ( ropt_net_176 ) ,
|
||||
.X ( SC_OUT_TOP ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,862 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module sb_1__2_ ( pReset , chanx_right_in , right_top_grid_pin_1_ ,
|
||||
right_bottom_grid_pin_36_ , right_bottom_grid_pin_37_ ,
|
||||
right_bottom_grid_pin_38_ , right_bottom_grid_pin_39_ ,
|
||||
right_bottom_grid_pin_40_ , right_bottom_grid_pin_41_ ,
|
||||
right_bottom_grid_pin_42_ , right_bottom_grid_pin_43_ , chany_bottom_in ,
|
||||
bottom_left_grid_pin_44_ , bottom_left_grid_pin_45_ ,
|
||||
bottom_left_grid_pin_46_ , bottom_left_grid_pin_47_ ,
|
||||
bottom_left_grid_pin_48_ , bottom_left_grid_pin_49_ ,
|
||||
bottom_left_grid_pin_50_ , bottom_left_grid_pin_51_ , chanx_left_in ,
|
||||
left_top_grid_pin_1_ , left_bottom_grid_pin_36_ ,
|
||||
left_bottom_grid_pin_37_ , left_bottom_grid_pin_38_ ,
|
||||
left_bottom_grid_pin_39_ , left_bottom_grid_pin_40_ ,
|
||||
left_bottom_grid_pin_41_ , left_bottom_grid_pin_42_ ,
|
||||
left_bottom_grid_pin_43_ , ccff_head , chanx_right_out ,
|
||||
chany_bottom_out , chanx_left_out , ccff_tail , SC_IN_BOT , SC_OUT_BOT ,
|
||||
pReset_S_in , pReset_E_in , pReset_W_in , pReset_W_out , pReset_E_out ,
|
||||
prog_clk_0_S_in ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chanx_right_in ;
|
||||
input [0:0] right_top_grid_pin_1_ ;
|
||||
input [0:0] right_bottom_grid_pin_36_ ;
|
||||
input [0:0] right_bottom_grid_pin_37_ ;
|
||||
input [0:0] right_bottom_grid_pin_38_ ;
|
||||
input [0:0] right_bottom_grid_pin_39_ ;
|
||||
input [0:0] right_bottom_grid_pin_40_ ;
|
||||
input [0:0] right_bottom_grid_pin_41_ ;
|
||||
input [0:0] right_bottom_grid_pin_42_ ;
|
||||
input [0:0] right_bottom_grid_pin_43_ ;
|
||||
input [0:29] chany_bottom_in ;
|
||||
input [0:0] bottom_left_grid_pin_44_ ;
|
||||
input [0:0] bottom_left_grid_pin_45_ ;
|
||||
input [0:0] bottom_left_grid_pin_46_ ;
|
||||
input [0:0] bottom_left_grid_pin_47_ ;
|
||||
input [0:0] bottom_left_grid_pin_48_ ;
|
||||
input [0:0] bottom_left_grid_pin_49_ ;
|
||||
input [0:0] bottom_left_grid_pin_50_ ;
|
||||
input [0:0] bottom_left_grid_pin_51_ ;
|
||||
input [0:29] chanx_left_in ;
|
||||
input [0:0] left_top_grid_pin_1_ ;
|
||||
input [0:0] left_bottom_grid_pin_36_ ;
|
||||
input [0:0] left_bottom_grid_pin_37_ ;
|
||||
input [0:0] left_bottom_grid_pin_38_ ;
|
||||
input [0:0] left_bottom_grid_pin_39_ ;
|
||||
input [0:0] left_bottom_grid_pin_40_ ;
|
||||
input [0:0] left_bottom_grid_pin_41_ ;
|
||||
input [0:0] left_bottom_grid_pin_42_ ;
|
||||
input [0:0] left_bottom_grid_pin_43_ ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chanx_right_out ;
|
||||
output [0:29] chany_bottom_out ;
|
||||
output [0:29] chanx_left_out ;
|
||||
output [0:0] ccff_tail ;
|
||||
input SC_IN_BOT ;
|
||||
output SC_OUT_BOT ;
|
||||
input pReset_S_in ;
|
||||
input pReset_E_in ;
|
||||
input pReset_W_in ;
|
||||
output pReset_W_out ;
|
||||
output pReset_E_out ;
|
||||
input prog_clk_0_S_in ;
|
||||
|
||||
wire ropt_net_166 ;
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size10_1_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size10_mem_1_ccff_tail ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_6_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_7_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size5_4_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size5_mem_4_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size6_3_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size6_mem_3_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_5_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_6_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_7_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size7_8_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size7_mem_8_ccff_tail ;
|
||||
wire [0:3] mux_tree_tapbuf_size8_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size8_1_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size8_2_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size8_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size8_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size8_mem_2_ccff_tail ;
|
||||
wire [0:3] mux_tree_tapbuf_size9_0_sram ;
|
||||
wire [0:3] mux_tree_tapbuf_size9_1_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size9_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size9_mem_1_ccff_tail ;
|
||||
|
||||
assign pReset_E_in = pReset_S_in ;
|
||||
assign pReset_E_in = pReset_W_in ;
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
sb_1__2__mux_tree_tapbuf_size7_0 mux_right_track_0 (
|
||||
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_38_[0] ,
|
||||
right_bottom_grid_pin_41_[0] , chany_bottom_in[9] ,
|
||||
chany_bottom_in[20] , chanx_right_out[4] , chanx_right_out[20] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 } ) ,
|
||||
.out ( chanx_right_out[0] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_1 mux_right_track_2 (
|
||||
.in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_39_[0] ,
|
||||
right_bottom_grid_pin_42_[0] , chany_bottom_in[8] ,
|
||||
chany_bottom_in[19] , chanx_right_out[7] , chanx_right_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
|
||||
SYNOPSYS_UNCONNECTED_6 } ) ,
|
||||
.out ( chanx_right_out[1] ) , .p0 ( optlc_net_150 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_2 mux_right_track_12 (
|
||||
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_41_[0] ,
|
||||
chany_bottom_in[4] , chany_bottom_in[15] , chany_bottom_in[26] ,
|
||||
chanx_right_out[12] , chanx_right_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
|
||||
SYNOPSYS_UNCONNECTED_9 } ) ,
|
||||
.out ( chanx_right_out[6] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_3 mux_right_track_20 (
|
||||
.in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_42_[0] ,
|
||||
chany_bottom_in[3] , chany_bottom_in[14] , chany_bottom_in[25] ,
|
||||
chanx_right_out[13] , chanx_right_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
|
||||
SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( chanx_right_out[10] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_4 mux_right_track_28 (
|
||||
.in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_43_[0] ,
|
||||
chany_bottom_in[2] , chany_bottom_in[13] , chany_bottom_in[24] ,
|
||||
chanx_right_out[15] , chanx_right_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
|
||||
SYNOPSYS_UNCONNECTED_15 } ) ,
|
||||
.out ( chanx_right_out[14] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_5 mux_left_track_1 (
|
||||
.in ( { chanx_left_out[4] , chanx_left_out[20] , chany_bottom_in[10] ,
|
||||
chany_bottom_in[21] , left_top_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_38_[0] , left_bottom_grid_pin_41_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
|
||||
SYNOPSYS_UNCONNECTED_18 } ) ,
|
||||
.out ( chanx_left_out[0] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_6 mux_left_track_13 (
|
||||
.in ( { chanx_left_out[12] , chanx_left_out[27] , chany_bottom_in[4] ,
|
||||
chany_bottom_in[15] , chany_bottom_in[26] , left_top_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_41_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
|
||||
SYNOPSYS_UNCONNECTED_21 } ) ,
|
||||
.out ( chanx_left_out[6] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_7 mux_left_track_21 (
|
||||
.in ( { chanx_left_out[13] , chanx_left_out[28] , chany_bottom_in[5] ,
|
||||
chany_bottom_in[16] , chany_bottom_in[27] ,
|
||||
left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_42_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
|
||||
SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( chanx_left_out[10] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7 mux_left_track_29 (
|
||||
.in ( { chanx_left_out[15] , chanx_left_out[29] , chany_bottom_in[6] ,
|
||||
chany_bottom_in[17] , chany_bottom_in[28] ,
|
||||
left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_43_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size7_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
|
||||
SYNOPSYS_UNCONNECTED_27 } ) ,
|
||||
.out ( chanx_left_out[14] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_mem_0 mem_right_track_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_0_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_mem_1 mem_right_track_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_1_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_mem_2 mem_right_track_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_2_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_mem_3 mem_right_track_20 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_3_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_mem_4 mem_right_track_28 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_4_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_mem_5 mem_left_track_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_5_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_mem_6 mem_left_track_13 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_6_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_mem_7 mem_left_track_21 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_7_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size7_mem mem_left_track_29 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size7_8_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size8_0 mux_right_track_4 (
|
||||
.in ( { right_bottom_grid_pin_37_[0] , right_bottom_grid_pin_40_[0] ,
|
||||
right_bottom_grid_pin_43_[0] , chany_bottom_in[7] ,
|
||||
chany_bottom_in[18] , chany_bottom_in[29] , chanx_right_out[8] ,
|
||||
chanx_right_out[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size8_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
|
||||
SYNOPSYS_UNCONNECTED_30 , SYNOPSYS_UNCONNECTED_31 } ) ,
|
||||
.out ( chanx_right_out[2] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size8_1 mux_left_track_3 (
|
||||
.in ( { chanx_left_out[7] , chanx_left_out[21] , chany_bottom_in[0] ,
|
||||
chany_bottom_in[11] , chany_bottom_in[22] ,
|
||||
left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_39_[0] ,
|
||||
left_bottom_grid_pin_42_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size8_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_32 , SYNOPSYS_UNCONNECTED_33 ,
|
||||
SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 } ) ,
|
||||
.out ( chanx_left_out[1] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size8 mux_left_track_5 (
|
||||
.in ( { chanx_left_out[8] , chanx_left_out[23] , chany_bottom_in[1] ,
|
||||
chany_bottom_in[12] , chany_bottom_in[23] ,
|
||||
left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_40_[0] ,
|
||||
left_bottom_grid_pin_43_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size8_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_36 , SYNOPSYS_UNCONNECTED_37 ,
|
||||
SYNOPSYS_UNCONNECTED_38 , SYNOPSYS_UNCONNECTED_39 } ) ,
|
||||
.out ( chanx_left_out[2] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size8_mem_0 mem_right_track_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size8_0_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size8_mem_1 mem_left_track_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size8_1_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size8_mem mem_left_track_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size8_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size8_2_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size10_0 mux_right_track_6 (
|
||||
.in ( { right_top_grid_pin_1_[0] , right_bottom_grid_pin_37_[0] ,
|
||||
right_bottom_grid_pin_39_[0] , right_bottom_grid_pin_41_[0] ,
|
||||
right_bottom_grid_pin_43_[0] , chany_bottom_in[6] ,
|
||||
chany_bottom_in[17] , chany_bottom_in[28] , chanx_right_out[9] ,
|
||||
chanx_right_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_40 , SYNOPSYS_UNCONNECTED_41 ,
|
||||
SYNOPSYS_UNCONNECTED_42 , SYNOPSYS_UNCONNECTED_43 } ) ,
|
||||
.out ( chanx_right_out[3] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size10 mux_left_track_7 (
|
||||
.in ( { chanx_left_out[9] , chanx_left_out[24] , chany_bottom_in[2] ,
|
||||
chany_bottom_in[13] , chany_bottom_in[24] , left_top_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_37_[0] , left_bottom_grid_pin_39_[0] ,
|
||||
left_bottom_grid_pin_41_[0] , left_bottom_grid_pin_43_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size10_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_44 , SYNOPSYS_UNCONNECTED_45 ,
|
||||
SYNOPSYS_UNCONNECTED_46 , SYNOPSYS_UNCONNECTED_47 } ) ,
|
||||
.out ( chanx_left_out[3] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size10_mem_0 mem_right_track_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size8_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_0_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size10_mem mem_left_track_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size8_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size10_1_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size9_0 mux_right_track_10 (
|
||||
.in ( { right_bottom_grid_pin_36_[0] , right_bottom_grid_pin_38_[0] ,
|
||||
right_bottom_grid_pin_40_[0] , right_bottom_grid_pin_42_[0] ,
|
||||
chany_bottom_in[5] , chany_bottom_in[16] , chany_bottom_in[27] ,
|
||||
chanx_right_out[11] , chanx_right_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size9_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_48 , SYNOPSYS_UNCONNECTED_49 ,
|
||||
SYNOPSYS_UNCONNECTED_50 , SYNOPSYS_UNCONNECTED_51 } ) ,
|
||||
.out ( chanx_right_out[5] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size9 mux_left_track_11 (
|
||||
.in ( { chanx_left_out[11] , chanx_left_out[25] , chany_bottom_in[3] ,
|
||||
chany_bottom_in[14] , chany_bottom_in[25] ,
|
||||
left_bottom_grid_pin_36_[0] , left_bottom_grid_pin_38_[0] ,
|
||||
left_bottom_grid_pin_40_[0] , left_bottom_grid_pin_42_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size9_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_52 , SYNOPSYS_UNCONNECTED_53 ,
|
||||
SYNOPSYS_UNCONNECTED_54 , SYNOPSYS_UNCONNECTED_55 } ) ,
|
||||
.out ( chanx_left_out[5] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size9_mem_0 mem_right_track_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size9_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size9_0_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size9_mem mem_left_track_11 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size10_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size9_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size9_1_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5_0 mux_right_track_36 (
|
||||
.in ( { right_bottom_grid_pin_38_[0] , chany_bottom_in[1] ,
|
||||
chany_bottom_in[12] , chany_bottom_in[23] , chanx_right_out[16] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_56 , SYNOPSYS_UNCONNECTED_57 ,
|
||||
SYNOPSYS_UNCONNECTED_58 } ) ,
|
||||
.out ( chanx_right_out[18] ) , .p0 ( optlc_net_148 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5_1 mux_right_track_44 (
|
||||
.in ( { right_bottom_grid_pin_39_[0] , chany_bottom_in[0] ,
|
||||
chany_bottom_in[11] , chany_bottom_in[22] , ropt_net_166 } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 ,
|
||||
SYNOPSYS_UNCONNECTED_61 } ) ,
|
||||
.out ( chanx_right_out[22] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5_2 mux_bottom_track_5 (
|
||||
.in ( { chanx_left_out[8] , bottom_left_grid_pin_46_[0] ,
|
||||
bottom_left_grid_pin_49_[0] , chanx_left_in[4] , chanx_right_out[8] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_62 , SYNOPSYS_UNCONNECTED_63 ,
|
||||
SYNOPSYS_UNCONNECTED_64 } ) ,
|
||||
.out ( chany_bottom_out[2] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5_3 mux_bottom_track_11 (
|
||||
.in ( { chanx_left_out[12] , bottom_left_grid_pin_46_[0] ,
|
||||
bottom_left_grid_pin_49_[0] , chanx_right_out[12] ,
|
||||
chanx_left_in[13] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 ,
|
||||
SYNOPSYS_UNCONNECTED_67 } ) ,
|
||||
.out ( chany_bottom_out[5] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5 mux_left_track_37 (
|
||||
.in ( { chanx_left_out[16] , chany_bottom_in[7] , chany_bottom_in[18] ,
|
||||
chany_bottom_in[29] , left_bottom_grid_pin_38_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size5_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_68 , SYNOPSYS_UNCONNECTED_69 ,
|
||||
SYNOPSYS_UNCONNECTED_70 } ) ,
|
||||
.out ( chanx_left_out[18] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5_mem_0 mem_right_track_36 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_0_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5_mem_1 mem_right_track_44 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_1_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5_mem_2 mem_bottom_track_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_2_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5_mem_3 mem_bottom_track_11 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_3_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size5_mem mem_left_track_37 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size7_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size5_4_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_0 mux_right_track_52 (
|
||||
.in ( { right_bottom_grid_pin_40_[0] , chany_bottom_in[10] ,
|
||||
chany_bottom_in[21] , chanx_right_out[19] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 ,
|
||||
SYNOPSYS_UNCONNECTED_73 } ) ,
|
||||
.out ( chanx_right_out[26] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_1 mux_bottom_track_13 (
|
||||
.in ( { chanx_left_out[13] , bottom_left_grid_pin_44_[0] ,
|
||||
chanx_right_out[13] , chanx_left_in[17] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_74 , SYNOPSYS_UNCONNECTED_75 ,
|
||||
SYNOPSYS_UNCONNECTED_76 } ) ,
|
||||
.out ( chany_bottom_out[6] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_2 mux_bottom_track_15 (
|
||||
.in ( { chanx_left_out[15] , bottom_left_grid_pin_45_[0] ,
|
||||
chanx_right_out[15] , chanx_left_in[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 ,
|
||||
SYNOPSYS_UNCONNECTED_79 } ) ,
|
||||
.out ( chany_bottom_out[7] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_3 mux_bottom_track_17 (
|
||||
.in ( { chanx_left_out[16] , bottom_left_grid_pin_46_[0] ,
|
||||
chanx_right_out[16] , chanx_left_in[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_80 , SYNOPSYS_UNCONNECTED_81 ,
|
||||
SYNOPSYS_UNCONNECTED_82 } ) ,
|
||||
.out ( chany_bottom_out[8] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_4 mux_bottom_track_19 (
|
||||
.in ( { chanx_left_out[17] , bottom_left_grid_pin_47_[0] , ropt_net_166 ,
|
||||
chanx_left_in[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 ,
|
||||
SYNOPSYS_UNCONNECTED_85 } ) ,
|
||||
.out ( chany_bottom_out[9] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_5 mux_bottom_track_37 (
|
||||
.in ( { chanx_left_out[29] , chanx_right_in[29] ,
|
||||
bottom_left_grid_pin_44_[0] , chanx_right_out[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_86 , SYNOPSYS_UNCONNECTED_87 ,
|
||||
SYNOPSYS_UNCONNECTED_88 } ) ,
|
||||
.out ( chany_bottom_out[18] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_6 mux_left_track_45 (
|
||||
.in ( { chanx_left_out[17] , chany_bottom_in[8] , chany_bottom_in[19] ,
|
||||
left_bottom_grid_pin_39_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 ,
|
||||
SYNOPSYS_UNCONNECTED_91 } ) ,
|
||||
.out ( chanx_left_out[22] ) , .p0 ( optlc_net_151 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4 mux_left_track_53 (
|
||||
.in ( { chanx_left_out[19] , chany_bottom_in[9] , chany_bottom_in[20] ,
|
||||
left_bottom_grid_pin_40_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_92 , SYNOPSYS_UNCONNECTED_93 ,
|
||||
SYNOPSYS_UNCONNECTED_94 } ) ,
|
||||
.out ( chanx_left_out[26] ) , .p0 ( optlc_net_152 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_mem_0 mem_right_track_52 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_mem_1 mem_bottom_track_13 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_mem_2 mem_bottom_track_15 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_mem_3 mem_bottom_track_17 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_mem_4 mem_bottom_track_19 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_mem_5 mem_bottom_track_37 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_mem_6 mem_left_track_45 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size4_mem mem_left_track_53 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size6_0 mux_bottom_track_1 (
|
||||
.in ( { chanx_left_out[4] , bottom_left_grid_pin_44_[0] ,
|
||||
bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] ,
|
||||
chanx_left_in[1] , chanx_right_out[4] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 ,
|
||||
SYNOPSYS_UNCONNECTED_97 } ) ,
|
||||
.out ( chany_bottom_out[0] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size6_1 mux_bottom_track_3 (
|
||||
.in ( { chanx_left_out[7] , bottom_left_grid_pin_45_[0] ,
|
||||
bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] ,
|
||||
chanx_left_in[2] , chanx_right_out[7] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_98 , SYNOPSYS_UNCONNECTED_99 ,
|
||||
SYNOPSYS_UNCONNECTED_100 } ) ,
|
||||
.out ( chany_bottom_out[1] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size6_2 mux_bottom_track_7 (
|
||||
.in ( { chanx_left_out[9] , bottom_left_grid_pin_44_[0] ,
|
||||
bottom_left_grid_pin_47_[0] , bottom_left_grid_pin_50_[0] ,
|
||||
chanx_left_in[5] , chanx_right_out[9] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 ,
|
||||
SYNOPSYS_UNCONNECTED_103 } ) ,
|
||||
.out ( chany_bottom_out[3] ) , .p0 ( optlc_net_152 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size6 mux_bottom_track_9 (
|
||||
.in ( { chanx_left_out[11] , bottom_left_grid_pin_45_[0] ,
|
||||
bottom_left_grid_pin_48_[0] , bottom_left_grid_pin_51_[0] ,
|
||||
chanx_left_in[9] , chanx_right_out[11] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size6_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_104 , SYNOPSYS_UNCONNECTED_105 ,
|
||||
SYNOPSYS_UNCONNECTED_106 } ) ,
|
||||
.out ( chany_bottom_out[4] ) , .p0 ( optlc_net_146 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size6_mem_0 mem_bottom_track_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_0_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size6_mem_1 mem_bottom_track_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_1_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size6_mem_2 mem_bottom_track_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size5_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_2_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size6_mem mem_bottom_track_9 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size6_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size6_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size6_3_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size3_0 mux_bottom_track_21 (
|
||||
.in ( { chanx_left_out[19] , bottom_left_grid_pin_48_[0] ,
|
||||
chanx_right_out[19] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
|
||||
.out ( chany_bottom_out[10] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size3_1 mux_bottom_track_23 (
|
||||
.in ( { chanx_left_out[20] , bottom_left_grid_pin_49_[0] ,
|
||||
chanx_right_out[20] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
|
||||
.out ( chany_bottom_out[11] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size3_2 mux_bottom_track_25 (
|
||||
.in ( { chanx_left_out[21] , bottom_left_grid_pin_50_[0] ,
|
||||
chanx_right_out[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
|
||||
.out ( chany_bottom_out[12] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size3 mux_bottom_track_27 (
|
||||
.in ( { chanx_left_out[23] , bottom_left_grid_pin_51_[0] ,
|
||||
chanx_right_out[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
|
||||
.out ( chany_bottom_out[13] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size3_mem_0 mem_bottom_track_21 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size3_mem_1 mem_bottom_track_23 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size3_mem_2 mem_bottom_track_25 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size3_mem mem_bottom_track_27 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_0 mux_bottom_track_29 (
|
||||
.in ( { chanx_left_out[24] , chanx_right_out[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
|
||||
.out ( chany_bottom_out[14] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_1 mux_bottom_track_31 (
|
||||
.in ( { chanx_left_out[25] , chanx_right_out[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
|
||||
.out ( chany_bottom_out[15] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_2 mux_bottom_track_33 (
|
||||
.in ( { chanx_left_out[27] , chanx_right_out[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_119 , SYNOPSYS_UNCONNECTED_120 } ) ,
|
||||
.out ( chany_bottom_out[16] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_3 mux_bottom_track_35 (
|
||||
.in ( { chanx_left_out[28] , chanx_right_out[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_121 , SYNOPSYS_UNCONNECTED_122 } ) ,
|
||||
.out ( chany_bottom_out[17] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_4 mux_bottom_track_39 (
|
||||
.in ( { chanx_right_in[25] , bottom_left_grid_pin_45_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_123 , SYNOPSYS_UNCONNECTED_124 } ) ,
|
||||
.out ( chany_bottom_out[19] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_5 mux_bottom_track_41 (
|
||||
.in ( { chanx_right_in[21] , bottom_left_grid_pin_46_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_125 , SYNOPSYS_UNCONNECTED_126 } ) ,
|
||||
.out ( chany_bottom_out[20] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_6 mux_bottom_track_43 (
|
||||
.in ( { chanx_right_in[17] , bottom_left_grid_pin_47_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_127 , SYNOPSYS_UNCONNECTED_128 } ) ,
|
||||
.out ( chany_bottom_out[21] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_7 mux_bottom_track_45 (
|
||||
.in ( { chanx_right_in[13] , bottom_left_grid_pin_48_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_129 , SYNOPSYS_UNCONNECTED_130 } ) ,
|
||||
.out ( chany_bottom_out[22] ) , .p0 ( optlc_net_147 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_8 mux_bottom_track_47 (
|
||||
.in ( { chanx_right_in[9] , bottom_left_grid_pin_49_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_131 , SYNOPSYS_UNCONNECTED_132 } ) ,
|
||||
.out ( chany_bottom_out[23] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_9 mux_bottom_track_49 (
|
||||
.in ( { chanx_right_in[5] , bottom_left_grid_pin_50_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_133 , SYNOPSYS_UNCONNECTED_134 } ) ,
|
||||
.out ( chany_bottom_out[24] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2 mux_bottom_track_51 (
|
||||
.in ( { chanx_right_in[4] , bottom_left_grid_pin_51_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_10_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_135 , SYNOPSYS_UNCONNECTED_136 } ) ,
|
||||
.out ( chany_bottom_out[25] ) , .p0 ( optlc_net_149 ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_0 mem_bottom_track_29 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_1 mem_bottom_track_31 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_2 mem_bottom_track_33 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_3 mem_bottom_track_35 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_4 mem_bottom_track_39 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_5 mem_bottom_track_41 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_6 mem_bottom_track_43 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_7 mem_bottom_track_45 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_8 mem_bottom_track_47 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem_9 mem_bottom_track_49 (
|
||||
.pReset ( pReset ) , .prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
|
||||
sb_1__2__mux_tree_tapbuf_size2_mem mem_bottom_track_51 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_E_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 pReset_W_FTB01 ( .A ( pReset_E_in ) ,
|
||||
.X ( net_net_137 ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 pReset_E_FTB01 ( .A ( pReset_E_in ) ,
|
||||
.X ( aps_rename_505_ ) ) ;
|
||||
sky130_fd_sc_hd__buf_16 prog_clk_0_FTB00 ( .A ( prog_clk_0_S_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_49__48 ( .A ( chanx_right_in[0] ) ,
|
||||
.X ( chany_bottom_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_50__49 ( .A ( chanx_right_in[1] ) ,
|
||||
.X ( chany_bottom_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_51__50 ( .A ( chanx_right_in[2] ) ,
|
||||
.X ( chany_bottom_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_52__51 ( .A ( chanx_right_in[3] ) ,
|
||||
.X ( chanx_left_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_53__52 ( .A ( chanx_right_in[6] ) ,
|
||||
.X ( chanx_left_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_right_in[7] ) ,
|
||||
.X ( chanx_left_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_right_in[8] ) ,
|
||||
.X ( chanx_left_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_right_in[10] ) ,
|
||||
.X ( chanx_left_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_right_in[11] ) ,
|
||||
.X ( chanx_left_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_right_in[12] ) ,
|
||||
.X ( chanx_left_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_59__58 ( .A ( chanx_right_in[14] ) ,
|
||||
.X ( chanx_left_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_right_in[15] ) ,
|
||||
.X ( chanx_left_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_61__60 ( .A ( chanx_right_in[16] ) ,
|
||||
.X ( chanx_left_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_62__61 ( .A ( chanx_right_in[18] ) ,
|
||||
.X ( chanx_left_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_63__62 ( .A ( chanx_right_in[19] ) ,
|
||||
.X ( chanx_left_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_64__63 ( .A ( chanx_right_in[20] ) ,
|
||||
.X ( chanx_left_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_65__64 ( .A ( chanx_right_in[22] ) ,
|
||||
.X ( chanx_left_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_66__65 ( .A ( chanx_right_in[23] ) ,
|
||||
.X ( chanx_left_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_67__66 ( .A ( chanx_right_in[24] ) ,
|
||||
.X ( chanx_left_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_68__67 ( .A ( chanx_right_in[26] ) ,
|
||||
.X ( chanx_left_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_69__68 ( .A ( chanx_right_in[27] ) ,
|
||||
.X ( chanx_left_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_70__69 ( .A ( chanx_right_in[28] ) ,
|
||||
.X ( chanx_left_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_71__70 ( .A ( chanx_left_in[0] ) ,
|
||||
.X ( chany_bottom_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_72__71 ( .A ( chanx_left_in[3] ) ,
|
||||
.X ( chanx_right_out[4] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_73__72 ( .A ( chanx_left_in[6] ) ,
|
||||
.X ( chanx_right_out[7] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_74__73 ( .A ( chanx_left_in[7] ) ,
|
||||
.X ( chanx_right_out[8] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_75__74 ( .A ( chanx_left_in[8] ) ,
|
||||
.X ( chanx_right_out[9] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_76__75 ( .A ( chanx_left_in[10] ) ,
|
||||
.X ( chanx_right_out[11] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_77__76 ( .A ( chanx_left_in[11] ) ,
|
||||
.X ( chanx_right_out[12] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_78__77 ( .A ( chanx_left_in[12] ) ,
|
||||
.X ( chanx_right_out[13] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_79__78 ( .A ( chanx_left_in[14] ) ,
|
||||
.X ( chanx_right_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_80__79 ( .A ( chanx_left_in[15] ) ,
|
||||
.X ( chanx_right_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 FTB_81__80 ( .A ( chanx_left_in[16] ) ,
|
||||
.X ( ropt_net_166 ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_82__81 ( .A ( chanx_left_in[18] ) ,
|
||||
.X ( chanx_right_out[19] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_83__82 ( .A ( chanx_left_in[19] ) ,
|
||||
.X ( chanx_right_out[20] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_84__83 ( .A ( chanx_left_in[20] ) ,
|
||||
.X ( chanx_right_out[21] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_85__84 ( .A ( chanx_left_in[22] ) ,
|
||||
.X ( chanx_right_out[23] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_86__85 ( .A ( chanx_left_in[23] ) ,
|
||||
.X ( chanx_right_out[24] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_87__86 ( .A ( chanx_left_in[24] ) ,
|
||||
.X ( chanx_right_out[25] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_88__87 ( .A ( chanx_left_in[26] ) ,
|
||||
.X ( chanx_right_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_89__88 ( .A ( chanx_left_in[27] ) ,
|
||||
.X ( chanx_right_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_90__89 ( .A ( chanx_left_in[28] ) ,
|
||||
.X ( chanx_right_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_91__90 ( .A ( SC_IN_BOT ) , .X ( SC_OUT_BOT ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 BUFT_RR_137 ( .A ( net_net_137 ) ,
|
||||
.X ( pReset_W_out ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_148 ( .LO ( SYNOPSYS_UNCONNECTED_137 ) ,
|
||||
.HI ( optlc_net_146 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_150 ( .LO ( SYNOPSYS_UNCONNECTED_138 ) ,
|
||||
.HI ( optlc_net_147 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_152 ( .LO ( SYNOPSYS_UNCONNECTED_139 ) ,
|
||||
.HI ( optlc_net_148 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_155 ( .LO ( SYNOPSYS_UNCONNECTED_140 ) ,
|
||||
.HI ( optlc_net_149 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_157 ( .LO ( SYNOPSYS_UNCONNECTED_141 ) ,
|
||||
.HI ( optlc_net_150 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_159 ( .LO ( SYNOPSYS_UNCONNECTED_142 ) ,
|
||||
.HI ( optlc_net_151 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_161 ( .LO ( SYNOPSYS_UNCONNECTED_143 ) ,
|
||||
.HI ( optlc_net_152 ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 ZBUF_6_f_inst_162 ( .A ( aps_rename_505_ ) ,
|
||||
.X ( pReset_E_out ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 ropt_mt_inst_1399 ( .A ( ropt_net_166 ) ,
|
||||
.X ( chanx_right_out[17] ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,744 @@
|
|||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
//
|
||||
module sb_2__0_ ( pReset , chany_top_in , top_left_grid_pin_44_ ,
|
||||
top_left_grid_pin_45_ , top_left_grid_pin_46_ , top_left_grid_pin_47_ ,
|
||||
top_left_grid_pin_48_ , top_left_grid_pin_49_ , top_left_grid_pin_50_ ,
|
||||
top_left_grid_pin_51_ , top_right_grid_pin_1_ , chanx_left_in ,
|
||||
left_bottom_grid_pin_1_ , left_bottom_grid_pin_3_ ,
|
||||
left_bottom_grid_pin_5_ , left_bottom_grid_pin_7_ ,
|
||||
left_bottom_grid_pin_9_ , left_bottom_grid_pin_11_ ,
|
||||
left_bottom_grid_pin_13_ , left_bottom_grid_pin_15_ ,
|
||||
left_bottom_grid_pin_17_ , ccff_head , chany_top_out , chanx_left_out ,
|
||||
ccff_tail , pReset_W_in , pReset_N_out , prog_clk_0_N_in ) ;
|
||||
input [0:0] pReset ;
|
||||
input [0:29] chany_top_in ;
|
||||
input [0:0] top_left_grid_pin_44_ ;
|
||||
input [0:0] top_left_grid_pin_45_ ;
|
||||
input [0:0] top_left_grid_pin_46_ ;
|
||||
input [0:0] top_left_grid_pin_47_ ;
|
||||
input [0:0] top_left_grid_pin_48_ ;
|
||||
input [0:0] top_left_grid_pin_49_ ;
|
||||
input [0:0] top_left_grid_pin_50_ ;
|
||||
input [0:0] top_left_grid_pin_51_ ;
|
||||
input [0:0] top_right_grid_pin_1_ ;
|
||||
input [0:29] chanx_left_in ;
|
||||
input [0:0] left_bottom_grid_pin_1_ ;
|
||||
input [0:0] left_bottom_grid_pin_3_ ;
|
||||
input [0:0] left_bottom_grid_pin_5_ ;
|
||||
input [0:0] left_bottom_grid_pin_7_ ;
|
||||
input [0:0] left_bottom_grid_pin_9_ ;
|
||||
input [0:0] left_bottom_grid_pin_11_ ;
|
||||
input [0:0] left_bottom_grid_pin_13_ ;
|
||||
input [0:0] left_bottom_grid_pin_15_ ;
|
||||
input [0:0] left_bottom_grid_pin_17_ ;
|
||||
input [0:0] ccff_head ;
|
||||
output [0:29] chany_top_out ;
|
||||
output [0:29] chanx_left_out ;
|
||||
output [0:0] ccff_tail ;
|
||||
input pReset_W_in ;
|
||||
output pReset_N_out ;
|
||||
input prog_clk_0_N_in ;
|
||||
|
||||
wire [0:0] prog_clk ;
|
||||
wire prog_clk_0 ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_10_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_11_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_12_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_13_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_14_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_15_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_16_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_17_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_18_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_19_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_20_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_21_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_22_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_23_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_24_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_25_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_26_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_27_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_28_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_29_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_30_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_31_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_32_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_33_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_34_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_35_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_3_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_4_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_5_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_6_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_7_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_8_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size2_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_10_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_11_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_12_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_13_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_14_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_15_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_16_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_17_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_18_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_19_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_20_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_21_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_22_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_23_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_24_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_25_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_26_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_27_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_28_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_29_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_30_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_31_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_32_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_33_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_34_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_8_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size2_mem_9_ccff_tail ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_0_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_1_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_2_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_3_sram ;
|
||||
wire [0:1] mux_tree_tapbuf_size3_4_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size3_mem_4_ccff_tail ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_0_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_10_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_11_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_1_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_2_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_3_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_4_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_5_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_6_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_7_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_8_sram ;
|
||||
wire [0:2] mux_tree_tapbuf_size4_9_sram ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_0_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_10_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_11_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_1_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_2_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_3_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_4_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_5_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_6_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_7_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_8_ccff_tail ;
|
||||
wire [0:0] mux_tree_tapbuf_size4_mem_9_ccff_tail ;
|
||||
|
||||
assign prog_clk_0 = prog_clk[0] ;
|
||||
|
||||
sb_2__0__mux_tree_tapbuf_size4_0 mux_top_track_0 (
|
||||
.in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
|
||||
top_left_grid_pin_50_[0] , chanx_left_in[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_1 , SYNOPSYS_UNCONNECTED_2 ,
|
||||
SYNOPSYS_UNCONNECTED_3 } ) ,
|
||||
.out ( chany_top_out[0] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_1 mux_top_track_2 (
|
||||
.in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
|
||||
top_left_grid_pin_51_[0] , chanx_left_in[29] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_4 , SYNOPSYS_UNCONNECTED_5 ,
|
||||
SYNOPSYS_UNCONNECTED_6 } ) ,
|
||||
.out ( chany_top_out[1] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_2 mux_top_track_4 (
|
||||
.in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
|
||||
top_right_grid_pin_1_[0] , chanx_left_in[28] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_7 , SYNOPSYS_UNCONNECTED_8 ,
|
||||
SYNOPSYS_UNCONNECTED_9 } ) ,
|
||||
.out ( chany_top_out[2] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_3 mux_top_track_6 (
|
||||
.in ( { top_left_grid_pin_44_[0] , top_left_grid_pin_47_[0] ,
|
||||
top_left_grid_pin_50_[0] , chanx_left_in[27] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_10 , SYNOPSYS_UNCONNECTED_11 ,
|
||||
SYNOPSYS_UNCONNECTED_12 } ) ,
|
||||
.out ( chany_top_out[3] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_4 mux_top_track_8 (
|
||||
.in ( { top_left_grid_pin_45_[0] , top_left_grid_pin_48_[0] ,
|
||||
top_left_grid_pin_51_[0] , chanx_left_in[26] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_13 , SYNOPSYS_UNCONNECTED_14 ,
|
||||
SYNOPSYS_UNCONNECTED_15 } ) ,
|
||||
.out ( chany_top_out[4] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_5 mux_top_track_10 (
|
||||
.in ( { top_left_grid_pin_46_[0] , top_left_grid_pin_49_[0] ,
|
||||
top_right_grid_pin_1_[0] , chanx_left_in[25] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_16 , SYNOPSYS_UNCONNECTED_17 ,
|
||||
SYNOPSYS_UNCONNECTED_18 } ) ,
|
||||
.out ( chany_top_out[5] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_6 mux_left_track_1 (
|
||||
.in ( { chany_top_in[0] , left_bottom_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_19 , SYNOPSYS_UNCONNECTED_20 ,
|
||||
SYNOPSYS_UNCONNECTED_21 } ) ,
|
||||
.out ( chanx_left_out[0] ) , .p0 ( optlc_net_165 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_7 mux_left_track_3 (
|
||||
.in ( { chany_top_in[29] , left_bottom_grid_pin_3_[0] ,
|
||||
left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_22 , SYNOPSYS_UNCONNECTED_23 ,
|
||||
SYNOPSYS_UNCONNECTED_24 } ) ,
|
||||
.out ( chanx_left_out[1] ) , .p0 ( optlc_net_165 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_8 mux_left_track_5 (
|
||||
.in ( { chany_top_in[28] , left_bottom_grid_pin_5_[0] ,
|
||||
left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_25 , SYNOPSYS_UNCONNECTED_26 ,
|
||||
SYNOPSYS_UNCONNECTED_27 } ) ,
|
||||
.out ( chanx_left_out[2] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_9 mux_left_track_7 (
|
||||
.in ( { chany_top_in[27] , left_bottom_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_7_[0] , left_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_28 , SYNOPSYS_UNCONNECTED_29 ,
|
||||
SYNOPSYS_UNCONNECTED_30 } ) ,
|
||||
.out ( chanx_left_out[3] ) , .p0 ( optlc_net_165 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_10 mux_left_track_9 (
|
||||
.in ( { chany_top_in[26] , left_bottom_grid_pin_3_[0] ,
|
||||
left_bottom_grid_pin_9_[0] , left_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_10_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_31 , SYNOPSYS_UNCONNECTED_32 ,
|
||||
SYNOPSYS_UNCONNECTED_33 } ) ,
|
||||
.out ( chanx_left_out[4] ) , .p0 ( optlc_net_168 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4 mux_left_track_11 (
|
||||
.in ( { chany_top_in[25] , left_bottom_grid_pin_5_[0] ,
|
||||
left_bottom_grid_pin_11_[0] , left_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size4_11_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_34 , SYNOPSYS_UNCONNECTED_35 ,
|
||||
SYNOPSYS_UNCONNECTED_36 } ) ,
|
||||
.out ( chanx_left_out[5] ) , .p0 ( optlc_net_168 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_0 mem_top_track_0 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) , .ccff_head ( ccff_head ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_0_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_1 mem_top_track_2 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_1_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_2 mem_top_track_4 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_2_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_3 mem_top_track_6 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_3_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_4 mem_top_track_8 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_4_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_5 mem_top_track_10 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_5_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_6 mem_left_track_1 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_6_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_7 mem_left_track_3 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_7_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_8 mem_left_track_5 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_8_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_9 mem_left_track_7 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_9_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem_10 mem_left_track_9 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_9_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_10_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size4_mem mem_left_track_11 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_10_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size4_11_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3_0 mux_top_track_12 (
|
||||
.in ( { top_left_grid_pin_44_[0] , top_right_grid_pin_1_[0] ,
|
||||
chanx_left_in[24] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_37 , SYNOPSYS_UNCONNECTED_38 } ) ,
|
||||
.out ( chany_top_out[6] ) , .p0 ( optlc_net_168 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3_1 mux_top_track_44 (
|
||||
.in ( { top_left_grid_pin_48_[0] , top_right_grid_pin_1_[0] ,
|
||||
chanx_left_in[8] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_39 , SYNOPSYS_UNCONNECTED_40 } ) ,
|
||||
.out ( chany_top_out[22] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3_2 mux_left_track_13 (
|
||||
.in ( { chany_top_in[24] , left_bottom_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_41 , SYNOPSYS_UNCONNECTED_42 } ) ,
|
||||
.out ( chanx_left_out[6] ) , .p0 ( optlc_net_168 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3_3 mux_left_track_29 (
|
||||
.in ( { chany_top_in[16] , left_bottom_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_43 , SYNOPSYS_UNCONNECTED_44 } ) ,
|
||||
.out ( chanx_left_out[14] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3 mux_left_track_45 (
|
||||
.in ( { chany_top_in[8] , left_bottom_grid_pin_1_[0] ,
|
||||
left_bottom_grid_pin_17_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size3_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_45 , SYNOPSYS_UNCONNECTED_46 } ) ,
|
||||
.out ( chanx_left_out[22] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3_mem_0 mem_top_track_12 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_0_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3_mem_1 mem_top_track_44 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_1_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3_mem_2 mem_left_track_13 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size4_mem_11_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_2_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3_mem_3 mem_left_track_29 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_3_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size3_mem mem_left_track_45 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size3_4_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_0 mux_top_track_14 (
|
||||
.in ( { top_left_grid_pin_45_[0] , chanx_left_in[23] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_0_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_47 , SYNOPSYS_UNCONNECTED_48 } ) ,
|
||||
.out ( chany_top_out[7] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_1 mux_top_track_16 (
|
||||
.in ( { top_left_grid_pin_46_[0] , chanx_left_in[22] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_1_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_49 , SYNOPSYS_UNCONNECTED_50 } ) ,
|
||||
.out ( chany_top_out[8] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_2 mux_top_track_18 (
|
||||
.in ( { top_left_grid_pin_47_[0] , chanx_left_in[21] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_2_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_51 , SYNOPSYS_UNCONNECTED_52 } ) ,
|
||||
.out ( chany_top_out[9] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_3 mux_top_track_20 (
|
||||
.in ( { top_left_grid_pin_48_[0] , chanx_left_in[20] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_3_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_53 , SYNOPSYS_UNCONNECTED_54 } ) ,
|
||||
.out ( chany_top_out[10] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_4 mux_top_track_22 (
|
||||
.in ( { top_left_grid_pin_49_[0] , chanx_left_in[19] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_4_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_55 , SYNOPSYS_UNCONNECTED_56 } ) ,
|
||||
.out ( chany_top_out[11] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_5 mux_top_track_24 (
|
||||
.in ( { top_left_grid_pin_50_[0] , chanx_left_in[18] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_5_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_57 , SYNOPSYS_UNCONNECTED_58 } ) ,
|
||||
.out ( chany_top_out[12] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_6 mux_top_track_26 (
|
||||
.in ( { top_left_grid_pin_51_[0] , chanx_left_in[17] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_6_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_59 , SYNOPSYS_UNCONNECTED_60 } ) ,
|
||||
.out ( chany_top_out[13] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_7 mux_top_track_28 (
|
||||
.in ( { top_right_grid_pin_1_[0] , chanx_left_in[16] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_7_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_61 , SYNOPSYS_UNCONNECTED_62 } ) ,
|
||||
.out ( chany_top_out[14] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_8 mux_top_track_36 (
|
||||
.in ( { top_left_grid_pin_44_[0] , chanx_left_in[12] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_8_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_63 , SYNOPSYS_UNCONNECTED_64 } ) ,
|
||||
.out ( chany_top_out[18] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_9 mux_top_track_38 (
|
||||
.in ( { top_left_grid_pin_45_[0] , chanx_left_in[11] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_9_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_65 , SYNOPSYS_UNCONNECTED_66 } ) ,
|
||||
.out ( chany_top_out[19] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_10 mux_top_track_40 (
|
||||
.in ( { top_left_grid_pin_46_[0] , chanx_left_in[10] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_10_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_67 , SYNOPSYS_UNCONNECTED_68 } ) ,
|
||||
.out ( chany_top_out[20] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_11 mux_top_track_42 (
|
||||
.in ( { top_left_grid_pin_47_[0] , chanx_left_in[9] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_11_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_69 , SYNOPSYS_UNCONNECTED_70 } ) ,
|
||||
.out ( chany_top_out[21] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_12 mux_top_track_46 (
|
||||
.in ( { top_left_grid_pin_49_[0] , chanx_left_in[7] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_12_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_71 , SYNOPSYS_UNCONNECTED_72 } ) ,
|
||||
.out ( chany_top_out[23] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_13 mux_top_track_48 (
|
||||
.in ( { top_left_grid_pin_50_[0] , chanx_left_in[6] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_13_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_73 , SYNOPSYS_UNCONNECTED_74 } ) ,
|
||||
.out ( chany_top_out[24] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_14 mux_top_track_50 (
|
||||
.in ( { top_left_grid_pin_51_[0] , chanx_left_in[5] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_14_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_75 , SYNOPSYS_UNCONNECTED_76 } ) ,
|
||||
.out ( chany_top_out[25] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_15 mux_left_track_15 (
|
||||
.in ( { chany_top_in[23] , left_bottom_grid_pin_3_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_15_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_77 , SYNOPSYS_UNCONNECTED_78 } ) ,
|
||||
.out ( chanx_left_out[7] ) , .p0 ( optlc_net_168 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_16 mux_left_track_17 (
|
||||
.in ( { chany_top_in[22] , left_bottom_grid_pin_5_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_16_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_79 , SYNOPSYS_UNCONNECTED_80 } ) ,
|
||||
.out ( chanx_left_out[8] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_17 mux_left_track_19 (
|
||||
.in ( { chany_top_in[21] , left_bottom_grid_pin_7_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_17_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_81 , SYNOPSYS_UNCONNECTED_82 } ) ,
|
||||
.out ( chanx_left_out[9] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_18 mux_left_track_21 (
|
||||
.in ( { chany_top_in[20] , left_bottom_grid_pin_9_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_18_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_83 , SYNOPSYS_UNCONNECTED_84 } ) ,
|
||||
.out ( chanx_left_out[10] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_19 mux_left_track_23 (
|
||||
.in ( { chany_top_in[19] , left_bottom_grid_pin_11_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_19_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_85 , SYNOPSYS_UNCONNECTED_86 } ) ,
|
||||
.out ( chanx_left_out[11] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_20 mux_left_track_25 (
|
||||
.in ( { chany_top_in[18] , left_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_20_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_87 , SYNOPSYS_UNCONNECTED_88 } ) ,
|
||||
.out ( chanx_left_out[12] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_21 mux_left_track_27 (
|
||||
.in ( { chany_top_in[17] , left_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_21_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_89 , SYNOPSYS_UNCONNECTED_90 } ) ,
|
||||
.out ( chanx_left_out[13] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_22 mux_left_track_31 (
|
||||
.in ( { chany_top_in[15] , left_bottom_grid_pin_3_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_22_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_91 , SYNOPSYS_UNCONNECTED_92 } ) ,
|
||||
.out ( chanx_left_out[15] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_23 mux_left_track_33 (
|
||||
.in ( { chany_top_in[14] , left_bottom_grid_pin_5_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_23_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_93 , SYNOPSYS_UNCONNECTED_94 } ) ,
|
||||
.out ( chanx_left_out[16] ) , .p0 ( optlc_net_166 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_24 mux_left_track_35 (
|
||||
.in ( { chany_top_in[13] , left_bottom_grid_pin_7_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_24_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_95 , SYNOPSYS_UNCONNECTED_96 } ) ,
|
||||
.out ( chanx_left_out[17] ) , .p0 ( optlc_net_169 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_25 mux_left_track_37 (
|
||||
.in ( { chany_top_in[12] , left_bottom_grid_pin_9_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_25_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_97 , SYNOPSYS_UNCONNECTED_98 } ) ,
|
||||
.out ( chanx_left_out[18] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_26 mux_left_track_39 (
|
||||
.in ( { chany_top_in[11] , left_bottom_grid_pin_11_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_26_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_99 , SYNOPSYS_UNCONNECTED_100 } ) ,
|
||||
.out ( chanx_left_out[19] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_27 mux_left_track_41 (
|
||||
.in ( { chany_top_in[10] , left_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_27_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_101 , SYNOPSYS_UNCONNECTED_102 } ) ,
|
||||
.out ( chanx_left_out[20] ) , .p0 ( optlc_net_165 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_28 mux_left_track_43 (
|
||||
.in ( { chany_top_in[9] , left_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_28_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_103 , SYNOPSYS_UNCONNECTED_104 } ) ,
|
||||
.out ( chanx_left_out[21] ) , .p0 ( optlc_net_165 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_29 mux_left_track_47 (
|
||||
.in ( { chany_top_in[7] , left_bottom_grid_pin_3_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_29_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_105 , SYNOPSYS_UNCONNECTED_106 } ) ,
|
||||
.out ( chanx_left_out[23] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_30 mux_left_track_49 (
|
||||
.in ( { chany_top_in[6] , left_bottom_grid_pin_5_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_30_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_107 , SYNOPSYS_UNCONNECTED_108 } ) ,
|
||||
.out ( chanx_left_out[24] ) , .p0 ( optlc_net_167 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_31 mux_left_track_51 (
|
||||
.in ( { chany_top_in[5] , left_bottom_grid_pin_7_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_31_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_109 , SYNOPSYS_UNCONNECTED_110 } ) ,
|
||||
.out ( chanx_left_out[25] ) , .p0 ( optlc_net_165 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_32 mux_left_track_53 (
|
||||
.in ( { chany_top_in[4] , left_bottom_grid_pin_9_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_32_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_111 , SYNOPSYS_UNCONNECTED_112 } ) ,
|
||||
.out ( chanx_left_out[26] ) , .p0 ( optlc_net_168 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_33 mux_left_track_55 (
|
||||
.in ( { chany_top_in[3] , left_bottom_grid_pin_11_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_33_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_113 , SYNOPSYS_UNCONNECTED_114 } ) ,
|
||||
.out ( chanx_left_out[27] ) , .p0 ( optlc_net_168 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_34 mux_left_track_57 (
|
||||
.in ( { chany_top_in[2] , left_bottom_grid_pin_13_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_34_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_115 , SYNOPSYS_UNCONNECTED_116 } ) ,
|
||||
.out ( chanx_left_out[28] ) , .p0 ( optlc_net_168 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2 mux_left_track_59 (
|
||||
.in ( { chany_top_in[1] , left_bottom_grid_pin_15_[0] } ) ,
|
||||
.sram ( mux_tree_tapbuf_size2_35_sram ) ,
|
||||
.sram_inv ( { SYNOPSYS_UNCONNECTED_117 , SYNOPSYS_UNCONNECTED_118 } ) ,
|
||||
.out ( chanx_left_out[29] ) , .p0 ( optlc_net_168 ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_0 mem_top_track_14 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_0_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_1 mem_top_track_16 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_0_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_1_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_2 mem_top_track_18 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_2_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_3 mem_top_track_20 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_3_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_4 mem_top_track_22 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_4_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_5 mem_top_track_24 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_5_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_6 mem_top_track_26 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_5_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_6_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_7 mem_top_track_28 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_6_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_7_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_8 mem_top_track_36 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_7_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_8_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_9 mem_top_track_38 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_8_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_9_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_10 mem_top_track_40 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_9_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_10_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_11 mem_top_track_42 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_10_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_11_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_11_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_12 mem_top_track_46 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_1_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_12_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_13 mem_top_track_48 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_12_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_13_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_14 mem_top_track_50 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_13_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_14_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_14_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_15 mem_left_track_15 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_2_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_15_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_16 mem_left_track_17 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_15_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_16_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_17 mem_left_track_19 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_16_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_17_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_18 mem_left_track_21 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_17_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_18_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_19 mem_left_track_23 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_18_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_19_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_20 mem_left_track_25 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_19_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_20_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_21 mem_left_track_27 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_20_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_21_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_21_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_22 mem_left_track_31 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_3_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_22_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_23 mem_left_track_33 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_22_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_23_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_24 mem_left_track_35 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_23_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_24_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_25 mem_left_track_37 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_24_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_25_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_26 mem_left_track_39 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_25_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_26_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_27 mem_left_track_41 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_26_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_27_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_28 mem_left_track_43 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_27_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_28_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_28_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_29 mem_left_track_47 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size3_mem_4_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_29_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_30 mem_left_track_49 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_29_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_30_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_31 mem_left_track_51 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_30_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_31_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_32 mem_left_track_53 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_31_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_32_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_33 mem_left_track_55 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_32_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_33_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem_34 mem_left_track_57 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_33_ccff_tail ) ,
|
||||
.ccff_tail ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) ,
|
||||
.mem_out ( mux_tree_tapbuf_size2_34_sram ) ) ;
|
||||
sb_2__0__mux_tree_tapbuf_size2_mem mem_left_track_59 ( .pReset ( pReset ) ,
|
||||
.prog_clk ( prog_clk ) ,
|
||||
.ccff_head ( mux_tree_tapbuf_size2_mem_34_ccff_tail ) ,
|
||||
.ccff_tail ( ccff_tail ) , .mem_out ( mux_tree_tapbuf_size2_35_sram ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 pReset_FTB00 ( .A ( pReset_W_in ) , .X ( pReset[0] ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_167 ( .LO ( SYNOPSYS_UNCONNECTED_119 ) ,
|
||||
.HI ( optlc_net_165 ) ) ;
|
||||
sky130_fd_sc_hd__buf_1 prog_clk_0_FTB00 ( .A ( prog_clk_0_N_in ) ,
|
||||
.X ( prog_clk[0] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_54__53 ( .A ( chanx_left_in[1] ) ,
|
||||
.X ( chany_top_out[29] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_55__54 ( .A ( chanx_left_in[2] ) ,
|
||||
.X ( chany_top_out[28] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_56__55 ( .A ( chanx_left_in[3] ) ,
|
||||
.X ( chany_top_out[27] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_57__56 ( .A ( chanx_left_in[4] ) ,
|
||||
.X ( chany_top_out[26] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_58__57 ( .A ( chanx_left_in[13] ) ,
|
||||
.X ( chany_top_out[17] ) ) ;
|
||||
sky130_fd_sc_hd__buf_6 FTB_59__58 ( .A ( chanx_left_in[14] ) ,
|
||||
.X ( chany_top_out[16] ) ) ;
|
||||
sky130_fd_sc_hd__buf_8 FTB_60__59 ( .A ( chanx_left_in[15] ) ,
|
||||
.X ( chany_top_out[15] ) ) ;
|
||||
sky130_fd_sc_hd__inv_8 BINV_R_125 ( .A ( BUF_net_126 ) , .Y ( pReset_N_out ) ) ;
|
||||
sky130_fd_sc_hd__inv_1 BINV_R_126 ( .A ( pReset_W_in ) , .Y ( BUF_net_126 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_170 ( .LO ( SYNOPSYS_UNCONNECTED_120 ) ,
|
||||
.HI ( optlc_net_166 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_172 ( .LO ( SYNOPSYS_UNCONNECTED_121 ) ,
|
||||
.HI ( optlc_net_167 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_174 ( .LO ( SYNOPSYS_UNCONNECTED_122 ) ,
|
||||
.HI ( optlc_net_168 ) ) ;
|
||||
sky130_fd_sc_hd__conb_1 optlc_176 ( .LO ( SYNOPSYS_UNCONNECTED_123 ) ,
|
||||
.HI ( optlc_net_169 ) ) ;
|
||||
endmodule
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
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Reference in New Issue